A timing calibration method for a critical path of a high-speed firearm

Abstract

The application discloses a kind of timing calibration methods of critical path of high-speed transmitter, comprising: determining frequency division coefficient according to target rate, and the sampling clock signal is outputted after frequency division to high-speed clock signal by phase interpolation;With sampling clock signal, parallel data is sampled and first level parallel-serial conversion is carried out, and medium-speed data signal and data clock signal are outputted;Equivalent delay circuit is constructed with the same path as medium-speed data signal, and equivalent clock signal is outputted by delaying data clock signal;With equivalent clock signal, high-speed clock signal is sampled, and phase control word is iterated to sampling result flip lock;According to locking value and sampling clock signal, high-speed serial data signal is outputted by second level parallel-serial conversion.The application solves the technical problems that sampling time deviates from the center of data effective window caused by frequency mismatch, phase coarse adjustment, path delay uncertainty and working condition change in two-level parallel-serial conversion architecture of high-speed transmitter.

Description

Technical Field

[0001] This invention relates to the field of high-speed serial data transmission technology, and specifically to a timing calibration method for the critical path of a high-speed transmitter. Background Technology

[0002] With the rapid development of technologies such as big data, cloud computing, and artificial intelligence, high-speed serial data transmission rates are constantly increasing, with single-channel transmission rates rising from the traditional several Gbps to the levels of 10.3125 Gbps, 25.78125 Gbps, and even 112 Gbps. In high-speed transmitters, to reduce the operating frequency of digital logic, a two-stage parallel-to-serial conversion architecture is typically used: the first stage converts wide-bit-width parallel data into medium-speed serial data, and the second stage converts the medium-speed serial data into the final high-speed serial data output.

[0003] However, the existing two-stage parallel-to-serial conversion architecture still has many technical problems. The fixed division ratio leads to frequency mismatch during multi-protocol switching, coarse-grained phase shift cannot meet the sub-picosecond resolution requirements, data path delay depends on simulation prediction and cannot track changes in operating conditions in real time, phase search is difficult to balance speed and accuracy between exhaustive search and fixed step size, and there is a lack of accurate phase alignment between the sampling clock of the second-stage parallel-to-serial conversion and the medium-speed data. Summary of the Invention

[0004] This invention provides a timing calibration method for the critical path of a high-speed transmitter. This invention solves the technical problem of sampling time deviating from the center of the effective data window caused by frequency mismatch, phase coarse adjustment, unmeasurable path delay, and changes in operating conditions between clocks and data at each stage in a two-stage parallel-to-serial conversion architecture of a high-speed transmitter.

[0005] In view of the above problems, the present invention provides a timing calibration method for the critical path of a high-speed transmitter, the method comprising: The target transmission rate of the high-speed transmitter is obtained, the frequency division coefficient is determined based on the target transmission rate, the input high-speed clock signal is frequency divided to obtain the frequency-divided clock signal, and the frequency-divided clock signal is input to the phase interpolation module for phase adjustment, and the sampling clock signal is output. Based on the sampling clock signal, the parallel data in the digital module is sampled and the first-stage parallel-to-serial conversion is performed to output a medium-speed data signal and the corresponding data clock signal. Construct an equivalent delay circuit with the same data path as the medium-speed data signal from the output of the first parallel-to-serial circuit to the input of the second parallel-to-serial circuit, receive the data clock signal and output an equivalent clock signal; The high-speed clock signal is sampled using the equivalent clock signal to obtain the sampling result, and the phase control word of the phase interpolation module is iteratively adjusted according to the sampling result until the sampling result undergoes a preset state flip, and the current phase control word is locked. Based on the locked current phase control word and the sampling clock signal, the medium-speed data signal is converted to a second-stage parallel-to-serial signal through the second parallel-to-serial circuit, and a high-speed serial data signal is output.

[0006] One or more technical solutions provided in this invention have at least the following technical effects or advantages: This invention achieves adaptive matching of the division ratio as the target data bit width changes by using the ratio of the high-speed clock frequency to the target transmission rate as the division coefficient, eliminating the frequency mismatch problem during multi-protocol switching when the division ratio is fixed. Through two-stage adjustment of coarse selection and fine interpolation in the phase interpolation module, the phase adjustment resolution is refined to the sub-picosecond level, providing a highly linear phase adjustment method for closed-loop search. By buffering the sampling clock and using it as the data clock signal for synchronous output with medium-speed data, a definite and traceable phase relationship between data and clock is established. By constructing an equivalent delay circuit that is completely identical to the data path in terms of logic gate level, wiring topology, and load conditions, accurate reproduction of data path delay is achieved, allowing real-time acquisition of delay information without off-chip measurement. By employing a D-flip-flop cross-sampling structure and a binary search algorithm, single-step conversion of phase relationships to digital levels and rapid convergence within at most B iterations at B-bit precision are achieved, resulting in an exponential improvement in search efficiency compared to exhaustive search. Combined with a historical phase control word library containing three-dimensional operating conditions (temperature, voltage, and speed), the search range is compressed from global to local, reducing the number of iterations by 50% to over 70%. Furthermore, historical data is continuously reused across power-on cycles, and the calibration speed increases with the number of uses. Finally, the locked sampling clock phase ensures that the sampling edge of the second parallel-to-serial converter is precisely aligned with the center of the effective window of the medium-speed data signal, avoiding setup or hold time violations.

[0007] In summary, this invention solves the technical problem of sampling time deviating from the center of the effective data window caused by frequency mismatch, phase coarse adjustment, unmeasurable path delay, and changes in operating conditions between clocks and data at each stage in a two-stage parallel-to-serial conversion architecture of a high-speed transmitter. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a flowchart illustrating a timing calibration method for a critical path of a high-speed transmitter provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the internal processing flow of the phase interpolation module in a timing calibration method for a critical path of a high-speed transmitter provided in an embodiment of the present invention. Detailed Implementation

[0010] This invention provides a timing calibration method for the critical path of a high-speed transmitter, specifically addressing the technical problem of sampling time deviating from the center of the effective data window caused by frequency mismatch, phase coarse adjustment, unmeasurable path delay, and changes in operating conditions between clocks and data at each stage in a two-stage parallel-to-serial conversion architecture of a high-speed transmitter.

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0012] Examples, such as Figure 1 As shown, this invention provides a timing calibration method for the critical path of a high-speed transmitter, the method comprising: S100: Obtain the target transmission rate of the high-speed transmitter, determine the frequency division coefficient based on the target transmission rate, perform frequency division processing on the input high-speed clock signal to obtain the frequency-divided clock signal, input the frequency-divided clock signal into the phase interpolation module for phase adjustment, and output the sampling clock signal.

[0013] In existing high-speed serial transmitter designs, as transmission rates climb to Gbps levels and above, the effective data window width is drastically compressed to the order of hundreds or even tens of picoseconds. Frequency mismatch between any clock division path and the parallel data loading path leads to cumulative phase drift at the sampling time, potentially causing bit misalignment. Simultaneously, traditional delay chains or coarse-tuning phase shifters, limited by the inherent step size and severe nonlinearity of process gate delays, cannot provide sufficiently fine and monotonically controllable phase adjustment capabilities under conditions of drastic changes in chip process angles, voltage, and temperature. This causes closed-loop calibration algorithms to frequently fall into local convergence due to excessive initial phase deviations or ambiguities in the transfer function, failing to accurately capture the optimal opening position of the data eye diagram. Therefore, how to achieve precise algebraic locking between the divided clock and the parallel data loading rate in the frequency domain, and construct a linear adjustment mechanism in the phase domain with both large dynamic range and sub-picosecond resolution, thus providing an unambiguous and rapidly converging adjustment prerequisite for subsequent feedback calibration, has become a pressing technical problem to be solved.

[0014] Step S100 in the method provided in this embodiment of the invention includes: Obtain the frequency of the high-speed clock signal; The ratio of the frequency of the high-speed clock signal to the data bit width of the target transmission rate is used as the frequency division coefficient.

[0015] In this embodiment of the invention, the clock management and frequency configuration unit inside the transmitter first accurately obtains the frequency value of the high-speed clock signal currently input to the transmitter's analog front end through a built-in frequency detector or from the frequency lock indication signal of the phase-locked loop, and records this frequency as f. c The unit is Hz. Simultaneously, this frequency configuration unit obtains the required target serial transmission rate by reading the pre-configured current communication mode or protocol standard from the transmitter link control register, and denotes this target serial transmission rate as f. d The unit is bps, which is bits per second. In addition, it is also necessary to obtain the fixed data bit width used for parallel processing in the digital module. This fixed data bit width is fixed by the transmitter system architecture during the chip design stage. For example, in a typical 16:1 or 32:1 high-speed SerDes structure, the parallel data bit width is usually 16, 32 or 40 bits. Here, this fixed bit width is denoted as N, and the unit is bits.

[0016] Furthermore, after obtaining the frequency value of the high-speed clock signal, the target serial transmission rate, and the fixed data bit width, the ratio of the high-speed clock signal frequency to the target transmission rate data bit width is used as the frequency division coefficient M. It should be noted that the target transmission rate data bit width physically refers to the quotient of the target transmission rate and the parallel data bit width, i.e., f. d / N, this quotient represents the actual bit update frequency carried on each parallel data channel, and is also the frequency reference value of the sampling clock required by the first-stage parallel-to-serial converter circuit in the process of converting parallel data into serial data. Therefore, the mathematical expression for the frequency division coefficient M is: ; In practical engineering implementations, the division factor M is written into the mode control register inside the programmable frequency divider after calculation. This divider typically employs a counter-based cascaded structure. Its internal counters cyclically count the rising edges of the input high-speed clock signal. Each time the count accumulates to M-1, a logic level flip occurs at the output, generating a divided clock signal with a duty cycle of approximately 50% and a frequency that strictly meets the requirements. It should be noted that in many practical engineering applications, to simplify the clock network architecture, a bit clock is directly used as the input high-speed clock, and the frequency value of this bit clock is equal to the target transmission rate. In this case, the division factor is M=N in numerical calculation, meaning the division factor is exactly equal to the parallel data bit width.

[0017] For example, suppose a high-speed backplane transmitter needs to support the current mainstream 10G Ethernet passive optical network standard, and its target transmission rate is set to f. d =10.3125Gbps, the internal digital module uses a parallel data bit width of N=16bit. At this point, the target transmission rate data bit width is f. d / N=10.3125Gbps / 16bit, if the high-speed clock signal frequency provided by the chip clock unit is f c =10.3125GHz, then the frequency division coefficient M is calculated as (10.3125GHz × 16bit) / 10.3125Gbps = 16.

[0018] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on the present invention.

[0019] Step S100 in the method provided in this embodiment of the invention, as follows: Figure 2 As shown, it also includes: Based on the registers of the digital module, a phase control word is output to the phase interpolation module; The phase interpolation module selects a target phase from multiple equally spaced phases of the frequency division clock signal according to the phase control word, and outputs the sampled clock signal by weighting adjacent phases.

[0020] In this embodiment of the invention, after obtaining a frequency-matched clock signal through frequency division processing, since this signal only solves the alignment problem in the frequency domain, the phase position of its edge relative to the actual data effective window still has uncertainty. Therefore, it is necessary to send the frequency-divided clock signal to the phase interpolation module for fine phase adjustment. Specifically, the digital module has a dedicated phase control register group corresponding to the phase interpolation module. During the calibration process, the calibration state machine or microcontroller dynamically calculates the required phase offset according to a preset search strategy and converts it into a digital phase control word, denoted as PCW. This phase control word is transmitted in real time through a dedicated on-chip parallel control bus or a high-speed serial peripheral interface and written into the input latch of the phase interpolation module.

[0021] Furthermore, the phase interpolation module integrates a high-precision multiphase generation circuit based on a delay-locked loop or a passive multiphase filter network. This high-precision multiphase generation circuit first receives the input frequency-divided clock signal and, using its internal voltage-controlled delay chain or resistor-capacitor phase-shifting network, uniformly extracts and generates 2π phases at equal intervals within a single complete clock cycle. K Two coarse-tuning reference phases, where K is an integer determined during design. KThe coarse adjustment phases are uniformly distributed within a complete 360° cycle, meaning the interval between two adjacent coarse adjustment phases is 360° / 2. K These constitute the basic set for phase coarse selection. The high-order bits of the phase control word (PCW) are responsible for selecting from these two... K Among the coarse adjustment phases, a pair of adjacent phases are selected as the reference for subsequent fine interpolation. Let the selected pair of adjacent coarse adjustment phases be θ. a With θ a+1 .

[0022] Simultaneously, the low-order field of the phase control word (PCW) is fed into the digital-to-analog converter (DAC) integrated within the phase interpolation module. This DAC converts the digital code of the low-order field into an analog control quantity, which determines the weight ratio of two adjacent reference phases when superimposed on the output. Specifically, the weighting coefficient is defined as α, and its value is strictly limited to the closed interval [0,1]. The value of α is linearly determined by the conversion result of the low-order field. In the core summing unit of the phase interpolation module, the first reference phase θ is summed using current-mode logic or a voltage-mode adder structure. a Multiply by the weighting factor (1-α), and simultaneously set the second reference phase θ. a+1 Multiply by a weighting coefficient α, then perform analog superposition and buffering shaping on the two weighted signals at the node, finally outputting the phase θ of the sampling clock signal. out Satisfying the following linear interpolation relationship: θ out =(1-α)×θ a +α×θ a+1 .

[0023] The weighting coefficient α is linearly determined by the low-order bits of the phase control word after digital-to-analog conversion. Let the bit width of the low-order bits be M, and its binary value range be 0 to 2. M -1, this value, after being converted into an analog voltage by a digital-to-analog converter (DAC), exhibits a strictly linear proportional relationship between its output voltage and the input digital code due to the DAC's internal equal-resistor series voltage divider structure. Therefore, α and the lower-order field value PCW low The condition α=PCW is satisfied between them. low / (2 M -1). When the lower-order bits are all 0, α=0, and the output phase is exactly equal to the first reference phase θ. a When the lower-order bits are all 1s, α=1, and the output phase is exactly equal to the second reference phase θ. a+1 When the lower-order field takes the middle value, α takes values ​​proportionally within the range of 0 to 1, with the minimum change step being 1 / (2). M-1). By changing the value of the low-order field of PCW, that is, changing the continuous value of the weight coefficient α between 0 and 1, very fine phase interpolation steps can be achieved within the adjacent coarse adjustment phase interval, and its minimum phase adjustment resolution is much smaller than the coarse adjustment step size.

[0024] It should be noted that when the boundary conditions α=0 or α=1, the phase interpolation module can directly switch to the corresponding reference phase output through the selector without going through the weighted summation unit, so as to eliminate the risk of signal distortion under extreme weights.

[0025] For example, assume the frequency of the divided clock signal is 644.53125MHz, corresponding to a period of approximately 1.551 nanoseconds. If the internal design parameter K=4 of the phase interpolation module, providing 16 coarse adjustment phases, then the angular step size between adjacent coarse adjustment phases is 360° / 16=22.5°. In a certain calibration iteration, if the high bit of the current PCW specifies θ... a =67.5°, θ a+1 =90°, and the weighting coefficient of the lower-order output after digital-to-analog conversion is α=0.4, then the sampling clock phase of the final interpolated output is: 67.5°×(1-0.4)+90°×0.4=67.5°×0.6+90°×0.4=40.5°+36°=76.5°.

[0026] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on the present invention.

[0027] In this embodiment of the invention, adaptive frequency division in the frequency domain and weighted interpolation in the phase domain work together. The frequency division clock frequency is always strictly locked to the bit update rate of the parallel data, eliminating the cumulative phase drift caused by frequency misalignment. The phase interpolation module, through a hierarchical architecture of coarse and fine adjustment, maintains monotonic and continuous phase transfer characteristics without jumps across the entire temperature range and voltage domain, refining the phase adjustment resolution to the sub-picosecond level. The synergistic effect of these two technologies enables subsequent closed-loop calibration to converge rapidly to the optimal sampling phase point in a very small number of iterations, significantly improving the horizontal eye diagram opening of the transmitter's high-speed serial data output, and stabilizing the inherent bit error rate to an extremely low level. At the same time, under extreme high and low temperature shocks and drastic power supply voltage fluctuations, the timing margin fluctuation range of the critical data path is significantly narrowed, thereby significantly improving the mass production yield of the product and providing a solid guarantee for long-term stable operation in complex electromagnetic environments.

[0028] S200: Based on the sampling clock signal, the parallel data in the digital module is sampled and the first-stage parallel-to-serial conversion is performed to output a medium-speed data signal and the corresponding data clock signal.

[0029] In a two-stage parallel-to-serial converter architecture for high-speed transmitters, the first-stage parallel-to-serial converter plays a crucial role in bridging the low-speed parallel data domain with the high-speed serial data domain. However, in traditional designs, there is often a lack of a clear and traceable phase relationship between the sampling clock used by the first-stage parallel-to-serial converter and the output serial data. This causes the second-stage parallel-to-serial converter circuit to be unable to accurately determine the effective window position of the data when receiving the medium-speed data signal, and it has to rely on additional clock recovery circuits or complex phase detection mechanisms to re-establish synchronization. This increases circuit overhead and introduces additional timing uncertainties.

[0030] Meanwhile, due to the different buffers and wiring delays experienced by the sampling clock signal along the transmission path, there is often an unpredictable phase difference between the arrival time of the second-stage parallel-to-serial converter and the arrival time of the medium-speed data signal. This phase difference can severely compress the second-stage sampling window under high-speed transmission conditions, directly leading to setup or hold time violations. Therefore, how to ensure that the medium-speed data signal output from the first-stage parallel-to-serial converter carries a companion clock signal with a definite phase relationship and that can directly reflect the sampling time, thereby providing a clear time reference for subsequent calibration and serialization, has become a crucial technical problem that needs to be solved to ensure reliable data transmission between the two stages of parallel-to-serial conversion.

[0031] Step S200 in the method provided in this embodiment of the invention includes: The first parallel-to-serial converter uses the sampling clock signal as the sampling clock to sample the N-bit parallel data output by the digital module. The N-bit parallel data is output bit by bit in a predetermined order to form a serial medium-speed data signal, and the sampling clock signal is buffered and output as a data clock signal. The rate of the medium-speed data signal is N times that of the parallel data.

[0032] In this embodiment of the invention, after obtaining the phase-adjusted sampling clock signal, the parallel data output by the digital module is sampled using the sampling clock signal, and a first-stage parallel-to-serial conversion is performed. Specifically, the clock input terminal of the first parallel-to-serial conversion circuit is connected to the output terminal of the phase interpolation module, using the sampling clock signal as its sampling clock. The data input terminal of the first parallel-to-serial conversion circuit is connected to the parallel data output bus of the digital module, receiving N bits of parallel data output by the digital module; for example, when N=16, it is 16 bits of parallel data.

[0033] Furthermore, within each sampling clock cycle, the first parallel-to-serial converter performs parallel latching sampling of the N-bit parallel data in its internal shift register or latch array. After sampling, the first parallel-to-serial converter serially outputs the latched N-bit parallel data bit by bit according to a pre-set bit output order, typically from the most significant bit to the least significant bit, or from the least significant bit to the most significant bit. Each output bit corresponds to one cycle of the sampling clock signal; therefore, the N-bit parallel data is sequentially expanded into N consecutive bits, forming a serial medium-speed data signal.

[0034] Simultaneously, the first parallel-to-serial conversion circuit also sends the sampling clock signal into an internal clock buffer or driver unit. After buffering, it outputs the data clock signal from the circuit's data clock output terminal as a data clock signal that is synchronously transmitted with the medium-speed data signal. It should be noted that this data clock signal maintains the same frequency and phase as the sampling clock signal. Its function is to provide a synchronous clock reference with a known phase relationship to the medium-speed data signal for the subsequent second-stage parallel-to-serial conversion circuit. Based on the above conversion process, the rate of the medium-speed data signal is numerically equal to the frequency of the sampling clock signal, and since the frequency of the sampling clock signal is set to f... d / N, which is the target transmission rate divided by the parallel data bit width, means that the rate of the medium-speed data signal is equal to N times the parallel data rate. In other words, the number of bits transmitted by the medium-speed data signal per unit time is N times the number of data words transmitted by the parallel data bus per unit time.

[0035] For example, suppose the parallel data bit width N=16 and the sampling clock signal frequency is 644.53125MHz. During the first sampling clock cycle, the first parallel-to-serial converter sample and latch the 16-bit parallel data output from the digital module. Then, according to a pre-set bit order, for example from the most significant bit to the least significant bit, it outputs one bit of data sequentially in each sampling clock cycle. After continuously outputting 16 bits, a complete parallel data word is expanded into a serial data sequence consisting of 16 consecutive bits. The rate of this serial data sequence is 16 × 644.53125Mbps = 10.3125Gbps, which is exactly equal to the target transmission rate. Simultaneously, the first parallel-to-serial converter outputs the buffered sampling clock signal as the data clock signal. This data clock signal is synchronized with the output serial medium-speed data signal, providing an accurate clock reference for the subsequent second-stage parallel-to-serial converter to resample and serialize the medium-speed data signal.

[0036] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on the present invention.

[0037] This invention, through buffering, directly outputs the sampled clock signal as the data clock signal, synchronously with the medium-speed data signal. This ensures that the data clock signal and the medium-speed data signal originate from the same clock source, follow a traceable path, and have a definite and stable phase correspondence. This data clock signal provides an accurate clock reference for the subsequent construction of the equivalent delay circuit and the sampling operation of the second-stage parallel-to-serial conversion, enabling the equivalent delay circuit to accurately replicate the delay characteristics of the data path, thereby ensuring the effectiveness and accuracy of subsequent phase calibration. Simultaneously, since this data clock signal is transmitted synchronously with the medium-speed data signal, the second-stage parallel-to-serial conversion circuit can reliably sample the data directly using this clock without additional clock recovery or phase detection, effectively eliminating uncertainties caused by path delay differences. This saves additional synchronization overhead at the circuit level and provides clear and controllable timing boundaries for the entire two-stage parallel-to-serial conversion architecture at the timing level.

[0038] S300: Construct an equivalent delay circuit with the same data path as the medium-speed data signal from the output of the first parallel-to-serial circuit to the input of the second parallel-to-serial circuit, receive the data clock signal and output an equivalent clock signal.

[0039] In the two-stage parallel-to-serial conversion architecture of a high-speed transmitter, the data path from the output of the first parallel-to-serial circuit to the input of the second parallel-to-serial circuit exhibits a non-negligible propagation delay. This delay drifts significantly with variations in process angle, voltage, and temperature, and since this path lies between the two parallel-to-serial conversion stages, it cannot be directly measured. Traditional designs rely on pre-fabrication simulation to estimate fixed phase compensation values, which cannot track real-time delay changes under actual operating conditions, causing the second-stage sampling time to deviate from the center of the effective data window. Therefore, how to reproduce the delay characteristics of this data path in real time within the chip without introducing complex measurement circuits has become a pressing technical problem to be solved.

[0040] Step S300 in the method provided in this embodiment of the invention includes: The equivalent delay circuit is a replication circuit of the data path between the output of the first parallel-to-serial circuit and the input of the second parallel-to-serial circuit. The equivalent delay circuit has the same number of logic gates, wiring topology and load conditions as the data path. The equivalent delay circuit receives the data clock signal and outputs the delayed equivalent clock signal.

[0041] In this embodiment of the invention, the equivalent delay circuit is constructed as a replica of the complete data path between the output of the first parallel-to-serial circuit and the input of the second parallel-to-serial circuit. This data path refers to the entire physical path traversed by the medium-speed data signal from the data output of the first parallel-to-serial circuit, through on-chip traces, intermediate buffers, level conversion units, and other circuit components, finally reaching the data input of the second parallel-to-serial circuit. The core design principle of the equivalent delay circuit is that it is not an arbitrary simplification or equivalent approximation of the data path, but rather requires consistency with the real data path in three key dimensions, or matching after equivalent scaling or compensation. The equivalent delay circuit and the second parallel-to-serial circuit are structurally independent, used only to generate an equivalent clock signal for calibration, and do not participate in the actual data signal transmission path.

[0042] Specifically, in terms of the number of logic gates, the number and type of series logic gates contained in the equivalent delay circuit are exactly the same as the number and type of all logic gates traversed in the data path from the output of the first parallel-to-serial circuit to the input of the second parallel-to-serial circuit. For example, if a medium-speed data signal passes through one output buffer, a two-stage inverter drive chain, and one input buffer in sequence during transmission, then the equivalent delay circuit must also contain the same number of buffers and inverters in series, and their cascading order must be consistent with the data path.

[0043] In terms of routing topology, the signal routing within the equivalent delay circuit, including the connection order between nodes, the number of routing corners, routing levels, and routing spacing, is designed to be consistent with the actual physical routing topology of the data path. By adopting the same layout and routing strategy as the data path, the equivalent delay circuit can replicate the transmission delay introduced by parasitic resistance and capacitance in the data path.

[0044] In terms of load conditions, the load driven by the output of the equivalent delay circuit is the same as the load conditions presented by the input of the second parallel-to-serial circuit. Specifically, the output of the equivalent delay circuit is connected to a replicated load unit, which is composed of transistors of the same size and type as those at the input of the second parallel-to-serial circuit and has the same input capacitance value. By ensuring the equivalence of the output load conditions, the equivalent delay circuit can reproduce the signal transition characteristics at the end of the data path at the rising and falling edge slew rates during signal transitions.

[0045] Furthermore, the input of the equivalent delay circuit receives the data clock signal from the data clock output of the first parallel-to-serial circuit. This data clock signal, after passing through the same logic gate stages, wiring topology, and load conditions as the data path, is output from the output of the equivalent delay circuit, resulting in a delayed equivalent clock signal. Since the equivalent delay circuit and the data path are strictly identical in the above three dimensions, the delay of the equivalent clock signal relative to the original data clock signal is precisely equal to the data path delay experienced by the medium-speed data signal as it propagates from the output of the first parallel-to-serial circuit to the input of the second parallel-to-serial circuit.

[0046] This invention constructs an equivalent delay circuit that is identical to the data path in terms of logic gate levels, wiring topology, and load conditions. This transfers the originally unobservable data path delay to the clock path and outputs it as an equivalent clock signal, providing an accurate delay reference for subsequent phase calibration. Because this replicated circuit shares the same power supply, substrate, and temperature environment as the real data path, any delay drift caused by PVT changes can be synchronously reproduced. This allows subsequent calibration loops to close the loop and compensate for the entire delay of the data path, eliminating the need for off-chip measurements or complex time-to-digital conversion circuits, effectively improving the transmitter's timing robustness under extreme operating conditions.

[0047] S400: The high-speed clock signal is sampled using the equivalent clock signal to obtain the sampling result, and the phase control word of the phase interpolation module is iteratively adjusted according to the sampling result until the sampling result undergoes a preset state flip, and the current phase control word is locked.

[0048] The digital module has an internal calibration state machine, which is connected to the register interface of the phase interpolation module and the output of the D flip-flop via a parallel control bus. This calibration state machine is used to read the sampling results and iteratively output the phase control word.

[0049] In the timing calibration closed loop of high-speed transmitters, the phase relationship between the equivalent clock signal and the high-speed clock signal needs to be converted into a logic level that can be determined by digital circuits. However, traditional solutions rely on complex analog phase detectors or time-to-digital converters, which have large area and power consumption overhead and are easily affected by process deviations. At the same time, even if a determinable sampling result is obtained, exhaustive search is too time-consuming, and fixed-step scanning cannot balance speed and accuracy. Transmitters frequently face changes in operating conditions such as temperature, voltage, and speed. If a global search is started from zero after each change, the accumulated calibration time and power consumption overhead are unacceptable in scenarios requiring frequent recalibration. Therefore, how to construct a complete calibration closed loop from phase determination to fast search to history reuse has become an urgent technical problem to be solved.

[0050] Step S400 in the method provided in this embodiment of the invention includes: The equivalent clock signal is used as the clock input signal of the D flip-flop, and the high-speed clock signal is used as the data input signal of the D flip-flop. The D flip-flop samples the current level of the high-speed clock signal on the rising edge of the equivalent clock signal and outputs the sampling result.

[0051] In this embodiment of the invention, the equivalent clock signal output by the equivalent delay circuit is connected to the clock input terminal of a D flip-flop, typically labeled CK. The high-speed clock signal is connected to the data input terminal of the D flip-flop, typically labeled D. The D flip-flop is configured as a rising-edge triggered flip-flop. Its operating principle is to sample and latch the current level state of the data input terminal only at the instant the clock input signal transitions from logic low to logic high, and then maintain and output this sampling result at its output terminal, typically labeled Q, until the next rising clock edge arrives and updates it with a new sample value.

[0052] Traditional D flip-flops typically connect the data signal to the D terminal and the clock signal to the CK terminal to achieve synchronous sampling of the data signal. This embodiment of the invention reverses this connection, using the equivalent clock signal as the sampling reference and the high-speed clock signal as the sampled object. This connection allows the observation of the output level of the D flip-flop at different rising edges of the equivalent clock signal to deduce the positional relationship between the rising edge of the equivalent clock signal and the edge of the high-speed clock signal. Specifically, if the high-speed clock signal is at a high level when the rising edge of the equivalent clock signal arrives, the sampling result is logic "1"; if the high-speed clock signal is at a low level, the sampling result is logic "0". Under the condition that the high-speed clock signal is an ideal square wave and the duty cycle is close to 50%, when the rising edge of the equivalent clock signal is near the center of the high-level interval of the high-speed clock signal, the sampling result is "1"; when the rising edge is near the center of the low-level interval, the sampling result is "0"; and when the rising edge just sweeps across the rising or falling edge of the high-speed clock signal, the sampling result will undergo a deterministic flip from "1" to "0" or from "0" to "1".

[0053] Therefore, the positional difference between the rising edge of the equivalent clock signal and the edge of the high-speed clock signal is converted into a high-low level difference at the output of the D flip-flop. This high-low level, as a digital logic signal, can be directly read and judged by the calibration state machine without any analog-to-digital conversion or level decision circuitry. The sampling result remains stable until the next rising edge of the equivalent clock signal arrives, providing ample time margin for subsequent calibration decisions.

[0054] Step S400 in the method provided in this embodiment of the invention further includes: The phase control word is adjusted successively using a binary search algorithm. After each adjustment, the updated phase control word is output to the phase interpolation module, and the current sampling result is obtained. If the current sampling result does not result in the preset state flip, the next search direction and search step size are determined based on the current sampling result. The preset state flip is the level of the output terminal of the D flip-flop flipping from low level to high level or from high level to low level. The search step size is halved with each iteration until the sampling result is flipped by the preset state, and the current phase control word is locked. If the search step size reaches the minimum adjustment granularity of the phase interpolation module and the sampling result is still not flipped, the phase control word corresponding to the current sampling result is used as the locking value.

[0055] In this embodiment of the invention, after obtaining a determinable digital sampling result through D flip-flop sampling, a binary search algorithm is used to iteratively adjust the phase control word of the phase interpolation module. The design goal of this binary search algorithm is to find the critical phase control word that causes the sampling result to exactly flip to a preset state within the fewest possible number of iterations. The rising edge of the equivalent clock signal corresponding to this critical control word is exactly aligned with the edge of the high-speed clock signal.

[0056] Specifically, before the first iteration begins, the calibration state machine first determines the entire adjustable range of the phase control word. Let the bit width of the phase control word be B bits; in a typical design, B can be 8, 10, or 12 bits. Its adjustable value range is 0 to 2^B - 1, where 0 corresponds to the minimum phase offset and 2^B - 1 corresponds to the maximum phase offset. The lower bound of the entire search interval is denoted as L and initialized to 0, and the upper bound is denoted as U and initialized to 2^B - 1. The search step size for the first iteration is set to half the interval width, i.e., 2^B - 1.

[0057] Furthermore, in each iteration, the calibration state machine calculates the candidate value of the phase control word for this iteration based on the midpoint of the current search interval. This updated phase control word is output to the phase interpolation module via the control bus. The phase interpolation module then adjusts the phase of the sampling clock signal accordingly, thereby affecting the phase of the equivalent clock signal output by the equivalent delay circuit, ultimately reflected in the change of the D flip-flop sampling result. The calibration state machine reads the current sampling result output by the D flip-flop, which is either a logic high level or a logic low level, and determines whether the preset state transition has occurred.

[0058] In this context, the preset state flip-flop's output level flips from low to high, meaning the sampling result changes from low to high, or vice versa. Essentially, this flip-flop's response is the digital domain response generated when the rising edge of the equivalent clock signal passes the edge of the high-speed clock signal. Physically, it means the rising edge of the equivalent clock signal has crossed from one level interval of the high-speed clock signal into an adjacent level interval.

[0059] Furthermore, if the current sampling result has not yet undergone a preset state flip, the calibration state machine determines the direction of the next search based on the specific value of the current sampling result. If the current sampling result is low, i.e., the D flip-flop output is low, it indicates that the rising edge of the equivalent clock signal currently falls within the low-level range of the high-speed clock signal. To approach the edge position of the high-speed clock signal, the phase of the sampling clock signal needs to be adjusted in the direction that shifts the rising edge of the equivalent clock signal backward. In the search interval, this means that the target flip point is located to the right of the current phase value, i.e., in the direction of a larger value. Therefore, the lower bound L of the search interval needs to be updated to the current phase control word value, while the upper bound U remains unchanged. If the current sampling result is high, i.e., the D flip-flop output is high, it indicates that the rising edge of the equivalent clock signal currently falls within the high-level range of the high-speed clock signal. To approach the edge position of the high-speed clock signal, the phase of the sampling clock signal needs to be adjusted in the direction that shifts the rising edge of the equivalent clock signal forward. In the search interval, this means that the target flip point is located to the left of the current phase value, i.e., in the direction of a smaller value. Therefore, the upper bound U of the search interval needs to be updated to the current phase control word value, while the lower bound L remains unchanged.

[0060] Furthermore, regardless of the above scenario, the search step size for the next iteration is set to half the width of the current search interval; that is, the search step size halves with each iteration. If the initial search step size is 2 to the power of B-1, then the search step size for each iteration is successively 2 to the power of B-2, 2 to the power of B-3, until the step size decreases to 1. This means that the algorithm rapidly approaches the target flip point with large steps in the early stages of the search, and performs fine positioning with small steps in the later stages, ensuring both search speed and final positioning accuracy.

[0061] Finally, the above iterative process continues until the sampling result undergoes a preset state flip. This flip occurs when the rising edge of the equivalent clock signal has crossed the edge of the high-speed clock signal. The corresponding phase control word at this point is the optimal control word that aligns the rising edge of the equivalent clock signal with the edge of the high-speed clock signal. The calibration state machine then locks the current phase control word and stops iterating, ending the calibration process.

[0062] It should be noted that in practical engineering, there is a possible scenario where the search step size has been reduced to the minimum adjustment granularity supported by the phase interpolation module, which is the minimum phase change corresponding to the least significant bit of the phase control word, but the sampling result still has not undergone the preset state flip. This situation usually means that the edge of the high-speed clock signal is exactly between two adjacent adjustable phases, that is, the flip point falls within the quantization interval, and the flip point itself cannot be accurately located using discrete phase control words. In this case, the calibration state machine uses the phase control word corresponding to the current sampling result as the lock value, that is, it uses the adjustable phase closest to the flip point as the final calibration result. This processing method ensures that even under the most unfavorable quantization conditions, the phase error will not exceed the minimum adjustment granularity of the phase interpolation module, thereby maintaining the deterministic nature of the calibration accuracy.

[0063] For example, assume the phase control word is 8 bits wide and adjustable from 0 to 255. The initial search interval has a lower bound L of 0 and an upper bound U of 255. The first iteration has a search step size of 128, the phase control word is set to 128, and the sampling result is read. If the result is low, the flip point is to the right of 128, and L is updated to 128; if the result is high, the flip point is to the left of 128, and U is updated to 128. The second iteration halves the search step size to 64, and the new phase control word is set to take L plus 64 if the previous result was low, and take U minus 64 if the previous result was high. The sampling result is read again, and the above judgment is repeated. The third iteration halves the step size to 32, the fourth to 16, the fifth to 8, the sixth to 4, the seventh to 2, and the eighth to 1. If the sampling result has not flipped by the eighth iteration, the current phase control word is used as the lock value. It can be seen that only 8 iterations are needed to complete the full binary search of 256 discrete phase control words, which is 32 times more efficient than the 256 iterations required for successive traversals.

[0064] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on the present invention.

[0065] Before successively adjusting the phase control word using the binary search algorithm, the method further includes: Based on the operating conditions of the high-speed transmitter, the historical phase control word library is queried to obtain a historical locked phase control word that matches the current operating conditions as the initial phase control word; The historical phase control word library contains the correspondence between the working conditions and the locked phase control words during each calibration.

[0066] The operating conditions include the current temperature, operating voltage, and the target transmission rate of the high-speed transmitter. When a historical locked phase control word with a deviation from the current working conditions within a preset tolerance range is found, the historical locked phase control word is used as the initial value of the binary search algorithm, and a local search is performed starting from the initial value.

[0067] Based on the binary search algorithm as the core calibration mechanism, this embodiment of the invention also introduces an acceleration strategy based on historical data reuse to further shorten calibration time and reduce calibration power consumption. The core idea of ​​this strategy is that the changes in the operating conditions of the transmitter in actual operation often occur gradually within a certain range, rather than jumping from one extreme state to another. Therefore, the locked phase control word obtained from each calibration has significant reference value for the optimal value under the current operating conditions.

[0068] In this embodiment of the invention, a historical phase control word library is pre-established and continuously maintained in a non-volatile memory or a permanently stored on-chip register group inside the transmitter. This non-volatile memory can be EEPROM or flash memory. The core data structure of this historical phase control word library is a multi-dimensional index table, where each record contains at least four fields: first, a temperature field, the chip junction temperature value read in real time by the on-chip temperature sensor, in degrees Celsius; second, a voltage field, the current operating voltage value measured in real time by the on-chip voltage detection circuit, in volts; third, a rate field, i.e., the target transmission rate value of the high-speed transmitter, in bits per second; and fourth, the corresponding locked phase control word, i.e., the phase control word value finally locked and stored at that calibration moment.

[0069] Specifically, after each calibration process is successfully completed and the phase control word is locked, the calibration state machine automatically triggers a record saving operation. This operation first reads the current chip junction temperature through the on-chip temperature sensor, reads the current operating voltage through the on-chip voltage detection circuit, and obtains the current rate configuration parameters from the configuration register. Then, these three operating condition parameters are bound to the just-locked phase control word to form a complete record entry, which is stored in the historical phase control word library according to a certain index order, such as a hierarchical organization method with temperature and voltage as two-dimensional indexes and rate as a first-level index. As the transmitter is repeatedly calibrated and operated under various operating conditions for a long time, this historical phase control word library gradually accumulates a rich dataset covering different temperature points, different voltage points, and different rate points, and its reference value continues to increase with the increase in data volume. These temperature points include, for example, -40 degrees Celsius, 0 degrees Celsius, 25 degrees Celsius, 85 degrees Celsius, and 125 degrees Celsius; voltage points include, for example, 90%, 100%, and 110% of the nominal voltage; and speed points include, for example, 1.25Gbps, 10.3125Gbps, and 25.78125Gbps.

[0070] When the transmitter restarts calibration, such as during electrical initialization, rate switching, or periodic timing recalibration, the calibration state machine performs historical data lookup and reuse according to the following steps.

[0071] First, the calibration state machine reads the current chip junction temperature, denoted as T, through the on-chip temperature sensor; reads the current operating voltage, denoted as V, through the on-chip voltage detection circuit; and obtains the currently set target transmission rate, denoted as R, through the system configuration register.

[0072] The calibration state machine uses the three parameters T, V, and R as a joint index to traverse all historical records in the historical phase control character set, searching for a record that matches the current operating conditions. A match is defined as the deviation between the historical operating conditions and the current operating conditions being within a preset tolerance range. Specifically, temperature deviation is within ±5 degrees Celsius, or more strictly within ±3 degrees Celsius; voltage deviation is within ±5%, or more strictly within ±3%; and speed, since it is usually a discrete value specified by a standard protocol, requires complete consistency without tolerance.

[0073] If a historical record satisfying the above tolerance conditions is found, in actual engineering, due to the continuous variation of temperature and voltage, there are often multiple candidate records that meet the conditions. In this case, the calibration state machine can select the record with the smallest deviation, or take the average value of the phase control words corresponding to multiple records as the final initial value. The calibration state machine then extracts the corresponding locked phase control word from the historical record and uses it as the initial phase control word for this binary search algorithm.

[0074] Since the initial value is a valid value obtained from actual measurement and locking in historical records, its value is very close to the true optimal value under the current working conditions. Especially when the deviation between the current working conditions and the working conditions recorded in the historical records is extremely small, the initial value is almost the optimal value itself. Therefore, the subsequent binary search does not need to start from the midpoint of the entire adjustable range, but directly starts from this historical value for a local search. That is, it only needs to make fine adjustments within a small interval near the historical value to converge to the precise optimal value under the current conditions. This small interval can be, for example, centered on the historical value and offset by several search steps (positive or negative).

[0075] If no historical record matching the current operating conditions is found in the historical phase control word library—for example, when the transmitter is powered on for the first time at a new temperature or started under a voltage condition never used before—the calibration state machine automatically reverts to the default global search mode, which performs a standard binary search starting from the midpoint of the entire adjustable range of the phase control word. Simultaneously, the locked phase control word obtained after this calibration is bound to the current operating conditions and stored as a new historical record in the historical phase control word library for reuse in future calibrations.

[0076] For example, when the transmitter is first powered on under operating conditions of 85 degrees Celsius, 1.0 volt, and 10.3125 Gbps, the historical phase control word library is empty. The calibration state machine starts searching from the midpoint of the entire range, taking 8 iterations to complete the lock, and records the locked phase control word under this condition as 180 in the historical library. Several hours later, the transmitter is powered on again due to service requirements. At this time, the temperature has slightly changed to 87 degrees Celsius, the voltage remains 1.0 volt, and the rate remains 10.3125 Gbps. The calibration state machine queries the historical library and finds a record corresponding to 85 degrees Celsius, 1.0 volt, 10.3125 Gbps, with a lock value of 180. The temperature deviation of 2 degrees Celsius is within the tolerance range, so 180 is directly used as the initial value for this search. Since the actual inversion point may shift slightly to around 182 due to temperature drift, the binary search only needs to perform a small number of iterations from 180 outwards, such as 2 to 3 iterations, to converge to 182. This reduces the calibration time by about 65% compared to the 8 iterations required for the initial calibration. With the continuous accumulation of data in the historical database, the transmitter calibration under most operating conditions can achieve a fast response with immediate query results and immediate locking for fine-tuning.

[0077] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on the present invention.

[0078] This invention achieves single-step conversion of phase relationship to digital level using a D flip-flop sampling structure, with significantly lower area and power consumption compared to traditional analog detection schemes. At B-bit control word precision, a binary search algorithm converges to the optimal phase control word in at most B iterations, resulting in an exponentially higher search efficiency than exhaustive search. The step size is halved with each iteration, balancing speed and accuracy, while boundary handling ensures deterministic convergence under all conditions. By utilizing a historical phase control word library, the search scope is compressed from global to local during operating condition matching, drastically reducing the number of iterations. Furthermore, the historical library becomes faster with each use and is continuously reused across power-on cycles. The D flip-flop sampling structure, binary search algorithm, historical phase control word library, and its query and reuse mechanism together constitute a complete timing calibration closed-loop scheme that is high-precision, fast-converging, low-overhead, and possesses self-learning capabilities.

[0079] S500: Based on the locked current phase control word and the sampling clock signal, the second parallel-to-serial conversion of the medium-speed data signal is performed through the second parallel-to-serial circuit to output a high-speed serial data signal.

[0080] In a two-stage parallel-to-serial converter architecture, the second stage performs the final conversion function, transforming medium-speed data signals into high-speed serial data output. However, in traditional designs, the sampling clock used by the second-stage parallel-to-serial converter often lacks precise phase alignment with the input medium-speed data signal. The edge of the sampling clock may fall near the transition edge of a data bit rather than the center of the effective window, causing the second-stage parallel-to-serial converter to read unstable transition levels during sampling, resulting in output data errors. Although this problem can be mitigated by reserving timing margins in the front-end design, as transmission rates continue to increase to Gbps and even tens of Gbps, the unit bit interval is compressed to the order of hundreds or even tens of picoseconds, making the traditional approach of reserving timing margins insufficient to meet accuracy requirements. Therefore, ensuring that the sampling time of the second-stage parallel-to-serial converter is precisely aligned with the center of the effective window of the medium-speed data signal, thereby obtaining error-free high-speed serial data at the final output, becomes a key technical problem that needs to be solved in the entire two-stage parallel-to-serial converter architecture.

[0081] In this embodiment of the invention, after locking the current phase control word, the sampling clock signal corresponding to the locked phase control word is used to perform a second-stage parallel-to-serial conversion on the medium-speed data signal through a second parallel-to-serial conversion circuit, and finally outputs a high-speed serial data signal.

[0082] Specifically, the clock input of the second parallel-to-serial converter receives the sampling clock signal, which is the sampling clock signal whose phase has been locked to the optimal value after the aforementioned calibration process. The data input of the second parallel-to-serial converter receives the medium-speed data signal output from the first parallel-to-serial converter. Within each sampling clock cycle, the second parallel-to-serial converter outputs each bit of the medium-speed data signal arriving sequentially, following the same bit order as the first-stage parallel-to-serial conversion, to form the final high-speed serial data signal.

[0083] It should be noted that the output data rate of the second parallel-to-serial converter is numerically equal to the frequency of the sampling clock signal. Since the frequency of the sampling clock signal is set to f... d / N, while the rate of a medium-speed data signal is numerically equal to f. d / N, therefore, the second-stage parallel-to-serial conversion essentially involves, under the clock signal control, directly transmitting a relatively low-speed, medium-speed data signal to the output, forming a signal with a speed equal to f. d High-speed serial data signal.

[0084] Furthermore, at the circuit implementation level, the second parallel-to-serial converter can employ various structures. In lower-speed applications, a simple 2:1 multiplexer cascade structure or shift register structure can be used, extracting one bit from the serial input data stream and sending it to the output in each sampling clock cycle. In ultra-high-speed applications, a half-speed or quarter-speed architecture can be used, reducing the operating frequency of the internal flip-flops and multiplexers to half or a quarter of the data rate through multi-phase clocking, thereby alleviating the timing convergence pressure and power consumption overhead caused by high-speed clocks. Regardless of the specific architecture used, its core function is to completely transmit the medium-speed data signal to the transmitter output under the control of the sampling clock signal.

[0085] Finally, regarding the data path connection, the input data path of the second parallel-to-serial converter is the medium-speed data signal transmission path. The propagation delay of this transmission path has been accurately replicated by the equivalent delay circuit and compensated for through the calibration loop. Therefore, when the second parallel-to-serial converter samples the medium-speed data signal at the edge of the sampling clock signal, the sampling time is precisely aligned with the center of the effective window of the medium-speed data signal, thereby ensuring the data reliability of the second-stage parallel-to-serial conversion.

[0086] For example, suppose the sampling clock signal frequency is 644.53125MHz, and the medium-speed data signal is the serial data stream expanded from the 16-bit parallel data output by the first parallel-to-serial circuit, with a rate of 644.53125Mbps. The second parallel-to-serial circuit uses this 644.53125MHz sampling clock signal as its cycle, reading one bit from the input medium-speed data signal and outputting it to the transmitter output in each clock cycle. Since each bit cycle of the medium-speed data signal corresponds perfectly in time to each cycle of the sampling clock signal, the second parallel-to-serial circuit completes the transfer of exactly one bit in each clock cycle. After continuous transmission, each bit in the medium-speed data signal is output sequentially, ultimately forming a high-speed serial data signal with a rate of 16 × 644.53125Mbps = 10.3125Gbps at the transmitter output, which is the target transmission rate.

[0087] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on the present invention.

[0088] This invention utilizes the sampling clock signal corresponding to the locked optimal phase control word to drive the second parallel-to-serial conversion circuit to perform the final parallel-to-serial conversion on the medium-speed data signal. Since the phase of this sampling clock signal has been precisely adjusted through a complete forward calibration closed loop, its edge is precisely aligned with the center of the effective window of the medium-speed data signal. Therefore, the second-stage parallel-to-serial conversion can read each data bit at the optimal sampling time, avoiding setup or hold time violations caused by the sampling clock edge deviating from the effective data window. Under normal operating conditions after calibration, each bit of the high-speed serial data signal output by the second parallel-to-serial conversion circuit has sufficient timing margin, maximizing the horizontal opening of the transmitter's output eye diagram and thus minimizing the system bit error rate. Simultaneously, because the aforementioned calibration mechanism can track changes in process angle, voltage, and temperature in real time, the optimal sampling time of the second-stage parallel-to-serial conversion can automatically follow throughout the chip's entire lifecycle, without manual intervention or off-chip debugging, significantly improving the long-term reliability and mass production consistency of the transmitter in complex operating environments.

[0089] In summary, the embodiments of the present invention have at least the following technical effects: This invention achieves adaptive matching of the division ratio as the target data bit width changes by using the ratio of the high-speed clock frequency to the target transmission rate as the division coefficient, eliminating the frequency mismatch problem during multi-protocol switching when the division ratio is fixed. Through two-stage adjustment of coarse selection and fine interpolation in the phase interpolation module, the phase adjustment resolution is refined to the sub-picosecond level, providing a highly linear phase adjustment method for closed-loop search. By buffering the sampling clock and using it as the data clock signal for synchronous output with medium-speed data, a definite and traceable phase relationship between data and clock is established. By constructing an equivalent delay circuit that is completely identical to the data path in terms of logic gate level, wiring topology, and load conditions, accurate reproduction of data path delay is achieved, allowing real-time acquisition of delay information without off-chip measurement. By employing a D-flip-flop cross-sampling structure and a binary search algorithm, single-step conversion of phase relationships to digital levels and rapid convergence within at most B iterations at B-bit precision are achieved, resulting in an exponential improvement in search efficiency compared to exhaustive search. Combined with a historical phase control word library containing three-dimensional operating conditions (temperature, voltage, and speed), the search range is compressed from global to local, reducing the number of iterations by 50% to over 70%. Furthermore, historical data is continuously reused across power-on cycles, and the calibration speed increases with the number of uses. Finally, the locked sampling clock phase ensures that the sampling edge of the second parallel-to-serial converter is precisely aligned with the center of the effective window of the medium-speed data signal, avoiding setup or hold time violations.

[0090] In summary, this invention solves the technical problem of sampling time deviating from the center of the effective data window caused by frequency mismatch, phase coarse adjustment, unmeasurable path delay, and changes in operating conditions between clocks and data at each stage in a two-stage parallel-to-serial conversion architecture of a high-speed transmitter.

[0091] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0092] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0093] This specification and accompanying drawings are merely illustrative examples of the invention and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its scope. Therefore, if such modifications and modifications fall within the scope of the invention and its equivalents, the invention is intended to include these modifications and modifications.

Claims

1. A timing calibration method for the critical path of a high-speed transmitter, characterized in that, The method includes: The target transmission rate of the high-speed transmitter is obtained, the frequency division coefficient is determined based on the target transmission rate, the input high-speed clock signal is frequency divided to obtain the frequency-divided clock signal, and the frequency-divided clock signal is input to the phase interpolation module for phase adjustment, and the sampling clock signal is output. Based on the sampling clock signal, the parallel data in the digital module is sampled and the first-stage parallel-to-serial conversion is performed to output a medium-speed data signal and the corresponding data clock signal. Construct an equivalent delay circuit with the same data path as the medium-speed data signal from the output of the first parallel-to-serial circuit to the input of the second parallel-to-serial circuit, receive the data clock signal and output an equivalent clock signal; The high-speed clock signal is sampled using the equivalent clock signal to obtain the sampling result, and the phase control word of the phase interpolation module is iteratively adjusted according to the sampling result until the sampling result undergoes a preset state flip, and the current phase control word is locked. Based on the locked current phase control word and the sampling clock signal, the medium-speed data signal is converted into a second-stage parallel-to-serial signal through the second parallel-to-serial circuit, and a high-speed serial data signal is output.

2. The timing calibration method for the critical path of a high-speed transmitter according to claim 1, characterized in that, Obtain the target transmission rate of the high-speed transmitter, determine the frequency division coefficient based on the target transmission rate, and perform frequency division processing on the input high-speed clock signal to obtain a frequency-divided clock signal, including: Obtain the frequency of the high-speed clock signal; The ratio of the frequency of the high-speed clock signal to the data bit width of the target transmission rate is used as the frequency division coefficient.

3. The timing calibration method for the critical path of a high-speed transmitter according to claim 2, characterized in that, The frequency-divided clock signal is input to the phase interpolation module for phase adjustment, and a sampling clock signal is output, including: Based on the registers of the digital module, a phase control word is output to the phase interpolation module; The phase interpolation module selects a target phase from multiple equally spaced phases of the frequency division clock signal according to the phase control word, and outputs the sampled clock signal by weighting adjacent phases.

4. The timing calibration method for the critical path of a high-speed transmitter according to claim 1, characterized in that, Based on the sampling clock signal, the parallel data in the digital module is sampled and the first-stage parallel-to-serial conversion is performed to output a medium-speed data signal and a corresponding data clock signal, including: The first parallel-to-serial converter uses the sampling clock signal as the sampling clock to sample the N-bit parallel data output by the digital module. The N-bit parallel data is output bit by bit in a predetermined order to form a serial medium-speed data signal, and the sampling clock signal is buffered and output as a data clock signal. The rate of the medium-speed data signal is N times that of the parallel data.

5. The timing calibration method for the critical path of a high-speed transmitter according to claim 1, characterized in that, The equivalent delay circuit is a replication circuit of the data path between the output of the first parallel-to-serial circuit and the input of the second parallel-to-serial circuit. The equivalent delay circuit has the same number of logic gates, wiring topology and load conditions as the data path. The equivalent delay circuit receives the data clock signal and outputs the delayed equivalent clock signal.

6. The timing calibration method for the critical path of a high-speed transmitter according to claim 1, characterized in that, The high-speed clock signal is sampled using the equivalent clock signal to obtain the sampling result, including: The equivalent clock signal is used as the clock input signal of the D flip-flop, and the high-speed clock signal is used as the data input signal of the D flip-flop. The D flip-flop samples the current level of the high-speed clock signal on the rising edge of the equivalent clock signal and outputs the sampling result.

7. The timing calibration method for the critical path of a high-speed transmitter according to claim 6, characterized in that, The phase control word of the phase interpolation module is iteratively adjusted based on the sampling results until the sampling results undergo a preset state flip, and the current phase control word is locked, including: The phase control word is adjusted successively using a binary search algorithm. After each adjustment, the updated phase control word is output to the phase interpolation module, and the current sampling result is obtained. If the current sampling result does not result in the preset state flip, the next search direction and search step size are determined based on the current sampling result. The preset state flip is the level of the output terminal of the D flip-flop flipping from low level to high level or from high level to low level. The search step size is halved with each iteration until the sampling result is flipped by the preset state, and the current phase control word is locked. If the search step size reaches the minimum adjustment granularity of the phase interpolation module and the sampling result is still not flipped, the phase control word corresponding to the current sampling result is used as the lock value.

8. The timing calibration method for the critical path of a high-speed transmitter according to claim 1, characterized in that, Before successively adjusting the phase control word using the binary search algorithm, the method further includes: Based on the operating conditions of the high-speed transmitter, the historical phase control word library is queried to obtain a historical locked phase control word that matches the current operating conditions as the initial phase control word; The historical phase control word library contains the correspondence between the working conditions and the locked phase control words during each calibration.

9. The timing calibration method for the critical path of a high-speed transmitter according to claim 8, characterized in that, The operating conditions include the current temperature, operating voltage, and the target transmission rate of the high-speed transmitter. When a historical locked phase control word whose deviation from the current working conditions is within a preset tolerance range is found, the historical locked phase control word is used as the initial value of the binary search algorithm, and a local search is performed starting from the initial value.

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