A high-density data transmission clock synchronization method for CPO optoelectronic interconnection

Abstract

The application discloses a high-density data transmission clock synchronization method for CPO optoelectronic interconnection and relates to the technical field of data transmission clock synchronization, and comprises the following steps: acquiring CPO optoelectronic interconnection synchronization configuration data, dividing a clock synchronization group and generating a clock synchronization basic record; sending a synchronization training block, completing receiver group phase-locked loop locking and initial sampling phase determination of each data channel; matching the synchronization training block in the group, measuring time difference of each data channel, and adjusting a channel alignment buffer, an intra-word symbol selection position and a phase interpolator according to a fixed channel phase reference; re-measuring the phase of each data channel during payload transmission, updating group clock, clock tree branch or single-channel control parameters according to the phase change result, and performing channel realignment and standby synchronization channel switching. The application unifies a multi-channel phase measurement reference, and improves clock synchronization stability during CPO high-density optoelectronic interconnection operation.

Description

Technical Field

[0001] This invention relates to the field of data transmission clock synchronization technology, and in particular to a high-density data transmission clock synchronization method for CPO optoelectronic interconnects. Background Technology

[0002] As switching chips, computing accelerators, and optical engines move towards co-packaging, CPO optoelectronic interconnects are gradually adopting multi-channel parallel transmission structures to improve data exchange density inside and outside the package. Conventional clock synchronization methods typically involve the transmitter providing a reference clock, the receiver recovering the frequency through a phase-locked loop, and combining training sequences, phase interpolators, and channel alignment buffers to complete multi-channel sampling phase determination and word-level alignment; during operation, the sampling clock is further corrected based on periodic training blocks, temperature, or supply voltage changes.

[0003] However, existing methods still have two limitations: First, group clock locking, initial sampling phase search of each channel, and channel arrival time measurement are usually handled separately, and fixed path difference and operational changes may be measured using different calibers; Second, during operation, fixed-cycle retesting or independent adjustment of a single channel are often used, making it difficult to distinguish between common changes within the group, clock tree branch changes, and single-channel changes, and the connection between control parameter updates and payload transmission is relatively complex. Summary of the Invention

[0004] In view of the problems existing in the above-mentioned methods, the present invention is proposed.

[0005] Therefore, this invention provides a high-density data transmission clock synchronization method for CPO optoelectronic interconnects, which solves the problems of inconsistent multi-channel phase measurement benchmarks and difficulty in graded adjustment of phase changes during operation in CPO high-density optoelectronic interconnects.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] This invention provides a high-density data transmission clock synchronization method for CPO optoelectronic interconnects, comprising: acquiring CPO optoelectronic interconnect synchronization configuration data, dividing clock synchronization groups and generating CPO optoelectronic interconnect clock synchronization basic records; sending synchronization training blocks based on the CPO optoelectronic interconnect clock synchronization basic records, locking the receiving end group phase-locked loop, determining the initial sampling phase of each data channel, and generating CPO optoelectronic interconnect initial synchronization records; matching synchronization training blocks within the group according to the CPO optoelectronic interconnect clock synchronization basic records and CPO optoelectronic interconnect initial synchronization records, measuring the arrival time difference of each data channel, adjusting the channel alignment buffer, intra-word symbol selection position and phase interpolator according to a fixed channel phase reference, and generating CPO optoelectronic interconnect channel phase adjustment records; retesting the phase of each data channel during payload transmission based on the CPO optoelectronic interconnect clock synchronization basic records and CPO optoelectronic interconnect channel phase adjustment records, updating the group clock, clock tree branch or single channel control parameters according to the phase change results, processing channel realignment and primary / backup synchronization channel switching, and generating CPO optoelectronic interconnect operating phase retest records.

[0008] As a preferred embodiment of the high-density data transmission clock synchronization method for CPO optoelectronic interconnects described in this invention, the step of dividing clock synchronization groups and generating basic records for CPO optoelectronic interconnect clock synchronization includes: dividing clock synchronization groups according to the consistency of optical engine affiliation, transmit phase-locked loop, transmit clock division ratio, data baud rate, modulation method, line coding method, forward error correction coding method, receiver group phase-locked loop connection relationship, and phase interpolator input reference; sorting data channels within the group that meet the fixed training sequence detection conditions, determining the main synchronization channel and the backup synchronization channel, and measuring the fixed channel phase reference of each data channel relative to the main synchronization channel.

[0009] As a preferred embodiment of the high-density data transmission clock synchronization method for CPO optoelectronic interconnects described in this invention, the step of recording and transmitting a synchronization training block based on the CPO optoelectronic interconnect clock synchronization, locking the receiver's group phase-locked loop, and determining the initial sampling phase of each data channel includes: the synchronization training block is composed of a protocol-reserved control block; the transmitter repeatedly transmits a fixed training sequence field during the initial synchronization period; the receiver extracts the signal edge from the main synchronization channel and completes the frequency locking and phase locking of the receiver's group phase-locked loop; if the main synchronization channel fails to complete locking within the corresponding locking allowable time, the group phase-locked loop frequency control word is maintained or restored according to the frequency locking result, and the system switches to a backup synchronization channel to continue locking.

[0010] As a preferred embodiment of the high-density data transmission clock synchronization method for CPO optoelectronic interconnects described in this invention, the step of recording and transmitting the synchronization training block based on the CPO optoelectronic interconnect clock synchronization foundation, locking the receiver group phase-locked loop, and determining the initial sampling phase of each data channel includes: after the receiver group phase-locked loop completes locking, scanning the control words of the phase interpolator of each data channel within a unit interval, determining the effective sampling interval based on the number of symbol errors in the fixed training sequence field, the number of missed detections at the specified detection edges, and the synchronization training block type identification result, and selecting the midpoint of the phase of the effective sampling interval as the initial sampling phase of the corresponding data channel.

[0011] As a preferred embodiment of the high-density data transmission clock synchronization method for CPO optoelectronic interconnection described in this invention, the following is included: the matching group synchronization training block measures the arrival time difference of each data channel, and adjusts the channel alignment buffer, the word symbol selection position, and the phase interpolator according to the fixed channel phase reference. The group parallel clock is formed by frequency division of the clock output from the receiving end group phase-locked loop. For the specified detection edge of the same training sequence number, the receiving end records the group parallel clock count value, the position of the symbol corresponding to the specified detection edge in the logical parallel data word, and the signed fine time difference relative to the main synchronization channel. The current arrival time difference of each data channel relative to the main synchronization channel is calculated based on the three.

[0012] As a preferred embodiment of the high-density data transmission clock synchronization method for CPO optoelectronic interconnects described in this invention, the following is included: the synchronization training block within the matching group measures the arrival time difference of each data channel, and adjusts the channel alignment buffer, intra-word symbol selection position, and phase interpolator according to the fixed channel phase reference. This includes: the fixed channel phase reference and the current arrival time difference are formed using the same specified detection edge and measurement method; when the main synchronization channel used is inconsistent with the main synchronization channel used in factory calibration, the fixed channel phase reference of each data channel relative to the current main synchronization channel is calculated based on the fixed channel phase reference of the backup synchronization channel relative to the factory calibration main synchronization channel.

[0013] As a preferred embodiment of the high-density data transmission clock synchronization method for CPO optoelectronic interconnects described in this invention, the following steps are included: The matching group synchronization training block measures the arrival time difference of each data channel. Adjusting the channel alignment buffer, intra-word symbol selection position, and phase interpolator based on a fixed channel phase reference includes: generating candidate combinations of channel alignment buffer read address offset, intra-word symbol selection position, and phase interpolator control word based on the difference between the current arrival time difference and the fixed channel phase reference; filtering out candidate combinations where the buffer occupancy exceeds the limit, the intra-word symbol selection position exceeds the limit, or the phase interpolator control word exceeds the effective sampling range; writing the selected combination into the working registers of each data channel within the same group's parallel clock boundary; and restoring the control parameters before the update if the remaining phase difference after the updated compensation has not decreased.

[0014] As a preferred embodiment of the high-density data transmission clock synchronization method for CPO optoelectronic interconnection described in this invention, the step of re-measuring the phase of each data channel during payload transmission, updating the group clock, clock tree branch, or single-channel control parameters based on the phase change results, and handling channel realignment and main / backup synchronization channel switching includes: calculating the channel arrival time change of each data channel, the equivalent compensation time formed by the current control parameters, and the remaining phase difference after compensation during payload transmission; calculating the remaining phase margin based on the remaining phase difference after compensation and the allowable remaining phase difference; and determining the transmission time of the synchronization training block based on the channel arrival time change at adjacent re-measuring times and the arrival time changes corresponding to temperature and voltage.

[0015] As a preferred embodiment of the high-density data transmission clock synchronization method for CPO optoelectronic interconnects described in this invention, the following steps are included: re-measuring the phase of each data channel during payload transmission, updating the group clock, clock tree branch, or single-channel control parameters based on the phase change results, and handling channel realignment and main / backup synchronization channel switching: determining the actual arrival phase change of each data channel relative to the group clock based on the phase change of the main synchronization channel relative to the group clock and the channel arrival time change of each data channel; updating the group clock phase offset control word when the actual arrival phase change direction of the data channels within the group is consistent and the discrete range meets the group-level adjustment conditions; updating the corresponding branch delay control word when the data channels within the clock tree branch meet the branch-level adjustment conditions; updating the corresponding phase interpolator control word for the remaining data channels; and confirming the control parameters based on the updated and compensated remaining phase difference.

[0016] As a preferred embodiment of the high-density data transmission clock synchronization method for CPO optoelectronic interconnection described in this invention, the following steps are included: during payload transmission, the phase of each data channel is remeasured, and the group clock, clock tree branch, or single-channel control parameters are updated based on the phase change results. The processing of channel realignment and switching between primary and backup synchronization channels includes: when the remaining phase difference after compensation reaches one unit interval, the phase interpolator control word exceeds the effective sampling range, or the channel alignment buffer occupancy reaches the allowable boundary, the payload of the clock synchronization group is paused at the forward error correction codeword boundary, and channel alignment is re-executed; when the primary synchronization channel fails, the phase difference between the backup synchronization channel reference edge and the holding state group clock is measured, and the reference input is switched when the phase difference meets the no-glitch switching condition; otherwise, the payload is shut down and the receiver group phase-locked loop is re-executed.

[0017] The beneficial effects of this invention are as follows: By matching the synchronous training block within the group, the arrival time difference of the data channel is measured based on the group parallel clock count value, symbol position, and signed fine time difference. Combined with the fixed channel phase reference, the channel alignment buffer, the intra-word symbol selection position, and the phase interpolator are adjusted to achieve multi-channel phase correction under a unified measurement reference. By re-measuring the data channel phase during payload transmission, updating the control parameters according to the phase changes within the group, clock tree branches, or single channels, and handling channel realignment and switching between primary and backup synchronous channels, hierarchical synchronization maintenance is achieved, thereby improving the clock synchronization stability of CPO optoelectronic interconnects. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a high-density data transmission clock synchronization method for CPO optoelectronic interconnects.

[0020] Figure 2 Flowchart for synchronous training block transmission and initial sampling phase determination.

[0021] Figure 3 Flowchart for measuring data channel arrival time and adjusting channel alignment.

[0022] Figure 4 This is a flowchart of phase remeasurement and synchronization control parameter adjustment during payload transmission.

[0023] Figure 5 A comparison chart of the absolute error in measuring the change in channel arrival time under different disturbance scenarios.

[0024] Figure 6 A comparison chart showing the normalized results of the remaining phase difference after compensation under different phase change sources. Detailed Implementation

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0027] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0028] Reference Figures 1-6 This is one embodiment of the present invention, which provides a high-density data transmission clock synchronization method for CPO optoelectronic interconnects, comprising the following steps:

[0029] S1. Obtain CPO optoelectronic interconnect synchronization configuration data, divide clock synchronization groups, and generate CPO optoelectronic interconnect clock synchronization basic records.

[0030] Acquiring CPO optoelectronic interconnect synchronization configuration data includes Co-Packaged Optics (CPO) interface configuration data, transmit clock configuration data, receive clock configuration data, data transmission configuration data, package connection data, power supply area and temperature detection location data, and factory synchronization calibration data. Verify the optoelectronic channel correspondence between the transmit end data channel and the receive end data channel. Divide the clock synchronization group according to the transmit reference clock relationship, the receive end group phase-locked loop connection relationship, and the optical engine affiliation. Determine the main synchronization channel, backup synchronization channel, fixed channel phase reference, allowable remaining phase difference, lock judgment parameters, phase measurement parameters, and channel alignment adjustment parameters. Generate the CPO optoelectronic interconnect clock synchronization basic record.

[0031] CPO interface configuration data is read from the interface configuration register, including the interface number, transmitter chip number, receiver chip number, optical engine number, data channel enable status, and transmission direction. Connections between the transmitter and receiver are established according to the transmission direction, and data channels for different transmission directions are grouped.

[0032] The transmit clock configuration data is read from the transmit-side PLL, clock divider, and transmit serializer configuration registers, including the transmit PLL number and output frequency, transmit reference clock source, transmit clock division ratio, transmit reference clock counter number, and transmit serializer clock input number. The receive clock configuration data is read from the receive-side MLL, phase interpolator, and receive deserializer configuration registers, including the receive-side MLL number, MLL frequency capture range, MLL phase detection range, phase interpolator number, phase interpolator control word range, phase interpolator minimum adjustment step, time-to-digital converter measurement range, and maximum measurement error. The receive-side MLL provides a common frequency reference to all data channels within the group, and each data channel forms its sampling clock through its respective phase interpolator.

[0033] Data transmission configuration data includes the transmit logical channel number, transmit physical channel number, receive physical channel number, receive logical channel number, channel rearrangement relationship, data baud rate, modulation scheme, line coding scheme, scrambling scheme, forward error correction coding scheme, receive deserializer parallel width, channel alignment buffer storage width, storage depth, width conversion relationship, and protocol maintenance time slot position. Under two-level amplitude modulation, one modulation symbol carries one bit; under four-level pulse amplitude modulation, one modulation symbol carries two bits. The unit interval is determined according to the duration of one modulation symbol.

[0034] The encapsulated connection data includes the correspondences between the transmitter serializer output and the optical modulator driver, the optical modulator and the optical waveguide, the optical waveguide and the photodetector, the photodetector and the transimpedance amplifier, and the transimpedance amplifier and the receiver deserializer. Matching is performed sequentially according to the transmitter logical channel number, transmitter physical channel number, receiver physical channel number, and receiver logical channel number. When the physical channel order differs from the logical channel order, a correspondence is established based on the channel rearrangement. If any level of connection number is missing, there is a one-to-many or many-to-one connection, or a unique correspondence cannot be established, the corresponding data channel is marked as having an abnormal connection relationship and will not participate in the clock synchronization group division.

[0035] Read power supply area data and temperature detection location data to determine the power supply domain number, voltage monitoring terminal number, temperature sensor number, clock tree branch number, and temperature detection area number corresponding to each data channel. When one data channel corresponds to multiple temperature sensors, record the number of each sensor.

[0036] Data channels with normal connectivity and enabled status are assigned to the same clock synchronization group if they meet the following conditions: the transmitting optical modulator and the receiving photodetector belong to the same optical engine channel group; the transmitting clock is provided by the same transmitting phase-locked loop (PLL); the transmitting clock division ratio, data baud rate, modulation scheme, line coding scheme, and forward error correction coding scheme are the same; the corresponding receiving deserializer can be connected to the same receiving end group PLL; and the corresponding phase interpolator uses the output clock of the same receiving end group PLL as its input reference. If any condition is inconsistent, the data channels are assigned to different clock synchronization groups. If any configuration field involved in the grouping changes, the original clock synchronization group number is discontinued, and the data is regrouped.

[0037] Calculate the unit interval based on the data baud rate: ;

[0038] in, The unit interval representing a modulation symbol; This represents the data baud rate. Data channels within the same group have the same data baud rate and unit interval. The time corresponding to a channel alignment buffer storage unit is obtained by multiplying the number of modulation symbols it contains by the unit interval.

[0039] Read the factory synchronization calibration data, including the fixed training sequence field, the number of synchronization training block verification errors, the group phase-locked loop establishment time, the phase measurement range, the photoelectric path insertion loss, the number of signal loss times, and the continuous effective reception time. Filter out data channels where the fixed transition field cannot be detected, the phase measurement result exceeds the measurement range of the time-to-digital converter, the phase interpolator cannot form a continuous effective sampling interval, the received optical power exceeds the receiver's allowable range, the signal loss indication is valid, or the calibration data is missing.

[0040] The remaining data channels are sorted in the following order: number of synchronization training block verification errors (from lowest to highest), number of signal losses (from lowest to highest), phase measurement range (from lowest to highest), group phase-locked loop (group lock) establishment time (from lowest to highest), photoelectric path insertion loss (from lowest to highest), and continuous effective reception time (from longest to shortest). If the preceding item is different, the following item is not compared; if all are the same, they are sorted in ascending order by data channel number. The data channel ranked first is designated as the primary synchronization channel, and the data channel ranked second is designated as the backup synchronization channel. When there is only one valid candidate channel, only the primary synchronization channel is recorded, and the backup synchronization channel is marked as unconfigured. If the primary synchronization channel fails to complete group clock locking during initial synchronization, the corresponding clock synchronization group locking is directly marked as failed. If the primary synchronization channel fails during payload transmission, the payload is shut down and group clock locking is re-executed. When there are zero valid candidate channels, the corresponding clock synchronization group is marked as having a synchronization configuration error.

[0041] The synchronization training block adopts the protocol-reserved control block format. After the payload data completes scrambling, line coding, and forward error correction coding, the training block insertion circuit, located between the forward error correction coding output and the channel allocation circuit input, replaces the corresponding control block position with the synchronization training block during the initial synchronization period or protocol maintenance time slot. The synchronization training block is not part of the payload forward error correction codeword; the receiver sends it into the synchronization processing path based on the control block type. The synchronization training block includes a fixed training sequence field, clock synchronization group number, data channel number, training sequence number, synchronization transmission count value, and a check field. The fixed training sequence field is used for group clock locking and phase measurement, while the remaining fields are used to match synchronization training blocks transmitted in the same round.

[0042] Under factory calibration conditions, each power supply domain is set to its rated voltage, and the temperature is set to the ambient temperature test point used for chip electrical characteristic testing. The transmitting end triggers each data channel in the group to send a synchronization training block with the same training sequence number and synchronization transmission count value through the same transmission reference clock counter. When the transmission reference clock counter of each transmission queue reaches the synchronization transmission count value, the synchronization training block is sent to the corresponding gearbox. The receiving end scans the control word range of each data channel phase interpolator, extracts the control word interval in which the fixed transition field is continuously and correctly received, and selects the midpoint of this interval as the calibration sampling control word.

[0043] The calibration sampling control word reads the specified detection edges of the fixed transition fields of each data channel under the same training sequence number. The arrival time difference of each data channel relative to the main synchronization channel is measured through a time-to-digital converter circuit. The phase reference of the main synchronization channel relative to itself is recorded as zero. Each data channel is continuously measured according to the number of phase calibration measurements. Measurement values ​​corresponding to verification errors, signal loss, and overflow / underflow of the time-to-digital converter circuit are deleted. The remaining measurement values ​​are sorted and the median is taken as the fixed channel phase reference. If the number of valid measurement values ​​does not reach the number of phase calibration measurements, the fixed channel phase reference calibration is marked as failed. The fixed channel phase reference includes the fixed time difference generated by the transmitting digital processing, serializer, optical modulator, optical waveguide, photodetector, receiving amplifier circuit, and fixed transition field detection path.

[0044] The time-to-digital converter (TD-SCDMA) circuit is used to measure the signed fine time difference between the data channel and the main synchronization channel at specified detection edges. The receiver first determines the coarse arrival time difference, consisting of integer parallel clock cycles and integer unit intervals, based on the difference in the group parallel clock counts and the sign position difference within the logical parallel data word corresponding to the same synchronization training block. Then, the coarse arrival time difference is subtracted from the total arrival time difference of the specified detection edges to obtain the fine time difference to be measured, which is less than one unit interval. This fine time difference is then measured by the TD-SCDMA circuit. If the fine time difference to be measured exceeds the measurement range of the TD-SCDMA circuit, the synchronization training block matching relationship, the group parallel clock counts, and the sign position within the logical parallel data word are re-verified. If the measurement range is still exceeded after verification, the corresponding data channel is marked as having insufficient fine phase measurement range.

[0045] The channel alignment buffer read address adjustment should be reserved after the current arrival time difference measurement is completed. It is used to compensate for the channel arrival time variation together with the in-word symbol selection position and the phase interpolator control word. It should not be written into the time-to-digital converter circuit measurement range processing procedure.

[0046] Based on the effective eye diagram horizontal opening obtained for each data channel under the target bit error rate, specified received optical power, and measurement bandwidth, calculate the allowable remaining phase difference: ;

[0047] in, Indicates the first The allowable remaining phase difference of each data channel; Indicates the first The effective eye diagram horizontal opening of each data channel; This indicates the maximum measurement error of the corresponding time-to-digital converter circuit; This indicates the maximum phase adjustment time between adjacent control words of the corresponding phase interpolator; This indicates the sampling time retained by the corresponding receiving sampler; Indicates the data channel number.

[0048] The target bit error rate is read from the link acceptance parameters in the CPO optoelectronic interconnect synchronization configuration data, and determined based on the modulation scheme, line coding scheme, and forward error correction coding scheme used. Its value range is [amount]% of the bit error rate before forward error correction decoding. to The specified received optical power is determined based on the minimum output optical power of the transmitter, the maximum optical path loss within the package, and the receiver sensitivity. The receiver sensitivity is taken to be within a range three decibels higher than the actual receiver sensitivity, and the lower of these ranges is used to complete the effective eye diagram horizontal aperture measurement. The measurement bandwidth is determined based on the data channel baud rate and the three decibels bandwidth of the receiver front end, ranging from one-half to three-quarters of the data channel baud rate, but not exceeding the calibration bandwidth of the eye diagram measurement circuit. The target bit error rate, specified received optical power, and measurement bandwidth remain constant during measurements of each data channel within the same clock synchronization group, and the specific values ​​are recorded in the CPO optoelectronic interconnect clock synchronization baseline record.

[0049] The effective eye diagram horizontal opening is determined by the bathtub curve formed by the receiver sampler gradually changing the sampling phase within a unit interval. The time width between the corresponding sampling phases when the bit error rate on both sides of the bathtub curve reaches the target bit error rate is taken. The measurement results include transmit clock jitter, receive clock jitter, and receive front-end noise. When the remaining phase difference is not greater than zero, the corresponding data channel is marked as having insufficient sampling phase margin and is not included in the selection of the primary or backup synchronization channel.

[0050] The read channel alignment buffer storage depth, the number of modulation symbols contained in each storage cell, the intra-word symbol selection range, the phase interpolator control word range, and the phase interpolator minimum adjustment step are used to calculate the buffer read address adjustment range, intra-word symbol selection adjustment range, and phase interpolator adjustment range, respectively. The sum of these three is taken as the total phase adjustment range for a single channel. If the total phase adjustment range for a single channel is less than the sum of the absolute value of the fixed channel phase reference and the maximum calibrated phase change within the chip's allowable temperature and voltage range, the corresponding data channel is marked as having insufficient phase adjustment range. If any data channel within the group forms the aforementioned abnormal flag, a valid clock synchronization group configuration is not generated.

[0051] Based on the PLL capture range, the permissible deviation of the transmitting data baud rate, and the permissible input frequency range of the receiving deserializer, the most restrictive range is taken as the permissible frequency locking range. Based on the half-width of the effective sampling interval of the fixed transition field of the main synchronization channel and half of the linear detection range of the PLL phase detector, the lower of the two is taken as the permissible phase locking range. Through repeated phase-locked loop tests under different temperature, supply voltage, input jitter, and received optical power conditions, the time required for the PLL to maintain a valid lock indication within a specified number of training blocks after satisfying the permissible frequency locking and phase locking ranges is recorded, and the maximum value is taken as the lock confirmation time.

[0052] The maximum initial synchronization time is obtained by subtracting the optical modulator startup time, photodetector settling time, and receiver digital path initialization time from the link recovery time specified in the communication protocol. If the calculated result is not greater than zero, the interface initialization time configuration is marked as abnormal. When reading historical valid synchronization control words, the optical engine number, data channel number, data transmission parameters, MLL version, phase interpolator version, and factory calibration version are compared; if all are consistent, the control word is retained; if any field is inconsistent, the factory calibration control word is used.

[0053] Write the channel connection relationship, grouping results, primary and backup synchronization channel numbers, transmit and receive clock parameters, data transmission parameters, unit interval, fixed channel phase reference, allowable remaining phase difference, lock judgment parameters, phase measurement parameters, channel alignment adjustment parameters, correspondence between power supply area and temperature detection location, and valid historical synchronization control words into the CPO optoelectronic interconnect clock synchronization basic record.

[0054] S2. Based on the CPO optoelectronic interconnect clock synchronization basic record, transmit the synchronization training block, lock the receiving end group phase-locked loop, determine the initial sampling phase of each data channel, and generate the CPO optoelectronic interconnect initial synchronization record.

[0055] Read the CPO optoelectronic interconnect clock synchronization basic record, and obtain the data channel number, main synchronization channel number, backup synchronization channel number, transmit reference clock counter number, receiver group phase-locked loop number, fixed training sequence field format, number of control blocks occupied by synchronization training blocks, frequency locking allowable range, phase locking allowable range, locking confirmation time, main synchronization channel locking allowable time, backup synchronization channel locking allowable time, maximum initial synchronization time, number of phase search sampling training blocks, number of initial phase confirmation training blocks, number of consecutive training block loss confirmations, upper limit of phase search times, control word range of phase interpolator for each data channel, and valid historical synchronization control words based on the clock synchronization group number.

[0056] The allowable locking time for the primary synchronization channel and the allowable locking time for the backup synchronization channel are determined based on the factory synchronization calibration results. The control response reserve time is the sum of the maximum values ​​of the control command write delay, cross-clock domain synchronization delay, reference input gating switching delay, and status read delay within the allowable range of the supply voltage and operating temperature, plus one set of parallel clock cycles, rounded up to an integer multiple of the set of parallel clock cycles. The value ranges from two to sixteen sets of parallel clock cycles. Specific values ​​and test conditions are recorded in the CPO optoelectronic interconnect clock synchronization basic record.

[0057] The minimum number of training symbols is determined based on the allowable bit error rate (BER) and confidence requirements of the training sequence, using a 99% confidence level. It is the minimum number of symbols required to ensure that the upper confidence limit of the BER corresponding to a zero-error measurement result does not exceed the allowable BER of the training sequence, and is not less than the number of symbols contained in a fixed training sequence field, but does not exceed the number of training symbols that can be received within the allowable time of a single phase search. The minimum number of consecutive correct training symbols is the sum of the maximum number of consecutive correct training symbols appearing in the invalid sampling interval during factory synchronization calibration and the number of symbols in a fixed training sequence field; if this number exceeds the number of symbols that can be received within the allowable time of initial phase confirmation, the initial phase confirmation time is marked as insufficient. Both quantities and the corresponding calibration version are written into the CPO optoelectronic interconnect clock synchronization basic record.

[0058] The upper limit for the number of phase searches is determined by subtracting the allowed locking time of the main synchronization channel, the allowed locking time of the backup synchronization channel, the initial phase confirmation time, and the control response reserve time from the maximum initial synchronization time. The remaining time is then divided by the time required for a single phase search and rounded down to the nearest integer. The time required for a single phase search is calculated based on the number of control words to be scanned by the phase interpolator, the number of phase search sampling training blocks, the transmission cycle of the synchronization training blocks, and the control word switching time. If the calculated upper limit for the number of phase searches is less than one, the corresponding clock synchronization group is marked as having insufficient maximum initial synchronization time. The basis for determining the aforementioned parameters, the number of tests, the calculation results, and the parameter versions are recorded in the CPO optoelectronic interconnect clock synchronization basic record.

[0059] When the interface powers on, exits low-power state, the receiver's group-locked loop (MLL) loses lock, or a resynchronization command is received, the current interface configuration and synchronization training block transmission conditions are verified. The transmitter is then controlled to send the synchronization training block, and the frequency and phase locking of the receiver's MLL are performed using the main synchronization channel. If the main synchronization channel fails to lock within its allowed locking time, the system switches to the backup synchronization channel and continues to perform receiver MLL locking within its allowed locking time. If the backup synchronization channel still fails to lock, the current clock synchronization group lock is marked as failed.

[0060] After the receiving end group's phase-locked loop (PLL) completes locking, it scans the phase interpolator control word of each data channel according to the number of phase search sampling training blocks. It verifies the training sequence number, synchronization transmission count, and fixed training sequence field detection results of the synchronization training blocks. Based on the effective sampling interval, it determines the candidate initial sampling phase for each data channel and performs continuous confirmation according to the number of initial phase confirmation training blocks. When the number of consecutively lost synchronization training blocks reaches the required number of consecutive training block loss confirmations, the phase search for the current data channel is re-executed. If the number of phase search attempts reaches the upper limit without obtaining a valid sampling interval, or if the candidate initial sampling phase fails to pass continuous confirmation, the corresponding data channel is marked as having failed to determine the initial sampling phase. After processing each data channel within the group, it records the group clock locking result, the usage result of the main synchronization channel or backup synchronization channel, the effective sampling interval of each data channel, the initial sampling phase, the phase interpolator control word, the number of phase search attempts, and the anomaly flag, generating a CPO optoelectronic interconnect initial synchronization record.

[0061] Read the current interface configuration and data transmission configuration, and compare them with the corresponding fields in the CPO optoelectronic interconnect clock synchronization basic record. If all fields are consistent, the data channel within the group is allowed to be used, the optical modulator and photodetector enter the working state, and the receiving end group phase-locked loop has not formed a hardware fault mark, then shut down the payload output of the corresponding clock synchronization group and enter the synchronization training block transmission process. If any configuration field is inconsistent, terminate this initial synchronization and re-execute the clock synchronization channel grouping and basic parameter determination; if any hardware state is not met, keep the payload output closed and record abnormal data.

[0062] A synchronization training block consists of one or more consecutive protocol-reserved control blocks. The number of control blocks is determined by the total length of the fixed training sequence field, clock synchronization group number field, data channel number field, training sequence number field, synchronization transmission count value field, and cyclic redundancy check field, and is consistent with the number of control blocks occupied by the synchronization training blocks in the basic record. The length of each field is determined by the number of clock synchronization groups allowed to be established by the interface, the number of interface data channels, the number of training blocks that can be transmitted within the maximum initial synchronization time, and the effective bit width of the transmission reference clock counter. The cyclic redundancy check field is calculated according to the generator polynomial, initial value, and field input order specified in the interface protocol.

[0063] The fixed training sequence field uses a fixed symbol arrangement jointly stored by the transmitter and receiver. The maximum number of consecutive identical symbols in the fixed symbol arrangement does not exceed the maximum number of consecutive non-jumping symbols allowed by the receiver's group phase-locked loop. The fixed training sequence field is used to extract signal edges, measure frequency differences, and phase differences; the remaining fields are used to verify the source of the training blocks, the correspondence between data channels, and the transmission order after group clock locking. The training block generation circuit converts each field into a protocol reserved control block that has already completed line coding. After the payload data completes scrambling, line coding, and forward error correction coding, the training block insertion circuit writes the synchronization training block into the initial synchronization period or protocol maintenance time slot between the output of the forward error correction coding and the input of the channel allocation circuit. The synchronization training block is not included in the payload forward error correction codeword. The receiver identifies the protocol reserved control block and sends it to the corresponding processing path before the payload forward error correction decoding.

[0064] The upper limit of the transmit queue waiting time is determined based on the depth of each transmit queue, the current occupancy, the minimum output rate, the number of control blocks occupied by the synchronization training block, and the remaining initial synchronization time. The time required for each transmit queue to release the write space of a complete synchronization training block is calculated, and the maximum value within the group is taken, along with the transmit queue status update cycle and control response reservation time, to serve as the upper limit of the transmit queue waiting time. This time is not less than one transmit queue status update cycle and not greater than the remaining time after deducting the time required for group clock locking, phase search, and initial phase confirmation from the maximum initial synchronization time. The specific value is recorded in the CPO optoelectronic interconnect clock synchronization basic record.

[0065] The frequency measurement time window is determined based on the allowable frequency lock-in range, the specified detection edge frequency, the counter bit width, and the corresponding allowable lock-in time for the synchronization channel. An integer multiple of the fixed training sequence field period is selected as the frequency measurement time window, ensuring that the sum of the edge count quantization error, counter timing error, and edge detection error does not exceed the allowable frequency lock-in range. Furthermore, the detected edge count value and the group-locked loop output clock edge count value must not exceed the counter's upper limit. The sum of the frequency measurement time window and the control response reserved time must not exceed the corresponding allowable lock-in time for the synchronization channel; if no time window meets the conditions, the frequency measurement parameter configuration is marked as abnormal.

[0066] Once the frequency difference enters the allowable range, the current frequency control word is maintained, and the time difference between the detection edge specified in the fixed training sequence field and the output clock edge of the MLL is measured using the MLL phase detector. When the specified detection edge arrives later than the MLL output clock edge, the phase difference is positive; as the MLL phase control word increases, the MLL output clock edge is delayed. When the phase difference exceeds the allowable phase locking range, the phase control word is updated sequentially in the direction that reduces the absolute value of the phase difference. If the phase difference still exceeds the allowable range after the phase control word reaches its upper or lower limit, the main synchronization channel phase locking is marked as failed.

[0067] When the frequency deviation is within the frequency locking allowable range, the phase deviation is within the phase locking allowable range, the fixed training sequence field is detected correctly, the receiver's group-locked loop (PLL) lock indication is valid, and no periodic slip mark has been formed, the lock holding time is accumulated; if any condition is not met, the lock holding time is reset to zero. The expanded difference between two adjacent phase measurement results is calculated. When the absolute value of this expanded difference and the absolute value of the difference between two unit intervals are not greater than the sum of twice the maximum measurement error of the time-to-digital converter and the minimum phase adjustment time between adjacent valid control words of the phase interpolator, and the training sequence number and synchronous transmission count value of the corresponding synchronous training block are continuous, a periodic slip mark is formed. When the lock holding time reaches the lock confirmation time and no periodic slip mark has been formed, a group clock lock mark is generated.

[0068] If the primary synchronization channel fails to form a group clock lock flag within the allowed locking time, the lock input is switched according to the failure type. If the frequency difference has entered the allowable range but phase locking has not been completed, the current frequency control word is maintained and the phase detection input is switched to the backup synchronization channel. If the frequency difference has not entered the allowable range, the valid historical frequency control word corresponding to the backup synchronization channel is read. If the control word does not exist, the factory synchronization calibration initial frequency control word is restored, and then the frequency and phase detection inputs are switched to the backup synchronization channel. If the backup synchronization channel is unavailable or a group clock lock flag has not been formed within the allowed locking time, a group clock initial lock failure flag is generated. When using the backup synchronization channel to complete locking, only the actual synchronization channel number is written to the initial synchronization record.

[0069] After the group clock is locked, the transmitter stops individually repeating the fixed training sequence field and sends the complete synchronization training block to all data channels within the group. The receiver keeps the group phase-locked loop frequency control word unchanged and controls the phase interpolator of each data channel to perform the initial sampling phase search. It reads the correspondence between the control word and the phase obtained from the factory calibration of each phase interpolator and calculates the phase time covered by the control word range; if the coverage time is not less than one unit interval, a scan is performed; if the coverage time is less than one unit interval or the control word and the phase do not satisfy the monotonic correspondence, an abnormal phase search range marker is generated.

[0070] If a valid historical phase control word exists, it is used as the search starting point; otherwise, the midpoint of the phase interpolator control word range is used as the search starting point. The search proceeds by scanning sequentially in the direction of increasing control word size until the upper limit, then returns to the search starting point and scans sequentially in the direction of decreasing control word size until the lower limit. Under each candidate phase control word, a fixed training sequence field corresponding to the number of phase search sampling training blocks is continuously received, and the number of training symbol errors, the number of missed detections at specified detection edges, and the synchronous training block type identification results are recorded.

[0071] The maximum number of training symbol errors allowed for candidate phase control words is expressed as: ;

[0072] in, Indicates the maximum number of training symbol errors allowed for the candidate phase control word; This represents the allowable bit error rate of the training sequence stored in the CPO optoelectronic interconnect clock synchronization baseline record; This indicates the number of training symbols actually received under the candidate phase control word; This indicates rounding down to the nearest integer.

[0073] The allowable bit error rate (BER) of the training sequence is determined based on the target pre-decoding BER, the data channel modulation scheme, and the symbol mapping relationship of the fixed training sequence fields. When a training symbol carries one coded bit, the allowable BER of the training sequence is taken as the target pre-decoding BER. When a training symbol carries multiple coded bits, and the errors of each coded bit are independent and have the same BER, the error of at least one coded bit within a training symbol is considered a training symbol error. The training symbol error rate is calculated based on the number of coded bits carried by a training symbol and the probability that none of the coded bits are erroneous. This process also considers the case where multiple coded bits err simultaneously. When the coded bit errors do not meet the independence condition or when different protection levels are used for symbol mapping, the training symbol error rate is determined by the ratio of the number of erroneous training symbols in the factory synchronization calibration to the total number of received training symbols. The smaller value between the converted or calibrated training symbol error rate and the training symbol error rate corresponding to the boundary of the effective sampling interval is determined as the allowable BER of the training sequence.

[0074] The allowable bit error rate for the training sequence applies only to clock synchronization groups where the modulation scheme, line coding scheme, fixed training sequence field format, and specified received optical power and measurement bandwidth are consistent with the factory synchronization calibration conditions. If any of these conditions change, the factory synchronization calibration must be re-performed or the allowable bit error rate for the training sequence corresponding to the current configuration must be read. The specific value of the allowable bit error rate for the training sequence, the target bit error rate before decoding, the number of coded bits carried by the training symbols, the calibration conditions, and the parameter version are written into the CPO optoelectronic interconnect clock synchronization basic record.

[0075] Candidate phase control words are marked as valid sampling control words when the number of training symbol errors does not exceed the maximum allowed number of training symbol errors, the number of missed detections at specified detection edges is zero, and the synchronous training block type is correctly identified. Following the actual phase order, consecutive valid sampling control words are grouped into the same valid sampling interval; when the beginning and end of a control word are adjacent in phase, the two segments are merged. If only one valid sampling interval is formed, that interval is selected; if multiple valid sampling intervals are formed, the interval with the largest phase width is selected; if the widths are the same, the interval with the smallest phase distance between its midpoint and a valid historical phase control word is selected; if no valid historical phase control word exists or the phase distances are still the same, the interval with the smaller initial control word value is selected. Based on the phase interpolator control word and actual phase correspondence table, the control word with the smallest distance between the actual phase and the midpoint of the interval phase is selected; if two control words with the same distance exist, the one with the smaller control word value is selected.

[0076] If no valid sampling interval is formed, the remaining initial synchronization time and the number of completed scans are read. If the remaining initial synchronization time can cover a complete scan and the initial phase confirmation time, and the number of completed scans has not reached the phase search limit, the scan is restarted; otherwise, an initial sampling phase search failure flag is generated. If the data baud rate, modulation scheme, line coding scheme, forward error correction coding scheme, or transmission reference clock source changes during the scan, or if the interface re-enters a low-power state, the current scan is terminated and unconfirmed phase search results are cleared.

[0077] The selected initial phase control word is written to the corresponding phase interpolator, and all fields of the complete synchronization training block are read. When all number fields, training sequence number, synchronization transmission count value, and cyclic redundancy check pass verification, the synchronization training block is marked as valid. If the training sequence number returns to zero after reaching its maximum representation value, it is processed continuously; if the synchronization transmission count value reaches the counter's maximum value, the adjacent differences are calculated based on the counter's modulus. When the number of consecutive valid synchronization training blocks reaches the initial phase confirmation training block count, the initial sampling phase of the corresponding data channel is determined.

[0078] After all data channels within the group form the initial sampling phase, a correspondence between synchronization training blocks is established according to the training sequence number. If a single training sequence number is missing, the training block is not used to measure the channel's arrival phase; if the number of consecutive missing numbers reaches the consecutive training block loss confirmation number, the corresponding data channel's synchronization training block reception is marked as abnormal. When the initial synchronization cumulative time reaches the maximum initial synchronization time, or if any data channel fails to form a group clock initial lock, experiences an abnormal phase search range, fails the initial sampling phase search, or is marked as having a synchronization training block reception abnormality, the payload output of the entire clock synchronization group remains off.

[0079] The synchronization channel number, PLL frequency control word, PLL phase control word, training sequence number range used for locking, effective sampling interval of each data channel, initial phase control word, synchronization training block verification result, synchronization transmission count value, initial synchronization cumulative time and abnormal data are written into the CPO optoelectronic interconnect initial synchronization record for reading when the channel arrives at the phase measurement and channel alignment adjustment.

[0080] S3. Based on the CPO optoelectronic interconnect clock synchronization base record and the CPO optoelectronic interconnect initial synchronization record, match the synchronization training block within the group, measure the arrival time difference of each data channel, adjust the channel alignment buffer, word symbol selection position and phase interpolator according to the fixed channel phase reference, and generate the CPO optoelectronic interconnect channel phase adjustment record.

[0081] Read the CPO opto-interconnect clock synchronization basic record and CPO opto-interconnect initial synchronization record. Based on the clock synchronization group number, obtain the actual synchronization channel number, MLL frequency control word, MLL phase control word, effective sampling interval of each data channel, initial phase control word, unit interval, fixed channel phase reference, allowable remaining phase difference of each data channel, channel alignment buffer parameters, word symbol selection range, phase interpolator control word and actual phase correspondence table, time-to-digital conversion circuit parameters, upper limit of phase measurement count, and upper limit of phase adjustment count. The actual synchronization channel number is the data channel number that provides the reference edge when the receiver MLL completes locking. The current arrival time difference, fixed channel phase reference, and channel arrival time change are all referenced to the actual synchronization channel.

[0082] When the actual synchronization channel used differs from the synchronization channel used in the factory synchronization calibration, the fixed channel phase reference for each data channel relative to the actual synchronization channel is calculated based on the fixed channel phase reference between the two synchronization channels. When switching to a backup synchronization channel during payload transmission, the backup synchronization channel number is updated to the actual synchronization channel number, the fixed channel phase reference is recalculated, and the updated actual synchronization channel number, fixed channel phase reference, and reference version are written into the CPO optoelectronic interconnect operation phase retest record.

[0083] The upper limit for the number of phase measurements is determined based on the factory synchronization calibration results, the allowable phase measurement time, and the time required for a single phase measurement. Within the specified range of received optical power, supply voltage, and operating temperature, the specified detection edge measurement is repeatedly performed on each data channel, gradually increasing the number of measurements until the range of multiple measurement results is no greater than the sum of twice the maximum measurement error of the time-to-digital converter and the maximum phase adjustment time between adjacent effective control words of the phase interpolator. The number of measurements required to reach this condition is compared with the result of dividing the allowable phase measurement time by the time required for a single phase measurement and rounding down; the smaller value is taken as the upper limit for the number of phase measurements. The upper limit for the number of phase measurements is three to sixteen times, and the specific values ​​and corresponding calibration results are recorded in the CPO optoelectronic interconnect clock synchronization basic record.

[0084] The upper limit for the number of phase adjustments is determined based on the allowed channel phase adjustment time, the single control parameter write and confirmation time, the single glitch-free adjustment amount allowed by the phase interpolator, and the maximum channel arrival time change to be compensated. First, the maximum channel arrival time change to be compensated is divided by the single glitch-free adjustment amount and rounded up to obtain the number of adjustments required to complete the phase adjustment. This result is then compared with the allowed channel phase adjustment time divided by the single control parameter write and confirmation time and rounded down. The smaller value is taken as the upper limit for the number of phase adjustments. The upper limit for the number of phase adjustments ranges from one to eight. The specific values, calculation basis, and parameter versions are recorded in the CPO optoelectronic interconnect clock synchronization basic record. If the calculated result is less than the number of adjustments required to complete the phase adjustment, the corresponding data channel is marked as having insufficient phase adjustment time.

[0085] The transmitting end sends synchronous training blocks with the same training sequence number and synchronous transmission count value within the group. The receiving end matches synchronous training blocks sent in the same round. Using the group parallel clock count value, the specified position of the detection edge within the logical parallel data word, and the specified signed fine time difference between the detection edges, the current arrival time difference of each data channel relative to the synchronous channel used this time is calculated. If the synchronous channel used this time is inconsistent with the synchronous channel used in the factory synchronization calibration, the fixed channel phase reference of each data channel relative to the synchronous channel used this time is converted based on the fixed channel phase reference between the two synchronous channels.

[0086] Subtract the current arrival time difference from the converted fixed channel phase reference to obtain the channel arrival time change; read the current channel alignment buffer read address offset, word symbol selection position, and phase interpolator control word, and calculate the current equivalent compensation time according to the time adjustment direction and time adjustment amount corresponding to each control parameter; subtract the current equivalent compensation time from the channel arrival time change to obtain the compensated remaining phase difference. If the number of phase measurements has not reached the upper limit, and the discrete range of multiple channel arrival time changes does not meet the confirmation condition, continue to send synchronization training blocks and repeat the measurement; if the upper limit of phase measurements is reached and the confirmation condition is still not met, mark the corresponding data channel as having unstable phase measurement results.

[0087] Based on the remaining phase difference after compensation, determine the channel alignment buffer read address offset, intra-word symbol selection position, and phase interpolator control word. Confirm the control parameters using the measurement results of the adjusted synchronization training block. If the remaining phase difference after compensation does not fall within the allowable remaining phase difference range, re-determine the control parameters within the maximum number of phase adjustment attempts. If the maximum number of phase adjustment attempts is reached and the remaining phase difference still does not fall within the allowable remaining phase difference range, restore the control parameters before adjustment and mark the corresponding data channel as having failed phase adjustment. After processing each data channel within the group, record the synchronization channel number used, current arrival time difference, channel arrival time change, equivalent compensation time, remaining phase difference after compensation, number of phase measurements, number of phase adjustments, control parameters, and anomaly flags to generate a CPO optoelectronic interconnect channel phase adjustment record.

[0088] The system reads the current interface configuration version, initial synchronization configuration version, data baud rate, modulation scheme, line coding scheme, forward error correction coding scheme, and group-locked loop (PLL) lock indicator. If the current interface configuration version matches the initial synchronization configuration version, the PLL lock indicator is valid, and all data channels within the group have formed initial sampling phases without any synchronization training block reception anomaly flags, the system proceeds to arrival phase measurement. If the configuration versions are inconsistent, unconfirmed phase adjustment data is cleared and synchronization training is re-executed. If the PLL is unlocked, the main synchronization channel signal is lost, or the interface re-enters a low-power state, the current measurement is stopped, and the payload output remains off.

[0089] The group parallel clock is obtained by dividing the receiver's group phase-locked loop output clock according to the parallel width of the receiver deserializer, without passing through the phase interpolators of each data channel. The group parallel clock counter is cleared to zero on the rising edge of the specified group parallel clock after initial synchronization is completed, and incremented by one in each group parallel clock cycle. The reset status and counting continuity of the group parallel clock counter are read; if it is not cleared to zero on the specified edge, the count value is repeated, or the count value jumps across cycles, abnormal group parallel clock counting data is generated, and the current counting result is not used.

[0090] The sending end continuously transmits complete synchronization training blocks at the protocol maintenance position. Synchronization training blocks in the same round use the same training sequence number and synchronization transmission count, and are written to the corresponding data channel number. The receiving end reads the data channel number, training sequence number, synchronization transmission count, and cyclic redundancy check result, and matches the synchronization training blocks within the group according to the training sequence number and synchronization transmission count. If any data channel lacks a valid synchronization training block, the arrival time difference is not calculated using that round of training blocks; when the number of consecutive failures to form a complete match within the group reaches the consecutive training block loss acknowledgment count, abnormal training block matching data for the corresponding data channel is generated.

[0091] The fixed training sequence field is a field where all data channels use the same symbol arrangement. A specific symbol transition within this field is selected as the defined detection edge. The symbol number, edge direction, and position within the field corresponding to the defined detection edge are written into the clock synchronization base record. The receiving end extracts the defined detection edge at the output of the limiting amplifier and confirms the synchronization training block to which the edge belongs in the receiving digital path according to the training sequence number, thus binding the analog edge measurement result with the digital field record according to the training sequence number.

[0092] Each data channel within the group is configured with a specified detection edge input. The time-to-digital converter (TD-DCB) circuit is configured with a group parallel clock reference input, the input of the current synchronization channel, and multiple inputs for the data channels under test. The receiver first determines the coarse arrival time difference of the data channel under test relative to the current synchronization channel based on the difference in the group parallel clock count value corresponding to the same round of synchronization training blocks and the position difference of the specified detection edge within the logical parallel data word. The TD-DCB circuit then measures the fine phase of the specified detection edge of the current synchronization channel and the specified detection edge of the data channel under test relative to the same group parallel clock reference edge. The edge priority determination circuit determines the order of these two phases and normalizes the difference between the two fine phases to a single unit interval, forming the signed residual time difference after deducting the coarse arrival time difference.

[0093] The time corresponding to the difference in parallel clock counts, the time corresponding to the difference in position within the logical parallel data word, and the signed residual time difference are added together to obtain the current arrival time difference of the data channel under test relative to the synchronous channel used in this test. The time-to-digital converter inputs the channel number, training sequence number, synchronous transmission count value, fine phase of the two specified detection edges, signed residual time difference, and overflow or underflow flags into the same measurement record. If the input channel number is inconsistent with the current data channel number under test, the training sequence number or synchronous transmission count value does not match, or an overflow or underflow flag is formed, the measurement result is deleted and the fine phase measurement is re-executed.

[0094] When a symbol corresponding to a specified detection edge enters the logical parallel data word, the current count value of the latch group's parallel clock counter is recorded, along with the symbol's position within the logical parallel data word. Symbol positions within the logical parallel data word are numbered from zero according to the transmission order; an increment in the position number indicates that the specified detection edge entered the received digital path one unit interval later. All data channels use the same logical parallel data word width after width conversion; if the width conversion relationship is missing or cannot form the same logical parallel data word width, channel-aligned data width anomaly data is generated.

[0095] The time representation of a logically parallel data word is: ;

[0096] in, This represents the time corresponding to a logically parallel data word. Indicates the number of modulation symbols contained in a logically parallel data word; It represents the unit interval corresponding to a modulation symbol.

[0097] For the For each data channel, the current arrival time difference is calculated using the group parallel clock count, symbol position, and fine time difference under the same training sequence number: ;

[0098] in, Indicates the first The time difference of arrival of each data channel relative to the current primary synchronization channel; and They represent the first The group parallel clock count value latched when the corresponding symbol of the detection edge enters the logical parallel data word in each data channel and the current main synchronization channel; and These represent the sign positions of the corresponding detection edges within the logical parallel data word; The time-to-digital converter circuit measures the first... Each data channel specifies the signed fine time difference of the detection edge relative to the detection edge specified by the current main synchronization channel; This indicates the sequence number of the data channel to be tested within the group. This indicates the primary synchronization channel for this operation.

[0099] When a parallel clock counter experiences a loopback, the counting difference is expanded according to the counter modulus, and the results from the expanded results are selected based on the current arrival time difference being within the total phase adjustment range of a single channel. If multiple results exist, the result with the smallest absolute value of the phase difference with the corresponding fixed channel reference is selected; if no unique result can be obtained, the training sequence number for that round is marked as an anomaly in the counting loop judgment.

[0100] The fixed channel phase reference is formed using a specified detection edge with the same arrival time difference as the current time difference, the group parallel clock count value, the sign position, the time-to-digital converter input, and count wrap-around processing. When using the factory-calibrated main synchronization channel as the phase reference, the corresponding fixed channel phase reference is directly read. When using the backup synchronization channel to complete group clock locking, the converted reference channel is represented as follows: ;

[0101] in, Indicates the first The fixed channel phase reference of each data channel relative to the backup synchronization channel used in this application; Indicates the first Each data channel has a fixed channel phase reference relative to the factory-calibrated master synchronization channel; This indicates the fixed channel phase reference of the backup synchronization channel relative to the factory-calibrated main synchronization channel; This indicates the backup synchronization channel used in this instance. This indicates the factory-calibrated main synchronization channel.

[0102] For each data channel, valid matching training blocks are continuously read. The range of the current arrival time difference is calculated starting from two valid measurements, and the number of measurements is increased sequentially. When the range is no greater than the maximum adjacent phase step within the valid sampling interval of the corresponding phase interpolator, the number of measurements is stopped, and all valid measurement results are arranged in ascending order of value. When the number of valid measurements is odd, the middle measurement result is taken as the median; when the number of valid measurements is even, the average of the two middle measurements is taken as the median, and this median is used as the current arrival time difference. If the range condition is still not met after reaching the upper limit of the number of phase measurements, abnormal arrival phase measurement data is generated. Data corresponding to cyclic redundancy check errors, missed detections at specified detection edges, errors in the input channel of the time-to-digital converter, and counting anomalies are not included in the range and median calculations. The same calculation rules are used for the median involved in fixed channel phase references and group-level and branch-level adjustments.

[0103] Calculate the remaining phase difference based on the current arrival time difference and the converted fixed channel phase reference: ;

[0104] in, Indicates the first The remaining phase difference of each data channel; Indicates the first The time difference of arrival of each data channel relative to the current primary synchronization channel; This indicates the fixed channel phase reference, which is used as a reference for the current main synchronization channel. A positive value indicates the first Each data channel arrives with a delay relative to the fixed channel phase reference. A negative value indicates early arrival.

[0105] The data is read from the channel alignment buffer, including the current read address offset, initial read address offset, minimum number of occupied memory units, maximum number of occupied memory units, intra-word sign selection position, and the current control word of the phase interpolator. The channel alignment buffer read address offset represents the number of memory units reserved between the write address and the read address. Increasing the offset delays the data output time, while decreasing the offset advances the data output time.

[0106] The ratio of the compensated remaining phase difference to the unit interval is converted into an integer unit interval adjustment candidate value. If only one of these ratios is closest to an integer, that integer is selected as the first candidate value. If the ratio is in the middle of two adjacent integers, or if the distance difference between two adjacent integers is not greater than the converted value of the compensated remaining phase difference measurement error, both integers are selected as the first batch of candidate values. The upper and lower limits of the candidate values ​​are determined based on the channel alignment buffer read address allowable range, the word symbol selection range, and the effective control word range of the phase interpolator, and they are arranged in ascending order of the absolute value of the compensated remaining phase difference. If the absolute values ​​are the same, the candidate value with the smaller absolute value of the integer unit interval adjustment is selected first.

[0107] For each integer unit interval, adjust the candidate value by multiplying the current channel alignment buffer read address offset by the number of modulation symbols contained in one buffer storage unit, and then adding this multiplication to the current intra-word symbol selection position to obtain the current combined read position. Add the integer unit interval adjustment candidate value to the current combined read position according to the adjustment direction to obtain the candidate combined read position. The integer quotient obtained by dividing the candidate combined read position by the number of modulation symbols contained in one buffer storage unit determines the candidate channel alignment buffer read address offset, and the remainder determines the candidate intra-word symbol selection position. If the candidate channel alignment buffer read address offset or the candidate intra-word symbol selection position exceeds the corresponding allowable range, the candidate value is deleted; the remaining candidate values ​​are used to continue determining the phase interpolator control word.

[0108] Calculate the phase difference (less than one unit interval) corresponding to each integer candidate value. Read the phase interpolator control word and actual phase correspondence table. Within the allowable adjustment direction of the current control word, filter the candidate control word whose actual phase change is closest to the phase difference. Delete combinations where the read address offset exceeds the minimum or maximum occupied range, the sign selection position within the word is out of bounds, the candidate control word is not in the valid sampling range, or the version of the control word and phase correspondence table is inconsistent. Among the remaining combinations, first select the combination with the smallest absolute value of phase adjustment error; if they are the same, select the combination with the smaller change in phase interpolator control word; if they are still the same, select the combination with the smaller change in read address offset. If no valid combination is formed, generate data for insufficient channel phase adjustment range.

[0109] The selected read address offset, intra-word sign selection position, and phase interpolator control word are written to the configuration register, which does not directly change the data path. When all data channels within the group detect the specified training sequence number, the configuration register write verification is correct, and the group parallel clock counter is in normal status, the configuration register value is written to the working register at the same group parallel clock boundary. If any data channel fails to detect the specified training sequence number or the working register return value is inconsistent with the configuration value, the update for this round is not retained, and all data channels are restored to the control values ​​before adjustment.

[0110] The single glitch-free adjustment range is determined based on the maximum glitch-free control word change specified in the phase interpolator hardware datasheet and the factory synchronization calibration result, taking the smaller of the two values. This range is one to four adjacent valid control words and is written into the CPO optoelectronic interconnect clock synchronization baseline record. When the phase interpolator control word change exceeds the single glitch-free adjustment range, the change is split into multiple control word update amounts in the same direction. Each update does not exceed the single glitch-free adjustment range, and at least one complete synchronization training block is received between two adjacent updates. After each update, the remaining phase difference after compensation is remeasured; if the absolute value of the remaining phase difference after compensation decreases, the current control word is retained; otherwise, the previous valid control word is restored. If the remaining initial synchronization time can cover one complete measurement and one control parameter update, and the number of phase adjustments has not reached the upper limit of the phase adjustment count, candidate combinations are regenerated; otherwise, abnormal phase adjustment data is generated.

[0111] When the number of valid measurement results continuously acquired by each data channel reaches the initial phase confirmation training block count, and the absolute value of the remaining phase difference is not greater than the allowable remaining phase difference of the corresponding data channel, the channel phase adjustment is recorded as complete. The transmitter records the sequence number of the last complete forward error correction codeword transmitted before pausing the payload, and resumes data transmission starting from the next forward error correction codeword. The receiver checks the forward error correction codeword start marker and codeword sequence number of each data channel in the group. If they are all consistent, the payload output is enabled; if the codeword sequence number of any data channel is inconsistent, the output remains disabled.

[0112] The current arrival time difference of each data channel, fixed channel phase reference, remaining phase difference, read address offset, word symbol selection position, phase interpolator control word, measurement results before and after adjustment, training sequence number range, effective measurement count, adjustment count, and abnormal data are written into the CPO optoelectronic interconnect channel phase adjustment record for phase retesting and control parameter update during payload transmission.

[0113] S4. Based on the CPO optoelectronic interconnect clock synchronization basic record and CPO optoelectronic interconnect channel phase adjustment record, remeasure the phase of each data channel during payload transmission, update the group clock, clock tree branch or single channel control parameters according to the phase change results, process channel realignment and main / backup synchronization channel switching, and generate CPO optoelectronic interconnect operation phase remeasurement record.

[0114] Read the CPO optoelectronic interconnect clock synchronization basic record, CPO optoelectronic interconnect initial synchronization record, and CPO optoelectronic interconnect channel phase adjustment record. Based on the clock synchronization group number, obtain the main synchronization channel number, backup synchronization channel number, fixed channel phase reference for each data channel, allowable remaining phase difference, confirmed channel alignment buffer read address offset, word symbol selection position, phase interpolator control word, group clock phase offset control word, clock tree branch delay control word, and the correspondence between each control word and the actual time adjustment. During payload transmission, collect temperature values, power supply voltage values, group phase-locked loop status, synchronization training block reception results, and current arrival time differences for each data channel. Calculate the channel arrival time change, the compensation time corresponding to the current control parameters, and the remaining phase difference after compensation. Determine the synchronization training block transmission time based on the remaining phase margin after compensation and the channel arrival time change rate. Update the corresponding control parameters according to the common phase change within the group, the common phase change of the clock tree branches, or the single-channel phase change. Confirm the control parameters based on the retest results and generate the CPO optoelectronic interconnect operation phase retest record.

[0115] The system reads the current interface configuration version, group-locked loop (PLL) lock indicator, main synchronization channel signal loss indicator, group parallel clock counter status, enable status of each data channel, and forward error correction codeword count. If the current interface configuration version matches the configuration version in the channel phase adjustment record, the PLL lock indicator is valid, the group parallel clock count is continuous, and all allowed data channels within the group are in payload reception mode, the system proceeds to phase retesting. If the interface configuration version changes, the PLL is unlocked, the group parallel clock count is abnormal, or the interface enters a low-power state, the current retest is terminated, and unconfirmed measurement results are not used.

[0116] Based on the temperature sensor number, voltage monitoring terminal number, sampling period, and effective measurement range in the clock synchronization baseline record, the temperature and voltage values ​​of each data channel corresponding to the optical engine area, clock tree branch, and power supply domain are collected. Simultaneously, the sampling time, sensor status, analog-to-digital conversion completion marker, and calibration version are recorded. If the sensor status is abnormal, analog-to-digital conversion is incomplete, the collected value exceeds the factory calibration range, or the calibration version is inconsistent with the current hardware version, the phase change rate is not calculated based on the corresponding collected value, and the synchronization training block transmission time is set to the next available protocol maintenance position.

[0117] The transmitter saves the calibration control parameters for each data channel upon completion of factory calibration and initial channel alignment. These parameters include the group clock phase offset control word, clock tree branch delay control word, channel alignment buffer read address offset, intra-word sign selection position, and phase interpolator control word. During operation, it reads the current control parameters and their correspondence with the actual time adjustment, and calculates the... The equivalent compensation time for the current control parameters of each data channel relative to the calibration control parameters: ;

[0118] in, Indicates the first The equivalent compensation time that has been executed for each data channel; a positive value indicates that the current control parameters are used to compensate for the delayed arrival of the data channel. This indicates the amount of time adjustment that the group clock phase offset control word is formed relative to the calibration control word; Indicates the first The time adjustment amount formed by the delay control word of each data channel corresponding to the clock tree branch; This represents the difference between the current channel alignment buffer read address offset and the calibration read address offset. This indicates the number of modulation symbols contained in a single buffer storage unit; Indicates unit interval; This indicates the difference between the current selected symbol position within the character and the calibrated selected symbol position within the character. Indicates the first The actual phase adjustment time formed by the current phase interpolator control word relative to the calibration control word for each data channel. When the read address offset or the sign selection position within the word increases, the data output time is delayed; therefore, a negative sign is used in the equivalent compensation time.

[0119] Read the current arrival time difference obtained from the most recent synchronous training block retest, and detect the edges, group parallel clock count, sign position within the logical parallel data word, and time-to-digital conversion result according to the same specifications as the factory calibration, and calculate the... Changes in arrival time for each data channel: ;

[0120] in, Indicates the first The amount of time of arrival of each data channel relative to the phase reference of a fixed channel; Indicates the first The time difference of arrival of each data channel relative to the current primary synchronization channel; This indicates the fixed channel phase reference, which is used as a reference for the current main synchronization channel. A positive value indicates that the data channel arrives with a delay relative to the calibration state. A negative value indicates early arrival. The change in channel arrival time is caused by the delay changes in the photoelectric transmission path and the transmitting and receiving circuits, and is not changed by updates to the receiving end control parameters.

[0121] Calculate the remaining phase difference and remaining phase margin after compensation based on the channel arrival time variation and equivalent compensation time: ; ;

[0122] in, Indicates the first The remaining phase difference after the current control parameters are compensated by each data channel; Indicates the first Remaining phase margin for each data channel; Indicates the first Each data channel allows for a remaining phase difference; This represents the absolute value of the remaining phase difference after compensation. When the remaining phase margin is not greater than zero, the nearest available maintenance location is determined directly without waiting for a fixed retest cycle.

[0123] When there are two or more valid arrival time measurements, the measured rate of change is calculated based on the channel arrival time changes at the two measurement times; if there is only one valid result, no measured rate of change is generated. The temperature change versus channel arrival time change and voltage change versus channel arrival time change correspondence tables are read. Based on the current temperature, voltage, and the calibration interval where the previous acquisition value is located, the corresponding phase change between the two acquisitions is calculated and divided by the acquisition time interval to obtain the corresponding rate of change for temperature and voltage. If the temperature or voltage value exceeds the calibration range, interval extrapolation is not performed. The temperature change versus channel arrival time change and voltage change versus channel arrival time change correspondence tables are generated through factory synchronization calibration. Under the specified received optical power and measurement bandwidth, no fewer than five sampling points are set at equal intervals within the allowable operating temperature range and the allowable supply voltage range, respectively. Each sampling point is measured at least three times, the median of the channel arrival time change is taken, and linear interpolation is applied to adjacent sampling points. The sampling points, measurement results, interpolation method, applicable conditions, and table version are written into the CPO optoelectronic interconnect clock synchronization basic record.

[0124] When there are two or more valid arrival time measurements, the measured rate of change is calculated based on the change in channel arrival time between two adjacent measurement times; if there is only one valid result, no measured rate of change is generated. Based on the current temperature, voltage, and the calibration interval where the previous acquisition value is located, the phase change and rate of change corresponding to the temperature and voltage are calculated respectively; if the temperature or voltage value exceeds the calibration range, interval extrapolation is not performed.

[0125] When obtaining both the measured rate of change and the corresponding rates of change for temperature and voltage, the absolute values ​​of each rate of change are taken, and the result with the largest absolute value is used as the current channel arrival time rate of change. If only one result is obtained, the absolute value of that result is used. When the remaining phase margin is not greater than zero, the nearest protocol maintenance position is directly selected to send the synchronization training block. When the remaining phase margin is greater than zero and the channel arrival time rate of change is greater than zero, the synchronization training block transmission waiting time is calculated. When the channel arrival time rate of change is equal to zero or no valid rate of change is obtained, the retest time is determined according to the maximum synchronization training block transmission interval allowed by the protocol. The temperature and voltage calculation results are only used to determine the synchronization training block transmission time and are not directly used to generate phase control words.

[0126] No. The allowed waiting time for each data channel is expressed as: ;

[0127] in, This indicates the allowed waiting time from the current acquisition time to the initiation of sending a synchronous training block; Indicates the first The rate of change of arrival time currently used by each data channel; This indicates the time required for the receiving end to send a retest request through the existing reverse data channel link maintenance control block and for the sending end to complete the parsing. This indicates the maximum time required to wait for an available protocol to maintain the location; This indicates the time required for the sending end to generate and send the synchronous training block; This indicates the time required for the receiving end to complete training block matching and phase measurement.

[0128] The minimum allowed waiting time for all permitted data channels within the group is taken as the retest waiting time. If the retest waiting time exceeds the maximum allowed transmission interval of the protocol, the maximum allowed transmission interval is used. The waiting time from the current position to the next protocol maintenance position is calculated. If the retest waiting time is not less than this waiting time, a synchronization training block is sent at the next protocol maintenance position. If the retest waiting time is less than this waiting time, the payload within the group is paused after the current forward error correction codeword ends, and synchronization training blocks are continuously sent. The calculation of the retest waiting time already includes the time required for sending synchronization training blocks and phase measurement; this time is not deducted again when determining the maintenance position.

[0129] The receiving end calculates the current arrival time difference of each data channel according to the measurement method used for channel phase adjustment recording, and updates them accordingly. , , and If any permitted data channel within a group fails to obtain a valid measurement result, group-level phase adjustment will not be performed; if any permitted data channel within the same clock tree branch fails to obtain a valid result, the corresponding branch phase adjustment will not be performed.

[0130] The phase change of the specified detection edge of the main synchronization channel relative to the output clock edge of the group-locked loop is read and denoted as... And calculate the actual arrival phase change of each data channel relative to the group clock: ;

[0131] in, Indicates the first The actual arrival phase change of each data channel relative to the group clock; This indicates the amount of phase change of the detection edge relative to the group clock in this main synchronization channel. It is used to determine whether there is a phase change arriving in the same direction within the group or clock tree branch, but not to confirm the compensation result at the receiving end.

[0132] The maximum phase measurement error within a group, the maximum adjacent control word phase step, the minimum effective adjustment of the group clock, and the phase detection repeatability error are all determined through factory synchronization calibration. The maximum phase measurement error within a group is the maximum absolute deviation between the phase measurement value of each permissible data channel and the calibration reference value; the maximum adjacent control word phase step is the maximum value of the phase difference between the corresponding phase words of adjacent effective control words in the group clock phase offset control word and the actual phase correspondence table; the phase detection repeatability error is the maximum absolute deviation of the repeated phase measurement result relative to the median under the same calibration conditions; the minimum effective adjustment of the group clock is the minimum control word adjustment that ensures consistent phase change direction within the group and that the phase change exceeds the phase detection repeatability error. The calibration conditions, values, applicable scope, and versions of these four parameters are recorded in the CPO optoelectronic interconnect clock synchronization basic record.

[0133] When group-level adjustment conditions are not met, data channels are divided according to the clock tree branch number. Each branch must contain at least two usable data channels, and all data channels within the branch must obtain valid measurement results. When the directions are consistent and the discrete range does not exceed the branch measurement error range, calculate the branch within the range. The median. A corresponding table of programmable delay circuit numbers and control words exists in the basic record. When the absolute value of the median is greater than the minimum effective adjustment of the branch, a candidate branch delay control word is generated. When no branch programmable delay circuit is configured, candidate phase interpolator control words are generated for each data channel within the branch. The branch measurement error range is determined based on the maximum discrete range of repeated phase measurement results for each data channel in the same clock tree branch during factory synchronization calibration, and the sum of the maximum measurement error of the double-time digital conversion circuit and the maximum adjacent adjustment step of the phase interpolator; the larger of the two values ​​is taken. The minimum effective adjustment of the branch is the sum of the branch measurement error range and the delay time corresponding to one effective control word of the branch programmable delay circuit. The specific values, calibration conditions, and parameter versions of these two parameters are written into the CPO optoelectronic interconnect clock synchronization basic record.

[0134] For data channels that do not meet the group-level and branch-level adjustment conditions, the candidate control word for the phase interpolator is selected based on the remaining phase difference after compensation. The candidate control word is filtered using a phase interpolator control word-to-actual phase correspondence table and is limited to the effective sampling interval in the initial synchronization record. The buffer boundary reservation is calculated by converting the occupancy corresponding to the maximum channel arrival time change rate within the maximum synchronization training block transmission interval allowed by the protocol upwards to the number of complete storage units, and then adding one storage unit to determine the value. The specific value is written into the CPO optoelectronic interconnect clock synchronization basic record. When the absolute value of the remaining phase difference after compensation for any data channel reaches one unit interval, the candidate control word for the phase interpolator exceeds the effective sampling interval, or the number of storage units between the current occupancy of the channel alignment buffer and the allowed upper or lower limit is not greater than the buffer boundary reservation, the entire clock synchronization group enters the maintenance transmission state after the current forward error correction codeword ends, records the last complete codeword count value, and re-executes the channel arrival phase measurement and channel alignment adjustment.

[0135] The candidate group clock phase offset control word, candidate branch delay control word, and candidate phase interpolator control word are first written to the configuration register. When the specified training sequence number within the group is fully received, the configuration register is correctly verified, and the group's parallel clock count is normal, the control word is written to the working register at the same group's parallel clock boundary. After the update, the remaining phase difference after compensation is recalculated using the next round of complete synchronous training blocks. If the absolute value decreases, the control parameters are retained; otherwise, the previous valid control parameters are restored.

[0136] The upper limit for the number of operational control parameter adjustments is determined based on the protocol maintenance time slot length and the time required for writing, updating, measuring, and confirming a single control parameter. It is set to the maximum number of complete adjustments that can be performed within a single protocol maintenance time slot, and must not exceed the number of adjustments that can be performed within the interface's allowed continuous maintenance time. The specific value is recorded in the CPO optoelectronic interconnect clock synchronization baseline record. If, even after reaching the upper limit for the number of operational control parameter adjustments, a data channel still exceeds the allowed remaining phase difference, the effective payload within the group is shut down, and the group clock and initial sampling phase are re-established.

[0137] The main synchronization channel signal loss indication is continuously maintained until the signal loss confirmation time, the group-locked loop reference input loss is continuously maintained until the reference input loss confirmation time, or when the number of consecutive training block loss confirmations for which no fixed training sequence field of the main synchronization channel is detected within the predetermined receiving window of the synchronization training block reaches the consecutive training block loss confirmation number, the current group clock phase offset control word, branch delay control word, and phase interpolator control word of each data channel are frozen. The signal loss confirmation time and reference input loss confirmation time are determined based on the sum of the maximum detection delay and dejitter time of the receiver signal detection circuit and the group-locked loop reference input detection circuit, respectively, and are written into the CPO optoelectronic interconnect clock synchronization basic record.

[0138] Measure the phase difference between the backup synchronization channel reference edge and the hold-state group clock. If the phase difference is not greater than the maximum switching phase difference allowed by the glitch-free clock selection circuit, disable the current reference input clock gating. After both reference input gating outputs remain low, enable the backup reference input clock gating; otherwise, disable the payload and re-execute the group clock locking. After the switching is complete, verify the group PLL lock indicator, training sequence number, synchronization transmission count value, and period slip mark. If all requirements are met, record the synchronization channel number used this time.

[0139] After phase retesting or integer unit interval adjustment is completed, the transmitter resumes transmission from the next codeword after the last complete forward error correction codeword before the pause. The receiver checks the codeword start marker and codeword count value of each data channel in the group; if all are consistent, payload output is enabled.

[0140] The temperature value, voltage value, channel arrival time change, equivalent compensation time, remaining phase difference after compensation, remaining phase margin, arrival time change rate, synchronous training block transmission time, various control words, control parameter confirmation results, main and backup synchronous channel switching results, forward error correction code word count value, and abnormal data are written into the CPO optoelectronic interconnect operation phase retest record.

[0141] To verify the feasibility of calculating channel arrival time variations using a unified measurement caliber, and to verify the processing results of updating the group clock phase offset control word, clock tree branch delay control word, or data channel phase interpolator control word based on the source of phase change, a 64-channel CPO optoelectronic interconnect co-simulation environment was established, divided into four clock tree branches according to the clock tree connection relationship. Each data channel uses 53.125 gigabitord four-level pulse amplitude modulation. The transmit link is configured with a training block insertion circuit, channel allocation circuit, transmit queue, gearbox, serializer, and optical modulation channel in sequence. The receive link is configured with a photodetector channel, receive amplifier circuit, receiver group phase-locked loop, deserializer, channel alignment buffer, phase interpolator, and time-to-digital converter circuit in sequence.

[0142] In the simulation, the time-to-digital converter uses 8-bit quantization with a quantization resolution of 0.005 unit intervals. The phase interpolator sets 64 effective control words within one unit interval. The actual phase error between adjacent control words follows a normal distribution with a mean of zero and a standard deviation of 0.0015 unit intervals, limited to ±0.004 unit intervals. The measurement noise of the receiving channel follows a normal distribution with a mean of zero and a standard deviation of 0.003 unit intervals. The random number seed is set to 20260729. The effective eye diagram horizontal opening of each data channel is set to 0.62 unit intervals, and the receiver sampler retention time is set to 0.08 unit intervals. Based on this, the allowable residual phase difference is set to 0.218 unit intervals.

[0143] Figure 5 Forty-five simulation samples are generated for each of the four scenarios: baseline operation, temperature variation, power supply voltage variation, and combined temperature and power supply voltage variation. The temperature varies according to a triangular wave from 25 degrees Celsius to 85 degrees Celsius, and the power supply voltage varies according to a step and sine wave superposition of ±5% of the rated voltage. Channel delay perturbations are generated based on the correspondence tables of temperature variation and channel arrival time variation, and voltage variation and channel arrival time variation. Figure 6 The simulation covers four scenarios: common phase change within the group, clock tree branch phase change, single-channel phase change, and mixed phase change. For each scenario, 45 rounds of phase retesting are performed continuously. Ramp, triangular wave, or pulse-type arrival phase changes are applied to all data channels, one clock tree branch, one data channel, and multiple layers superimposed, respectively. Input parameters, random seeds, measurement results, and control parameter update results for each scenario are all written into the simulation log for generation. Figure 5 and Figure 6 .

[0144] To form Figure 5 The corresponding data is configured with four scenarios: baseline operation, temperature variation, power supply voltage variation, and combined temperature and power supply voltage variation. Forty-five independent samples are generated for each scenario. Each sample stores the actual channel arrival time variation and calculates the channel arrival time variation using three data combinations: parallel clock count only, parallel clock count plus sign position within the logical parallel data word, and parallel clock count plus sign position within the logical parallel data word plus signed fine time difference. The absolute value of the difference between the measured result and the actual channel arrival time variation is normalized according to unit intervals to obtain... Figure 5 The three curves in the image.

[0145] like Figure 5 As shown, when using the group parallel clock count, the sign position within the logical parallel data word, and the signed fine time difference for calculation, the absolute measurement error under each disturbance scenario is lower than that of the other two data combinations. The sum of twice the maximum measurement error of the time-to-digital converter and the maximum adjacent control word phase step of the phase interpolator is subtracted from a unit interval as the unit interval jump judgment value; when the absolute value of the difference between two adjacent channel arrival time changes reaches this judgment value, a measurement jump corresponding to the unit interval is determined to have occurred. Under the scenario of superimposed temperature and supply voltage changes, the difference between adjacent measurement results did not reach this judgment value. This result indicates that by using the same specified detection edge and measurement data for the fixed channel phase reference and the current arrival time difference, the calculation deviation of the channel arrival time change caused by not jointly including the parallel data word boundary, sign position, and fine phase can be reduced.

[0146] To form Figure 6The corresponding data, during payload transmission, sequentially sets four scenarios: intra-group common phase change, clock tree branch phase change, single-channel phase change, and mixed phase change. Forty-five rounds of synchronous training block retesting are performed for each scenario. Each retesting round records the channel arrival time change, the equivalent compensation time formed by the current control parameters, the compensated remaining phase difference, and the allowable remaining phase difference. These are calculated using intra-group, clock tree branch and single-channel hierarchical adjustment, group-only clock phase offset adjustment, and fixed-period single-channel phase adjustment, respectively. The ratio of the absolute value of the largest compensated remaining phase difference within the group to the allowable remaining phase difference is taken in each retesting round. Figure 6 The figure shows three control result curves, with the horizontal dashed line representing the allowable boundary.

[0147] like Figure 6 As shown, the ratio of the absolute value of the compensated remaining phase difference to the corresponding allowable remaining phase difference is used as the normalization result. A ratio not greater than one indicates the phase difference is within the allowable boundary, while a ratio greater than one indicates it exceeds the allowable boundary. When using intra-group, clock tree branch, and single-channel hierarchical adjustments, the normalization results for all four phase change scenarios are not greater than one. When only group clock phase offset adjustment is used, the normalization results are greater than one in clock tree branch change, single-channel change, and mixed change scenarios. Similarly, when using fixed-period single-channel phase adjustment, the normalization results are also greater than one during scenario switching and mixed changes. This result indicates that selecting the corresponding control parameters based on the actual arrival phase change direction and discrete range of each data channel relative to the group clock, and determining the synchronous training block transmission time based on the remaining phase margin and the channel arrival time change rate, can keep the compensated remaining phase difference of the intra-group data channels within the corresponding allowable range.

[0148] In summary, this invention achieves multi-channel phase correction under a unified measurement benchmark by matching the synchronous training block within the group, measuring the arrival time difference of the data channel based on the group's parallel clock count value, symbol position, and signed fine time difference, and adjusting the channel alignment buffer, intra-word symbol selection position, and phase interpolator in conjunction with a fixed channel phase reference. By re-measuring the data channel phase during payload transmission, updating control parameters according to phase changes within the group, clock tree branches, or single channels, and handling channel realignment and switching between primary and backup synchronous channels, hierarchical synchronization maintenance is achieved, improving the clock synchronization stability of CPO optoelectronic interconnects.

[0149] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high-density data transmission clock synchronization method for CPO optoelectronic interconnects, characterized in that, include: Acquire CPO opto-interconnect synchronization configuration data, divide clock synchronization groups, and generate CPO opto-interconnect clock synchronization basic records; Based on the CPO opto-interconnect clock synchronization basic record transmission synchronization training block, lock the receiver group phase-locked loop, determine the initial sampling phase of each data channel, and generate the CPO opto-interconnect initial synchronization record. Based on the CPO optoelectronic interconnect clock synchronization basic record and the CPO optoelectronic interconnect initial synchronization record, the synchronization training block within the group is matched, the arrival time difference of each data channel is measured, and the channel alignment buffer, intra-word symbol selection position and phase interpolator are adjusted according to the fixed channel phase reference to generate the CPO optoelectronic interconnect channel phase adjustment record. Based on the CPO optoelectronic interconnect clock synchronization basic record and the CPO optoelectronic interconnect channel phase adjustment record, the phase of each data channel is remeasured during the payload transmission period. The group clock, clock tree branch or single channel control parameters are updated according to the phase change results. Channel realignment and main / backup synchronization channel switching are processed to generate the CPO optoelectronic interconnect operation phase remeasurement record.

2. The high-density data transmission clock synchronization method for CPO optoelectronic interconnects as described in claim 1, characterized in that, The process of dividing clock synchronization groups and generating CPO optoelectronic interconnect clock synchronization baseline records includes: Clock synchronization groups are divided according to the optical engine affiliation, transmit phase-locked loop, transmit clock division ratio, data baud rate, modulation method, line coding method, forward error correction coding method, receiver group phase-locked loop connection relationship, and consistency of phase interpolator input reference. The data channels that meet the detection conditions of the fixed training sequence within the group are sorted to determine the main synchronization channel and the backup synchronization channel, and the fixed channel phase reference of each data channel relative to the main synchronization channel is measured.

3. The high-density data transmission clock synchronization method for CPO optoelectronic interconnects as described in claim 2, characterized in that, The basic recording and transmission synchronization training block based on CPO optoelectronic interconnect clock synchronization, locking the receiving end group phase-locked loop, and determining the initial sampling phase of each data channel includes: The synchronous training block consists of a protocol-reserved control block. During the initial synchronization period, the transmitting end repeatedly sends a fixed training sequence field, and the receiving end extracts the signal edge from the main synchronization channel and completes the frequency locking and phase locking of the receiving end's group phase-locked loop. If the main synchronization channel fails to complete locking within the corresponding lockout time, the group phase-locked loop frequency control word is maintained or restored according to the frequency locking result, and the system switches to the backup synchronization channel to continue locking.

4. The high-density data transmission clock synchronization method for CPO optoelectronic interconnects as described in claim 1 or 3, characterized in that, The basic recording and transmission synchronization training block based on CPO optoelectronic interconnect clock synchronization, locking the receiving end group phase-locked loop, and determining the initial sampling phase of each data channel includes: After the receiving end group of phase-locked loops completes locking, it scans the control words of each data channel phase interpolator within a unit interval. Based on the number of symbol errors in the fixed training sequence field, the number of missed detections at the specified detection edges, and the identification results of the synchronous training block type, it determines the effective sampling interval and selects the midpoint of the effective sampling interval as the initial sampling phase of the corresponding data channel.

5. The high-density data transmission clock synchronization method for CPO optoelectronic interconnects as described in claim 4, characterized in that, The synchronized training block within the matching group measures the arrival time difference of each data channel and adjusts the channel alignment buffer, intra-word symbol selection position, and phase interpolator according to a fixed channel phase reference, including: The parallel clock is formed by dividing the output clock of the phase-locked loop at the receiving end. For the same training sequence number, the receiving end records the parallel clock count, the position of the symbol corresponding to the specified detection edge in the logical parallel data word, and the signed fine time difference relative to the main synchronization channel for the specified detection edge. Based on these three, the current arrival time difference of each data channel relative to the main synchronization channel is calculated.

6. The high-density data transmission clock synchronization method for CPO optoelectronic interconnects as described in claim 5, characterized in that, The synchronized training block within the matching group measures the arrival time difference of each data channel and adjusts the channel alignment buffer, intra-word symbol selection position, and phase interpolator according to a fixed channel phase reference, including: The fixed channel phase reference and the current time difference of arrival are formed using the same specified detection edge and measurement method; When the main synchronization channel used is inconsistent with the main synchronization channel used in the factory calibration, the fixed channel phase reference of each data channel relative to the main synchronization channel in this test is calculated based on the fixed channel phase reference of the backup synchronization channel relative to the factory calibration main synchronization channel.

7. The high-density data transmission clock synchronization method for CPO optoelectronic interconnects as described in claim 6, characterized in that, The synchronized training block within the matching group measures the arrival time difference of each data channel and adjusts the channel alignment buffer, intra-word symbol selection position, and phase interpolator according to a fixed channel phase reference, including: Based on the difference between the current arrival time difference and the fixed channel phase reference, candidate combinations of channel alignment buffer read address offset, word sign selection position and phase interpolator control word are generated. Candidate combinations that exceed the buffer occupancy limit, word sign selection position limit, or phase interpolator control word limit are filtered out. The selected combinations are written to the working registers of each data channel in the same group of parallel clock boundaries. If the remaining phase difference does not decrease after the updated compensation, restore the control parameters before the update.

8. The high-density data transmission clock synchronization method for CPO optoelectronic interconnects as described in claim 7, characterized in that, The process of re-measuring the phase of each data channel during payload transmission, updating the group clock, clock tree branch, or single-channel control parameters based on the phase change results, and handling channel realignment and primary / backup synchronization channel switching includes: During payload transmission, the channel arrival time change of each data channel, the equivalent compensation time formed by the current control parameters, and the remaining phase difference after compensation are calculated respectively. The remaining phase margin is calculated based on the remaining phase difference after compensation and the allowable remaining phase difference. The transmission time of the synchronous training block is determined based on the channel arrival time change of adjacent retest times and the arrival time change corresponding to temperature and voltage.

9. The high-density data transmission clock synchronization method for CPO optoelectronic interconnects as described in claim 8, characterized in that, The process of re-measuring the phase of each data channel during payload transmission, updating the group clock, clock tree branch, or single-channel control parameters based on the phase change results, and handling channel realignment and primary / backup synchronization channel switching includes: Based on the phase change of the main synchronization channel relative to the group clock and the channel arrival time change of each data channel, determine the actual arrival phase change of each data channel relative to the group clock. When the actual arrival phase change direction of the data channels within the group is consistent and the discrete range meets the group-level adjustment conditions, the group clock phase offset control word is updated. When the data channels within the clock tree branch meet the branch-level adjustment conditions, the corresponding branch delay control word is updated. The remaining data channels update the corresponding phase interpolator control word, and the control parameters are confirmed based on the updated and compensated remaining phase difference.

10. The high-density data transmission clock synchronization method for CPO optoelectronic interconnects as described in claim 9, characterized in that, The process of re-measuring the phase of each data channel during payload transmission, updating the group clock, clock tree branch, or single-channel control parameters based on the phase change results, and handling channel realignment and primary / backup synchronization channel switching includes: When the remaining phase difference after compensation reaches one unit interval, the phase interpolator control word exceeds the effective sampling range, or the channel alignment buffer occupancy reaches the allowable boundary, the effective payload of the clock synchronization group is paused at the forward error correction codeword boundary and channel alignment is re-executed. When the main synchronization channel fails, the phase difference between the reference edge of the backup synchronization channel and the clock of the hold-state group is measured. If the phase difference meets the no-glitch switching condition, the reference input is switched; otherwise, the payload is turned off and the receiver group phase-locked loop is re-executed.

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