Automated channel management peripheral direct memory access control for encryption control module

Abstract

The present application provides an automatic channel management peripheral direct memory access control device with encryption control module, which is suitable for at least one peripheral and includes at least one channel, an encryption control module, an embedded static random access memory, a peripheral request preprocessing module and a channel control module. The encryption control module includes an encryption engine, a true random number generator and a key storage module. The embedded static random access memory is used to store the channel description table of each channel and record the transmission message, and includes block encryption storage space for realizing block encryption and key management functions. The peripheral request preprocessing module is used to process the request sent by the peripheral. The channel control module selects the appropriate channel according to the information provided by the peripheral request preprocessing module to perform data transmission.

Description

Technical Field

[0001] This invention relates to an automatic channel management peripheral direct memory access (PDMA) control device with an encryption control module, and more specifically, to an automatic channel management PDMA control device that automatically configures PDMA channels without software intervention and has a built-in encryption control module. Background Technology

[0002] Figure 1 It is a well-known cryptographic accelerator design, including a pseudo random number generator (PRNG)110, and supports various encryption algorithms, such as, but not limited to, Advanced Encryption Standard (AES), Data Encryption Standard / Triple Data Encryption Standard (DES / TDES), Secure Hash Algorithm (SHA), Hash Message Authentication Code (HMAC), and Elliptic Curve Cryptography (ECC). It also provides Direct Memory Access (DMA) mode. Figure 1 The encryption accelerator shown has a DMA channel 112a for the AES algorithm and a DMA channel 112c for SHA / HMAC. Once the DMA register 108 is configured, the transfer of data between the encryption engine and static random access memory (SRAM) is entirely automated by DMA.

[0003] However, Figure 1 The architecture shown has DMA built into the encryption engine. The number of DMA channels is very small, and it is limited to moving data in SRAM or synchronous dynamic random access memory (SDRAM). It cannot be directly applied to communication interfaces that require encryption protection.

[0004] Therefore, there is an urgent need for a PDMA control device and method with an encryption control module. The encryption engine is built into the PDMA controller, which can not only automatically allocate channels according to the time occupied by data transmission in each PDMA channel, but also meet the requirement of data encryption on all communication interfaces. Summary of the Invention

[0005] One objective of this invention is to provide an automatic channel management peripheral direct memory access control device with an encryption control module, applicable to at least one peripheral, including at least one channel, an encryption control module, embedded static random access memory, a peripheral request preprocessing module, and a channel control module. The encryption control module includes an encryption engine, a true random number generator, and a key storage module. The embedded static random access memory stores a channel description table for each channel and records at least one transmission message, and includes block encryption storage space. It is signal-connected to the encryption control module to implement block encryption and key management functions. The peripheral request preprocessing module processes requests issued by the at least one peripheral. The channel control module selects a suitable channel from the at least one peripheral for data transmission based on the information provided by the peripheral request preprocessing module.

[0006] Another objective of this invention is to provide an automatic channel management peripheral direct memory access control method with an encryption control module, applicable to at least one peripheral, comprising: setting up an automatic channel management peripheral direct memory access control device with an encryption control module, enabling one or more channels; when the automatic channel management peripheral direct memory access control device with an encryption control module receives a request from the at least one peripheral, starting a timer to record the start time of transmission, simultaneously obtaining a peripheral description table to confirm the peripheral identifier and the amount of data to be transmitted, and estimating the required transmission time based on the previous transmission time and the amount of data transmitted recorded in the recording buffer; selecting the channel currently occupying the shortest transmission time according to the number of incomplete requests and allocating it to the next received request, while updating the peripheral description table to the channel description table of the channel; performing data transmission, pausing the timer while waiting for data transmission, and resuming the timer when data transmission begins; if an encryption algorithm is triggered, performing encryption control, through the automatic channel management peripheral direct memory access control device built into the encryption control module. The encryption engine, true random number generator, key storage module, and block encryption storage space in the embedded static random access memory of the automatic channel management peripheral direct memory access control device with encryption control module are operated to realize hardware acceleration functions for encryption and decryption; when a channel completes data transmission, the validity of the next peripheral description table is checked, and the transmission time is updated to the record buffer; if the next peripheral description table exists, the next peripheral description table of the available channel is obtained, and data transmission is performed again; and if the next peripheral description table does not exist, the peripheral description table of the available channel is removed and the transmission model is updated, and data transmission is completed.

[0007] As can be seen from the above, the PDMA control device with encryption control module provided by the present invention has an encryption engine built into the PDMA controller. In addition to automatically allocating channels according to the time that data transmission will take up at the moment of each PDMA channel, it can also meet the requirement of data encryption on all communication interfaces. Attached Figure Description

[0008] The accompanying drawings are provided to enable those skilled in the art to further understand the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and are used, together with the specification, to explain the principles of the invention. A brief description of the figures follows:

[0009] Figure 1 Designed for well-known cryptographic accelerators.

[0010] Figure 2 This is a device architecture diagram of an automatic channel management PDMA control device with an encryption control module according to an embodiment of the present invention.

[0011] Figure 3 This is a flowchart of an automatic channel management PDMA control device with an encryption control module according to an embodiment of the present invention.

[0012] Explanation of reference numerals in the attached figures:

[0013] 102… Advanced Microcontroller Bus Architecture (AMBA); 104… Advanced High-Performance Bus Wrapper (AHBwrapper); 106… Advanced High-Performance Bus Arbiter (AHB arbiter); 108… DMA Cache; 110… Pseudo-Random Number Generator (PRNG); 11… Master Channel; 12… Slave Channel; 111a, 111b… First-In-First-Out (FIFO); 112a, 112b, 112c, 112d… Direct Memory Access (DMA); 113a, 113b, 113c, 113d… Finite State Machine; 114a… AES Algorithm; 114b… TDES Algorithm; 114c… HMAC Algorithm; 114d… ECC Algorithm; 115a… AES Engine; 115b… TDES / DES Engine; 115c… HMAC Engine; 115d… ECC Engine; 200… Automatic channel management PDMA control device with encryption control module; 202… Embedded SRAM; 203… Channel description table; 204a, 204b, …, 204n… Peripheral description table; 205… Record buffer; 210… Peripheral request preprocessing module; 212… Timer; 214… Peripheral description table; 216… Transmission model; 220… Channel control module; 222a… Channel 0; 222b… Channel 1; 222m… Channel m; 230… Encryption control module; 232… Encryption engine; 234… True random number generator; 236… Key storage module; 242… Block encryption storage space; 250a… Peripheral description table 0; 250n… Peripheral description table n; 252a… Peripheral 0; 252n… Peripheral n; S302~S324… Steps. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any inventive contributions are within the scope of protection of the present invention.

[0015] In view of the above problems, the present invention provides a PDMA control device with an encryption control module. The encryption engine is built into the PDMA controller. In addition to automatically allocating channels according to the time occupied by data transmission in each PDMA channel, it can also meet the requirement of data encryption on all communication interfaces.

[0016] Please see Figure 2This invention provides an automatic channel management (PDMA) control device 200 with an encryption control module, including an embedded static random access memory (SRAM) 202 for storing a channel descriptor table for each PDMA channel and recording valid transmission messages. In an embodiment with m channels and n peripherals (where the number of channels m is less than the number of peripherals n), the channel descriptor tables 203 for channels 0, 1, ..., m are stored in the embedded SRAM 202 respectively. For each peripheral, peripheral descriptor tables 204a, 204b, ..., 204n are stored in the embedded SRAM 202, storing the descriptor table for each channel for each peripheral. For example, peripheral description table 204a includes description table P(0) for peripheral 0 to channel 0, description table P(1) for peripheral 1 to channel 1, ..., description table P(m) for peripheral m to channel m. Peripheral description table 204b includes description table P(m+1) for peripheral (m+1) to channel 0, description table P(m+2) for peripheral (m+2) to channel 1, ..., description table P(2m) for peripheral 2m to channel m, .... Peripheral description table 204n includes description table P(nm) for peripheral (nm) to channel 0, description table P(n-m+1) for peripheral (n-m+1) to channel 1, ..., description table P(n) for peripheral n to channel m. Embedded SRAM 202 also includes record buffer 205 for recording valid transmission information, such as peripheral identifier (ID), amount of data transmitted, transmission time, etc.

[0017] The automatic channel management PDMA control device 200 with encryption control module further includes a perimeter request preprocessing module 210 for processing PDMA requests from the perimeter. The perimeter request preprocessing module 210 includes a timer 212, a perimeter description table 214, and a transmission model 216. When a request signal is received from the perimeter, the perimeter request preprocessing module 210 starts the timer 212 to record the transmission time. This timer 212 uses hardware timing, so it does not require baud information from the signal transmission to record the transmission time. Simultaneously, the perimeter request preprocessing module 210 obtains the perimeter description table 214 from the perimeter (e.g., perimeter description table 0 250a for perimeter 0 252a, ..., perimeter description table n 250n for perimeter n 252n) to confirm the transmission type, the amount of data transmitted, the perimeter identifier (ID), and whether encryption / decryption operations are required. The perimeter request preprocessing module 210 also includes a transmission model 216, which can estimate the required transmission time based on previous valid transmission records, including transmission time and the amount of data transmitted.

[0018] The automatic channel management PDMA control device 200 with encryption control module also includes a channel control module 220, which selects a suitable PDMA channel (e.g., channel 0 222a, channel 1 222b, ..., channel m 222m) for data transmission based on the information provided by the perimeter request preprocessing module 210. When all channels are active, the channel control module 220 can also allocate the channel with the least transmission time to a newly received perimeter request based on the currently pending transmission requests, and update the perimeter description table to the channel description table of this channel.

[0019] The Automatic Channel Management (PDMA) control device 200 with an encryption control module also includes an encryption control module 230, providing an encryption engine 232, a true random number generator (TRNG) 234, and a key storage module 236. The encryption engine 232 supports various encryption algorithms, such as, but not limited to, Advanced Encryption Standard (AES), Data Encryption Standard / Triple Data Encryption Standard (DES / TDES), Secure Hash Algorithm (SHA), Hash Message Authentication Code (HMAC), and Elliptic Curve Cryptography (ECC). The embedded SRAM 202 contains a block encryption storage space 242, which is signal-connected to the encryption control module 230, used to implement block encryption and key management functions. By integrating the encryption module into the PDMA control device and its internal embedded SRAM, the requirement for data encryption on all communication interfaces can be met. The encryption principles and steps of the encryption engine 232, the true random number generator 234, the key storage module 236, and the block encryption storage space 242 are well-known technologies and will not be elaborated here.

[0020] This invention also provides a PDMA control method with an encryption control module, which can automatically allocate channels based on the current data transmission time of each PDMA channel, and also meet the requirement of data encryption on all communication interfaces. Please refer to [link to relevant documentation]. Figure 3 See also Figure 2 To gain a more detailed understanding of the operation flow of the PDMA control method with encryption control module provided by this invention.

[0021] First, in step S302, the process begins.

[0022] Next, in step S304, the automatic channel management PDMA control device 200 with encryption control module is configured to enable one or more PDMA channels.

[0023] Subsequently, in step S306, the process splits into two paths depending on whether there is a surrounding transmission request. If yes, the process proceeds to step S308. If no, the process returns to step S304.

[0024] In step S308, when the automatic channel management PDMA control device receives a peripheral transmission request signal from the peripheral, the peripheral request preprocessing module 210 starts timer 212 to record the start time of transmission, and obtains the peripheral description table 214 to confirm the peripheral identifier (ID) and the amount of data to be transmitted. Based on the previous transmission time and the amount of data to be transmitted recorded in the recording buffer 205, the next required transmission time is estimated.

[0025] Subsequently, in step S310, the channel control module 220 selects the channel with the shortest transmission time currently occupied based on the number of uncompleted requests and allocates it to the next received peripheral request, while updating the peripheral description table to the channel description table of this channel.

[0026] Subsequently, in step S312, PDMA data transmission is performed. While waiting for PDMA data transmission, timer 212 is paused and resumed when data transmission begins.

[0027] Subsequently, in step S314, the process splits into two paths based on whether the available PDMA has completed the transmission. If yes, the process proceeds to step S316. If no, the process returns to step S312 to continue data transmission.

[0028] In step S316, after the PDMA completes a data transmission service, if encryption is required, the data is temporarily stored in the block encryption storage space 242 in the embedded SRAM 202, and the encryption engine 232 implements hardware acceleration for encryption and decryption. If encryption is not required, the validity of the next peripheral description table is checked, and the transmission time is updated to the record buffer 205. Depending on whether the encryption algorithm (e.g., AES) is triggered, the process proceeds to step S318. If not, the process proceeds to step S320. It should be noted that since the automatic channel management PDMA control device 200 with an encryption control module provided by this invention does not require software intervention in channel management, the determination of whether the encryption algorithm is triggered is based on the data in the PDMA control register. Figure 2 The determination depends on whether there are encryption / decryption operation requirements recorded in the data (not shown in the text).

[0029] In step S318, encryption control is performed. The encryption engine 232, true random number generator 234, key storage module 236, and block encryption storage space 242 built into the automatic channel management PDMA control device 200 with encryption control module are used to realize the hardware acceleration function of encryption and decryption.

[0030] In step S320, when a channel completes data transmission, the validity of the next peripheral description table is checked, and the transmission time is updated to the record buffer 205. Depending on whether the next peripheral description table exists, the process proceeds to two paths. If yes, the process continues to step S322. If no, the process continues to step S324.

[0031] In step S322, the next-next-peripheral description table of the available PDMA channels is obtained. Then, the process returns to step S312, and data transmission is performed again.

[0032] In step S324, the surrounding description table of the available PDMA channel is removed and the transmission model is updated. Data transmission is completed and the process ends.

[0033] As can be seen from the above, the PDMA control device with encryption control module provided by the present invention has an encryption engine built into the PDMA controller. In addition to automatically allocating channels according to the time that data transmission will take up at the moment of each PDMA channel, it can also meet the requirement of data encryption on all communication interfaces.

[0034] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An automatic channel management peripheral direct memory access control device with an encryption control module, applicable to at least one peripheral, characterized in that, include: At least one channel; An encryption control module includes an encryption engine, a true random number generator, and a key storage module; An embedded static random access memory is used to store a channel description table for each of the channels and to record at least one transmission message, and includes a block encryption storage space, which is signal-connected to the encryption control module to implement block encryption and key management functions. A peripheral request preprocessing module is used to process a request issued by the at least one peripheral entity; as well as A channel control module selects a suitable channel from the at least one channel for data transmission based on the information provided by the peripheral request preprocessing module.

2. The automatic channel management peripheral direct memory access control device with an encryption control module as described in claim 1, characterized in that, For each of the aforementioned peripherals, a peripheral description table is stored in the embedded static random access memory, which stores the description table of each peripheral for each of the aforementioned channels.

3. The automatic channel management peripheral direct memory access control device with an encryption control module as described in claim 1, characterized in that, The embedded static random access memory includes a recording buffer for recording the at least one transmission message.

4. The automatic channel management peripheral direct memory access control device with an encryption control module as described in claim 3, characterized in that, The at least one transmission message includes a combination of the following items: a perimeter identifier, a transmission data volume, and a transmission time.

5. The automatic channel management peripheral direct memory access control device with an encryption control module as described in claim 1, characterized in that, The surrounding request preprocessing module includes a timer. When the request is received from the surrounding area, the surrounding request preprocessing module starts the timer to record a transmission time.

6. The automatic channel management peripheral direct memory access control device with an encryption control module as described in claim 1, characterized in that, The perimeter request preprocessing module obtains at least one perimeter description table from the at least one perimeter to confirm a transmission type, a transmission data volume, a perimeter identifier, and whether encryption / decryption operations are required.

7. The automatic channel management peripheral direct memory access control device with an encryption control module as described in claim 1, characterized in that, The peripheral request preprocessing module includes a transmission model that estimates a second transmission time based on a previous transmission record, wherein the previous transmission record includes a first transmission time and a transmission data volume.

8. The automatic channel management peripheral direct memory access control device with an encryption control module as described in claim 1, characterized in that, When all of the aforementioned channels are available, the channel control module allocates the channel with the least transmission time to the newly received request based on the currently pending requests, and updates a surrounding description table to the channel description table of the channel.

9. The automatic channel management peripheral direct memory access control device with an encryption control module as described in claim 1, characterized in that, The encryption engine supports a combination of the following algorithms: Advanced Encryption Standard (AES), Data Encryption Standard / Triple Data Encryption Standard (DES / TDES), Secure Hash Algorithm (SHA), Hash Message Authentication Code (HMAC), and Elliptic Curve Cryptography (ECC).

10. An automatic channel management peripheral direct memory access control method with an encryption control module, applicable to at least one peripheral, characterized in that: Configure an automatic channel management peripheral direct memory access control device with an encryption control module to enable one or more channels; When the automatic channel management peripheral direct memory access control device with encryption control module receives a request from at least one peripheral, it starts a timer to record the start time of transmission, obtains a peripheral description table to identify a peripheral identifier and a transmission data volume, and estimates the next required transmission time based on the previous transmission time and transmission data volume recorded in a recording buffer. Based on the number of uncompleted requests, select the channel with the shortest current transmission time and allocate it to the next received request, while updating the surrounding description table to the channel description table of the channel. During data transmission, the timer is paused while waiting for data transmission to occur, and then resumed when data transmission begins. If the encryption algorithm is triggered, encryption control is performed. The hardware acceleration function of encryption and decryption is realized through the operation of an encryption engine, a true random number generator, a key storage module, and a block encryption storage space in an embedded static random access memory in the automatic channel management peripheral direct memory access control device with encryption control module. When a channel completes data transmission, check if the next surrounding description table is valid and update the transmission time to the record buffer; If the next-next-peripheral description table exists, obtain the next-next-peripheral description table of an available channel and perform data transmission again; as well as If the next surrounding description table does not exist, remove the surrounding description table of the available channel and update a transmission model, and the data transmission is completed.

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