A dynamic reconfigurable interface system of commercial secret and anti-quantum cryptography algorithm

Abstract

The application relates to the fields of network security communication and digital integrated circuit technology, and discloses a dynamic reconfigurable interface system of commercial secret and anti-quantum cryptographic algorithm, which comprises a northbound interface module, a metadata manager, an algorithm adaptation layer, a dynamic reconfiguration engine, a dynamic partial reconfiguration subsystem, a cryptographic acceleration core and an output link module. The application extracts the hardware resource demand and the number of concurrent flip lines by loading the algorithm metadata file, and calculates the transient protection duration in combination with the bus electrical parameter; then, the reconfiguration scheduling instruction is generated based on the duration, the target partition is guided to complete the boundary isolation, transaction emptying, local bitstream loading and synchronous reset; when the plaintext data is ready at the output end, the output waiting window equivalent to the transient protection duration is forced to enter, and the electric signal sequence is emitted outward after the signal interference is attenuated. The application realizes high real-time dynamic core replacement, and significantly improves the electrical reliability of bus transmission.

Description

Technical Field

[0001] This invention relates to the fields of network security communication and digital integrated circuit technology, and more specifically, to a dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms. Background Technology

[0002] With the continuous evolution of information security standards, modern cryptographic devices not only need to support traditional commercial cryptographic standards but also need to be compatible with new quantum-resistant cryptographic algorithms for the future. To balance the support of multiple algorithms and computational performance with limited hardware resources, dynamic local reconfiguration technology for dynamically hot-swapping cryptographic acceleration cores on programmable devices such as field-programmable gate arrays has become an important development direction for current cryptographic interface systems. In existing dynamic reconfigurable interface systems, to achieve seamless hot-swapping of algorithm cores, the system must sequentially execute a series of core operations during operation, including forced termination of bus transactions, boundary isolation of reconfiguration regions, loading of local reconfiguration data streams, and synchronous reset of modules after loading. However, while this dynamic core-swapping mechanism greatly improves system flexibility, it also introduces insurmountable underlying electrical reliability conflicts. Specifically, when the reconfiguration process ends and the cryptographic acceleration core is de-reset and data output resumes instantaneously, a high-density synchronous switching output will be formed in a very short time due to the state switching of a large number of data cables and control cables at the same clock edge. This high-density synchronous switching action will inevitably cause significant synchronous switching noise on the underlying communication bus, such as ground bounce. The direct manifestation of this noise is that, in the initial stage of each core swap, the plaintext electrical signal sequence inevitably experiences a transient jitter period with abnormal amplitude fluctuations (i.e., the start-up transient tail segment). In existing technologies, traditional general interface control mechanisms do not incorporate the aforementioned transient electrical interference caused by dynamic reconfiguration into the system's global scheduling considerations. This leads to a dilemma for existing systems: blindly increasing the global waiting delay to ensure the stability of the backend receiver's signal decision will severely compromise the real-time response capability of dynamic core swapping, resulting in a significant increase in end-to-end latency and failing to meet the calling requirements of high-speed cryptographic devices; conversely, allowing the bus to transmit plaintext electrical signals directly without intervention during the transient jitter period will cause severe short-term bit errors due to the drastic fluctuations in bus levels, greatly reducing the electrical reliability of plaintext data transmission. Summary of the Invention

[0003] This invention provides a dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms, solving the technical problems mentioned in the background art.

[0004] This invention provides a dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms: Metadata manager is used to receive call parameter packages, load the algorithm metadata file corresponding to the call parameter packages, and parse and generate hardware mapping constraints; The algorithm adaptation layer is used to extract the hardware resource requirements and the number of concurrent switching lines set in the bus output terminal of the system according to the hardware mapping constraints, and to calculate the transient protection duration in combination with the bus electrical parameters. The dynamic reconfiguration engine is used to generate reconfiguration scheduling instructions based on the transient protection duration and the hardware resource requirements. The dynamic partial reconfiguration subsystem is used to implement boundary isolation and bus transaction termination on the target partition in the reconfigurable area of ​​the system according to the reconfiguration scheduling instruction to clear the in-transit transactions, then load the partial reconfiguration data stream into the target partition, and perform synchronous reset after the reconfiguration is completed. A cryptographic acceleration core, located within the target partition, is used to initiate computation after the synchronization reset is completed, converting input data into output plaintext data and writing it into a static area cache within the system. The output link module is used to enter an output waiting window with a duration equal to the transient protection duration when the output plaintext data is detected to be ready; to maintain the bus in an idle state within the output waiting window to wait for signal interference to attenuate; and to convert the output plaintext data into an electrical signal sequence and transmit it outward after the output waiting window ends.

[0005] The beneficial effects of this invention are as follows: by introducing transient protection duration as a core constraint resource, the interference attenuation period caused by high-density synchronous switching is accurately evaluated during dynamic core replacement, and a global scheduling instruction and a forced execution output waiting window are generated based on this period. Thus, without compromising the high real-time response capability of dynamic hot replacement of cryptographic algorithms, the level jitter and short-time bit errors of the plaintext electrical signal sequence at the output end during the burst period are effectively avoided, and the technical conflict between real-time scheduling and the reliability of underlying bus communication in traditional core replacement mechanisms is completely resolved. Attached Figure Description

[0006] Figure 1 This is a flowchart of a dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms of the present invention; Figure 2 This is a schematic diagram of a dynamically reconfigurable interface system architecture for commercial cryptography and quantum-resistant cryptographic algorithms according to the present invention. Detailed Implementation

[0007] The subject matter described herein will now be discussed with reference to exemplary embodiments. It should be understood that these embodiments are discussed only to enable those skilled in the art to better understand and implement the subject matter described herein, and changes may be made to the function and arrangement of the elements discussed without departing from the scope of this specification. Various processes or components may be omitted, substituted, or added as needed in the examples. Furthermore, features described in some examples may be combined in other examples.

[0008] like Figure 1 As shown, a dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms is presented: Metadata manager is used to receive call parameter packages, load the algorithm metadata file corresponding to the call parameter packages, and parse and generate hardware mapping constraints; The algorithm adaptation layer is used to extract the hardware resource requirements and the number of concurrent switching lines set in the bus output terminal of the system according to the hardware mapping constraints, and to calculate the transient protection duration in combination with the bus electrical parameters. The dynamic reconfiguration engine is used to generate reconfiguration scheduling instructions based on the transient protection duration and the hardware resource requirements. The dynamic partial reconfiguration subsystem is used to implement boundary isolation and bus transaction termination on the target partition in the reconfigurable area of ​​the system according to the reconfiguration scheduling instruction to clear the in-transit transactions, then load the partial reconfiguration data stream into the target partition, and perform synchronous reset after the reconfiguration is completed. A cryptographic acceleration core, located within the target partition, is used to initiate computation after the synchronization reset is completed, converting input data into output plaintext data and writing it into a static area cache within the system. The output link module is used to enter an output waiting window with a duration equal to the transient protection duration when the output plaintext data is detected to be ready; to maintain the bus in an idle state within the output waiting window to wait for signal interference to attenuate; and to convert the output plaintext data into an electrical signal sequence and transmit it outward after the output waiting window ends.

[0009] Preferably, the metadata manager receives the call parameter package and loads the algorithm metadata file corresponding to the call parameter package, and parses it to generate hardware mapping constraints, including: extracting the algorithm category identifier, cryptographic operation type, and message length from the call parameter package P. End-to-end latency requirement D; Bus symbol rate and bus parallel bit width ; Set the maximum allowed loading time And it satisfies the calculation formula: Within the maximum allowed loading time, the retrieval and reading of the algorithm metadata file J are completed; normalized semantic expansion processing is performed on the read algorithm metadata file J to generate the hardware mapping constraint G, which satisfies the calculation formula: In the formula, This indicates the normalized semantic expansion process; the parameter extraction operation is performed by combining the invocation parameter package with the hardware mapping constraints. Obtain the security level number s and the operation mode index m; The security level number, the operation mode index, the message bit length, the end-to-end latency requirement, the bus symbol rate, and the bus parallel bit width are assembled into a joint parameter group p, which serves as the input for the algorithm adaptation layer to call, and satisfies the calculation formula: In the formula, p is the joint parameter set.

[0010] Algorithm category identifiers are unique identifiers used to distinguish between commercial cryptographic algorithms and quantum-resistant cryptographic algorithms. Cryptographic operation type refers to the type of operation the cryptographic algorithm performs. Message bit length refers to the length of the data to be processed, measured in bits. End-to-end latency requirement refers to the maximum allowed time from receiving the call request to outputting the processing result, measured in seconds. Bus symbol rate refers to the number of symbols transmitted per second on the physical bus, measured in symbols per second. Bus parallel bit width refers to the number of bits of data transmitted per transmission on the physical bus. The call parameter packet is a structured data set containing algorithm configuration, data information, constraints, etc. The algorithm metadata file is a structured file that records information such as algorithm hardware requirements, parameter configuration, and implementation constraints.

[0011] The maximum allowed loading time is the longest permitted time for retrieving, reading, and initially parsing the algorithm metadata file, measured in milliseconds. It is preferably the smaller of one-tenth of the end-to-end latency requirement and 5 milliseconds. The standardized semantic expansion processing rules are the operational guidelines for semantic parsing and format standardization of the algorithm metadata file, preferably following the JSON-LD (Semantic Data Format) version 1.1 expansion specification. Hardware mapping constraints are structured data containing information such as the algorithm's corresponding hardware resource requirements, interface constraints, and implementation rules, consisting of entity nodes and associated paths. The parameter extraction operation is the operational logic for extracting key configuration parameters from the call parameter package and hardware mapping constraints and assembling them. The security level number is a number that distinguishes different security strength configurations of the algorithm, preferably an integer from 1 to 5, corresponding to different security levels, meeting the industry's common security level classification standards, and facilitating system adaptation to different security requirements. The operation mode index is an index value that digitally identifies the cryptographic operation type, preferably an integer from 1 to 6, corresponding to encryption, decryption, signing, signature verification, key encapsulation, and key decapsulation operations, respectively. The joint parameter group is a structured data set integrating key parameters such as the security level number, operation mode index, and message length, preferably in the form of an ordered parameter vector. Entity nodes are the basic data units in hardware mapping constraints, used to record single hardware resource requirements or constraint information. They are preferably structured data items containing entity type, attributes, and values. Association paths are the connection information in hardware mapping constraints used to represent the logical relationships between entity nodes, preferably in the form of ordered associations between entity node identifiers. A latency ratio of 0.1 is a fixed ratio used to calculate the maximum allowable loading time, preferably 0.1, which strikes a balance between loading reliability and real-time performance. A 5-millisecond maximum loading time threshold is the upper limit of the maximum allowable loading time, measured in milliseconds, preferably 5 milliseconds. Considering the read speed of hardware storage media and the typical size of metadata files, 5 milliseconds can meet the metadata loading requirements in most scenarios.

[0012] The rules for setting the maximum allowable loading time are as follows: the end-to-end latency requirement is a real-time constraint of the entire system. One-tenth of it is used as the reference upper limit for loading time because metadata loading is only one step in the system processing flow, and sufficient time needs to be reserved for subsequent hardware mapping, reconfiguration scheduling, algorithm calculation and other steps; at the same time, a fixed upper limit of 5 milliseconds is set to take into account that even if the end-to-end latency requirement is large (such as exceeding 50 milliseconds), metadata loading does not need to consume too much time, so as to avoid resource waste.

[0013] The method for normalized semantic expansion is as follows: First, parse the context definition in the algorithm metadata file to identify the abbreviated terms and relative resource identifiers; then, based on the context mapping relationship, replace the abbreviated terms with complete terms and convert the relative resource identifiers into absolute resource locators; finally, sort out the various types of information in the metadata to construct structured data containing entity nodes and associated paths.

[0014] The hardware mapping constraints are constructed as follows: First, unstructured or semi-structured information in the metadata file is converted into structured data through normalized semantic expansion; then, key hardware-related information, such as hardware resource requirements, interface protocol types, and implementation constraints, is extracted from it and used as entity nodes; finally, based on the logical relationships between the entity nodes, such as resource dependencies and interface adaptation relationships, an association path is established to form a complete hardware mapping constraint.

[0015] The execution standard for normalized semantic expansion processing is as follows: the expansion specification of JSON-LD version 1.1 is adopted, and the execution steps include parsing the context definition in the metadata file, identifying abbreviated terms and relative resource identifiers, replacing them with the full form according to the context mapping relationship, verifying semantic consistency, and constructing structured entity nodes and associated paths.

[0016] In hardware mapping constraints, entity nodes and associated paths are defined as follows: An entity node is a structured data item containing four elements: identifier, attribute, value, and constraint. The identifier is a unique absolute resource locator, the attribute indicates the node type, the value is a parameter value, and the constraint is the range of values ​​or implementation requirements. An associated path is an identifier that represents the logical relationship between entity nodes, including three types: containment relationship, dependency relationship, and adaptation relationship, which are represented by has, needs, and adaptsTo, respectively.

[0017] The exception handling method for exceeding the maximum allowed loading time is as follows: If the metadata loading time exceeds the maximum allowed loading time, the loading operation is terminated immediately and the relevant resources are released; an error response frame is generated with the error code set to 1001 and the error description is metadata loading timeout; the error response frame is returned to the upper layer application through the northbound interface, and a loading timeout log is recorded, including the request identifier, timeout time, loading progress and other information.

[0018] Preferably, the algorithm adaptation layer extracts the hardware resource requirements and the number of concurrent switching lines at the bus output end based on the hardware mapping constraints, and calculates the transient protection duration in combination with the bus electrical parameters, including: Extract the following from the hardware mapping constraint G: number of lookup tables (LUTs), number of flip-flops (FFs), number of block random access memories (BRAMs), number of digital signal processing units (DSPs), and desired clock frequency. Candidate partition set On-chip interconnect bus protocol type Combine these into the hardware resource requirement h, and satisfy: Obtain the number of control lines from the hardware mapping constraint G. Perform static timing analysis on the bus output to obtain the percentage of cables that undergo state switching within a preset alignment window, and use this percentage as the edge alignment. The number of concurrent toggle lines is calculated based on the number of control lines, the parallel bus width, and the edge alignment. And satisfy: Obtain the bus electrical parameters The bus electrical parameters include single-wire load capacitance. Equivalent inductance Edge transition time Voltage swing decay time constant and allowable transient threshold ; Calculate the initial ground bounce amplitude And satisfy: Calculate decay time And satisfy: Based on the attenuation time and the bus symbol rate Calculate the transient protection duration k, which satisfies: In the formula, Indicates the minimum protection threshold. This indicates the maximum protection threshold.

[0019] The number of lookup tables is the total number of lookup table cells required to implement logic functions in a Field-Programmable Gate Array (FPGA). The number of flip-flops is the total number of flip-flop cells used to store data or state in the FPGA. The number of block random access memory (BRAM) cells used for data caching in the FPGA is typically measured in 36 kilobits. The number of digital signal processing units (DSPs) is the total number of dedicated processing units used to implement digital signal operations in the FPGA. The desired clock frequency is the clock signal frequency required for the cryptographic acceleration core to operate normally, measured in Hertz (Hz). The candidate partition set is the set of reconfigurable partition identifiers within the reconfigurable region of the system that can accommodate the current cryptographic acceleration core. The on-chip interconnect bus protocol type is the bus protocol type followed for data transmission between the system's internal static area and reconfigurable partitions. The number of control lines is the total number of cables used to transmit control signals at the bus output. The single-wire load capacitance is the equivalent load capacitance carried by a single data cable on the bus, including pin capacitance, trace capacitance, and receiver input capacitance, measured in picofarads (PFAs). Equivalent inductance is the combined equivalent inductance of the bus cable and return path, including package inductance, via inductance, and loop inductance, measured in nanohenries. Edge transition time is the time it takes for a bus signal to switch from low to high or vice versa, measured in nanoseconds. Voltage swing is the voltage difference between a high and low bus signal level, measured in volts. Decay time constant is the time constant for bus synchronization switching noise to decay to a negligible level, measured in nanoseconds. Allowable transient threshold is the maximum allowable bus transient noise amplitude for the receiver to correctly determine the signal, measured in millivolts.

[0020] The hardware resource requirements are a structured data set containing the quantity of various hardware resources, clock constraints, and interface protocols required for the integrated cryptographic acceleration core. Preferably, it is an ordered parameter vector including the number of lookup tables, triggers, block random access memory, digital signal processing units, desired clock frequency, candidate partition set, and on-chip interconnect bus protocol type. The preset alignment window is a time window used to statistically analyze the proportion of synchronous switching of bus cables, measured in nanoseconds. It is preferably the larger of 0.1 times the edge transition time and 0.5 nanoseconds to ensure accurate capture of cable synchronous switching behavior while avoiding statistical distortion due to an excessively large window. The edge alignment degree is the ratio of the number of bus cables undergoing state switching within the preset alignment window to the total number of bus cables, ranging from 0 to 1, to quantify the density of cable synchronous switching. The total number of bus cables is the sum of the number of data cables and control cables at the bus output end, preferably the sum of the bus parallel bit width and the number of control lines, to comprehensively cover all cables that may participate in switching and ensure the accuracy of noise calculation. The concurrent flip-over line count is the number of bus cables simultaneously switching states within a preset alignment window. It is preferably the product of the total number of bus cables and the edge alignment, rounded to the nearest integer to quantify the scale of cables switching synchronously, directly related to the intensity of synchronous switching noise. The bus electrical parameter set is a collection of integrated electrical characteristic parameters related to bus transmission. It is preferably a set of parameters including single-wire load capacitance, equivalent inductance, edge transition time, voltage swing, decay time constant, and allowable transient threshold, as the system encompasses key electrical factors affecting bus noise. The single-wire current change rate is the rate of current change of a single bus cable during state switching, measured in amperes per second. It is preferably the product of single-wire load capacitance and voltage swing, divided by the square of the edge transition time, to accurately reflect the current change characteristics during single-wire switching based on the principle of capacitor charging and discharging. The initial ground bounce amplitude is the initial ground bounce noise amplitude caused by concurrent bus flip-over, measured in volts. It is preferably the product of the single-wire current change rate, the concurrent flip-over line count, and the equivalent inductance, to quantify the noise intensity caused by synchronous switching based on the principle of electromagnetic induction. The attenuation time is the time required for the initial ground bounce amplitude to decay to the allowable transient threshold, measured in seconds. Preferably, when the initial ground bounce amplitude is greater than the allowable transient threshold, it is the product of the attenuation time constant and the natural logarithm of the ratio of the initial ground bounce amplitude to the allowable transient threshold. When the initial ground bounce amplitude is less than or equal to the allowable transient threshold, it is set to 0, to accurately calculate the time it takes for noise to decay to a safe level based on an exponential attenuation model. The initial symbol length is the number of symbols the bus can transmit within the attenuation time, preferably the product of the attenuation time and the bus symbol rate, to convert the time-dimensional attenuation time into the symbol-dimensional bus transmission. The minimum protection threshold is the minimum value of the transient protection duration, measured in symbols, preferably 1, to ensure that even with an extremely short attenuation time, at least one symbol cycle of protection is provided, avoiding the impact of synchronization switching noise.The maximum protection threshold is the maximum value of the transient protection duration, expressed in symbols, preferably 4096, to balance protection effectiveness and system real-time performance, avoiding excessive end-to-end delay due to excessive protection duration. The transient protection duration is the number of symbols corresponding to the output waiting window duration, used to wait for synchronous switching noise attenuation. Ideally, it is the maximum value of the initial symbol length and the minimum protection threshold, plus the minimum value of the maximum protection threshold, to ensure sufficient noise attenuation while limiting the upper limit of the protection duration, thus guaranteeing system real-time performance. Static timing analysis rules are the operational guidelines for analyzing the switching timing of the bus output cables. Preferably, it is based on a timing constraint file, analyzing the switching arrival time from cable reset release to the first output cycle to obtain the timing distribution of cable switching.

[0021] The edge alignment is calculated as follows: First, determine the duration of the preset alignment window to ensure that the window can cover the time period of concentrated cable switching; then, perform static timing analysis on all cables at the bus output end to obtain the switching arrival time of each cable in the first frame after the output is restored; count the number of cables whose switching arrival time falls within the preset alignment window; finally, divide this number by the total number of bus cables to obtain the edge alignment.

[0022] The calculation logic for the concurrent switching line count is as follows: the total number of bus cables covers all data and control cables that may participate in the switching, and the edge alignment reflects the proportion of these cables switching synchronously within the same time window. Multiplying the two values ​​quantifies the scale of cables switching synchronously, and this value determines the intensity of synchronous switching noise.

[0023] The initial ground bounce amplitude is calculated as follows: the single-wire current change rate reflects the intensity of current change during single-wire switching; the number of concurrent switching lines determines the cable size for synchronous switching; and the equivalent inductance reflects the electromagnetic induction characteristics of the bus loop. Multiplying these three factors allows for accurate calculation of the initial ground bounce noise amplitude caused by synchronous switching based on the principle of electromagnetic induction.

[0024] The logic for determining attenuation time is as follows: The allowable transient threshold is the maximum noise tolerance at which the receiver can operate normally. When the initial ground bounce amplitude is greater than this threshold, data transmission must wait for the noise to attenuate below the threshold. At this time, the attenuation time is calculated by the natural logarithm of the attenuation time constant and the amplitude ratio, which can accurately reflect the time pattern of noise attenuation. When the initial ground bounce amplitude is less than or equal to the allowable transient threshold, the noise itself will not affect the receiver's decision, so the attenuation time is set to 0.

[0025] The calculation rules for transient protection duration are as follows: the initial symbol length converts the attenuation time into the symbol dimension of bus transmission to ensure that the protection duration matches the bus transmission rhythm; the maximum value is taken with the minimum protection threshold to avoid insufficient protection due to excessively short attenuation time; the minimum value is taken with the maximum protection threshold to prevent the real-time performance of the system from deteriorating due to excessively long attenuation time.

[0026] The default alignment window is determined by the larger of 0.1 times the edge transition time and 0.5 nanoseconds. The calibration method for the default alignment window is as follows: First, refer to the device datasheet for the typical edge transition time of the bus output device. If the edge transition time given in the datasheet is 1 nanosecond, then 0.1 times the edge transition time is 0.1 nanoseconds, which is less than 0.5 nanoseconds, so the default alignment window is 0.5 nanoseconds. If the edge transition time is 6 nanoseconds, then 0.1 times the edge transition time is 0.6 nanoseconds, which is greater than 0.5 nanoseconds, so the default alignment window is 0.6 nanoseconds.

[0027] The minimum protection threshold is fixed at 1 symbol. The maximum protection threshold is fixed at 4096 symbols. The minimum protection threshold is the system default configuration and cannot be modified, ensuring basic protection is provided even with extremely short attenuation times. The maximum protection threshold can be flexibly configured according to the system's end-to-end latency requirements, but it must not exceed 4096 symbols. When configuring, it is necessary to ensure that the end-to-end latency meets the requirements in the calling parameter package.

[0028] The criterion for determining the state transition of the bus output cable is the moment when the cable voltage amplitude crosses a decision threshold. The decision threshold is 50% of the voltage swing; that is, when the cable voltage rises from a low level to 50% of the voltage swing, it is determined to be a transition from low to high level; when the cable voltage falls from a high level to 50% of the voltage swing, it is determined to be a transition from high to low level. If the cable does not cross the decision threshold within the analysis period, it is determined that no state transition has occurred.

[0029] The effective range for edge alignment is 0.1 to 0.9. If the value is less than 0.1, it indicates that the cable switching is dispersed and the synchronous switching noise has minimal impact. If the value is greater than 0.9, it indicates that the cable switching is highly concentrated and the synchronous switching noise has a significant impact, requiring close attention.

[0030] Preferably, the dynamic reconfiguration engine generates reconfiguration scheduling instructions based on the transient protection duration and the hardware resource requirements, including: The dynamic reconstruction engine traverses the candidate partition set and filters out the corresponding available resource limits. Candidate partitions with a value not less than the hardware resource requirement h are used to generate a candidate instruction set. The candidate instruction set contains multiple candidate scheduling instructions. And satisfy: Dividing the transient protection time by the bus symbol rate yields the output wait window time. And it satisfies the calculation formula: For each candidate scheduling instruction in the candidate instruction set, calculate the shutdown waiting time. Reconfiguration loading time Reset time Execution time The output waiting window time With signal transmission time The sum of these values ​​yields the total link time. And it satisfies the calculation formula: Candidate scheduling instructions whose total link latency exceeds the end-to-end latency requirement D are excluded. Retain the candidate scheduling instructions that meet the requirements. And it satisfies the hard constraint conditions: For the reserved candidate scheduling instructions Calculate the objective cost function value And it satisfies the calculation formula: In the formula, This represents the time-consuming weighting coefficient. This represents the protection weighting coefficient. This represents the energy consumption weighting coefficient. Indicates the corresponding candidate scheduling instruction The estimated energy consumption; From the retained candidate scheduling instructions Search for the corresponding target cost function value in the middle. Minimum target candidate scheduling instruction And satisfy: When there are multiple target candidate scheduling instructions The target cost function value If the values ​​are the same, uniqueness is selected in the following order: minimum output waiting window time, minimum reconfiguration loading time, and minimum candidate partition index value. The single target candidate scheduling instruction obtained after screening As the reconfiguration scheduling instruction.

[0031] The available resource limit is the maximum number of various hardware resources that a reconfigurable partition can provide, including lookup tables, triggers, block random access memory, digital signal processing units, etc. The energy consumption estimate is the estimated energy consumption required for the reconfigurable partition corresponding to the candidate scheduling instruction to perform reconfiguration, computation, and other operations, measured in joules. The candidate instruction set is the set of all candidate scheduling instructions selected by the dynamic reconfiguration engine that meet the hardware resource requirements. Preferably, it includes a set of all candidate scheduling instructions whose available resource limit is not less than the hardware resource requirement, to comprehensively cover all feasible scheduling schemes. The candidate scheduling instruction is a structured instruction containing information such as the reconfigurable partition identifier, reconfiguration timing, and resource allocation. Preferably, it includes an instruction structure containing the target partition identifier, reconfiguration loading timing, reset timing, and computation scheduling rules. The output waiting window duration is the time required for the output link module to wait for synchronous switching noise attenuation, measured in seconds. Preferably, it is the transient protection duration divided by the bus symbol rate, thereby converting the symbol-dimensional transient protection duration into a time-dimensional one, consistent with system timing calculations. The estimated shutdown wait time is the estimated time required for reconfigurable partition boundary isolation and bus transaction clearing, in seconds. It is preferably the sum of the longest clearing time and the safety reserve margin, based on the worst-case scenario of bus transaction processing, ensuring the conservatism and reliability of the estimated time. The estimated reconfiguration load time is the estimated time required to load the local reconfiguration data stream into the reconfigurable partition, in seconds. It is preferably the size of the local reconfiguration data stream divided by the transmission rate of the internal configuration read channel, based on the data transmission rate formula, to accurately estimate the load time. The estimated reset time is the estimated time required for the reconfigurable partition to synchronously reset, in seconds. It is preferably 32 divided by the desired clock frequency, to follow the reset duration calculation rules and maintain parameter consistency. The estimated operation execution time is the estimated time required for the cryptographic acceleration core to complete data processing, in seconds. It is preferably the sum of the startup ready time and the message bit length divided by the data throughput rate, to ensure the consistency of timing calculations. The estimated signal transmission time is the estimated time required for the output link module to convert the output plaintext data into an electrical signal sequence and transmit it, measured in seconds. Preferably, it is the sum of the pure payload transmission time and the frame header overhead time, to accurately estimate the transmission time based on the bus transmission rate and frame structure. The estimated total link time is the estimated total time from the start of reconfiguration to the completion of data transmission, measured in seconds. Preferably, it is the sum of the estimated shutdown waiting time, estimated reconfiguration loading time, estimated reset time, estimated computation execution time, output waiting window time, and estimated signal transmission time, to comprehensively cover the time consumed at each stage of the link and ensure that end-to-end delay constraints are met. The time weighting coefficient is a coefficient used to adjust the weights of the estimated reconfiguration loading time and the estimated computation execution time in the target cost function, with a preferred value range of 0.3 to 0.7.The protection weight coefficient is used to adjust the weight of the output waiting window time in the target cost function. Its preferred value range is 0.2 to 0.5, allowing for flexible adjustment based on the system's transmission reliability requirements; a larger value is used for high reliability requirements. The energy consumption weight coefficient is used to adjust the weight of the energy consumption estimate in the target cost function. Its preferred value range is 0.1 to 0.3, allowing for flexible adjustment based on the system's energy consumption requirements; a larger value is used for low-power scenarios. The target cost function value is a quantitative indicator that comprehensively reflects the time consumption, reliability, and energy consumption of candidate scheduling instructions. It is preferably the sum of the first, second, and third products to comprehensively balance system performance across multiple dimensions and achieve optimal scheduling selection. The target candidate scheduling instruction is the candidate scheduling instruction with the smallest target cost function value, preferably the instruction with the smallest target cost function value among the retained candidate scheduling instructions, to select the scheduling scheme with the best overall performance. The reconfiguration scheduling instruction is the scheduling instruction finally generated and issued by the dynamic reconfiguration engine. It is preferably the target candidate scheduling instruction after uniqueness screening to ensure the uniqueness and validity of the scheduling instructions and avoid execution conflicts. The candidate partition index value is a number used to uniquely identify the candidate partition. It is an integer from 0 to the total number of reconfigurable partitions minus 1, in order to simplify partition identification and facilitate uniqueness filtering in the scheduling logic.

[0032] The candidate partition selection rule is as follows: The dynamic reconstruction engine traverses the candidate partition set and compares the available resource limit of each partition with the hardware resource requirement. Only when the available quantity of various resources such as lookup tables and triggers in a partition is not less than the corresponding value in the hardware resource requirement will the partition be included in the candidate instruction set.

[0033] The output waiting window duration is calculated as follows: the output waiting window duration is directly derived from the transient protection duration and the bus symbol rate. The transient protection duration is a parameter calculated based on the bus noise attenuation law, which links the noise attenuation requirement with the bus transmission rhythm.

[0034] The candidate scheduling instruction selection logic is as follows: First, based on the end-to-end latency requirement as a hard constraint, candidate instructions that exceed the estimated total link time are eliminated to ensure system real-time performance; then, the time consumption, reliability, and energy consumption of the remaining instructions are comprehensively evaluated through the objective cost function to select the instruction with the best overall performance.

[0035] In particular, when multiple candidate instructions have the same target cost function value, they are filtered in the order of minimum output waiting window time, minimum estimated reconfiguration loading time, and minimum candidate partition index value to ensure the uniqueness of the final scheduling instruction.

[0036] The estimated shutdown wait time is calculated by taking the longest drain time plus a safety margin. The longest drain time is the preset upper limit of in-transit transactions divided by the preset minimum service rate of the interconnect bus, and the safety margin is fixed at 2 microseconds. The estimated reconfiguration load time is the size of the local reconfiguration data stream divided by the internal configuration read channel transmission rate, which is fixed at 200 megabytes per second. The estimated reset time is 32 divided by the expected clock frequency.

[0037] The sum of the weight coefficients of the objective cost function is 1. The values ​​of the time consumption weight coefficient, protection weight coefficient, and energy consumption weight coefficient need to be adjusted according to the system application scenario. In the high-speed cryptographic device scenario, the time consumption weight coefficient is 0.7, the protection weight coefficient is 0.2, and the energy consumption weight coefficient is 0.1; in the low-power scenario, the time consumption weight coefficient is 0.3, the protection weight coefficient is 0.4, and the energy consumption weight coefficient is 0.3; in the balanced scenario, the three are 0.5, 0.3, and 0.2 respectively.

[0038] It should be noted that if the estimated total link latency of all candidate scheduling instructions is greater than the end-to-end latency requirement, the system generates an error response frame with error code 2001, describing the error as no scheduling scheme that meets the latency requirement. The frame is returned to the upper-layer application through the northbound interface, and an error log is recorded, including information such as the end-to-end latency requirement and the estimated total link latency of each candidate instruction. At the same time, the system is triggered to adaptively adjust and reduce non-core constraints on hardware resource requirements (such as appropriately reducing the clock frequency), and regenerate and filter the candidate instruction set.

[0039] Preferably, the dynamic partial reconfiguration subsystem performs boundary isolation and bus transaction termination on the target partition within the system according to the reconfiguration scheduling instruction to clear in-transit transactions, then loads the partial reconfiguration data stream into the target partition, and performs a synchronous reset after the reconfiguration is completed, including: Synchronously raise the boundary isolation signal at the boundary of the target partition; maintain the final state level of the data cable of the target partition and force the active enable cable to zero; obtain the preset upper limit of the number of transactions in transit. Minimum service rate with preset interconnect bus Calculate the longest emptying time And satisfy: Based on the longest emptying time and the safety reserve margin Calculate the shutdown waiting time. And satisfy: If the pending transactions are not cleared within the specified time, and the transaction is still not cleared after the specified time, the bus transaction is forcibly terminated and an error response frame is output. If the clearing is completed within the specified time, the local reconfiguration data stream is obtained and verified through the internal configuration read channel. After verification, the local reconfiguration data stream is loaded into the target partition. After loading, the synchronization reset operation is performed on the internal registers of the cryptographic acceleration core, the partition boundary handshake register, and the write port of the static area cache. Based on the desired clock frequency... Calculate the reset time And maintain the reset active level during the reset time, and satisfy: After canceling the synchronous reset operation, the boundary isolation signal is kept high for two clock cycles corresponding to the desired clock frequency, and then the boundary isolation signal is pulled low to release the boundary isolation.

[0040] The preset in-transit transaction limit is the maximum number of incomplete transactions allowed on the interconnect bus by the system, measured in bytes. It can be calibrated offline based on bus bandwidth and latency requirements and then written to the configuration register. The preset minimum interconnect bus service rate is the minimum data transfer rate (bytes per second) for handling in-transit transactions on the interconnect bus. The nominal minimum rate can be found in the bus device manual. The local reconfiguration data stream is binary data used for configuring the algorithm core of the reconfigurable partition. It contains hardware logic layout and parameter configuration information and can be read from the internal configuration storage medium. The cryptographic acceleration core internal registers are register units in the cryptographic acceleration core used to store operation states, key fragments, and intermediate results. They can be obtained through the hardware logic definition of the field-programmable gate array (FPGA). The partition boundary handshake register is a register located at the boundary between the reconfigurable partition and the static area. It is used to implement signal interaction and synchronization between the partition and other modules in the system and can be extracted from the system hardware design file. The static area cache write port is the hardware interface in the static area cache used to receive output data from the cryptographic acceleration core and can be obtained from the cache controller's hardware design document.

[0041] Boundary isolation signals are hardware control signals used to isolate the reconfigurable target partition from other modules in the system. They are preferably active high-level digital signals with a level standard consistent with the system core voltage to ensure the driving capability of the isolation signal and achieve reliable electrical isolation between the partition and the system. The final state level of the data cable is the last effective level state of the data cable of the reconfigurable target partition before entering the isolation state. It is divided into high and low levels, preferably the actual level state of the data cable before the transaction ends, to avoid additional electromagnetic interference caused by sudden level changes and ensure the stability of the isolation process. The active enable cable is used to control the bus data transmission enable state. Its level state determines whether the bus is in data transmission mode; preferably, a high level indicates active enable, and a low level indicates inactive enable. The maximum queue time is the maximum estimated time required for the interconnect bus to complete all in-transit transactions, in seconds. It is preferably a preset upper limit for the number of in-transit transactions divided by a preset minimum service rate of the interconnect bus, as it is based on the worst-case scenario of bus transaction processing, ensuring the conservatism of the estimated time. The safety reserve margin is an additional buffer time added to avoid bus transaction emptying timeouts, measured in seconds, preferably 2 microseconds. This duration can cover transaction emptying fluctuations in most scenarios, preventing accidental transaction termination. The internal configuration read channel is a dedicated hardware channel used in the system to read local reconfiguration data streams and transmit them to reconfigurable partitions. It is preferably a high-speed transmission channel based on a serial configuration protocol, with a transmission rate of no less than 200 megabytes per second, to ensure the loading speed of the reconfiguration data stream and improve the real-time performance of dynamic core switching. The clock cycle is the time it takes for the system or cryptographic acceleration core's clock signal to complete one high-low level switch, measured in seconds, and is the reciprocal of the desired clock frequency. The error response frame is a structured data frame generated by the system when an anomaly is detected, used to provide feedback on the anomaly. It is preferably a fixed-format data frame containing the error code, anomaly type, and occurrence time, with a frame length of 64 bytes, to facilitate rapid anomaly type identification by upper-layer applications and achieve accurate fault diagnosis. The reset active level is the hardware level state used to trigger the reset operation of the cryptographic acceleration core and related registers, preferably active low, with the level standard conforming to the system's digital circuit design specifications. The 32 reset clock cycle constant is a fixed number of clock cycles set by the system to ensure that the reset operation is completely completed. This number of cycles ensures that the register state is completely cleared, avoiding calculation errors caused by incomplete reset.

[0042] The boundary isolation operation is as follows: After receiving the reconfiguration scheduling command, the system first synchronously pulls the boundary isolation signal high on all boundary interfaces of the target partition to achieve electrical isolation between the target partition and other modules of the system; at the same time, it maintains the final state level of the data cables of the target partition to avoid interference caused by level changes, and sets all effective enable cables to invalid to prohibit any data transmission between the partition and the outside.

[0043] The calculation rule for the actual shutdown waiting time is as follows: the longest drain time is the estimated time based on the worst-case processing capacity of the bus, plus a fixed safety reserve margin, to obtain the actual shutdown waiting time.

[0044] The preset upper limit of the number of transactions in transit is determined based on the deep cache capacity of the interconnect bus, taking 80% of the cache capacity. For example, if the bus cache capacity is 512 bytes, then the preset upper limit of the number of transactions in transit is 4096 bits, or 512 bytes. The preset minimum service rate of the interconnect bus is determined based on the nominal minimum transmission rate in the bus device manual. If the nominal minimum rate in the manual is 256 megabytes per second, then that number is taken directly.

[0045] The default value for the safety reserve tolerance is 2 microseconds, which is a fixed value and does not change with bus parameters. If the system is used in a high-latency scenario, it can be adjusted to 4 microseconds or 8 microseconds through the system configuration register, with an adjustment step of 2 microseconds and a maximum of 16 microseconds.

[0046] Preferably, the cryptographic acceleration core starts operation after the synchronization reset is completed, converts the input data into output plaintext data and writes it into the static area buffer, including: Obtain the key index handle from the call parameter package, search for the real key payload corresponding to the key index handle in the static key mapping table, and inject the real key payload into the cryptographic acceleration core; if the real key payload is not found, output an error response frame; Obtain the number of parallel processing channels P, the interface transmission block width B, and the worst-case execution cycle C per block of the cryptographic acceleration core. max ; Based on the number of parallel processing channels, the interface transmission block width, the expected clock frequency, and the worst-case execution cycle count per block, the data throughput R is calculated and satisfies the following formula: Obtain the setupCysles (setup overhead cycles), and calculate the startup readiness time T based on the setupCysles and the desired clock frequency. setup And it satisfies the calculation formula: Based on the message length, the data throughput, and the startup ready time, the computation execution time T is calculated. exe And it satisfies the calculation formula: The input data is received based on the pipelining handshake protocol, the input data is divided into data blocks aligned with the bit width of the interface transmission block, and the data blocks are subjected to cryptographic transformation processing in combination with the real key payload to generate the output plaintext data. The plaintext output data is sequentially written to the write port of the static area buffer, and an output ready status is issued after the data writing is completed.

[0047] The key index handle is a unique identifier used to retrieve the actual key payload. It corresponds one-to-one with the index entries in the static key mapping table and can be obtained by parsing the key configuration field in the call parameter package. This field is a fixed-length number field preset by the system.

[0048] The static key mapping table is a structured data table that stores the correspondence between key index handles and actual key payloads. It is tamper-proof and can be loaded from secure storage during system initialization. The actual key payload is the actual key data required by the cryptographic acceleration core to perform cryptographic operations. It contains the core data of either symmetric or asymmetric keys and can be retrieved by matching the key index handles in the static key mapping table. After retrieval, it is temporarily stored in the encrypted buffer. The number of parallel processing channels is the total number of independent channels in the cryptographic acceleration core that can perform cryptographic operations simultaneously. It can be obtained by parsing the computational resource entity nodes in the hardware mapping constraints. The interface transmission block width is the minimum block length for data transmission between the cryptographic acceleration core and the static buffer, measured in bits. It can be obtained by reading the interface configuration entity nodes in the hardware mapping constraints. The worst-case execution cycle count per block is the maximum number of clock cycles required for the cryptographic acceleration core to process one interface transmission block of data. It is a measured value under worst-case conditions and can be obtained through offline hardware testing and calibration, then written to the algorithm metadata file. The startup overhead cycle count is the number of clock cycles required for the cryptographic acceleration core to go from reset to normal operation, including the time spent on internal logic initialization. It can be obtained through hardware testing, and different acceleration cores for different algorithms correspond to different calibration values. Input data is the raw data that needs to be processed by the cryptographic acceleration core. It is the data to be processed received by the system and can be obtained through the system's general data input interface. After being obtained, it is temporarily stored in the input buffer of the static area.

[0049] Data throughput is the maximum amount of data that the cryptographic acceleration core can process per unit time, measured in bits per second. It is preferably calculated by multiplying the number of parallel processing channels, the interface transmission block width, and the desired clock frequency, then dividing by the worst-case execution cycle count per block. This ensures the conservatism and accuracy of the throughput prediction based on hardware computing resources and worst-case execution conditions. Startup readiness time is the time it takes for the cryptographic acceleration core to complete initialization and acquire computational capabilities from reset and release, measured in seconds. It is preferably calculated by dividing the startup overhead cycle count by the desired clock frequency to convert clock cycles into actual time, adapting to the system's timing computation architecture. The pipelined handshake protocol is a synchronization protocol for data transmission between the cryptographic acceleration core and the static area, enabling non-blocking continuous data transmission. It is preferably a custom pipelined handshake rule based on AXIS (Stream Bus Protocol), including bidirectional handshake signals for data validity and readiness, balancing protocol universality and hardware implementation simplicity to improve data transmission efficiency. A data block is a data unit of equal length, aligned with the width of the interface transmission block, after the input data has been segmented. Preferably, it is a binary data unit with a length equal to the width of the interface transmission block, padded with zeros to match the parallel processing granularity of the cryptographic acceleration core and improve computational efficiency. The output plaintext data is the plaintext result data obtained after the input data has been transformed by the cryptographic acceleration core. Preferably, it is binary data with the same length as the input data, with zeros automatically removed during output to ensure data integrity and avoid redundant data transmission. The output ready state is a status signal sent by the cryptographic acceleration core to the output link module after completing all data operations and writing the output plaintext data to the buffer. Preferably, it is a high-level active digital hardware signal synchronized with the system clock for rapid detection by the output link module and to ensure timing synchronization. The cryptographic transformation processing rules are the specific computational logic executed by the cryptographic acceleration core according to the algorithm type, including the execution steps of encryption, decryption, signature verification, etc. Preferably, it is computational logic that conforms to commercial cryptographic standards or quantum-resistant cryptographic algorithm standards to ensure the compliance and correctness of the algorithm operation.

[0050] The key injection method is as follows: after extracting the key index handle from the call parameter packet, the key is not directly passed to the cryptographic acceleration core. Instead, a secondary lookup is performed through the static key mapping table. The key is injected only after it is matched with the corresponding real key payload. If it is not found, an error response frame is immediately output.

[0051] The calculation logic for data throughput is as follows: combine the number of parallel processing channels of the cryptographic acceleration core, the interface transmission block width, and the expected clock frequency to calculate the theoretical maximum computing power, and then correct it by the worst-case execution cycle number of a single block.

[0052] The calculation rule for the computation execution time is as follows: divide the message bit length by the data throughput to get the pure computation time, and then add it to the startup and ready time to get the actual computation execution time.

[0053] The input data is processed as follows: Input data is received based on a pipelined handshake protocol to ensure the synchronization and non-blocking nature of data transmission. At the same time, the input data is divided into data blocks that are aligned with the width of the interface transmission block, so that each data block can match the parallel operation granularity of the cryptographic acceleration core and improve the overall operation efficiency.

[0054] The latency design principle based on the worst-case execution cycle count of a single block is as follows: in the process of calculating data throughput and computation execution time, the average execution cycle count is not used, but the worst-case execution cycle count of a single block is selected.

[0055] The calculation rule for startup readiness time is as follows: the startup initialization time of the cryptographic acceleration core is calculated separately and included in the operation execution time, rather than being merged into the number of single block execution cycles.

[0056] Preferably, when the output link module detects that the output plaintext data is ready, it enters an output waiting window with a duration equal to the transient protection duration; within the output waiting window, it maintains a bus idle state to wait for signal interference to attenuate; after the output waiting window ends, it converts the output plaintext data into an electrical signal sequence and transmits it outward, including: Within the output waiting window, the bus enable signal is set to an invalid state, and the bus data cable maintains the level state of the previous cycle to maintain the bus idle state. The transient protection duration Loaded into an internally configured decrementing counter; decrementing the decrementing counter in each bus clock cycle until the count value reaches zero to end the output wait window; Obtain the cache depth configuration value of the static area cache. Launch start delay time Determine whether the cache depth configuration value meets the cache overflow prevention condition. The cache overflow prevention condition is defined as the cache depth configuration value being greater than or equal to the depth safety lower bound, and satisfying the constraint formula: In the formula, T g R represents the output waiting window time, R represents the data throughput, and B represents the interface transmission block width. If the buffer overflow prevention condition is not met, the transmission operation will be blocked. If the buffer overflow prevention condition is met, the output plaintext data is encapsulated into a transmission data frame after the count value is zeroed; the transmission data frame sequentially includes a preamble sequence, a header sequence, a payload sequence, and a cyclic redundancy check sequence. Obtain the fixed symbol overhead count and calculate the frame header overhead time. And it satisfies the calculation formula: In the formula, f s This indicates the bus symbol rate, and the number 18 represents the fixed symbol overhead. The signal transmission time T is calculated based on the message bit length, the bus parallel bit width, the bus symbol rate, and the frame header overhead time. tx And it satisfies the calculation formula: The transmitted data frames are converted into electrical signal sequences according to the symbol period and transmitted. During the transmission process, the Hamming weight change value of the bus data cable is counted according to the symbol period. The Hamming weight change value is divided by the cumulative average value of the bus parallel bit width to obtain the data cable flip density. Record the results, and ensure they meet the calculation formula: In the formula, N sym x represents the total number of symbols emitted. j x represents the cable status value during the j-th symbol period. j-1 This represents the cable state value during the (j-1)th symbol period, and Hamming represents the function used to calculate the Hamming weight change value.

[0057] The cache depth configuration value is the maximum bit length of data that the static area cache can store. It is a hardware configuration parameter of the cache and can be obtained by reading the configuration register of the cache controller. The transmit start delay is the inherent delay time in seconds from detecting the output ready state to initiating data transmission by the output link module. It can be obtained through hardware calibration. The decrement counter is a hardware counting unit in the output link module used to measure the output waiting window duration. It has the function of loading an initial value and decrementing cycle by cycle and can be obtained through the system hardware logic definition. The Hamming weight change value is the number of bits that change in the bus data cable level state within adjacent symbol cycles. It is used to quantify the degree of cable switching and can be obtained by real-time detection of the cable state value in adjacent cycles through a hardware comparison circuit. Cable state value x j This is a combination of the level states of all data cables on the bus during the j-th symbol cycle. It is a binary value and can be obtained by sampling at the rising edge of each symbol cycle using a bus state sampling circuit. Cable state value x j-1 It is a combination of the level states of all data cables on the bus during the (j-1)th symbol period. It is a binary value and can be obtained by sampling at the rising edge of the (j-1)th symbol period through the bus state sampling circuit.

[0058] The bus idle state is a working state in which the bus stops data transmission and the cable level remains stable, with no new level switching behavior. Preferably, the enable cable is disabled and the data cable maintains the level of the previous cycle to avoid additional synchronization switching noise caused by cable level switching and ensure natural interference attenuation. The counter value is a real-time value in a decrementing counter, used to characterize the remaining duration of the output waiting window. Preferably, it is an integer that decreases to 0 cycle by cycle from the transient protection duration to directly reflect the remaining time of the waiting window and ensure accurate triggering of the timing end. The deep safety lower bound is the minimum buffer depth set to prevent buffer overflow within the output waiting window, in bits. Preferably, it is the sum of the output waiting window duration and the transmit start delay duration multiplied by the data throughput rate, plus twice the interface transmission block width, to cover the maximum data write volume within the waiting window and reserve a safety margin of twice the transmission block width. The buffer overflow prevention rule is a logical criterion for determining whether the static area buffer meets the data transmission conditions. Preferably, if the buffer depth configuration value is greater than or equal to the lower bound of the depth safety, the condition is met; otherwise, it is not met. This hard threshold determination ensures no buffer overflow risk and guarantees the integrity of data transmission. The transmitted data frame is a structured data unit after encapsulating plaintext data, containing a frame header and payload. Preferably, it has a fixed structure containing a preamble sequence, header sequence, payload sequence, and cyclic redundancy check sequence in sequence, conforming to common data transmission frame structure specifications and improving data transmission reliability and compatibility. The preamble sequence is the start sequence of the transmitted data frame, used for clock synchronization and frame start identification at the receiver. It is preferably a 16-bit alternating 0 / 1 binary sequence to facilitate rapid clock synchronization at the receiver and reduce the false positive rate for frame start identification. The header sequence is the sequence in the transmitted data frame used to carry data-related information. It follows the preamble sequence and is preferably a 32-bit binary sequence containing message bit length, algorithm identifier, and frame sequence number information, thus carrying core control information within a limited bit length without consuming excessive transmission resources. The payload sequence is the core sequence carrying the plaintext data in the transmitted data frame. It represents the actual service data to be transmitted and is preferably a binary sequence with the same length as the plaintext data to ensure data transmission integrity. The cyclic redundancy check (CRC) sequence is the check sequence for the transmitted data frame, used by the receiver to detect errors during data transmission. It is preferably a 32-bit binary checksum, calculated based on the payload sequence, as the 32-bit checksum has a high error detection rate and can cover most transmission errors. The fixed symbol overhead is the number of symbols occupied by the frame header in the transmitted data frame. It is a fixed value, preferably 18 symbols, to match the total bit width of the preamble, header, and CRC sequence with the bit width of the bus symbols, ensuring the accuracy of the frame header overhead quantization. The frame header overhead time is the time required for the frame header to be transmitted through the bus, measured in seconds. It is preferably the fixed symbol overhead divided by the bus symbol rate, thus converting the symbol-dimensional frame header overhead into a time-dimensional value.The pure payload transmission time is the time required for the payload sequence of the transmitted data frame to be transmitted through the bus, measured in seconds. It is preferably calculated by dividing the message bit length by the product of the bus parallel bit width and the bus symbol rate, to accurately estimate the payload transmission time based on the actual transmission capacity of the bus. The data cable flip density is the average degree of flipping of the bus data cable during data transmission, preferably calculated by dividing the Hamming weight change value by the cumulative average of the bus parallel bit width, serving as a quantitative indicator of standardized flipping degree. The symbol period is the time required to transmit one symbol on the bus, measured in seconds, preferably the reciprocal of the bus symbol rate, satisfying the relationship between the symbol period and the symbol rate to ensure the accuracy of bus transmission timing calculations. The total number of transmitted symbols is the total number of symbols transmitted through the bus after the output plaintext data is encapsulated into transmitted data frames. It is preferably the sum of the number of header symbols and the number of payload symbols to comprehensively count the number of transmitted symbols on the bus. The electrical signal sequence is the analog electrical signal obtained after the transmitted data frame undergoes digital-to-analog conversion, which can be transmitted through the physical bus. It is preferably an analog voltage sequence that corresponds one-to-one with the binary sequence of the transmitted data frame, converting the digital signal into an electrical signal that conforms to the physical bus transmission standard, ensuring that the receiver can recognize it. The Hamming function is an algorithm used to calculate the number of 1s in the XOR result of two cable status values, i.e., to calculate the Hamming weight change value. It is preferably a fast calculation algorithm based on hardware XOR circuit and adder to realize the hardware real-time calculation of the Hamming weight change value and meet the requirements of high-speed transmission.

[0059] The method for maintaining the bus idle state is as follows: within the output waiting window, the active enable cable is set to an inactive state, prohibiting any data transmission operation on the bus. At the same time, the hardware latch circuit maintains the previous cycle level state of the data cable, without any new level switching behavior.

[0060] The timing control method for the output waiting window is as follows: the transient protection duration is loaded as the initial value into the decrementing counter. The counter uses the bus clock as the counting clock and performs a decrementing operation once every bus clock cycle until the count value reaches zero, at which point the output waiting window ends.

[0061] The calculation of the deep safety lower bound comprehensively considers the maximum amount of data written within the output wait window and the transmit start delay, i.e., data throughput multiplied by the total latency, while adding an additional two times the interface transmission block width as a safety margin. This formula ensures that even if data is continuously written to the cache during the latency period, the cache will not overflow, guaranteeing data integrity.

[0062] If the cache depth configuration value is less than the depth safety lower bound, the transmit operation is immediately blocked to avoid data loss due to cache overflow. If the cache depth configuration value is greater than or equal to the depth safety lower bound, the data encapsulation and transmit operations are initiated only after the output waiting window has ended. This rule binds the cache hardware state to the transmit operation, mitigating the risk of data overflow at the hardware level and ensuring the reliability of data transmission.

[0063] The calculation logic for the actual signal transmission time is as follows: the actual signal transmission time is the sum of the pure payload transmission time and the frame header overhead time. The transmission times of the effective payload and the frame header are calculated separately and then summed.

[0064] The statistical method for data cable flip-over density is as follows: During transmission, the cable status value x of adjacent cycles is detected in real time according to the symbol period. j and x j-1 The Hamming weight change value is calculated using the Hamming function. The Hamming weight change value for each symbol period is divided by the bus parallel bit width to obtain the single-flip ratio. Finally, the cumulative average of all single-flip ratios is taken to obtain the data cable flip density.

[0065] The conversion method from digital signal to electrical signal is as follows: the packaged transmission data frame is split into symbol periods, and the binary data of each symbol period is converted into the corresponding analog voltage signal through a digital-to-analog converter circuit to form a continuous electrical signal sequence, which is then transmitted outward through the physical bus.

[0066] like Figure 2 As shown, Figure 2 This paper presents a dynamically reconfigurable interface system architecture for commercial cryptographic and quantum-resistant cryptographic algorithms. The application system sends a call parameter package to the cryptographic machine through a standardized northbound interface. The metadata manager in the static area of ​​the FPGA within the cryptographic machine loads the algorithm metadata file (JSON-LD) from secure storage and generates hardware mapping constraints based on the call parameter package. The dynamic reconfiguration engine generates reconfiguration scheduling instructions based on the hardware mapping constraints, driving the dynamic partial reconfiguration subsystem (ICAP) to dynamically reconfigure the target cryptographic acceleration core in the reconfigurable area, thereby achieving algorithm switching. The data processed by the cryptographic acceleration core is written to the static area buffer, converted into an electrical signal sequence by the output link module, and sent to external devices or receivers through the underlying physical communication bus. The entire process realizes the standardization and reconfigurable adaptation of dynamic algorithm core switching and interface.

[0067] It should be noted that the interval and threshold sizes are set for ease of comparison. The size of the threshold depends on the amount of sample data and the base number set by those skilled in the art for each set of sample data, as long as it does not affect the proportional relationship between the parameter and the quantized value. Furthermore, the above formulas are all dimensionless calculations, and the formulas are derived from software simulations using a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0068] The embodiments of this example have been described above. However, this example is not limited to the above-described implementation methods. The above-described implementation methods are merely illustrative and not restrictive. Those skilled in the art can make many other variations based on the guidance of this example, all of which fall within the protection scope of this example.

Claims

1. A dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms, characterized in that: Metadata manager is used to receive call parameter packages, load the algorithm metadata file corresponding to the call parameter packages, and parse and generate hardware mapping constraints; The algorithm adaptation layer is used to extract the hardware resource requirements and the number of concurrent switching lines set in the bus output terminal of the system according to the hardware mapping constraints, and to calculate the transient protection duration in combination with the bus electrical parameters. The dynamic reconfiguration engine is used to generate reconfiguration scheduling instructions based on the transient protection duration and the hardware resource requirements. The dynamic partial reconfiguration subsystem is used to implement boundary isolation and bus transaction termination on the target partition in the reconfigurable area of ​​the system according to the reconfiguration scheduling instruction to clear the in-transit transactions, then load the partial reconfiguration data stream into the target partition, and perform synchronous reset after the reconfiguration is completed. A cryptographic acceleration core, located within the target partition, is used to initiate computation after the synchronization reset is completed, converting input data into output plaintext data and writing it into a static area cache within the system. The output link module is used to enter an output waiting window with a duration equal to the transient protection duration when the output plaintext data is detected to be ready. The bus remains idle within the output waiting window to allow signal interference to attenuate; after the output waiting window ends, the output plaintext data is converted into an electrical signal sequence and transmitted outward.

2. The dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms according to claim 1, characterized in that, The metadata manager receives the call parameter package, loads the algorithm metadata file corresponding to the call parameter package, and parses it to generate hardware mapping constraints, including: Extract the algorithm category identifier, cryptographic operation type, message bit length, end-to-end latency requirement, bus symbol rate, and bus parallel bit width from the call parameter package; The smaller value between one-tenth of the end-to-end latency requirement and five milliseconds is set as the maximum allowable loading time. Within the maximum allowed loading time, the retrieval and reading of the algorithm metadata file are completed; The read algorithm metadata file is subjected to normalized semantic expansion processing to eliminate contextual abbreviations and convert them into absolute resource locators, generating the hardware mapping constraints consisting of entity nodes and associated paths.

3. The dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms according to claim 2, characterized in that, The algorithm adaptation layer extracts the hardware resource requirements and the number of concurrent switching lines at the bus output terminal based on the hardware mapping constraints, and calculates the transient protection duration in conjunction with the bus electrical parameters, including: The number of lookup tables, the number of triggers, the number of block random access memory, the number of digital signal processing units, the desired clock frequency, the candidate partition set, and the on-chip interconnect bus protocol type are extracted from the hardware mapping constraints and combined to form the hardware resource requirements. Obtain the number of control lines from the hardware mapping constraints; Perform static timing analysis on the bus output terminal to obtain the proportion of cables that undergo state switching within a preset alignment window, and use it as the edge alignment degree. The total number of bus cables is obtained by adding the number of control lines to the parallel bit width of the bus. Multiply the total number of bus cables by the edge alignment to obtain the number of concurrent flip lines; The bus electrical parameters are obtained, including single-wire load capacitance, equivalent inductance, edge transition time, voltage swing, decay time constant, and allowable transient threshold. Multiply the single-line load capacitance by the voltage swing and divide by the square of the edge transition time to obtain the single-line current change rate; multiply the single-line current change rate, the number of concurrent flip lines, and the equivalent inductance together to obtain the initial ground bounce amplitude. Determine whether the initial ground bounce amplitude is greater than the allowable transient threshold; if so, divide the initial ground bounce amplitude by the allowable transient threshold and take the natural logarithm, then multiply it by the decay time constant to obtain the decay time; if not, set the decay time to zero. Multiply the attenuation time by the bus symbol rate, and round up the product to obtain the initial symbol length; take the maximum value of the initial symbol length and the minimum protection threshold, and then take the minimum value of the minimum protection threshold, as the transient protection duration.

4. The dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms according to claim 3, characterized in that, The dynamic reconfiguration engine generates reconfiguration scheduling instructions based on the transient protection duration and the hardware resource requirements, including: The dynamic reconfiguration engine traverses the candidate partition set, filters out candidate partitions whose corresponding available resource upper limit is not less than the hardware resource requirement, and generates a candidate instruction set, which contains multiple candidate scheduling instructions. Divide the transient protection duration by the bus symbol rate to obtain the output wait window time. For each candidate scheduling instruction in the candidate instruction set, calculate the sum of the estimated shutdown waiting time, estimated reconfiguration loading time, estimated reset time, estimated operation execution time, the output waiting window time, and the estimated signal transmission time to obtain the estimated total link time. Candidate scheduling instructions that are greater than the estimated total link time requirement are removed, and candidate scheduling instructions that meet the requirements are retained. For the retained candidate scheduling instructions, the estimated reconfiguration loading time and the estimated computation execution time are added together and then multiplied by a time weighting coefficient to obtain a first product; the output waiting window time is multiplied by a protection weighting coefficient to obtain a second product; the energy consumption estimate corresponding to the candidate scheduling instruction is multiplied by an energy consumption weighting coefficient to obtain a third product; the first product, the second product, and the third product are added together to obtain the target cost function value. The target candidate scheduling instruction with the smallest corresponding target cost function value is found from the retained candidate scheduling instructions; when there are multiple target candidate scheduling instructions with the same target cost function value, uniqueness screening is performed in the following order: the output waiting window time is the smallest, the estimated reconfiguration loading time is the smallest, and the candidate partition index value is the smallest. The unique target candidate scheduling instruction obtained after screening is used as the reconfiguration scheduling instruction.

5. The dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms according to claim 4, characterized in that, The dynamic partial reconfiguration subsystem performs boundary isolation and bus transaction termination on the target partition in the reconfigurable region within the system according to the reconfiguration scheduling instruction to clear in-transit transactions. It then loads the partial reconfiguration data stream into the target partition and performs a synchronous reset after reconfiguration is complete, including: Synchronously raise the boundary isolation signal at the boundary of the target partition; maintain the final state level of the data cable of the target partition and set the effective enable cable to zero; Obtain the preset upper limit of the number of transactions in transit and the preset minimum service rate of the interconnect bus. Divide the preset upper limit of the number of transactions in transit by the preset minimum service rate of the interconnect bus to obtain the longest emptying time. Add the longest drain time to the safety reserve margin to obtain the actual shutdown waiting time; If the pending transaction is not cleared after the time exceeds the maximum clearing time, the bus transaction is terminated and an error response frame is output; if the clearing is completed within the maximum clearing time, the local reconfiguration data stream is obtained and verified through the internal configuration read channel. After the verification is passed, the local reconfiguration data stream is loaded into the target partition; After loading is complete, the synchronous reset is performed on the internal registers of the cryptographic acceleration core, the partition boundary handshake register, and the write port of the static area cache; thirty-two is divided by the expected clock frequency to obtain the actual reset time, and the reset valid level is maintained within the actual reset time; After the synchronous reset is cancelled, the boundary isolation signal is kept high for two clock cycles corresponding to the desired clock frequency, and then the boundary isolation signal is pulled low to release the boundary isolation.

6. The dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms according to claim 5, characterized in that, The cryptographic acceleration core starts operation after the synchronization reset is completed, converts the input data into output plaintext data and writes it into the static area buffer, including: Obtain the key index handle from the call parameter package, search for the real key payload corresponding to the key index handle in the static key mapping table, and inject the real key payload into the cryptographic acceleration core; if the real key payload is not found, output an error response frame; Obtain the number of parallel processing channels, the interface transmission block width, and the worst-case execution cycle count per block of the cryptographic acceleration core; multiply the number of parallel processing channels, the interface transmission block width, and the desired clock frequency together, and divide the result by the worst-case execution cycle count per block to obtain the data throughput; obtain the startup overhead cycle count and divide the startup overhead cycle count by the desired clock frequency to obtain the startup ready time. Divide the message length by the data throughput, add the quotient to the startup ready time, and get the actual computation execution time. The input data is received based on the pipelining handshake protocol, the input data is divided into data blocks aligned with the bit width of the interface transmission block, and the data blocks are subjected to cryptographic transformation processing in combination with the real key payload to generate the output plaintext data. The plaintext output data is sequentially written to the write port of the static area buffer, and an output ready status is issued after the data writing is completed.

7. The dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms according to claim 6, characterized in that, When the output link module detects that the output plaintext data is ready, it enters an output waiting window with a duration equal to the transient protection duration; within the output waiting window, it maintains a bus idle state to wait for signal interference to attenuate. After the output waiting window ends, the output plaintext data is converted into an electrical signal sequence and transmitted outward, including: Within the output waiting window, the active enable cable is set to an inactive state, and the data cable is kept at the level of the previous cycle to maintain the bus idle state. The transient protection duration is loaded into an internally configured decrementing counter; the decrementing counter is decremented in each bus clock cycle until the count value reaches zero to end the output wait window; Obtain the cache depth configuration value and the transmit start delay time of the static area cache; determine whether the cache depth configuration value is greater than or equal to the lower bound of the depth safety; the lower bound of the depth safety is equal to the sum of the output waiting window time and the transmit start delay time multiplied by the data throughput, plus twice the interface transmission block width.

8. The dynamically reconfigurable interface system for commercial cryptography and quantum-resistant cryptographic algorithms according to claim 7, characterized in that, When the output link module detects that the output plaintext data is ready, it enters an output waiting window with a duration equal to the transient protection duration; within the output waiting window, it maintains a bus idle state to wait for signal interference to attenuate. After the output waiting window ends, the plaintext output data is converted into an electrical signal sequence and transmitted outward, which also includes: If the cache depth configuration value is less than the depth safety lower bound, then the transmission operation is blocked; If the cache depth configuration value is greater than or equal to the depth security lower bound, then after the count value is zeroed, the output plaintext data is encapsulated into a transmission data frame; the transmission data frame sequentially includes a preamble sequence, a header sequence, a payload sequence, and a cyclic redundancy check sequence. Obtain a fixed symbol overhead number equal to eighteen, and divide the fixed symbol overhead number by the bus symbol rate to obtain the frame header overhead time. Divide the message bit length by the product of the bus parallel bit width and the bus symbol rate to obtain the pure payload transmission time; add the pure payload transmission time to the frame header overhead time to obtain the actual signal transmission time. The transmitted data frame is converted into the electrical signal sequence according to the symbol period and transmitted. During the transmission process, the Hamming weight change value of the data cable is counted according to the symbol period. The Hamming weight change value is divided by the cumulative average value of the bus parallel bit width as the data cable flip density and recorded.

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