A method and system for double frame header adaptive detection and VLAN hardware shunting

Abstract

The application belongs to the technical field of FPGA high-speed data acquisition and transmission, and particularly relates to a double-frame-header adaptive detection and VLAN hardware shunting method and system, which comprises the following steps: taking whether the second frame header configuration value in the FPGA is zero as a mode criterion to control the frame header detection logic to switch between two widths without additional hardware overhead; after the frame starts, a hardware extracts a classification identification field and submits a host with an index item, and drive software completes virtual local area network routing with a rule set; all virtual local area networks share the same physical ring receiving buffer and frame data is not copied, and each virtual local area network maintains an independent descriptor queue; a global read pointer is advanced by the minimum value of the consumption progress of all active virtual local area network queues, and a suspended virtual local area network does not participate in the calculation to isolate slow consumers. The application realizes frame header length runtime instant switching and multi-virtual local area network zero-copy shunting, and eliminates head line blockage.

Description

Technical Field

[0001] This invention relates to the field of FPGA high-speed data acquisition and transmission technology, and in particular to a dual-frame header adaptive detection and VLAN hardware traffic splitting method and system. Background Technology

[0002] In high-speed, multi-channel data acquisition scenarios using FPGAs, the FPGA encapsulates serial data from multiple channels into frame formats and writes them to host memory via PCIe DMA. Upper-layer software needs to distribute the data to different consumer processes for processing according to the frame type. At data throughput levels in the GB / s range, pure software solutions face a significant CPU utilization bottleneck.

[0003] The existing technology has the following main problems: First, traditional FPGA frame detection logic only supports a single fixed-length frame header. When different channels use different frame header lengths, traditional solutions require pre-programming different FPGA bitstreams or reconfiguring the FPGA logic, making dynamic switching at runtime impossible. Some solutions use additional mode selection register bits to distinguish different frame header widths, but this increases hardware resource consumption and carries the risk of software configuration errors where the mode register value does not match the actual frame header length. Furthermore, some solutions use the word aligner built into the FPGA transceiver for programmable mode matching, but the word aligner is a physical layer function, and its mode detection width is limited by the transceiver architecture. Moreover, the mode is fixed at compile time and does not support switching the application layer frame header width at runtime via software register writing.

[0004] Secondly, in traditional FPGA data acquisition schemes, the FPGA typically writes the raw received data into a single circular buffer, and the parsing and splitting of frame types are entirely handled by the upper-layer software. When there are multiple receivers with different consumption rates, the slow consumer will cause head-line blocking in the circular buffer. That is, even if subsequent frames belong to the fast consumer, they will be blocked after the frames that the slow consumer has not yet consumed, resulting in the overall system throughput being limited by the slowest consumer. Summary of the Invention

[0005] This invention proposes a dual-frame header adaptive detection and VLAN hardware traffic splitting method and system, aiming to solve the technical problem of how to achieve real-time switching of frame header length during runtime in FPGA high-speed multi-channel data acquisition scenarios without adding extra hardware registers and logic resources.

[0006] In a first aspect, the present invention provides a dual-frame header adaptive detection and VLAN hardware traffic splitting method, comprising: In the FPGA, a first frame header configuration value and a second frame header configuration value are set, and the mode criterion is whether the second frame header configuration value is zero: if the second frame header configuration value is zero, the frame start detection is performed with the width of the first frame header, and only the first frame header configuration value is matched; if the second frame header configuration value is non-zero, the frame start detection is performed with the width of the second frame header, and the first frame header configuration value and the second frame header configuration value are required to be cascaded and matched. After the frame start hit, the FPGA hardware extracts the classification identifier field from the frame data stream, assembles the classification identifier field together with the frame data address offset into an index entry, and writes it into the host memory through an independent index DMA channel. The host-side driver software reads the classification identifier field from the index entry, determines the virtual local area network to which the frame belongs based on the programmable rule set, and delivers the frame descriptor containing the frame data address offset to the independent frame queue of the corresponding virtual local area network. The frame descriptor points to the frame payload data in the shared physical ring receive buffer and does not copy the frame data itself. The global read pointer is advanced based on the minimum consumption progress among all active VLAN queues; paused VLANs are not included in the calculation of this minimum.

[0007] Furthermore, the cascading matching requires that the first frame header configuration value and the second frame header configuration value match simultaneously in two consecutive slots within the same data beat, and the first frame header configuration value must not fall in the last slot of that data beat.

[0008] Furthermore, when switching from the first frame header width mode to the second frame header width mode, all offset values ​​used for field extraction are uniformly increased by a compensation value. The compensation value is equal to the difference between the second frame header width and the first frame header width, and all offset values ​​are based on the frame header start byte as the zero point.

[0009] Furthermore, the index entry includes a frame header configuration value, a frame sequence number, a frame data address offset, and multiple user-configurable extraction fields, with the classification identifier field positioned at a predetermined location among these extraction fields; the index ring buffer and the shared physical ring receive buffer are located in different offset segments of the same large page memory and share the same PCIe base address register translation window.

[0010] Furthermore, the programmable rule set contains multiple rules, each containing a matching value, a mask, and a virtual local area network (VLAN) identifier. During routing decision-making, the rule set is scanned sequentially. If the matching value of the classification identifier matches the matching value of the current rule in the bit specified by the mask, the rule is matched, and the VLAN identifier of the rule is used as the routing result. If no match is found after traversing all rules, the frame is discarded. If the VLAN identifier of the rule is a predetermined discard value, the frame is discarded.

[0011] Furthermore, the independent frame queue delivered to the corresponding VLAN includes: checking the pause status flag of the target VLAN; if it is in a paused state, the frame is discarded directly without blocking the advancement of the global read pointer; if it is not in a paused state, delivery is performed; if there is no consumer process in the target VLAN, the frame is discarded directly; the pause status flag is read and written through atomic operations to ensure concurrency safety.

[0012] Furthermore, the advancement of the global read pointer includes: traversing all virtual local area networks (VLANs), calculating the distance of consumption progress relative to the current read pointer for each active and non-paused VLAN, and taking the minimum value among all distances as the advancement step size; if the advancement step size exceeds the distance of the hardware write pointer relative to the current read pointer, then the advancement step size is clamped to the distance of the hardware write pointer.

[0013] Furthermore, when no VLAN is consumed, the system automatically enters a no-consumer mode, where the driver only advances the read pointer to immediately follow the write pointer to release buffer space, without performing frame parsing or route delivery; once any VLAN is consumed for the first time, the system monotonically switches from the no-consumer mode to the consumer-enabled mode and does not roll back.

[0014] Furthermore, the host-side driver software completely replaces the programmable rule set at runtime via the IOCTL interface, and the replacement operation takes effect atomically; after performing a dynamic pause operation on any virtual LAN via the IOCTL interface, subsequent frames hitting that virtual LAN are discarded at the software routing layer and do not enter the queue; after performing a recovery operation via the IOCTL interface, normal delivery of frames to that virtual LAN is resumed; the pause operation does not stop the FPGA hardware DMA from continuously writing to the shared physical ring receive buffer.

[0015] Secondly, the present invention provides a dual-frame header adaptive detection and VLAN hardware traffic splitting system, the system being used to execute the method, including: The FPGA hardware layer includes a frame header detection module and a field extraction module. The frame header detection module includes a first frame header configuration register and a second frame header configuration register. The frame header detection logic switches between the first frame header width mode and the second frame header width mode based on whether the value of the second frame header configuration register is zero. After the frame start hit, the field extraction module extracts multiple fields from the frame data stream, including at least the classification identifier field, and assembles them into index entries. The PCIe DMA transport layer includes a main data DMA channel and an independent index DMA channel. The main data DMA channel writes frame payload data into a shared physical circular receive buffer in the host memory, and the independent index DMA channel writes the index entries into an index circular buffer in the host memory. The host kernel driver layer includes an index parsing thread, a virtual LAN routing rule engine, and a per-virtual LAN queue management module. The index parsing thread reads index entries from the index ring buffer and extracts the classification identifier field. The virtual LAN routing rule engine determines the virtual LAN to which the frame belongs based on the programmable rule set. The per-virtual LAN queue management module delivers the frame descriptor containing the shared buffer address offset to the corresponding queue without copying the frame payload data. The global read pointer collaborative advancement module is used to take the minimum value of the consumption progress of all active and non-paused VLAN queues to update the FPGA hardware read pointer register; The user-mode interface layer is used to provide runtime replacement of the rule set, dynamic pause or resumption of the virtual LAN, and statistical information reading functions.

[0016] The technical effects of this invention are: (1) The zero or non-zero state of the write value of the second frame header configuration register in the FPGA hardware is used as an implicit sentinel to control the frame header detection logic to switch between the first width mode and the second width mode. No additional mode selection register or logic resources are required, and the configuration error risk of inconsistent mode value and actual frame header length in the explicit mode register scheme is eliminated. (2) The FPGA hardware extracts the classification identifier field from the specified byte offset of the frame during frame detection and submits it to the host through an independent DMA channel along with the index entry, so that the classification identifier extraction is completed with zero delay in the hardware data path, avoiding the performance bottleneck of CPU scanning the data stream frame by frame at high speed. (3) The frame payload data of all virtual LANs share the same physical ring receive buffer. Each virtual LAN maintains an independent frame queue and only stores descriptors without copying frame data, eliminating multiple memory copies of frame data. The global read pointer is advanced by the minimum consumption progress of all active virtual LAN queues, achieving multi-consumer secure isolation on the shared physical buffer. (4) Supports dynamic pause of any virtual LAN during runtime. The paused virtual LAN does not participate in the calculation of the minimum value of the global read pointer, so that the blocking effect of slow consumers is isolated in its own pause domain, and fast consumers are not affected at all, thus fundamentally eliminating headline blocking. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a dual-frame header adaptive detection and VLAN hardware traffic splitting method proposed in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] To address the issues mentioned in the background section regarding how to achieve real-time switching of frame header length during runtime in FPGA high-speed multi-channel data acquisition scenarios without adding extra hardware registers and logic resources; and how to achieve independent frame splitting and consumption isolation for multiple VLAN channels under the constraint of a shared single physical ring receive buffer, eliminating header line congestion, ensuring overall system throughput is not limited by the slowest consumer, and keeping CPU utilization at an extremely low level at high data rates, this invention provides a dual-frame header adaptive detection and VLAN hardware splitting method, referencing... Figure 1 As shown, the specific steps include: Step S1: Configure frame header mode and criterion value.

[0020] The host-side driver software writes the lower 32 bits of the magic number of the frame header to the first frame header configuration register of the frame header detection module inside the FPGA through the PCIe configuration space, which serves as the reference value for comparison with the slot in the data tick when the frame starts to be detected.

[0021] The host-side driver software writes a 32-bit value to the second frame header configuration register through the PCIe configuration space. This written value serves two functions: first, when the value is non-zero, it is used as the high 32 bits of the frame header in the cascaded comparison for frame start detection; second, whether the written value is zero is used by the hardware frame detection logic as a mode selection criterion. If an all-zero value is written, the system enters the first width mode; if a non-zero value is written, the system enters the second width mode. This zero-value criterion utilizes the natural constraint that the high bits of the wider frame header typically carry non-zero information such as the frame version number and protocol identifier in real-world applications.

[0022] The host-side driver software configures multiple offset registers for the field extraction module. Each offset register stores a byte offset value relative to the start byte of the frame header, pointing to the position of the field to be extracted within the frame. The offset register for the second extracted field is pre-defined as the offset register for the classification identifier field. In the second width mode, all field offset values ​​need to be supplemented with a compensation value equal to the difference between the second and first frame header widths, but all offset values ​​still use the first byte of the frame header as the reference zero point. The driver software ensures that the offset configuration is consistent with the current frame header mode through parameter verification.

[0023] The host-side driver software enables the receive channel. After the receive is enabled, the FPGA frame detection logic automatically reads the value of the second frame header configuration register, and uses this value to determine the current operating mode each time a frame is detected.

[0024] Step S2: Perform intra-beat parallel comparison of the frame header detection logic.

[0025] The FPGA's internal frame header detection module receives serial data from the channel in data tick cycles. Each data tick contains N 32-bit slots, where N is determined by dividing the data bit width by 32. The frame header detection logic reads all N slots of the current data tick within each clock cycle and performs corresponding parallel comparison operations based on whether the second frame header configuration register is zero.

[0026] If the value of the second frame header configuration register is all zeros, i.e., in the first width mode, the frame detection logic enables N comparators in parallel to compare whether each slot is equal to the value of the first frame header configuration register. If any slot is equal to the first frame header configuration value, the frame start condition is determined to be met, the index of the matching slot is recorded, and the frame header length is determined to be the first width.

[0027] If the value of the second frame header configuration register is non-zero, i.e., in the second width mode, the frame detection logic enables N-1 cascaded comparators in parallel to compare whether two consecutive slots are equal to the first frame header configuration value and the second frame header configuration value, respectively. If there exists any position where two consecutive slots are cascaded and matched, the frame start condition is determined to be true, the index of the matching start slot is recorded, and the frame header length is determined to be the second width.

[0028] In the second width mode, a cascaded matching intra-beat constraint is applied: the first frame header configuration value must not fall in the last slot of the beat, meaning the matched starting slot index must be less than or equal to N-2. If it falls in the last slot, frame start is not triggered. This constraint avoids timing convergence problems caused by cross-beat detection. After a successful match, the hardware calculates the frame data start byte offset based on the mode and passes it to the subsequent field extraction module and DMA write address generation logic.

[0029] The frame header detection of this invention is located in the application layer data path. The detection object is the software-defined frame protocol magic number, which is fundamentally different from the physical layer word aligner built into the FPGA transceiver. The word aligner is used to align the byte or word boundaries in the encoded serial data stream. Its pattern detection width is limited by the transceiver architecture, and the pattern is fixed at compile time.

[0030] Step S3: Extract the category identifier field and assemble the index entries.

[0031] After the frame header detection module completes frame start detection and determines the start position of the frame data, the field extraction module performs field extraction operations on the current frame. This module contains multiple configurable field offset registers. As the frame data stream passes through the field extraction module in a tick-based manner, the module extracts a 32-bit field in parallel from the corresponding byte offset based on the value of each offset register. All field extractions are performed in parallel within the data path, without introducing additional clock delays. The second extracted field is designated as a classification identifier field, used to uniquely identify a virtual LAN channel.

[0032] After the fields are extracted, the index entry assembly logic assembles the following information into an index entry: the first frame header configuration value for software verification, the frame sequence number, the frame data address offset pointing to the starting address of the frame in the shared physical ring receive buffer, and multiple extracted user-configurable fields, of which the predetermined position is the classification identifier field.

[0033] After the index entries are assembled, they are written to the index circular buffer in host memory via an independent index DMA channel. Simultaneously, frame payload data is written to the shared physical circular receive buffer via the main data DMA channel. The two DMA channels operate independently and do not interfere with each other. The index circular buffer and the main data area are located in different offset segments of the same large page memory and share the same PCIe base address register translation window. The extraction of classification identifiers is completed entirely within the FPGA hardware data path without any software intervention, achieving zero-latency field extraction.

[0034] Step S4: The kernel worker thread polls the index entries and performs routing decisions.

[0035] The host-side driver software maintains a kernel worker thread that periodically checks the index circular buffer for new index entries in a polling manner. When a new entry is detected, an index entry is read, and the classification identifier value is extracted from the predetermined position of the index entry.

[0036] The VPN routing rule set is an array maintained by the driver software. Each rule contains a match value field, a mask field, and a VPN identifier field. The rule set is stored as an array, and the matching order is from the first rule to the last, with the first matching rule taking effect. The routing decision function takes the category identifier as input and performs sequential matching: it initializes the rule index to the first rule; it performs a bitwise AND operation between the category identifier and the mask field of the current rule to obtain the first intermediate value, and performs a bitwise AND operation between the match value field and the mask field of the current rule to obtain the second intermediate value; it compares the first and second intermediate values ​​for equality; if they are equal, the current rule is considered matched, and the VPN identifier of the current rule is used as the routing result; if they are not equal, it moves to the next rule to continue matching; if no match is found after traversing all rules, the VPN identifier is set to a predetermined discard value.

[0037] In the above matching mechanism, when a bit of the mask is zero, the corresponding bit in the category identifier is not compared and is considered a wildcard; when all bits of the mask are zero, the rule matches any category identifier value. By pointing the virtual LAN identifiers of multiple rules to the same virtual LAN, multiple different category identifier values ​​can be routed to the same virtual LAN queue.

[0038] Check if the routing result is the predetermined drop value. If so, discard the frame and increment the miss count. If the routing result is not the predetermined drop value, check if the pause status flag corresponding to the VLAN identifier is true. If true, discard the frame and increment the pause drop count. If the pause status is false, deliver the frame descriptor to the frame queue of the corresponding VLAN. If delivery is successful, increment the routing success count; if the queue is full and there are active consumers in the VLAN, trigger backpressure; if the queue is full and there are no consumers in the VLAN, discard the frame directly.

[0039] The driver software supports replacing the entire rule set at runtime. The replacement operation is performed when the index DMA channel is not enabled. The new rule set is written to the whole set at once and takes effect atomically. There is no need to regenerate the FPGA bit stream or stop the data flow.

[0040] Step S5: Maintain an independent frame queue for each virtual LAN and implement zero-copy delivery.

[0041] Each VLAN ID corresponds to an independent circular frame queue. Each frame queue contains a circular array of frame descriptors, producer write positions, consumer read positions, and user-space blocking wait queues. The classification identifier is 32 bits wide. The system can theoretically support a large number of independent VLAN IDs. In actual deployment, the number of VLANs is only limited by the available memory on the host, without any upper limit constraint at the FPGA hardware level.

[0042] Each frame descriptor contains: a data address field pointing to the frame payload data offset address within the shared physical ring receive buffer (this physical memory is the same buffer written to by the FPGA DMA), a data length field, the offset of the corresponding index entry in the index ring buffer, a classification identifier value, and a frame header snapshot. The data addresses in the frame descriptors of all VLAN queues point to different offset positions within the same physical ring receive buffer, and the frame data itself is not copied at all during the entire process.

[0043] The specific data flow is as follows: The FPGA directly writes the frame payload data to the shared physical ring receive buffer via the main data DMA; the kernel worker thread reads the index entries from the index ring buffer, extracts the classification identifier, and completes the routing decision; the kernel worker thread delivers the frame descriptor containing the data address to the frame queue of the corresponding virtual LAN; the user-space application maps the shared physical ring receive buffer to the user-space virtual address space through memory mapping; the user-space application reads the frame descriptor from the frame queue of each virtual LAN and directly accesses the mapped virtual address to read the frame data according to the data address.

[0044] When a kernel worker thread delivers a frame descriptor to the frame queue of a virtual local area network (VLAN), if the queue is full and there are no active consumers in the VLAN, the frame is discarded without generating backpressure. If the queue is full and there are active consumers in the VLAN, a backpressure signal is triggered, and the kernel worker thread stops delivering new frames to the queue. Subsequent frames hitting the VLAN are temporarily deferred at the routing layer, and the backpressure signal does not affect the data flow of other VLANs.

[0045] Step S6: Perform a dynamic pause or resume operation for the virtual LAN.

[0046] User-space applications perform runtime start / stop operations on any virtual LAN via the IOCTL system call. The driver software maintains a pause status flag for each virtual LAN in an atomically stored manner, and all read / write operations are guaranteed to be concurrently safe with kernel worker threads.

[0047] When a user-space call invokes the pause operation, the driver verifies whether the VLAN ID is within a valid range, atomically sets the pause status flag to true, and then returns. The entire pause operation is completed within microseconds. After the pause, frames hitting the VLAN are directly discarded during the routing decision phase, do not enter the per-VLAN frame queue, and the discarded frames do not update the consumption progress of the VLAN.

[0048] When a user-mode call to resume operation is made, the driver atomically sets the pause status flag to false, and subsequent frames hitting the virtual LAN resume normal delivery.

[0049] The pause or resume mechanism of this invention is fundamentally different from Ethernet priority flow control: Ethernet priority flow control operates at the physical layer and data link layer, and belongs to link-level hardware flow control, which blocks traffic of a specific priority on the link by sending pause frames; the pause or resume mechanism of this invention operates at the PCIe DMA buffer consumer driver layer, and belongs to consumer-level software flow control, which does not stop the continuous writing of FPGA hardware DMA, but only determines whether the frame is delivered to the user-space consumer.

[0050] Step S7: Perform multi-queue coordinated advancement of global read pointer.

[0051] In the zero-copy model, all VLANs share the same physical circular receive buffer. The FPGA hardware maintains a write pointer (indicating the position of the FPGA's next DMA write) and a read pointer (indicating the boundary that the driver has confirmed is safe for the FPGA to overwrite). When the distance between the write pointer and the read pointer reaches the buffer size, the FPGA determines that the buffer is full and stops DMA writing. The advancement of the read pointer must ensure that any unconsumed frame data in any VLAN is not overwritten by new data.

[0052] The global read pointer advance function in the driver software performs the following operations: reads the current hardware read pointer value; iterates through all virtual LANs (VLANs), skipping any VLAN that has never been consumed or is in a paused state; for VLANs that pass the screening, calculates their consumption progress relative to the forward distance of the current read pointer; takes the minimum value among all distances as the candidate advance step size; reads the current hardware write pointer value and calculates the forward distance of the write pointer relative to the current read pointer; if the candidate advance step size is greater than the forward distance of the write pointer, clamps the candidate advance step size to the forward distance of the write pointer, forming a PCIe pipeline delay barrier. When the FPGA writes payload data via DMA, the data needs a certain transmission delay to reach the host memory from the FPGA through the PCIe bus. During this period, the hardware write pointer may have been updated, but the payload data has not yet actually arrived in memory. The clamping operation ensures that the advance target of the read pointer does not exceed the currently confirmed completed write pointer position; if the advance step size is zero, it returns; writes the advanced read pointer value to the FPGA hardware read pointer register and advances the global read pointer.

[0053] Suspended VLANs are skipped from minimum value calculations, which is crucial for eliminating headline congestion. For example, a consumer in VLAN A has reached a relatively far position, while a consumer in VLAN B, due to slower processing, has only reached a closer position. If VLAN B is not paused, the global read pointer takes the smaller of the two values, and VLAN A is dragged down by VLAN B. After pausing VLAN B, its calculation is skipped, the global read pointer takes the progress of VLAN A, and VLAN A can continue to progress. The blocking effect of the slow consumer is completely isolated. VLANs that have never been consumed are also skipped from calculations, ensuring that VLANs that have not yet started consuming will not block the read pointer progress of already bound VLANs.

[0054] Step S8: Perform automatic switching between no-consumer mode and consumer-mode.

[0055] The system automatically switches between consumer-free mode and consumer-active mode based on whether any virtual LANs have started consuming data. When no virtual LANs have been consumed, the system enters consumer-free mode. The driver does not parse index entries or perform route delivery; it only advances the read pointer to closely follow the write pointer to release buffer space. All frame data is overwritten and discarded, and FPGA DMA continues to write smoothly.

[0056] When any VLAN is consumed by user space for the first time, the system monotonically switches from a no-consumer mode to a consumer-enabled mode, fully activating VLAN routing and queuing for each VLAN. Kernel worker threads begin parsing index entries, executing routing decisions, delivering frame descriptors, and calling the minimum value to advance the read pointer. The switching path is monotonically unidirectional; once a consumer is activated, it does not roll back. In consumer-enabled mode, all frames not bound to VLANs are discarded due to rule mismatches.

[0057] The no-consumer mode ensures that when the FPGA starts receiving data and writing it to memory immediately after the system is powered on, the read pointer can continue to advance to release the buffer space even if the consumer process has not yet started. This avoids the DMA stopping and back pressure on the link caused by the buffer being full, allowing the consumer to come online at any time during the continuous operation of the data stream without prior coordination of start and stop timing.

[0058] Step S9: Perform rule set replacement and state management through the user-space interface.

[0059] User-space applications perform the following operations through the IOCTL interface: replace the programmable rule set entirely at runtime, with the replacement operation taking effect atomically; perform a dynamic pause operation on any virtual LAN, after which frames hitting that virtual LAN are dropped at the software routing layer without entering the queue; perform a recovery operation on any virtual LAN, after which frames from that virtual LAN resume normal delivery; and read statistical information, including miss counts, pause / drop counts, and successful routing counts.

[0060] The following complete embodiment illustrates the entire workflow of the present invention from system startup to data consumption.

[0061] The system powers on, and the FPGA bitstream loading is complete. The FPGA begins receiving multi-channel data via the fiber optic interface. The driver software loads, allocates large pages of memory as a shared physical circular receive buffer, configures the first frame header to 0x5A5A5A5A, and the second frame header to all zeros (first width mode), and extracts the offset register from the configuration fields. The driver enables the receive channel, and the FPGA begins DMA writing. At this point, there are no user-space consumers, and the system automatically enters a no-consumer mode. The driver cycle advances the read pointer, closely following the write pointer, and data is overwritten and discarded, ensuring continuous FPGA DMA operation.

[0062] User-mode process A starts, binds to VLAN 0, and begins consuming data. The driver detects that VLAN 0 is being consumed for the first time, and the system monotonically switches from no-consumer mode to consumer-enabled mode. Kernel worker threads begin polling the index ring buffer, reading index entries, extracting category identifiers, and performing routing decisions. Assume that rule 0 in the current rule set matches category identifier 0x10000001 and points to VLAN 0. The kernel worker thread reads an index entry with category identifier 0x10000001, rule 0 is matched, and the VLAN identifier is 0. Checking that the pause state is false, the kernel thread delivers the frame descriptor to the frame queue of VLAN 0, with the data address in the frame descriptor pointing to the offset of the frame data in the shared ring buffer. User-mode process A reads the descriptor from the frame queue of VLAN 0 and directly accesses the frame data through memory mapping, achieving zero-copy.

[0063] User-space process A's consumption speed decreases, causing VLAN 0's consumption progress to fall behind. User-space process B (VLAN 1) consumes at a normal speed, but because the global read pointer takes the smaller of the two values, VLAN 1 is slowed down by VLAN 0. User-space process A performs a pause operation on VLAN 0, and the driver atomically sets the pause status flag to true. The kernel worker thread detects the pause status as true in subsequent routing, and frames hitting VLAN 0 are directly discarded. VLAN 0 is skipped in the global read pointer calculation, and the progress of VLAN 1 is taken. VLAN 1 resumes its normal progress speed, and the headline blockage is eliminated. After user-space process A finishes processing its backlog, it performs a recovery operation on VLAN 0. The driver atomically sets the pause status flag to false, the kernel worker thread resumes delivering frames to VLAN 0, VLAN 0 re-participates in the global read pointer calculation, and the system returns to normal dual-channel parallel consumption.

[0064] The present invention differs from the prior art in the following essential ways: The difference between this invention and the explicit mode register scheme lies in the fact that the explicit mode register scheme requires an additional mode selection register bit, increasing hardware resource consumption and posing a risk of software configuration errors where the mode register value does not match the actual frame header length. This invention uses the condition of whether the second frame header configuration value is zero as an implicit criterion, with the mode intrinsically determined by the frame header data value, thus achieving data-driven mode self-consistency.

[0065] The difference between this and a word aligner is that a word aligner is a physical layer function built into the FPGA transceiver, and its mode is fixed at compile time. The frame header detection in this invention is located in the application layer data path, and its mode can be hot-switched at runtime via software register writes.

[0066] The difference between this invention and the independent DMA descriptor ring scheme of smart NICs is that the smart NIC scheme trades hardware resources for isolation, and the number of virtual LANs is limited by hardware resources. This invention achieves multi-consumer isolation on a shared ring buffer through a minimum global read pointer coordination mechanism, and the number of virtual LANs is only limited by host memory.

[0067] The difference between this invention and the DPDK multi-consumer circular buffer lies in the fact that the DPDK multi-consumer circular buffer solves the software-level dequeue mutual exclusion problem. The minimum value read pointer of this invention solves the hardware DMA write overwrite boundary and multiple software consumer frame security issues. Directly porting the DPDK model to an FPGA DMA shared circular buffer scenario will not work.

[0068] The difference between this invention and Ethernet priority flow control is that Ethernet priority flow control is a link-level hardware flow control, and pausing will cause data transmission to stop on the link. This invention's pausing is a consumer-level software flow control, which does not stop FPGA DMA writing, but only determines whether a frame is delivered to user space.

[0069] Based on the same inventive concept, embodiments of the present invention also provide a dual-frame header adaptive detection and VLAN hardware traffic splitting system, the system being used to execute the method, including: The FPGA hardware layer includes a frame header detection module and a field extraction module. The frame header detection module includes a first frame header configuration register and a second frame header configuration register. The frame header detection logic switches between the first frame header width mode and the second frame header width mode based on whether the value of the second frame header configuration register is zero. After the frame start hit, the field extraction module extracts multiple fields from the frame data stream, including at least the classification identifier field, and assembles them into index entries. The PCIe DMA transport layer includes a main data DMA channel and an independent index DMA channel. The main data DMA channel writes frame payload data into a shared physical circular receive buffer in the host memory, and the independent index DMA channel writes the index entries into an index circular buffer in the host memory. The host kernel driver layer includes an index parsing thread, a virtual LAN routing rule engine, and a per-virtual LAN queue management module. The index parsing thread reads index entries from the index ring buffer and extracts the classification identifier field. The virtual LAN routing rule engine determines the virtual LAN to which the frame belongs based on the programmable rule set. The per-virtual LAN queue management module delivers the frame descriptor containing the shared buffer address offset to the corresponding queue without copying the frame payload data. The global read pointer collaborative advancement module is used to take the minimum value of the consumption progress of all active and non-paused VLAN queues to update the FPGA hardware read pointer register; The user-mode interface layer is used to provide runtime replacement of the rule set, dynamic pause or resumption of the virtual LAN, and statistical information reading functions.

[0070] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A dual-frame header adaptive detection and VLAN hardware traffic splitting method, characterized in that, include: In the FPGA, a first frame header configuration value and a second frame header configuration value are set, and the mode criterion is whether the second frame header configuration value is zero: if it is zero, the frame start detection is performed based on the width of the first frame header, and only the first frame header configuration value is matched; if it is non-zero, the frame start detection is performed based on the width of the second frame header, and the first frame header configuration value and the second frame header configuration value are required to be cascaded and matched. After the frame start hit, the FPGA hardware extracts the classification identifier field from the frame data stream, assembles the classification identifier field together with the frame data address offset into an index entry, and writes it into the host memory through an independent index DMA channel. The host-side driver software reads the classification identifier field from the index entry, determines the virtual local area network to which the frame belongs based on the programmable rule set, and delivers the frame descriptor containing the frame data address offset to the independent frame queue of the corresponding virtual local area network. The frame descriptor points to the frame payload data in the shared physical ring receive buffer and does not copy the frame data itself. The global read pointer is advanced based on the minimum consumption progress among all active VLAN queues; paused VLANs are not included in the calculation of this minimum.

2. The method according to claim 1, characterized in that, The cascading matching requires that the first frame header configuration value and the second frame header configuration value match simultaneously in two consecutive slots within the same data beat, and the first frame header configuration value must not fall in the last slot of that data beat.

3. The method according to claim 1, characterized in that, When switching from the first frame header width mode to the second frame header width mode, all offset values ​​used for field extraction are uniformly increased by a compensation value. The compensation value is equal to the difference between the second frame header width and the first frame header width, and all offset values ​​are based on the frame header start byte as the zero point.

4. The method according to claim 1, characterized in that, The index entry includes a frame header configuration value, a frame sequence number, a frame data address offset, and multiple user-configurable extraction fields. The predetermined position among these extraction fields is the classification identifier field. The index ring buffer and the shared physical ring receive buffer are located in different offset segments of the same large page memory and share the same PCIe base address register translation window.

5. The method according to claim 1, characterized in that, The programmable rule set contains multiple rules, each containing a matching value, a mask, and a virtual local area network (VLAN) identifier. During routing decision-making, the rule set is scanned sequentially. If the matching value of the classification identifier matches the current rule's matching value in the bit specified by the mask, the rule is matched, and the VLAN identifier of that rule is used as the routing result. If no match is found after traversing all rules, the frame is discarded. If the VLAN identifier of a rule is a predetermined discard value, the frame is discarded.

6. The method according to claim 1, characterized in that, The independent frame queue delivered to the corresponding VLAN includes: checking the pause status flag of the target VLAN; if it is in a paused state, the frame is discarded directly without blocking the advancement of the global read pointer; if it is not in a paused state, delivery is performed; if there is no consumer process in the target VLAN, the frame is discarded directly; the pause status flag is read and written through atomic operations to ensure concurrency safety.

7. The method according to claim 1, characterized in that, The advancement of the global read pointer includes: traversing all virtual local area networks (VLANs), calculating the distance of consumption progress relative to the current read pointer for each active and non-paused VLAN, and taking the minimum value among all distances as the advancement step size; if the advancement step size exceeds the distance of the hardware write pointer relative to the current read pointer, then clamping the advancement step size to the distance of the hardware write pointer.

8. The method according to claim 1, characterized in that, When no VLAN is consumed, the system automatically enters a no-consumer mode, where the driver only advances the read pointer to immediately follow the write pointer to release buffer space, without performing frame parsing or route delivery. Once any VLAN is consumed for the first time, the system monotonically switches from the no-consumer mode to the consumer-enabled mode and does not roll back.

9. The method according to claim 1, characterized in that, The host-side driver software replaces the programmable rule set entirely at runtime via the IOCTL interface, and the replacement operation takes effect atomically. After performing a dynamic pause operation on any virtual LAN via the IOCTL interface, subsequent frames hitting that virtual LAN are dropped at the software routing layer and do not enter the queue. After performing a recovery operation via the IOCTL interface, normal delivery of frames to that virtual LAN is resumed. The pause operation does not stop the FPGA hardware DMA from continuously writing to the shared physical ring receive buffer.

10. A dual-frame header adaptive detection and VLAN hardware traffic splitting system, characterized in that, The system is used to perform the method according to any one of claims 1-9, comprising: The FPGA hardware layer includes a frame header detection module and a field extraction module. The frame header detection module includes a first frame header configuration register and a second frame header configuration register. The frame header detection logic switches between the first frame header width mode and the second frame header width mode based on whether the value of the second frame header configuration register is zero. After the frame start hit, the field extraction module extracts multiple fields from the frame data stream, including at least the classification identifier field, and assembles them into index entries. The PCIe DMA transport layer includes a main data DMA channel and an independent index DMA channel. The main data DMA channel writes frame payload data into a shared physical circular receive buffer in the host memory, and the independent index DMA channel writes the index entries into an index circular buffer in the host memory. The host kernel driver layer includes an index parsing thread, a virtual LAN routing rule engine, and a per-virtual LAN queue management module. The index parsing thread reads index entries from the index ring buffer and extracts the classification identifier field. The virtual LAN routing rule engine determines the virtual LAN to which the frame belongs based on the programmable rule set. The per-virtual LAN queue management module delivers the frame descriptor containing the shared buffer address offset to the corresponding queue without copying the frame payload data. The global read pointer collaborative advancement module is used to take the minimum value of the consumption progress of all active and non-paused VLAN queues to update the FPGA hardware read pointer register; The user-mode interface layer is used to provide runtime replacement of the rule set, dynamic pause or resumption of the virtual LAN, and statistical information reading functions.

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