A method and system for enhancing the stability of a RapidIO network

Abstract

The application discloses a design method and system for enhancing working stability of a RapidIO network and belongs to the technical field of high reliability design of airborne embedded computers. In view of the problems of failure of initialization node enumeration of the existing RapidIO network and failure of recovery of an offline node in running, the application adopts a phased fault detection and recovery mechanism: in an initialization enumeration stage, error and state registers of each port of a switching chip are read, a plurality of flag bits are comprehensively judged, and enumeration is completed after reset of a recoverable abnormal port; in a network running stage, a port state is polled at a preset period, combined with multi-flag bit judgment and node identity authentication, port reset is executed on the offline node to realize automatic recovery. The application does not need additional hardware, improves network initialization success rate and self-healing capacity through software optimization, enhances the stability of the RapidIO network, and can be applied to various RapidIO networking systems.

Description

Technical Field

[0001] This invention relates to the field of high reliability design technology for airborne embedded computer products, specifically a method and system for enhancing the operational stability of RapidIO networks. Background Technology

[0002] RapidIO bus, as an embedded system bus, has wide applications in the airborne aviation field. RapidIO bus features high bandwidth and low latency, along with hardware error correction and retransmission mechanisms, meeting the needs of high-performance embedded systems for massive data exchange. Unlike the tree-like master-slave structure of the PCIe bus, RapidIO bus supports point-to-point interconnection, enabling the construction of complex network topologies through switch chips. Any node in the network can communicate directly, and data can be transmitted quickly within the system without passing through a master node.

[0003] Networks built using RapidIO switching chips typically employ a processor-equipped device as the network maintenance node. During system startup, this node enumerates devices, configures routes according to a configuration table, and allocates identifiers and space to each device. During system operation, it monitors and manages the status of nodes in the network. Because RapidIO nodes are diverse, including data processing units, large-capacity storage units, signal processing units, and intelligent processing units, node enumeration may fail during system initialization due to differences in startup time, port failures, or inconsistencies in identifiers. Alternatively, nodes may occasionally go offline during operation. Current maintenance operations use maintenance packets to initialize the RapidIO network and perform device fault detection and recovery. However, maintenance operations can only access the device's register fields; if the target device is offline, maintenance operations cannot be completed. In practical applications, the switch chip's error and status registers contain multiple flags. A single flag that only checks whether a port is in a normal state cannot accurately determine whether a port is truly communicable. This can lead to situations where the flag indicates a normal port, but the actual port communication is abnormal, resulting in abnormal nodes not being effectively identified and recovered. Without proper handling methods, disconnected nodes may not be able to come back online, affecting system performance.

[0004] Therefore, a design method is needed that can comprehensively judge the errors and status registers of the switching chip and effectively recover abnormal nodes during the initialization enumeration phase and the running phase, so as to ensure the high reliability of the RapidIO network. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention provides a method and system for enhancing the stability of RapidIO networks. By comprehensively judging the error and status registers of the RapidIO switching chip using multiple flag bits, recoverable abnormal nodes are identified and restored during the initialization enumeration phase and the running phase. This solves the problems of some nodes failing to come online during RapidIO network initialization and some nodes being unable to come back online after occasional disconnections during the running phase, thereby improving the stability of the RapidIO network.

[0006] This invention is achieved through the following technical solution: Firstly, this application provides a design method for enhancing the stability of RapidIO networks, comprising the following steps: Step 1: In the RapidIO network initialization enumeration phase, based on the RapidIO switching chip that has completed the basic configuration, the error and status registers of each port are read through maintenance read operations. Multiple flag bits are comprehensively judged to identify abnormal ports. After performing a reset recovery operation on recoverable abnormal ports, the enumeration is performed again to obtain the complete node enumeration result with all ports in normal status. Step 2: During the RapidIO network operation phase, based on the complete node enumeration results, the error and status registers of each port of the switching chip are polled at a preset detection cycle. Combining multi-flag comprehensive judgment and node authentication method, port reset recovery operation is performed on abnormally offline recoverable nodes to bring offline nodes back online.

[0007] Preferably, the multiple flag bits in step 1 include a port ready flag bit, an output error stop flag bit, and an input error stop flag bit; when the port ready flag bit is valid but the output error stop flag bit or the input error stop flag bit is set, the port is determined to be in a recoverable abnormal state.

[0008] Preferably, the reset and recovery operation performed on the recoverable abnormal port in step 1 includes: Perform shutdown and enable operations sequentially on the abnormal port, clear the set state of the output error stop flag and the input error stop flag, and complete the port abnormal state reset.

[0009] Preferably, the basic configuration in step 1 includes: parsing the system configuration table, completing routing configuration, allocating device identifiers, configuring input / output spaces, initializing the device identifier table and port status table, completing the configuration of the switching chip routing table and basic registers, and performing preliminary network enumeration operations.

[0010] Preferably, the multi-flag comprehensive judgment in step 2 includes: The port ready flag, output error stop flag, and input error stop flag are jointly checked; when the port ready flag is valid and the output error stop flag and input error stop flag are not set, the port's basic state is determined to be normal.

[0011] Preferably, the node authentication method in step 2 includes: After the basic status of the port is normal, the identifier register of the device connected to the port is read through the maintenance read operation. The read device identifier is compared with the expected identifier in the system configuration table. If they match, the corresponding node is confirmed to be online. If they do not match, the node is determined to be offline.

[0012] Preferably, before polling and detecting each port in step 2, the method further includes: first reading the error and status register of the main control processor port; if the status of the main control processor port does not meet the preset normal conditions, then performing a shutdown and enable operation on the main control processor port.

[0013] Preferably, the reset recovery operation includes at least one of port shutdown and enable operation, port link retraining, or transmission rate degradation.

[0014] Secondly, this application provides a design system for enhancing the operational stability of RapidIO networks, characterized by comprising: The initialization enumeration module is used during the initialization enumeration phase of the RapidIO network. Based on the RapidIO switching chip that has completed basic configuration, it reads the error and status registers of each port through maintenance read operations, makes a comprehensive judgment on multiple flag bits to identify abnormal ports, performs a reset recovery operation on recoverable abnormal ports, and then re-enumerates to obtain a complete node enumeration result with all ports in normal status. The operation detection and recovery module is used during the RapidIO network operation phase to poll the error and status registers of each port of the switching chip based on the complete node enumeration results at a preset detection cycle. Combining multi-flag comprehensive judgment and node authentication methods, it performs port reset recovery operation on recoverable nodes that have abnormally dropped online, so that the dropped nodes can come back online.

[0015] Thirdly, this application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the design method for enhancing the operational stability of the RapidIO network as described above.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: This application provides a design method to enhance the stability of RapidIO networks. Addressing the weakness of existing RapidIO networks that rely solely on port readiness flags to determine link status and fail to identify implicit port transmission anomalies, this method constructs a fault detection and recovery mechanism covering the entire lifecycle from initialization enumeration to operation. When a RapidIO switch chip port triggers an error stop flag due to a transmission anomaly, the port readiness flag may remain valid, resulting in a implicit fault where "the link appears normal, but actual transmission is impossible." Traditional solutions directly perform enumeration or node identity reading, leading to node enumeration initialization failure, unrecoverable offline nodes during operation, and even triggering processor bus anomalies. This method, through joint verification of port errors and multiple flags in the status register, identifies and resets abnormal ports before enumeration during initialization, clears port error states before node authentication during operation, and clears error flags and restores link transmission capability through port shutdown and enable operations. This method requires no new hardware circuitry and can solve the problem of node disconnection caused by latent faults simply through software logic optimization. It effectively improves the success rate of network initialization and the self-healing capability of faults during operation, reduces operation and maintenance intervention costs, and is suitable for high-reliability embedded application scenarios such as airborne systems. It has good engineering feasibility and promotion value.

[0017] This application also proposes a system, an electronic device, and a computer storage medium for enhancing the operational stability of RapidIO networks, possessing all the advantages of the aforementioned methods for enhancing the operational stability of RapidIO networks. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the RapidIO network topology using the TSI578 switching chip as an example. Figure 2 This is a schematic diagram of the port status register (CSR) of the TSI578 chip of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] A design method to enhance the stability of RapidIO networks includes the following steps: Step 1: During the RapidIO network initialization enumeration phase, the error and status registers of each port of the switching chip are read by maintaining read operations. The port ready flag, output error stop flag, and input error stop flag are comprehensively judged. When the port ready flag is valid but the output error stop flag or the input error stop flag is set, the port is determined to be abnormal. The abnormal port is closed and enabled, and then the enumeration is performed again to obtain the complete node enumeration result. Step 2: During the RapidIO network operation phase, based on the complete node enumeration results, the error and status registers of each port are polled at a preset period. The port ready flag, output error stop flag, and input error stop flag are comprehensively judged to identify abnormal offline nodes. For recoverable abnormal nodes, shutdown and enable operations are performed to bring the offline nodes back online.

[0023] In the port error and status registers of RapidIO switching chips, the port ready flag only reflects the training connection status of the physical link and cannot indicate whether the port has entered a stopped state due to transmission errors. When the port triggers the output error stop flag or the input error stop flag is set due to a transmission anomaly, the port has actually stopped transmitting and receiving data packets, but the port ready flag may still remain valid, forming a hidden anomaly of "link normal, communication failed". During the initialization enumeration phase, traditional solutions only rely on the port ready flag to determine the port status and directly perform node enumeration and device identity reading. This can lead to node enumeration failure due to the failure of the port's actual transmission capability. This method adds a multi-flag joint verification before enumeration. It first clears the error stop flag and restores the port's transmission capability through port shutdown and enable operations, and then performs the enumeration operation. This eliminates the impact of hidden port anomalies on the enumeration process from the root and improves the success rate of initialization node online. During network operation, traditional fault detection schemes do not preprocess the error stop flag. Directly reading the remote device identifier can easily trigger bus timeouts due to port transmission failures, leading to abnormal processor detection and making it impossible for offline nodes to recover. This method adopts a hierarchical detection logic of "clearing errors first, then verifying identity". It first resets the port error state to restore the transmission path, and then verifies the node's online status by comparing the device identifier. This avoids system disturbances caused by abnormal readings and can retrain the link through port reset, enabling offline nodes caused by occasional faults to automatically recover and come back online. This achieves fault self-healing during network operation and fully ensures the working stability of the RapidIO network throughout its entire lifecycle.

[0024] Example 1 This embodiment uses the RapidIO network of an airborne computer system as an implementation carrier to specifically illustrate the design method for enhancing the operational stability of the RapidIO network described in this invention. The network topology of this system is shown in Figure 1, comprising two CPU modules and seven service node devices. A cascaded network topology is constructed using two TSI578 RapidIO switching chips, each deployed on one of the two CPU modules. Each service node accesses the network through the physical ports of the switching chips, enabling full-node data interaction.

[0025] Reference Figure 1 and Figure 2 A design method to enhance the stability of RapidIO networks includes the following steps: Step 1: During the RapidIO network initialization enumeration phase, based on the RapidIO switching chip that has completed the basic configuration, the error and status registers of each port are read through maintenance read operations. Multiple flag bits are comprehensively judged to identify abnormal ports. After resetting and restoring the abnormal ports that can be recovered, the enumeration is performed again to obtain the complete node enumeration result with all ports in normal status.

[0026] The specific implementation method of step 1 will be described in detail below.

[0027] S1.1: Parse the system configuration table, complete the routing configuration, assign device identifiers, configure input / output space, initialize the device identifier table and port status table, complete the configuration of the switching chip routing table and basic registers, perform preliminary network enumeration operations, and build the basic network architecture.

[0028] Enumeration refers to the process by which network maintenance nodes scan, identify, and configure all connected node devices in the RapidIO network. This includes discovering node devices in the network, reading the identifiers and attribute information of each device, assigning unique identifiers and address spaces to each device according to the configuration table, and configuring the routing table of the switching chip to enable communication between any nodes in the network. After the initial network enumeration operation is completed, each node device is assigned a corresponding identifier, and the network topology is initially established.

[0029] S1.2: Before outputting the current status and attributes of the network node, the port error and status registers of all service ports of the switching chip are read sequentially through maintenance read operations, and the port ready flag, output error stop flag, input error stop flag and port uninitialized flag are extracted from the registers; See Figure 2 The port ready flag corresponds to bit 30 of the register, the output error stop flag corresponds to bit 15 of the register, the input error stop flag corresponds to bit 23 of the register, and the port uninitialized flag corresponds to bit 31 of the register.

[0030] S1.3: Perform joint verification on the flag bits of each port: When the port ready flag bit is valid, but the output error stop flag bit or the input error stop flag bit is set, the port is determined to be in a recoverable abnormal state. Perform shutdown and enable operations sequentially on the abnormal port, clear the set state of the output error stop flag and the input error stop flag, and complete the port abnormal state reset.

[0031] S1.4: After all ports have completed status verification and anomaly recovery, perform a complete node enumeration operation to confirm the status and attributes of all nodes on the network, obtain the final initialization enumeration result, and start the node fault detection and recovery task during the running phase.

[0032] During RapidIO network initialization enumeration, simply checking the port ready flag cannot accurately determine whether a port is truly in a communicable state. When the port ready flag shows normal, but the output error stop flag or input error stop flag is set, the port is actually unable to transmit data packets normally, and directly performing enumeration will cause node enumeration failure. This step adds a multi-flag comprehensive judgment process before enumeration is complete, identifying and resetting ports in a latent abnormal state in advance. This effectively eliminates enumeration failures caused by startup timing differences and momentary port transmission errors, ensuring that all recoverable nodes successfully come online during the initialization phase, thus improving the first-time success rate of network initialization.

[0033] As an alternative, the above method is applicable not only to the TSI578 RapidIO switching chip, but also to other RapidIO switching chips. The judgment logic and reset operation of the flag bits are adjusted according to the port status register definition of the corresponding chip, which has universal applicability.

[0034] As a preferred approach, port anomaly recovery during the initialization phase can also include port link retraining operations to adapt to more severe port anomaly scenarios such as link lockout, further enhancing the fault recovery capability during the initialization phase.

[0035] In one possible implementation, for a multi-chip cascaded RapidIO network, the status verification between the cascaded ports and the remote switching chip ports can be completed step by step through maintenance read operations with a specified number of hops, ensuring the success rate of initialization enumeration in multi-level networking scenarios.

[0036] Step 2: Based on the complete node enumeration results, poll the error and status registers of each port of the RapidIO switching chip at a preset detection cycle. Combine multi-flag comprehensive judgment, hierarchical port reset and node authentication methods to automatically reset and restore recoverable nodes that have abnormally dropped online, so that the dropped nodes can be brought back online, ensuring the integrity of node devices during the operation of the RapidIO network and enhancing the stability of network operation.

[0037] This mechanism is used for fault self-healing during continuous network operation, ensuring the online integrity and communication reliability of network nodes.

[0038] S2.1 Start the device detection and recovery task, and sequentially traverse all service ports of the switching chip according to the preset detection cycle; before querying the status of each slave node port, first read the port error and status register of the master control processor port. If the status of the master control processor port does not meet the preset normal conditions, first perform the shutdown and enable operation on the master control processor port to complete the status reset of the detection path.

[0039] S2.2. Differentiate between cascaded ports and ordinary service ports and perform register reads separately: For inter-processor cascaded ports, use a maintenance read operation with zero hops to read the port error and status registers of the corresponding port of the current-level switching chip; for ordinary service ports, first use a maintenance read operation with zero hops to read the port error and status registers of the current-level port to provide a port status basis for subsequent node authentication.

[0040] S2.3 Perform multi-flag joint verification on the read port error and status register values, and comprehensively judge the status of the port ready flag, output error stop flag, and input error stop flag. When the port ready flag is valid and neither the output error stop flag nor the input error stop flag is set, the basic status of the port is determined to be normal. If the output error stop flag or the input error stop flag is set, the port is determined to be in an abnormal state. Perform shutdown and enable operations on the corresponding port, clear the error stop flag, and then proceed to the subsequent verification stage.

[0041] S2.4 After the port's basic status is normal, the identifier register of the device connected to the port is read through a maintenance read operation with a specified number of hops. The read device identifier is compared with the expected identifier in the system configuration table. If the comparison is consistent, the corresponding node is confirmed to be online and working normally, and the node status table is updated. If the comparison is inconsistent, the node is determined to be offline, and the corresponding port is closed and enabled to retrain the link and complete the node recovery.

[0042] S2.5 After completing the detection and recovery operations of all ports, update the online status table of all network nodes to form the online node status output for the current period, which serves as the benchmark data for the next round of periodic detection.

[0043] During RapidIO network operation, nodes may experience occasional disconnections due to transient link interference, transmission timeouts, or other reasons. Traditional detection methods only check the port ready flag and the port uninitialized flag. When the output error stop flag or input error stop flag is set, the port has actually stopped transmitting data packets, but the ready flag may still show as normal. In this case, directly reading the device identifier can easily trigger processor machine detection anomalies, leading to node recovery failure. A hierarchical processing logic of master control port pre-check, port error clearing, and node authentication is adopted. The port error state is reset before node verification is performed, avoiding system anomalies caused by abnormal readings and accurately recovering repairable port faults. This allows occasionally disconnected nodes to automatically reconnect without manual intervention, significantly improving the stability and self-healing capability of the RapidIO network.

[0044] As a preferred approach, the preset period of the aforementioned periodic status detection can be adjusted according to the system's real-time requirements and computing resource configuration. It can be set to different durations such as 1 second, 2 seconds, or 5 seconds to adapt to application scenarios with different reliability levels.

[0045] As an alternative, node fault detection can also be combined with an interrupt-triggered mode, which immediately triggers the fault detection and recovery process when a port generates an erroneous interrupt, replacing the pure periodic polling mode and further shortening the fault response time.

[0046] As a preferred approach, node fault recovery can employ a tiered recovery strategy, sequentially executing different recovery methods such as port reset, link retraining, and transmission rate degradation according to the severity of the fault, thereby improving the recovery success rate in complex fault scenarios.

[0047] In one possible implementation, for a multi-chip cascaded RapidIO network, the status detection and fault recovery of the remote switching chip port can be completed through a step-by-step transparent maintenance read operation, adapting to a large-scale RapidIO system with multi-level networking.

[0048] By employing the dual mechanisms of pre-initialization detection and periodic self-healing during operation, the entire lifecycle of the RapidIO network can be effectively covered, resolving issues such as initialization enumeration failures and unrecoverable occasional disconnections during operation. This comprehensively enhances the operational stability of the RapidIO network, and the method can be widely applied to various embedded network systems built on RapidIO switching chips.

[0049] Example 2 Correspondingly, this application provides a design system for enhancing the stability of RapidIO networks, including: The initialization enumeration module is used during the initialization enumeration phase of the RapidIO network. Based on the RapidIO switching chip that has completed basic configuration, it reads the error and status registers of each port through maintenance read operations, makes a comprehensive judgment on multiple flag bits to identify abnormal ports, performs a reset recovery operation on recoverable abnormal ports, and then re-enumerates to obtain a complete node enumeration result with all ports in normal status. The operation detection and recovery module is used during the RapidIO network operation phase to poll the error and status registers of each port of the switching chip based on the complete node enumeration results at a preset detection cycle. Combining multi-flag comprehensive judgment and node authentication methods, it performs port reset recovery operation on recoverable nodes that have abnormally dropped online, so that the dropped nodes can come back online.

[0050] It should be noted that, in the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another device, or some features may be ignored or not executed. The modules described as separate components may or may not be physically separated. The components shown as modules may be one or more physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs.

[0051] Furthermore, in the various embodiments of the present invention, the modules can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The integrated unit described above can be implemented in hardware or as a software functional unit.

[0052] An electronic device provided in this application includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the steps of the design method for enhancing the working stability of the RapidIO network as described in any of the above embodiments.

[0053] Another electronic device provided in this application embodiment may further include: an input port connected to a processor for transmitting multimodal data collected by an external acquisition device to the processor; a display unit connected to the processor for displaying the processor's processing results to the outside world; and a communication module connected to the processor for enabling communication between the electronic device and the outside world. The display unit may be a display panel, a laser scanning display, etc.; the communication method adopted by the communication module includes, but is not limited to, Mobile High Definition Link (HML), Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI), and wireless connection (including Wi-Fi, Bluetooth, Bluetooth Low Energy, and IEEE 802.11s-based communication technology).

[0054] This application provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the steps of the design method for enhancing the operational stability of RapidIO networks as described in any of the above embodiments.

[0055] For descriptions of relevant parts of the design system, electronic device, and computer-readable storage medium for enhancing the stability of RapidIO networks provided in this application's embodiments, please refer to the detailed descriptions of the corresponding parts in the design method for enhancing the stability of RapidIO networks provided in this application's embodiments; they will not be repeated here. Furthermore, parts of the technical solutions provided in this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0056] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A design method for enhancing the stability of RapidIO networks, characterized in that, Includes the following steps: Step 1: In the RapidIO network initialization enumeration phase, based on the RapidIO switching chip that has completed the basic configuration, the error and status registers of each port are read through maintenance read operations. Multiple flag bits are comprehensively judged to identify abnormal ports. After performing a reset recovery operation on recoverable abnormal ports, the enumeration is performed again to obtain the complete node enumeration result with all ports in normal status. Step 2: During the RapidIO network operation phase, based on the complete node enumeration results, the error and status registers of each port of the switching chip are polled at a preset detection cycle. Combining multi-flag comprehensive judgment and node authentication method, port reset recovery operation is performed on abnormally offline recoverable nodes to bring offline nodes back online.

2. The design method for enhancing the stability of RapidIO networks according to claim 1, characterized in that, The multiple flags mentioned in step 1 include a port ready flag, an output error stop flag, and an input error stop flag. When the port ready flag is valid but the output error stop flag or the input error stop flag is set, the port is determined to be in a recoverable abnormal state.

3. The design method for enhancing the stability of RapidIO networks according to claim 2, characterized in that, Step 1, which describes performing a reset and recovery operation on the recoverable faulty port, includes: Perform shutdown and enable operations sequentially on the abnormal port, clear the set state of the output error stop flag and the input error stop flag, and complete the port abnormal state reset.

4. The design method for enhancing the stability of RapidIO networks according to claim 1, characterized in that, Step 1, which involves completing the basic configuration, includes parsing the system configuration table, completing routing configuration, assigning device identifiers, configuring input / output spaces, initializing the device identifier table and port status table, completing the configuration of the switching chip routing table and basic registers, and performing preliminary network enumeration operations.

5. The design method for enhancing the operational stability of RapidIO networks according to claim 1, characterized in that, The multi-flag comprehensive judgment in step 2 includes: The port ready flag, output error stop flag, and input error stop flag are jointly checked; when the port ready flag is valid and the output error stop flag and input error stop flag are not set, the port's basic state is determined to be normal.

6. The design method for enhancing the operational stability of RapidIO networks according to claim 5, characterized in that, The node authentication method described in step 2 includes: After the basic status of the port is normal, the identifier register of the device connected to the port is read through the maintenance read operation. The read device identifier is compared with the expected identifier in the system configuration table. If they match, the corresponding node is confirmed to be online. If they do not match, the node is determined to be offline.

7. The design method for enhancing the stability of RapidIO networks according to claim 1, characterized in that, Before polling and detecting each port in step 2, the process also includes: first reading the error and status registers of the main control processor port; if the status of the main control processor port does not meet the preset normal conditions, then the main control processor port is first turned off and enabled.

8. The design method for enhancing the stability of RapidIO networks according to claim 1, characterized in that, The reset and recovery operation includes at least one of port shutdown and enable operations, port link retraining, or transmission rate degradation.

9. A design system for enhancing the operational stability of RapidIO networks, characterized in that, include: The initialization enumeration module is used during the initialization enumeration phase of the RapidIO network. Based on the RapidIO switching chip that has completed basic configuration, it reads the error and status registers of each port through maintenance read operations, makes a comprehensive judgment on multiple flag bits to identify abnormal ports, performs a reset recovery operation on recoverable abnormal ports, and then re-enumerates to obtain a complete node enumeration result with all ports in normal status. The operation detection and recovery module is used during the RapidIO network operation phase to poll the error and status registers of each port of the switching chip based on the complete node enumeration results at a preset detection cycle. Combining multi-flag comprehensive judgment and node authentication methods, it performs port reset recovery operation on recoverable nodes that have abnormally dropped online, so that the dropped nodes can come back online.

10. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the design method for enhancing the operational stability of a RapidIO network as described in any one of claims 1 to 8.

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