Queue scheduling method, device and system

Abstract

The application relates to the network communication technical field, discloses a queue scheduling method, device and system, the queue scheduling method of the application comprises the following steps: determining a queue with a to-be-sent message as an effective request queue from each to-be-scheduled queue; in the same clock cycle, selecting a queue with the highest priority from each effective request queue as a candidate queue according to the priority configured for each to-be-scheduled queue, and when the counters of each candidate queue are all negative, determining an arbitration winning queue by polling arbitration on each candidate queue, and respectively adding the weight values corresponding to each candidate queue to the counters of the candidate queue; then, dequeuing the message in the arbitration winning queue, and deducting the byte length of the dequeued message from the counter of the arbitration winning queue. The application can complete the priority selection, polling arbitration and counter weighting of the queue in a single clock cycle, and improves the efficiency of queue scheduling.

Description

Technical Field

[0001] This application relates to the field of network communication technology, specifically to queue scheduling methods, devices, and systems. Background Technology

[0002] In network communication, when network overload or congestion occurs, queue scheduling is needed to ensure the orderly transmission of packets in each queue. Related technologies typically configure priority and weight values ​​for each queue and set counters for each queue. During queue scheduling, based on the priority, weight values, and counters of each queue, the winning queue is determined from the queues with packets waiting to be sent, and packets from the winning queue are dequeued. However, with the continuous increase in network bandwidth, higher demands are placed on the timeliness of queue scheduling. The methods used in these technologies to complete a single queue scheduling operation are time-consuming and inefficient, making it difficult to meet the scheduling needs of high-bandwidth scenarios.

[0003] Therefore, there is an urgent need for a queue scheduling method to solve the problem of low queue scheduling efficiency in related technologies. Summary of the Invention

[0004] This application provides a queue scheduling method, apparatus, and system to solve the problem of low queue scheduling efficiency in related technologies.

[0005] Firstly, this application provides a queue scheduling method, which includes: In each queue to be scheduled, the queue containing the message to be sent is identified as the valid request queue; Within the same clock cycle, based on the priority configured for each queue to be scheduled, the queue with the highest priority among the valid request queues is determined as a candidate queue. If the counters of each candidate queue are all negative, the candidate queues are polled and arbitrated to determine the winning queue. The counters of each candidate queue are then added with their respective weight values. Dequeue the message that wins the arbitration and subtract the length of the dequeued message from the counter of the winning arbitration queue.

[0006] In one alternative implementation, the method further includes: If the counters of each candidate queue are not all negative, round-robin arbitration is performed on the candidate queues with non-negative counters to determine the winning queue.

[0007] In one alternative implementation, the method further includes: Read the most significant bit of the counter for each candidate queue and determine the most significant bit as the sign bit of the counter for the corresponding queue; When the sign bit of the counter in each candidate queue is 1, it is determined that the counters in each candidate queue are negative.

[0008] In one optional implementation, subtracting the length of the dequeued message in bytes from the counter of the arbitration winner queue includes: The length of the message bytes corresponding to multiple dequeue operations is accumulated, and the accumulated length of bytes is deducted from the counter of the arbitration winner queue.

[0009] In one alternative implementation, the method further includes: When there is a queue in which the counter is both added to with the corresponding weight value and subtracted from the accumulated byte length within the same clock cycle, the queue is determined as the target queue. The weight value corresponding to the target queue is combined with the accumulated byte length for calculation, and the result of the combined calculation is written to the counter of the target queue.

[0010] In one optional implementation, the queue with the highest priority among the valid request queues is determined as a candidate queue, including: Construct a priority matrix, where rows correspond to priority levels and columns correspond to queue nodes of each queue to be scheduled. Queue nodes with messages to be sent have their matrix elements in the corresponding priority row set to 1, and the rest are set to 0. The highest priority is determined based on the priority matrix, and the data in the row corresponding to the highest priority in the priority matrix is ​​used as a request bitmap to indicate each candidate queue.

[0011] In one alternative implementation, a priority matrix is ​​constructed, including: The request vector representing the request status of each queue is bitwise ANDed with each row of the configuration matrix representing the priority configuration of each queue to obtain the priority matrix.

[0012] In one alternative implementation, determining the highest priority based on a priority matrix includes: Perform a bitwise OR operation on each row of the priority matrix to obtain a compressed vector. Each bit of the compressed vector indicates whether there is a valid request queue for the corresponding priority. Perform bitwise operations on the compressed vector to determine the priority level corresponding to the most significant bit in the compressed vector, which is then set as the highest priority.

[0013] In one optional implementation, bitwise operations are performed on the compressed vector to determine the priority level corresponding to the most significant bit in the compressed vector, including: Perform a bit reversal on the compressed vector to obtain the inverted vector; Subtract 1 from the inverted vector and then invert it. Perform a bitwise AND operation with the inverted vector to obtain the one-hot code corresponding to the rightmost bit set to 1 in the inverted vector. The one-hot code corresponding to the rightmost bit set to 1 is bit-reversed to obtain the one-hot code corresponding to the most significant bit in the compressed vector.

[0014] In one alternative implementation, the method further includes: After subtracting 1 from the one-hot code corresponding to the most significant bit, the bits set to 1 in the result are accumulated, and the accumulated result is used as the binary number corresponding to the highest priority.

[0015] The queue scheduling method in this application identifies queues with pending messages as valid request queues, ensuring that subsequent scheduling only targets queues with actual sending needs. It also identifies the highest-priority queue among the valid request queues as candidate queues based on the priorities configured for each queue, guaranteeing that messages from high-priority queues are scheduled first. Furthermore, when the counters of all candidate queues are negative, a round-robin arbitration is performed to determine the winning queue, and the counters of each candidate queue are simultaneously incremented by their respective weight values. This ensures that the round-robin arbitration and counter weighting operations are not performed sequentially but are completed within the same clock cycle as the determination of the highest-priority candidate queue, thus shortening the time required to complete one queue scheduling operation and improving efficiency. Finally, by dequeuing messages from the winning queue and subtracting the byte length of the dequeued message from the queue's counter, the counter accurately reflects the number of bytes of messages dequeued from each queue, ensuring the accuracy of scheduling each queue according to its configured weight values.

[0016] Secondly, this application provides a queue scheduling device, which includes: The request determination unit is used to determine the queue with the message to be sent as the valid request queue in each queue to be scheduled. The scheduling unit, connected to the request determination unit, is used to determine the queue with the highest priority among the valid request queues as a candidate queue within the same clock cycle according to the priority configured for each queue to be scheduled. When the counters of each candidate queue are all negative, the scheduling unit performs round-robin arbitration on each candidate queue to determine the winning queue, and adds the corresponding weight value to the counters of each candidate queue. The dequeue processing unit, connected to the scheduling unit, is used to dequeue the messages that have won the arbitration and to decrement the counter of the winning arbitration queue by the length of the dequeue message in bytes.

[0017] In one optional implementation, the scheduling unit includes a priority scheduling circuit, a parallel arbitration circuit, and a parallel weighting circuit. The priority scheduling circuit is used to determine the highest priority queue among the valid request queues as the candidate queue based on the priority configured for each queue to be scheduled. A parallel arbitration circuit, connected to a priority scheduling circuit, is used to poll and arbitrate each candidate queue when the counters of each candidate queue are all negative, in order to determine the winning queue. The parallel weighting circuit is used to add the corresponding weight value to the counter of each candidate queue within the same clock cycle as the parallel arbitration circuit when the counters of each candidate queue are all negative. The output of the priority scheduling circuit is connected to the input of the parallel arbitration circuit via a combinational logic path.

[0018] In one alternative implementation, the parallel weighting circuit includes a register for latching the weighting result obtained by the parallel weighting circuit in the current clock cycle and writing the latched weighting result into the counter of the corresponding queue in the next clock cycle.

[0019] In one alternative implementation, the arbitration logic of the parallel arbitration circuit is a pure combinational logic circuit, and the critical path of the arbitration logic consists of polling arbitration operations.

[0020] Thirdly, this application provides a queue scheduling system, which includes a priority scheduling subsystem and a polling arbitration subsystem; The priority scheduling subsystem includes: The request determination module is used to determine the queue with the message to be sent as the valid request queue in each queue to be scheduled. The candidate queue determination module, connected to the request determination module, is used to determine the queue with the highest priority among the valid request queues as the candidate queue based on the priority configured for each queue to be scheduled. The request bitmap output module, connected to the candidate queue determination module, is used to generate and output a request bitmap indicating each candidate queue; The input of the polling arbitration subsystem is connected to the output of the request bitmap output module. The polling arbitration subsystem includes: The parallel arbitration module is used to poll and arbitrate each candidate queue when the counters of each candidate queue are all negative, in order to determine the winning queue. The parallel weighting module is used to add the corresponding weight value to the counters of each candidate queue within the same clock cycle as the parallel arbitration module when the counters of each candidate queue are negative. The dequeue processing module, connected to the parallel arbitration module, is used to dequeue the messages that win the arbitration queue and decrement the byte length of the dequeue message from the counter of the winning arbitration queue. The priority scheduling subsystem and the polling arbitration subsystem complete their processing within the same clock cycle.

[0021] In one optional implementation, the output of the priority scheduling subsystem and the input of the polling arbitration subsystem are connected through a combinational logic path, so that the priority scheduling subsystem and the polling arbitration subsystem form a continuous combinational logic path within the same clock cycle. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a schematic flowchart of a first method for queue scheduling according to an embodiment of this application; Figure 2 This is a second flowchart illustrating the queue scheduling method according to an embodiment of this application; Figure 3 This is a structural block diagram of a queue scheduling device according to an embodiment of this application; Figure 4 This is a structural block diagram of a queue scheduling system according to an embodiment of this application; Figure 5 This is a schematic diagram of the conventional DWRR scheduling process according to an embodiment of this application; Figure 6 This is a schematic diagram of the DWRR parallel optimization scheduling process in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained.

[0026] SP (Strict Priority) is a traffic scheduling strategy that uses queue priority as the sole arbiter. Each queue is assigned a unique priority number, and the scheduling circuit strictly arbitrates according to priority from high to low. Low-priority queues are only scheduled after the high-priority queues have been completely cleared. Its core advantage lies in ensuring the low-latency forwarding requirements of high-priority traffic (such as real-time control messages).

[0027] DWRR (Deficit Weighted Round Robin): A weighted round-robin scheduling strategy that uses the number of bytes in a message as the arbitration unit. Each queue independently maintains a signed deficit counter and a pre-configured weight value. A queue can participate in the current round of arbitration only when the counter is greater than or equal to zero. After a message is dequeued, the counter is reduced by the length of the dequeued message in bytes. When the counters of all valid request queues are negative, the respective weight values ​​are added to the counters of each queue, and a new round of arbitration is started. This is to prevent low-priority queues from being scheduled for a long time and to ensure that the ratio of the number of bytes dequeued by each queue in the long term remains consistent with the ratio of the weight values.

[0028] RR (Round Robin): An arbitration strategy that sequentially and cyclically allocates scheduling opportunities to each participating queue. The queue identifier (Q_id) records the current inspection position. Starting from the identifier of the winning queue in the previous round of arbitration (last_winner) plus 1, the valid request queues are traversed in turn to ensure that each queue gets the opportunity to be selected in turn.

[0029] Q_id (Queue Identifier): A variable that identifies the queue number currently being checked during the polling arbitration process. It is traversed sequentially starting from last_winner+1 and is used to track the current check position during the polling process.

[0030] last_winner (Identifier of the winning queue in the previous round of arbitration): The register value that stores the number of the winning queue in the previous round of arbitration. It serves as the starting reference position for the current round of RR polling, ensuring that each valid request queue takes turns to obtain arbitration opportunities in order.

[0031] Deficit counter: A signed counter maintained independently by each queue in the DWRR schedule. The most significant bit (MSB) is the sign bit: a sign bit of 1 indicates that the current value of the counter is negative (deficit state), and a sign bit of 0 indicates that the current value is non-negative. This is used to track the scheduling credit limit of each queue.

[0032] One-hot encoding: A binary encoding method where only one bit is 1 and all other bits are 0, used to precisely and unambiguously mark the position of a specific bit. For example, the 8-bit one-hot encoding 0100_0000 indicates that bit 6 is the target position.

[0033] Bitmap: A data structure that uses a set of consecutive bits to compactly represent the state of multiple objects. In this embodiment, it is used to represent the request status of each queue node under a specific priority level. A bit of 1 indicates that there is a request to be scheduled in the queue, and a bit of 0 indicates that there is no request.

[0034] priority_matrix: The core data structure of the SP matrix scheduling circuit, organized with rows corresponding to priority levels and columns corresponding to queue nodes; it integrates the priority information configured by the software with the real-time request status of each queue, and is automatically refreshed every clock cycle to accurately mark the set of queues with pending scheduling requests at each priority level.

[0035] matrix_compress (matrix compression vector): A one-dimensional bit vector obtained by performing a bitwise OR operation on each row of the priority matrix. Each bit corresponds to a priority level: a bit of 1 indicates that there is a valid request queue for the corresponding priority, while a bit of 0 indicates that there is no valid request queue. It simplifies the information of multiple rows of matrix into a compact bit vector for subsequent operations.

[0036] max_priority (highest priority): The priority level number corresponding to the highest bit set to 1 in the matrix compression vector. It represents the highest priority among all valid request queues at the current moment. Subsequent arbitration will only be carried out in queues with this priority.

[0037] right_first_cond (rightmost 1-bit one-hot code): The intermediate value in the process of locating the highest priority, representing the one-hot code corresponding to the rightmost bit set to 1 in the inverted vector obtained after reversing the bit order of the matrix compression vector. It is used to restore the position of the most significant bit (leftmost bit set to 1) in the matrix compression vector.

[0038] As an optional application scenario of this application embodiment, the queue scheduling method of this application can be applied to network communication devices. For example, the application scenario may include several terminal devices and network switching devices, and the terminal devices are connected to the network switching devices through the network.

[0039] Specifically, the terminal device can be a computer, server, or any other device that generates or receives network traffic. The network switching device can be a switch, router, or network processor, which integrates scheduling circuitry for traffic scheduling. The queue scheduling method provided in this application is executed by the scheduling circuitry within the network switching device to achieve scheduling arbitration of packets in multiple queues to be scheduled. The network can be a wired network or a wireless network, examples of which include, but are not limited to, local area networks (LANs), wide area networks (WANs), the Internet, and combinations thereof.

[0040] It should be noted that the above optional application scenarios are merely examples of one application scenario and do not limit the scope of protection of this application.

[0041] In related technologies, when scheduling queues, it is necessary to first add the corresponding weight value to the counter of each queue, and then perform polling arbitration on the queues based on the weighted counters. Each operation is executed in sequence. In view of the technical problem that a complete queue scheduling requires multiple clock cycles and the scheduling efficiency is low, this application provides a queue scheduling method to complete the priority selection, polling arbitration and counter weighting of queues within a single clock cycle, thereby improving the queue scheduling efficiency.

[0042] According to an embodiment of this application, a queue scheduling method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed by combinational logic circuits in the scheduling circuit. Each step can be completed by pure hardware logic within a single clock cycle. Furthermore, although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than that shown here.

[0043] This embodiment provides a queue scheduling method that can be used in the aforementioned network communication devices, such as switches, routers, or network processors. Specifically, the method is executed by a scheduling circuit integrated within the network communication device. Figure 1 This is a flowchart of a queue scheduling method according to an embodiment of this application, such as... Figure 1 As shown, the process includes the following steps: Step S101: In each queue to be scheduled, the queue with the message to be sent is determined as the valid request queue.

[0044] The queue to be scheduled refers to all queues managed by the scheduling circuit that are used to buffer messages to be sent. Each queue is independent of the others and maintains its own message buffer and independent signed counter. The counter is used to track the current available scheduling credit for each queue, and its value can be positive, zero or negative.

[0045] The valid request queue refers to a queue that has at least one message to be sent and needs to participate in arbitration at the current scheduling time.

[0046] "Determination" refers to the scheduling circuit's real-time monitoring of the buffer status of each queue to be scheduled within each clock cycle to determine whether each queue has a message to be sent and to classify and mark the queues: queues with messages to be sent are marked as valid request queues and included in the subsequent arbitration scope; queues without messages to be sent do not participate in the scheduling arbitration of this cycle.

[0047] In practice, some queues in the scheduling queues may contain one or more messages to be sent, while others may be empty. The queues containing messages to be sent are identified as valid request queues; that is, queues with actual sending needs are selected for this scheduling process. For example, this can be determined based on whether each queue contains messages. For instance, assuming the network device has 12 queues (queues 0 to 11), and queues 1, 3, 5, and 8 currently contain messages to be sent, while the remaining queues are empty, then queues 1, 3, 5, and 8 are identified as valid request queues. Through this step, subsequent scheduling only needs to be performed on the valid request queues, eliminating the need to process empty queues.

[0048] Step S102: Within the same clock cycle, based on the priority configured for each queue to be scheduled, the queue with the highest priority among each valid request queue is determined as a candidate queue. If the counters of each candidate queue are all negative, round-robin arbitration is performed on each candidate queue to determine the winning queue. The counters of each candidate queue are then added with their respective weight values.

[0049] A clock cycle refers to one cycle of the operating clock of hardware circuits such as chips in network devices. Hardware circuits perform various operations in units of clock cycles.

[0050] Priority is a parameter configured for each queue to be scheduled, used to characterize the priority of the queue being scheduled. For example, each queue to be scheduled can be configured with a priority from 0 to 7. The larger the value, the higher the priority. Different queues to be scheduled can be configured with the same priority or different priorities.

[0051] A counter is a parameter set for a queue to be scheduled, used to record the available scheduling quota of the queue. The counter can take a positive or negative value. Every time the queue sends a certain number of bytes of message, its counter is deducted accordingly. A negative counter value indicates that the current scheduling quota of the queue has been exhausted.

[0052] Weight values ​​are parameters configured for each queue to be scheduled. They represent the proportion of scheduling opportunities allocated among the queues. For example, the larger the weight value configured for a queue, the more message bytes that queue can send during long-term scheduling.

[0053] Polling arbitration refers to an arbitration method that selects a queue from multiple queues in turn according to a preset polling order. By polling, each queue has a chance to be selected.

[0054] In practice, the first step is to identify the highest-priority queue from all valid request queues based on the priority configured for each queue to be scheduled. This queue can be one or more candidate queues. For example, continuing the previous example, assuming queues 1 and 3 are configured with a priority of 7, queue 5 with a priority of 5, and queue 8 with a priority of 2, then queues 1 and 3 are the highest-priority queues among the valid request queues, and are therefore identified as candidate queues.

[0055] Furthermore, it is determined whether the counters of each candidate queue are all negative. If the counters of each candidate queue are all negative, the following two operations are performed: one operation is to perform round-robin arbitration on each candidate queue, selecting one queue as the arbitration winner according to the round-robin order; the other operation is to add their respective weight values ​​to the counters of each candidate queue to supplement the scheduling quota of each candidate queue. For example, suppose that the counter of queue 1 is currently -100 with a corresponding weight value of 300, and the counter of queue 3 is currently -60 with a corresponding weight value of 200, both of which are negative. Then, on the one hand, round-robin arbitration is performed on queues 1 and 3. Assuming that queue 1 is selected in this round-robin order, queue 1 is the arbitration winner; on the other hand, the counter of queue 1 is incremented by 300, and the counter of queue 3 is incremented by 200.

[0056] It should be noted that the above operations of determining the candidate queue, polling arbitration, and adding weight values ​​to the counter are all completed within the same clock cycle. In other words, the polling arbitration of each candidate queue does not need to wait for the counter to complete the weighting before execution. Both are completed in the same clock cycle, so the arbitration winner queue for this scheduling can be determined within one clock cycle.

[0057] Step S103: Dequeue the message that wins the arbitration and dequeue the counter of the winning arbitration queue by the length of the dequeue message in bytes.

[0058] Dequeueing refers to the operation whereby the scheduling circuit retrieves the head message of the queue that won the arbitration from the queue's buffer and forwards it to the output port. The byte length of a dequeueed message refers to the actual number of bytes occupied by the message; the byte length can vary between different messages.

[0059] Subtracting the byte length of the outgoing message means subtracting the byte length of the outgoing message from the current value of the counter of the winning queue, and writing the difference back to the counter of that queue to complete the credit deduction for this scheduling. This deduction operation faithfully records the actual bandwidth consumed in this outgoing process, enabling the counter to accurately reflect the credit usage of the queue.

[0060] In practice, the winning queue of the arbitration receives the opportunity to send a message during this scheduling period. It dequeues the message from its queue and sends it. Simultaneously, it subtracts the length of the dequeued message from its counter to deduct the scheduling quota consumed in this transmission. For example, continuing the previous example, queue 1 is the winning queue. The length of the message dequeued in queue 1 this time is 512 bytes. After adding the weight value of 300, the counter for queue 1 becomes 200. Subtracting 512 from the counter yields -312. Since the counter supports negative values, even if the counter is negative after deduction, the quota consumed by the dequeued message is still recorded completely and accurately. This queue can only receive scheduling opportunities again after its counter recovers, thus ensuring that the actual number of bytes sent by each queue matches its configured weight value.

[0061] In summary, the queue scheduling method provided in this application determines queues with pending messages as valid request queues in each queue to be scheduled, ensuring that scheduling is only performed on queues with actual sending needs; it determines the highest priority queue among the valid request queues as candidate queues based on configured priorities, ensuring that messages in high-priority queues are scheduled first; it performs polling arbitration on each candidate queue when all candidate queue counters are negative, and adds their respective weight values ​​to the counters of each candidate queue, so that polling arbitration and counter weighting are completed in the same clock cycle, eliminating the need to perform weighting before arbitration, thus determining the winning queue in a single clock cycle, shortening the time required to complete one queue scheduling operation, and improving the efficiency of queue scheduling; by dequeuing messages from the winning queue and subtracting the length of the dequeued message from its counter, the counter can accurately record the quota consumption of each queue, ensuring the accuracy of scheduling each queue according to the configured weight values.

[0062] This embodiment provides a queue scheduling method that can be used in the aforementioned network communication devices, such as switches, routers, or network processors. Specifically, the method is executed by a scheduling circuit integrated within the network communication device. Figure 2 This is a flowchart of a queue scheduling method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps: Step S201: In each queue to be scheduled, the queue containing the message to be sent is identified as the valid request queue. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0063] Step S202: Within the same clock cycle, based on the priority configured for each queue to be scheduled, the queue with the highest priority among each valid request queue is determined as a candidate queue. If the counters of each candidate queue are all negative, round-robin arbitration is performed on each candidate queue to determine the winning queue. The counters of each candidate queue are then added with their respective weight values.

[0064] Considering that the number and priority configuration of valid request queues may change with business needs, in order to quickly determine candidate queues with less computation, some implementations determine the queue with the highest priority among the valid request queues as candidate queues, which may include: Construct a priority matrix, where rows correspond to priority levels and columns correspond to queue nodes of each queue to be scheduled. Queue nodes with messages to be sent have their matrix elements in the corresponding priority row set to 1, and the rest set to 0. Determine the highest priority based on the priority matrix, and use the data in the row corresponding to the highest priority in the priority matrix as a request bitmap to indicate each candidate queue.

[0065] In this context, a queue node refers to a column position in the matrix that corresponds one-to-one with each queue to be scheduled. The request bitmap refers to data using a set of binary bits to indicate which queues are candidate queues. Each bit in the bitmap corresponds to a queue, and setting it to 1 indicates that the corresponding queue is a candidate queue. For example, in a scenario with 12 queues to be scheduled and 8 priority levels, the priority matrix is ​​an 8-row, 12-column matrix. Row 0 corresponds to priority 0, row 7 corresponds to priority 7, and columns 0 to 11 correspond to queues 0 to 11, respectively. Continuing the example above, if queues 1 and 3 are configured with priority 7 and have requests, then the elements in columns 1 and 3 of row 7 are set to 1. If queue 5 is configured with priority 5 and has requests, then the element in column 5 of row 5 is set to 1. If queue 8 is configured with priority 2 and has requests, then the element in column 8 of row 2 is set to 1. All other elements in the matrix are 0.

[0066] In this way, the priority matrix marks which queues are requesting scheduling at each priority level. After determining the highest priority, the data in the row corresponding to the highest priority is directly retrieved. For example, the data in row 7, 0000_0000_1010, is the request bitmap indicating that queues 1 and 3 are candidate queues. By organizing the queue request status and priority configuration into a matrix form, the determination of candidate queues is transformed into row operations on the matrix, which is easy to implement with a simple circuit structure. Furthermore, the request bitmap can be directly used as input for subsequent polling arbitration without additional conversion processing.

[0067] In some implementations, the priority matrix can be constructed by performing a bitwise AND operation between the request vector representing the request status of each queue and each row of the configuration matrix representing the priority configuration of each queue. The configuration matrix is ​​a matrix pre-obtained based on the priorities configured for each queue. Each row represents a priority level, and each column corresponds to a queue. If a queue is configured with a certain priority, the corresponding row and column in the configuration matrix are set to 1.

[0068] For example, if queues 0, 1, and 3 are all configured with priority 7, then the elements in columns 0, 1, and 3 of row 7 of the configuration matrix are all 1. Performing a bitwise AND operation between the request vector 0001_0010_1010 and this row, since queue 0 has no requests, results in 0000_0000_1010, which is row 7 of the priority matrix. Because queue priorities are typically statically configured, the configuration matrix can be pre-generated and remain unchanged. Each clock cycle only requires performing a bitwise AND operation between the refreshed request vector and each row of the configuration matrix to obtain a real-time updated priority matrix. The computational logic is simple, and the operations on each row are independent and can be performed simultaneously, which helps to shorten computation time.

[0069] Regarding the method for determining the highest priority, in some implementations, the highest priority is determined based on a priority matrix, which may include: Perform a bitwise OR operation on each row of the priority matrix to obtain a compressed vector. Each bit in the compressed vector indicates whether a valid request queue exists for the corresponding priority. Perform bitwise operations on the compressed vector to determine the priority level corresponding to the most significant bit in the compressed vector, which is taken as the highest priority. The bitwise OR operation means performing an OR operation on all bits in a row; the result is 1 if there is at least one 1 in the row. The compressed vector is the vector obtained by compressing each row of the matrix into one bit. For example, for an 8-row, 12-column priority matrix, the compressed vector is 8 bits, denoted as compressed vector [7:0]. The most significant bit is the highest-positioned 1 bit in the compressed vector. Continuing the example above, if rows 7, 5, and 2 have elements set to 1, and the remaining rows are all 0, then the compressed vector is 1010_0100, where bits 7, 5, and 2 are 1, indicating that valid request queues exist for priorities 7, 5, and 2.

[0070] Determine the priority level corresponding to the most significant bit in the compressed vector, that is, determine the highest priority among the valid request queues. In this example, the most significant bit is bit 7, and the highest priority is priority 7. By first compressing the matrix into a vector and then locating the most significant bit in the vector, the search on the two-dimensional matrix is ​​simplified to bitwise operations on the one-dimensional vector, avoiding the need to compare the priorities of each queue one by one, which helps to reduce the amount of computation.

[0071] Furthermore, if a bit-by-bit traversal is used to find the most significant bit in the compressed vector, it is necessary to judge each bit sequentially, and the time consumption increases with the number of bits. Therefore, in some implementations, bitwise operations are performed on the compressed vector to determine the priority level corresponding to the most significant bit in the compressed vector, which may include: The compressed vector is bit-reversed to obtain an inverted vector. The inverted vector is then subtracted by 1, inverted, and bitwise ANDed with the inverted vector to obtain the one-hot code corresponding to the rightmost 1 bit in the inverted vector. The one-hot code corresponding to the rightmost 1 bit is bit-reversed to obtain the one-hot code corresponding to the most significant bit in the compressed vector. Bit reversal refers to reversing the order of the high and low bits of a group of binary bits, for example, reversing 1010_0100 to 0010_0101. One-hot encoding refers to an encoding where only one bit is 1 and the rest are 0.

[0072] In practical implementation, let A be the inverted vector obtained after bit reversing the compressed vector. The most significant bit in the compressed vector is converted to the rightmost bit of A. Taking advantage of the property that the subtraction operation will generate a borrow starting from the rightmost 1, the bitwise AND operation of A and the result of subtracting 1 and inverting A is calculated, i.e., A&(~(A-1)). In the result, only the rightmost bit of A is retained as 1. Continuing the example above, after reversing the compressed vector 1010_0100, A becomes 0010_0101. Subtracting 1 from A gives 0010_0100, which is inverted to 1101_1011. The bitwise AND operation with A gives 0000_0001, which is the one-hot code corresponding to the rightmost bit of A. Then, the bitwise AND operation is performed on it to obtain 1000_0000, which is the one-hot code corresponding to the most significant bit in the compressed vector, indicating a priority of 7. The above process only includes a few basic bit operations such as bit reversal, subtraction, inversion, and bitwise AND. There are no loops or bit-by-bit traversals, and each priority level does not need to be compared one by one. It can quickly locate the highest priority with fewer operation levels, which is beneficial to leave enough time for subsequent arbitration within one clock cycle.

[0073] Based on this, considering that some processing steps may require the highest priority to be expressed numerically, in some implementations, the method may further include: After subtracting 1 from the one-hot code corresponding to the most significant bit, all the 1 bits in the result are summed, and the sum is used as the binary number corresponding to the highest priority. For example, if the one-hot code corresponding to the most significant bit is 1000_0000, subtracting 1 gives 0111_1111, which has 7 1 bits. The sum is 7, meaning the binary number corresponding to the highest priority is 7. The conversion from one-hot code to binary number is completed by subtracting 1 and adding bits, relying only on basic bit operations. This allows the highest priority to be output in a compact binary form for use by other processing stages that require this number.

[0074] After identifying the candidate queues, it is necessary to determine whether the counters of each candidate queue are all negative. If this is done by comparing the counter values ​​to zero, it requires operations on each data bit of the counter. Therefore, in some implementations, the method may further include: reading the most significant bit of the counter for each candidate queue and determining it as the sign bit of the corresponding queue's counter; when the sign bits of the counters for each candidate queue are all 1, it is determined that the counters of each candidate queue are all negative. The counters can be stored in signed number form, with the most significant bit being the sign bit. A sign bit of 1 indicates a negative counter value, and a sign bit of 0 indicates a non-negative counter value.

[0075] For example, if the counter uses a 16-bit signed number, and the current value of the counter in queue 1 is -100, while the current value of the counter in queue 3 is -60, with both having a highest bit of 1, reading the highest bit of the counters in queues 1 and 3 will determine that both counters have negative values. Compared to comparing multiple bits of the counter, only reading one sign bit is needed to determine whether the value is positive or negative, simplifying the judgment logic and speeding up the judgment process.

[0076] When all candidate queue counters are negative, the following two operations are performed within the same clock cycle: First, a round-robin arbitration is performed on the candidate queues, selecting one queue as the winning queue according to the round-robin order. Second, the counters of each candidate queue are incremented by their respective weight values ​​to supplement their scheduling capacity. For example, if queue 1's counter is -100 with a weight of 300, and queue 3's counter is -60 with a weight of 200, both counters are negative. First, a round-robin arbitration is performed on queues 1 and 3. Assuming queue 1 is selected in the round-robin order, it becomes the winning queue. Second, the counters of queue 1 and 3 are incremented by 300, and the counters of queue 3 are incremented by 200.

[0077] Understandably, polling arbitration does not need to wait for the counter to complete weighting before execution; both are completed within the same clock cycle. Furthermore, since the weighting of the counter only supplements the scheduling quota of each candidate queue and does not change the ratio between the weight values ​​of each queue, from a longer time perspective, the total amount added to the counter of each queue is proportional to its respective weight value, and the total number of bytes of the outgoing messages of each queue also matches the weight value accordingly. Therefore, the scheduling ratio will not be affected.

[0078] The above content addresses the scenario where all candidate queue counters are negative. However, in actual scheduling, the counters of each candidate queue may not all be negative. In some implementations, this method may further include: when the counters of each candidate queue are not all negative, performing round-robin arbitration on the candidate queues with non-negative counters to determine the winning queue.

[0079] For example, suppose the current value of the counter in queue 1 is 200 and the current value of the counter in queue 3 is -60. Since not all the counters of the candidate queues are negative, round-robin arbitration is performed on the candidate queue with a non-negative counter, i.e., queue 1. For another example, if there are multiple candidate queues with non-negative counters, one of these queues is selected as the winning queue for arbitration according to the round-robin order.

[0080] In other words, candidate queues with non-negative counter values ​​indicate that their scheduling quota has not yet been exhausted, and polling and arbitration can be performed directly on these queues without weighting the counters. By handling the case where the counters are not all negative, the winning queue can be determined in both cases, making the method adaptable to various counter value states during scheduling and improving its applicability.

[0081] Step S203: Dequeue the message from the arbitration winner queue and decrement the counter of the arbitration winner queue by the length of the dequeued message in bytes. For details, please refer to [link to relevant documentation]. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0082] Step S204: Accumulate the length of the message bytes corresponding to multiple dequeue operations, and deduct the accumulated length of bytes from the counter of the arbitration winner queue.

[0083] In some implementations, to reduce the frequency of write operations to the counter and optimize the dynamic power consumption of the circuit, the length of the message bytes corresponding to multiple dequeue operations is accumulated, and the accumulated byte length is deducted from the counter of the arbitration winner queue. The final effect is completely equivalent to deducting each byte individually.

[0084] Multiple dequeue operations refer to multiple message dequeue events occurring within a number of consecutive or intermittent clock cycles in the arbitration winner queue. Accumulation refers to adding the byte lengths of each dequeued message to obtain a cumulative total byte length. This cumulative byte length is then used to perform a one-time subtraction operation on a counter, thus achieving an equivalent credit deduction with fewer write operations. For example, if the arbitration winner queue dequeues messages with lengths of 64 bytes, 128 bytes, and 256 bytes in three consecutive dequeues, the scheduling circuit can first accumulate the three dequeue byte lengths to obtain 448 bytes, and then subtract 448 bytes from the arbitration winner queue's counter. This is completely consistent with the final result of successively deducting 64 bytes, 128 bytes, and 256 bytes, but reduces the number of write operations to the counter, helping to reduce the dynamic power consumption of the scheduling circuit.

[0085] When using the above-described accumulation and deduction method, the following situation may occur: A queue's counter needs to be both added to with the corresponding weight value and deducted from its accumulated byte length within the same clock cycle. If these two modifications are written to the counter independently, write conflicts may occur. To address this situation, in some implementations, the method may further include: When there exists a queue in which the counter is both added to with the corresponding weight value and subtracted from the accumulated byte length within the same clock cycle, the queue is determined as the target queue; the weight value corresponding to the target queue is combined with the accumulated byte length, and the result of the combined calculation is written into the counter of the target queue.

[0086] The merging calculation refers to combining two modifications to the counter into a single operation. For example, the difference between the weight value and the accumulated byte length can be calculated, and then the result of the difference can be added to the current value of the counter to obtain the result written to the counter. For instance, if the current value of the counter for queue 1 is -100, and within the same clock cycle, the counter for queue 1 is both increased by the weight value of 300 and decreased by the accumulated byte length of 896, then queue 1 is identified as the target queue. The merging calculation yields -100 + 300 - 896 = -696, which is then written to the counter for queue 1. By merging the two modifications into a single calculation and a single write, both modifications are accurately reflected in the counter, avoiding write conflicts to the same counter within the same clock cycle and maintaining the accuracy of the counter value.

[0087] In summary, the queue scheduling method provided in this application identifies queues with pending messages as valid request queues in each queue to be scheduled, and determines the highest priority queue among the valid request queues as candidate queues based on the configured priority. This ensures that each scheduling operation is performed within the queues that meet the priority requirements, guaranteeing that high-priority messages are scheduled first. Furthermore, by polling and arbitrating each candidate queue when the counters of each candidate queue are negative, and simultaneously adding their respective weight values ​​to the counters of each candidate queue, the counter weighting and polling / arbitration operations are completed within the same clock cycle, eliminating the need for weighting and arbitration. This shortens the time required to complete one scheduling operation and improves the efficiency of queue scheduling. Moreover, since weighting only supplements the scheduling quota without changing the ratio between the weight values ​​of each queue, and the counter is deducted from the dequeued message's byte length after the message is dequeued, the scheduling ratio of each queue remains consistent with the configured weight values. Therefore, the improved scheduling efficiency does not affect the scheduling accuracy.

[0088] Furthermore, determining the sign of the counter by using the sign bit simplifies the logic for triggering conditions. The highest priority is determined using a priority matrix, a compressed vector, and bitwise operations based on bit reversal and bitwise AND, avoiding loop traversal and one-by-one comparisons. This allows for rapid selection of candidate queues with fewer computational layers, and provides input directly to the round-robin arbitration in the form of a request bitmap. Compatibility handling for cases where the counter is not entirely negative ensures the method covers various counter states in scheduling. Accumulated addition and subtraction of dequeue byte lengths, along with weighted and subtractive calculations, reduces the number of counter write operations and avoids write conflicts. These interconnected technical features enable efficient and accurate implementation of the entire scheduling process, from determining valid request queues and candidate queues to completing arbitration and counter updates, meeting the timeliness requirements of queue scheduling in high-bandwidth scenarios.

[0089] This embodiment provides a queue scheduling device for implementing the above embodiments. The contents that have already been described will not be repeated. The term "unit" used below can refer to a combination of hardware that performs a predetermined function. Figure 3 This is a schematic diagram of the structure of a queue scheduling device according to an embodiment of this application, as shown below. Figure 3 As shown, the device includes a request determination unit 301, a scheduling unit 302, and a dequeue processing unit 303.

[0090] The request determination unit 301 is used to determine the queues with pending messages as valid request queues among the queues to be scheduled. In specific implementation, the request determination unit 301 can generate a request signal representing the request status of each queue based on whether each queue has a buffered message. For example, it can output the request status of each queue in the form of a request vector, with the corresponding bit set to 1 when there is a pending message in the queue, thereby determining the queue with a pending message as a valid request queue.

[0091] The scheduling unit 302, connected to the request determination unit 301, is used to, within the same clock cycle, determine the highest-priority queue among the valid request queues as candidate queues based on the priorities configured for each queue to be scheduled. When the counters of all candidate queues are negative, it performs round-robin arbitration on each candidate queue to determine the winning queue, and adds its corresponding weight value to the counters of each candidate queue. The scheduling unit 302 is connected to the request determination unit 301 in that its input receives signals output by the request determination unit 301, such as the aforementioned request vector, to determine which queues are valid request queues.

[0092] The dequeue processing unit 303, connected to the scheduling unit 302, is used to dequeue the messages from the arbitration winner queue and decrement the byte length of the dequeue message from the counter of the arbitration winner queue. In specific implementation, the dequeue processing unit 303 receives the arbitration result output by the scheduling unit 302, controls the dequeueing and transmission of messages in the arbitration winner queue, and decrements the corresponding counter.

[0093] Regarding the internal structure of the scheduling unit 302, in some embodiments, the scheduling unit 302 may include a priority scheduling circuit, a parallel arbitration circuit, and a parallel weighting circuit.

[0094] The system includes a priority scheduling circuit, which determines the highest-priority queue among the valid request queues as a candidate queue based on the priority configured for each queue to be scheduled; a parallel arbitration circuit, connected to the priority scheduling circuit, which polls and arbitrates each candidate queue when the counters of each candidate queue are negative, to determine the winning queue; a parallel weighting circuit, which, in the same clock cycle as the parallel arbitration circuit, adds the corresponding weight value to the counters of each candidate queue when the counters of each candidate queue are negative; and the output of the priority scheduling circuit is connected to the input of the parallel arbitration circuit through a combinational logic path.

[0095] In this context, a combinational logic path refers to a signal transmission path consisting solely of combinational logic, without passing through sequential devices such as registers. Signal transmission through this path does not require crossing a clock cycle. In practical implementation, after the priority scheduling circuit determines the candidate queues, it sends signals indicating each candidate queue, for example, in the form of a request bitmap, directly to the parallel arbitration circuit via the combinational logic path. The parallel arbitration circuit can then conduct polling arbitration within the same clock cycle of receiving this signal. Simultaneously, the parallel weighting circuit weights the counters of each candidate queue. The weighting operation and polling arbitration are independent and performed separately in their respective circuits. By separating arbitration and weighting into two parallel circuits and connecting the priority scheduling circuit and the parallel arbitration circuit with a combinational logic path, the process from determining the candidate queues to obtaining the winning queue is completed within one clock cycle, which improves the scheduling efficiency of the device.

[0096] Furthermore, considering that the weighting result of the parallel weighting circuit needs to be reflected in the counter at an appropriate time, in some embodiments, the parallel weighting circuit may include a register. The register is used to latch the weighting result obtained by the parallel weighting circuit in the current clock cycle and write the latched weighting result into the counter of the corresponding queue in the next clock cycle. Latching refers to temporarily storing data in a register to keep the data stable after the clock edge. For example, the parallel weighting circuit calculates the result of adding the weight value of 300 to the counter of queue 1 in the current clock cycle, latches the result in a register, and writes it into the counter of queue 1 in the next clock cycle. Through register latching, the weighting operation occurs in the current clock cycle, while the update of the counter value is reflected in the next clock cycle. The weighting operation does not occupy the arbitration path time in the current clock cycle, and the timing of the counter update is clearly controlled, which is beneficial for the stable operation of the device at higher operating frequencies.

[0097] In some implementations of parallel arbitration circuits, the arbitration logic can be a pure combinational logic circuit, with the critical path consisting of polling arbitration operations. A pure combinational logic circuit is one whose output is determined solely by the current input and does not contain sequential devices such as registers. The critical path is the path with the longest signal transmission time, and the operating frequency achievable by the circuit is constrained by the time consumed by the critical path. Since the weighting operation is handled by a parallel weighting circuit, the arbitration logic of the parallel arbitration circuit no longer includes weighting operations and subsequent numerical comparison operations. Its critical path consists only of the polling arbitration operation itself, resulting in fewer logic levels along the path. The signal can be transmitted from the input to the arbitration result within one clock cycle, which is beneficial for the device to adapt to higher clock frequencies.

[0098] In summary, the queue scheduling device provided in this application embodiment filters out valid request queues through a request determination unit, completes candidate queue determination, polling arbitration, and counter weighting within the same clock cycle through a scheduling unit, and completes message dequeueing and counter deduction through a dequeue processing unit. Furthermore, the scheduling unit achieves parallel execution of arbitration and weighting through the division of priority scheduling circuit, parallel arbitration circuit, and parallel weighting circuit, and achieves non-clock cycle connection between circuits through combinational logic paths. Thus, queue scheduling within a single clock cycle is realized in the form of hardware circuits, improving the efficiency of queue scheduling.

[0099] This embodiment provides a queue scheduling system. Figure 4 This is a schematic diagram of the queue scheduling system according to an embodiment of this application, as shown below. Figure 4 As shown, the system includes a priority scheduling subsystem 401 and a polling arbitration subsystem 402. The processing involved in queue scheduling is completed by the two subsystems: the priority scheduling subsystem 401 is responsible for determining the candidate queues to participate in arbitration from each queue to be scheduled, and the polling arbitration subsystem 402 is responsible for determining the winning queue from the candidate queues and completing the message dequeueing and counter update.

[0100] Specifically, the priority scheduling subsystem 401 includes a request determination module, a candidate queue determination module, and a request bitmap output module.

[0101] The request determination module identifies queues with pending messages as valid request queues from among the queues to be scheduled. The candidate queue determination module, connected to the request determination module, identifies the highest-priority queue among the valid request queues as a candidate queue based on the priorities configured for each queue to be scheduled. The request bitmap output module, connected to the candidate queue determination module, generates and outputs a request bitmap indicating each candidate queue. The request bitmap uses a set of binary bits to indicate which queues are candidate queues. Each bit in the bitmap corresponds to a queue; setting it to 1 indicates that the corresponding queue is a candidate queue. For example, if queues 1 and 3 are candidate queues, the bits corresponding to queues 1 and 3 in the request bitmap are 1, and the remaining bits are 0. Through the request bitmap output module, the processing results of the priority scheduling subsystem 401 are output externally in a bitmap format, which is convenient for direct use by the hardware circuitry.

[0102] The input of the polling arbitration subsystem 402 is connected to the output of the request bitmap output module. That is, the request bitmap output by the request bitmap output module is directly used as the input of the polling arbitration subsystem 402, which then determines the candidate queues participating in the arbitration. The polling arbitration subsystem 402 includes a parallel arbitration module, a parallel weighting module, and a dequeue processing module.

[0103] The parallel arbitration module polls and arbitrates each candidate queue when their counters are all negative to determine the winning queue. The parallel weighting module, also with a negative counter, adds its respective weight value to the counters of each candidate queue within the same clock cycle as the parallel arbitration module. The dequeue processing module, connected to the parallel arbitration module, dequeues the message from the winning queue and decrements the counter of that queue by the length of the dequeue message. In practice, the parallel arbitration and parallel weighting modules operate in parallel; arbitration does not wait for weighting, and weighting does not consume arbitration processing time. The dequeue processing module then dequeues the message and decrements the counter based on the arbitration result output by the parallel arbitration module.

[0104] Furthermore, in this system, the processing of the priority scheduling subsystem 401 and the processing of the polling arbitration subsystem 402 are completed within the same clock cycle. That is to say, from the request determination module screening the valid request queue, to the candidate queue determination module determining the candidate queue, the request bitmap output module outputting the request bitmap, to the parallel arbitration module determining the arbitration winner queue, and the parallel weighting module completing the counter weighting, the above processes are completed sequentially or in parallel within one clock cycle. The arbitration winner queue can be obtained within a single clock cycle, and the message can be dequeued directly.

[0105] To support the completion of processing by the two subsystems within the same clock cycle, in some implementations, the output of the priority scheduling subsystem 401 and the input of the polling arbitration subsystem 402 can be connected via a combinational logic path, enabling the priority scheduling subsystem 401 and the polling arbitration subsystem 402 to form a continuous combinational logic path within the same clock cycle. Here, a combinational logic path refers to a signal transmission path composed solely of combinational logic, without passing through sequential devices such as registers; a continuous combinational logic path means that signal transmission within the two subsystems and at their junction is not separated by sequential devices, and the signal flows continuously from the input of the priority scheduling subsystem 401 to the output arbitration result of the polling arbitration subsystem 402 within one clock cycle.

[0106] In practice, the request bitmap output by the request bitmap output module is sent directly to the parallel arbitration module for arbitration without being buffered by registers or spanning clock cycles. This cascades the two subsystems into a single, complete processing link. Compared to the method where two subsystems are connected via registers and operate in different clock cycles, the continuous combinational logic path eliminates waiting between subsystems, allowing the complete scheduling process to be completed within a single clock cycle, thus improving system scheduling efficiency.

[0107] In summary, the queue scheduling system provided in this application uses a priority scheduling subsystem to filter valid request queues, determine candidate queues, and output request bitmaps. A polling arbitration subsystem performs polling arbitration and counter weighting in parallel when all counters are negative, and also performs message dequeueing and counter decrement. The processing of both subsystems is completed within the same clock cycle, and they are connected via combinational logic paths. This cascading subsystem approach achieves complete queue scheduling within a single clock cycle, improving the efficiency of queue scheduling and the system's adaptability to high-bandwidth scenarios.

[0108] To better illustrate the queue scheduling method, apparatus, and system of this application, a preferred embodiment will be provided below. This embodiment is intended to describe the implementation process of this application in detail, but is not intended to limit the scope of protection of this application.

[0109] The following uses a preferred example of a hybrid SP+DWRR scheduling scenario with 12 queues to be scheduled (queue numbers 0 to 11) and 8 priority levels (priority numbers 0 to 7, with level 7 being the highest priority) to specifically illustrate this embodiment. This configuration is chosen as the preferred example because 12 queues and 8 priorities represent a typical scheduling scale in current 400G / 800G high-bandwidth network chips, fully demonstrating the structural characteristics of the SP matrix scheduling circuit and the DWRR parallel optimization circuit, as well as the complete scheduling process of their cascaded cooperation. However, this embodiment is not limited to the above number of queues and priority levels; relevant parameters can be flexibly configured according to actual chip design requirements. Furthermore, this embodiment covers both the implementation of the queue scheduling method and the implementation of the corresponding device and system. The following section will comprehensively explain the two core improvements and their cascaded implementation.

[0110] In related technologies, as the demand for AI computing power drives network chip bandwidth to 400G and even 800G, chip clock speeds have reached 1000MHz to 1250MHz and above. At such high clock speeds, physical processes require that the number of combinational logic levels per clock cycle not exceed 30 to 36. However, traditional SP+DWRR hybrid scheduling circuits face significant timing bottlenecks: in DWRR scheduling, the multi-bit adder (used for counter weighting), comparator (used to determine whether the counter is non-negative), and RR polling circuit are connected in series, resulting in more than 50 combinational logic levels, far exceeding the aforementioned physical constraints; the queue priority in SP scheduling is fixed by hardware according to the queue number, and software cannot flexibly configure it; the SP phase and DWRR phase must be executed in a time-sharing manner, and hybrid scheduling requires two clock cycles, resulting in low scheduling efficiency.

[0111] The basic mechanism of DWRR scheduling is as follows: Each queue maintains an independent signed deficit counter. The highest bit of the counter is the sign bit. A sign bit of 1 indicates that the current value is negative, and a sign bit of 0 indicates that the current value is non-negative. Scheduling is based on the number of bytes in the message as the arbitration unit. Each queue is independently configured with a weight value. The weight value remains static after configuration, and the weight values ​​of different queues can be different.

[0112] Figure 5 This is a flowchart illustrating the traditional DWRR scheduling process. For example... Figure 5 As shown, traditional DWRR requires the following steps to be executed sequentially: First, it is determined whether the sign bit of the counters of all valid request queues (i.e., queues with messages to be sent) is 1 (i.e., whether all are negative); if so, the corresponding weight value is added to the counters of all queues; then, starting from the last_winner (identifier of the winning queue in the previous round of arbitration) incremented by 1 using Q_id (QueueIdentifier), each valid request queue is checked sequentially to determine whether its counter sign bit is 0 (i.e., whether the counter is non-negative); for valid queues with non-negative counters and requests, RR (Round Robin) arbitration is performed, and after selecting the winning queue, message dequeueing and counter deduction are completed. In the above process, the adder, comparator, and RR polling circuit are connected in series, resulting in more than 50 levels of combinational logic, which cannot be completed within a single clock cycle at a frequency of 1000MHz or higher.

[0113] To address the aforementioned bottlenecks, this embodiment proposes a parallel optimization method for DWRR. The core idea is to identify the special condition that "the counters of all valid request queues are negative." Under this condition, RR polling arbitration does not need to wait for the result of counter weighting, and the data dependency between the two can be eliminated. This transforms the weighting step and the polling arbitration step, which originally had to be executed serially, into parallel execution within the same clock cycle.

[0114] Figure 6 This is a flowchart illustrating the DWRR parallel optimization scheduling in this embodiment. The flowchart includes two parallel paths: the left side shows the arbitration path (operation A), and the right side shows the counter update path (operation B). Figure 6 As shown, the detailed steps of the DWRR parallel optimization process are as follows: Step 1: Quick sign bit detection.

[0115] The scheduling circuit monitors the counter status of all valid request queues in real time. Unlike traditional schemes that compare the magnitude of multiple bits of the counter, this embodiment directly reads the highest bit (i.e., the sign bit) of each valid request queue counter. By performing logical judgment on the sign bit of each valid request queue, it confirms whether all bits are 1 (i.e., whether all bits are negative). Since this judgment only requires reading a single bit and performing multi-input logic operations, without the need for multi-bit addition or comparison, the entire detection process introduces only about 1 to 2 levels of combinational logic, which has almost no additional impact on the overall critical timing path.

[0116] Step two: Execute two operation paths in parallel within the same clock cycle.

[0117] When the sign bit of the counter in each valid request queue is 1 (all are negative values), such as Figure 6 As shown in the flowcharts on both sides, the scheduling circuit initiates the following two operation paths in parallel within the same clock cycle: Operation A (arbitration path, Figure 6 (Left side): Without waiting for the weighted result of the counter, arbitration is directly performed on all currently valid request queues using a round-robin (RR) strategy. Starting from the queue corresponding to last_winner+1 with Q_id, the winning queue for this round of arbitration is quickly selected. Since the counters of all valid request queues are negative at this time, the arbitration process does not depend on the output of the weighted operation and can be executed independently.

[0118] Operation B (counter update path, Figure 6 (Right side): This operation runs completely parallel to the arbitration path. The scheduling circuit simultaneously adds the corresponding weight value to the counters of all queues. The weighting operations for each queue are independent and do not affect each other. Furthermore, this path does not consume critical timing resources of the arbitration path. It should be noted that the weighting result of operation B will only be written and take effect in the next clock cycle; the arbitration decision in the current cycle is unaffected.

[0119] In rare cases, the weighting operation of operation B and the counter decrement operation corresponding to the dequeue of the arbitrated winner queue message after operation A may simultaneously act on the counters of the same queue within the same clock cycle. For such situations, the scheduling circuit employs a combined calculation: the algebraic sum of the weighting and decrementing amounts is written to the counter all at once. This is completely equivalent in the final result to the step-by-step operation of performing weighting first and then decrementing, while simultaneously eliminating concurrent write conflicts to the same counter and ensuring the consistency of the counter data. Furthermore, to optimize the dynamic power consumption of the circuit, in some implementations, the message byte lengths corresponding to multiple dequeue operations can be accumulated, and the total accumulated byte length can be decremented uniformly from the counter of the arbitrated winner queue. This is completely equivalent in the long-term effect to decrementing individually one by one.

[0120] Step 3: Message dequeue and counter deduction.

[0121] After Operation A determines the arbitration winner queue, the scheduling circuit retrieves the head message of the queue from the buffer and forwards it to the output port. At the same time, it subtracts the byte length of the dequeue message from the counter of the arbitration winner queue to complete the credit deduction. The deduction rule is completely consistent with the traditional DWRR.

[0122] Step 4: Compatibility handling for non-full negative scenarios.

[0123] When there is a queue in the valid request queue with a counter greater than or equal to zero (not all negative), the scheduling circuit does not trigger the above parallel process, but instead processes it according to the standard RR polling process: starting from last_winner+1, it iterates sequentially using Q_id, and only performs polling arbitration on valid request queues with a counter sign bit of 0 (i.e., the counter is non-negative) and pending scheduling requests. The winning queue is selected, and the message is dequeued and the counter is decremented. The standard RR polling process itself meets the timing requirements at a 1000MHz main frequency.

[0124] The DWRR parallel optimization scheme only adjusts the timing of weight value loading and does not change the proportional relationship between the weight values ​​of each queue. Since the counter supports negative values, when the counter is negative, subsequent dequeue operations will still correctly deduct the corresponding byte length, and there is no situation where credit is under-deducted; the total weight of the counters of each queue increases proportionally to the weight, so the ratio of the total number of dequeued bytes of each queue is consistent with the ratio of the weight values, and the bandwidth allocation ratio, queue fairness, and scheduling accuracy are not affected.

[0125] After the above parallelization transformation, the critical timing path of DWRR scheduling is changed from a serial multi-level path of multi-bit adders, comparators, and RR polling to a single-path RR polling. The number of combinational logic levels is reduced from more than 50 levels to about 20 to 30 levels, which meets the timing convergence requirements of network chips with a main frequency of 1000MHz to 1250MHz.

[0126] The SP matrix scheduling circuit uses a software-configurable priority matrix (priority_matrix) instead of a fixed hardware priority ordering, enabling flexible configuration of queue priorities. At the same time, its output can be directly used as a valid request input for the DWRR parallel optimization circuit, supporting the direct cascading of SP and DWRR.

[0127] Table 1 is a schematic table of the priority matrix in this embodiment. As shown in Table 1, taking 12 queues and 8 priority levels as an example, the priority matrix is ​​a two-dimensional matrix with 8 rows and 12 columns: row indices 0 to 7 correspond to priority levels 0 to 7 (row 0 has the lowest priority and row 7 has the highest priority), and column indices 0 to 11 correspond to queue nodes 0 to 11; each element in the matrix follows the following rule: if there is a queue node with a pending scheduling request under the priority level, it is set to 1, otherwise it is set to 0.

[0128] Table 1; ; The priority matrix is ​​constructed as follows: Each clock cycle, the scheduling circuit collects the request status of each queue in real time, forming a 1x12 request vector A. Each column corresponds to a queue; a bit of 1 indicates that the queue has a request to be scheduled, and a bit of 0 indicates no request. Since dequeueing and enqueueing operations change the request status of each queue in real time, request vector A is automatically refreshed every clock cycle. Simultaneously, based on the priority information configured by the software, an 8x12 configuration matrix B is formed: a bit of 1 in the i-th row and j-th column of the configuration matrix indicates that the j-th queue is configured by the software to have the i-th priority. The configuration matrix is ​​statically maintained after being written and does not need to be updated with changes in the real-time request status. A bitwise AND operation is performed between request vector A and each row of configuration matrix B to obtain the priority matrix C (i.e., priority_matrix): the corresponding bit in the priority matrix is ​​set to 1 only when a queue simultaneously meets both conditions: "currently has a request to be scheduled" (bit of request vector A is 1) and "configured by the software to this priority" (bit of the corresponding row and column of configuration matrix B is 1); otherwise, it is set to 0.

[0129] Taking the priority matrix example shown in Table 1 as a reference, assuming that queue 0 is currently configured with priority 0 and has a request, a queue is configured with priority 3 and has a request, a queue is configured with priority 4 and has a request, a queue is configured with priority 6 and has a request, and queues 8, 10, and 11 are all configured with priority 7 and all have requests, then rows 0, 3, 4, 6, and 7 of the priority matrix will have their corresponding columns set to 1, and all bits in the remaining rows will be 0. Because the priority configuration is written in software rather than fixed in hardware, the priority mapping relationship of each queue can be flexibly adjusted under different business scenarios, completely eliminating the limitation of the strong binding between queue number and priority in traditional SP scheduling.

[0130] Perform a bitwise OR operation on each row (each priority level) of the priority matrix: if at least one bit in the row is 1, the bitwise OR result is 1, indicating that there is a valid request queue for the corresponding priority; if all bits in the row are 0, the result is 0, indicating that there is no valid request queue for the priority. Arrange the bitwise OR results of each row in sequence to obtain an 8-bit matrix compression vector (matrix_compress[7:0]), where each bit corresponds to the valid request status of a priority level. Through horizontal compression, the multi-row information of the priority matrix is ​​simplified into a compact 8-bit bit vector, providing a concise input for quickly locating the highest priority.

[0131] Table 2 shows an example of the corresponding matrix compression vector (matrix_compress). As shown in Table 2, following the example of the priority matrix above, the results of the bitwise OR operation are as follows: priority 0 results in 1, priority 1 results in 0, priority 2 results in 0, priority 3 results in 1, priority 4 results in 1, priority 5 results in 0, priority 6 results in 1, and priority 7 results in 1. Thus, we get matrix_compress[7:0] = 1101_1001 (from the high bit to the low bit, the priority corresponds to priority 7 to priority 0 respectively).

[0132] Table 2; ; The goal is to determine the priority level corresponding to the leftmost (most significant) bit set to 1 in matrix_compress[7:0], i.e., the current highest priority max_priority. Traditional methods involve bit-by-bit scanning, resulting in a high number of logical levels. This embodiment uses pure bitwise operations to complete the location with very few logical levels. The specific steps are as follows: Step 1: Reverse the position of matrix_compress to obtain the reversed vector A.

[0133] Reverse the order of the bits in `matrix_compress` (swap bit 0 with bit 7, bit 1 with bit 6, and so on) to obtain the reversed vector A. Using the example above, `matrix_compress` = 1101_1001, and after the bit reversal, A = 1001_1011. The bit reversal operation maps the leftmost 1-bit position (corresponding to the highest priority) in `matrix_compress` to the rightmost 1-bit position in A, thus transforming the problem of finding the leftmost 1 into finding the rightmost 1, which is easier to handle using efficient bitwise operations.

[0134] Step 2: Locate the rightmost position in the reversed vector A and set it to 1 to obtain right_first_cond.

[0135] Use the following bitwise operation formula: right_first_cond = A&(~(A-1)); Here, ~ indicates bitwise NOT, and & indicates bitwise AND.

[0136] The principle of this formula is as follows: After subtracting 1 from A, the rightmost bit becomes 0 and all the 0s to its right become 1, while the high bits on the left remain unchanged; after inverting the bits of A-1, the corresponding position of the rightmost bit becomes 1 and all the bits on the left are flipped; after performing a bitwise AND operation with A, only the 1 at the rightmost bit is retained, and all the other bits are 0, thus obtaining right_first_cond, a one-hot code where only the rightmost bit of A is 1.

[0137] Using the example above, we can verify that: A = 1001_1011; A-1 = 1001_1010; ~(A-1) = 0110_0101; A & ~(A-1) = 1001_1011 & 0110_0101 = 0000_0001, which means right_first_cond = 0000_0001, indicating that the rightmost bit of A is set to 1 at bit0.

[0138] Step 3: Reverse the bit order of right_first_cond to obtain the highest priority one-hot encoding.

[0139] Reverse the order of the bits in `right_first_cond`, restoring the rightmost 1-bit position in coordinate system A to the corresponding leftmost 1-bit position in coordinate system `matrix_compress`. This yields the one-hot encoded representation of the highest priority bit in `matrix_compress`. Using the example above: `right_first_cond = 0000_0001`, after reversing the bit order, we get `1000_0000`, indicating that the most valid 1-bit bit in `matrix_compress` is bit 7, corresponding to a current highest priority of 7.

[0140] Step 4: Convert the one-hot encoding into a binary priority number.

[0141] After subtracting 1 from the one-hot code obtained in the previous step, sum all the bits set to 1 in the result. The sum is the binary number max_priority corresponding to the highest priority. Using the example above: one-hot code = 1000_0000, subtracting 1 gives 0111_1111. There are 7 bits set to 1, and the sum is 7, meaning max_priority = 7, consistent with the expected result. This conversion method requires only two steps: subtraction and summation, resulting in minimal logical overhead.

[0142] After determining max_priority, the scheduling circuit extracts the data of the max_priority row from the priority matrix. This row of data is the request bitmap of all valid request queues under the current highest priority. The bits set to 1 correspond to the queue nodes with pending requests under this priority. This request bitmap is directly used as the valid request input of the DWRR parallel optimization circuit without the need for additional register buffering or cross-clock cycle transmission, realizing the direct cascading of the SP matrix scheduling circuit and the DWRR parallel optimization circuit.

[0143] Based on the two core improvements mentioned above, the SP matrix scheduling circuit and the DWRR parallel optimization circuit can be cascaded within the same clock cycle to achieve complete SP+DWRR hybrid scheduling. The complete single-cycle scheduling process is as follows: The input signals include real-time request signals from all queues, priority information configured by the software, weight configuration for each queue, and message byte length information. During the SP matrix scheduling phase, the scheduling circuit performs a bitwise AND operation between the request vector and each row of the configuration matrix to construct a priority matrix. It then performs a bitwise OR operation on each row to obtain a compressed matrix vector. Bitwise operations are used to quickly locate `max_priority`, and the request bitmap corresponding to the highest priority group is output to the DWRR parallel optimization circuit. During the DWRR parallel arbitration phase, the scheduling circuit uses the received request bitmap as valid request input and checks the sign bits of the counters for each valid request queue. If all signs are negative, parallel RR polling arbitration and counter weighted updates are performed. If not all signs are negative, standard RR arbitration is performed. Finally, the winning queue is output, completing message dequeueing and counter decrement. All of the above steps are completed within a single clock cycle.

[0144] Regarding timing constraints in circuit cascading, the comprehensive data under a certain advanced domestic process (less than 28nm) is as follows: the SP matrix scheduling circuit has approximately 15 combinational logic levels, the DWRR parallel optimization circuit has approximately 20 combinational logic levels, and the total number of combinational logic levels after cascading does not exceed 35, meeting the 30 to 36 level constraint required for a main frequency of 1000MHz to 1250MHz. In terms of hardware implementation characteristics, all circuits are implemented using pure combinational logic, without loop structures or multi-level nesting, requiring no real-time software intervention or register configuration switching, and supporting line-speed scheduling and arbitration of 400G / 800G bandwidth traffic at main frequencies of 1GHz to 1.25GHz.

[0145] In summary, this application's embodiments, by recognizing the decoupling nature of the data dependency between the DWRR weighting step and the RR polling arbitration step under the special condition that all valid request queue counters are negative, change the execution of the two from serial to parallel, reducing the combinational logic levels of the critical timing path of DWRR scheduling from over 50 levels to approximately 20 to 30 levels; replacing the fixed hardware priority sorting with a software-configurable priority matrix, the SP matrix circuit can quickly locate the highest priority with approximately 15 levels of combinational logic, and directly cascade the result to the DWRR arbitration circuit; the total number of logic levels after cascading does not exceed 35 levels, meeting the timing convergence requirements of network chips with main frequencies above 1000MHz, and completing the full SP+DWRR hybrid scheduling within a single clock cycle without sacrificing scheduling accuracy, while supporting flexible software configuration of queue priorities as needed.

[0146] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A queue scheduling method, characterized in that, The method includes: In each queue to be scheduled, the queue containing the message to be sent is identified as the valid request queue; Within the same clock cycle, based on the priority configured for each queue to be scheduled, the queue with the highest priority among the valid request queues is determined as a candidate queue. If the counters of each candidate queue are all negative, the candidate queues are polled and arbitrated to determine the winning queue. The counters of each candidate queue are then added with their respective weight values. The message from the arbitration winner queue is dequeued, and the counter of the arbitration winner queue is reduced by the length of the dequeued message in bytes.

2. The method according to claim 1, characterized in that, The method further includes: If the counters of each candidate queue are not all negative, a round-robin arbitration is performed on the candidate queues with non-negative counters to determine the winning queue.

3. The method according to claim 1, characterized in that, The method further includes: Read the highest bit of the counter of each candidate queue and determine the highest bit as the sign bit of the counter of the corresponding queue; When the sign bit of the counter in each candidate queue is 1, it is determined that the counter in each candidate queue is negative.

4. The method according to claim 1, characterized in that, Subtract the length of the dequeued message from the counter of the arbitration winner queue, including: The length of the message bytes corresponding to multiple dequeue operations is accumulated, and the accumulated length of bytes is deducted from the counter of the arbitration winner queue.

5. The method according to claim 4, characterized in that, The method further includes: When there exists a queue in which the counter is both added to with the corresponding weight value and subtracted from the accumulated byte length within the same clock cycle, the queue is determined as the target queue. The weight value corresponding to the target queue is combined with the accumulated byte length, and the result of the combined calculation is written into the counter of the target queue.

6. The method according to claim 1, characterized in that, The queue with the highest priority among the valid request queues is determined as the candidate queue, including: Construct a priority matrix, where the rows of the priority matrix correspond to the priority level and the columns correspond to the queue nodes of each queue to be scheduled. The matrix elements of the queue nodes with messages to be sent are set to 1 in the corresponding priority row, and the rest are set to 0. The highest priority is determined according to the priority matrix, and the data in the row corresponding to the highest priority in the priority matrix is ​​used as a request bitmap to indicate each of the candidate queues.

7. The method according to claim 6, characterized in that, Constructing a priority matrix includes: The priority matrix is ​​obtained by performing a bitwise AND operation between the request vector representing the request status of each queue and each row of the configuration matrix representing the priority configuration of each queue.

8. The method according to claim 6, characterized in that, The highest priority is determined based on the priority matrix, including: Perform a bitwise OR operation on each row of the priority matrix to obtain a compressed vector. Each bit of the compressed vector represents whether there is a valid request queue for the corresponding priority. Perform bitwise operations on the compressed vector to determine the priority level corresponding to the most significant bit in the compressed vector, which is then used as the highest priority.

9. The method according to claim 8, characterized in that, Perform bitwise operations on the compressed vector to determine the priority level corresponding to the most significant bit in the compressed vector, including: Perform a bit reversal on the compressed vector to obtain the inverted vector; Subtract 1 from the inverted vector and then invert it. Perform a bitwise AND operation with the inverted vector to obtain the one-hot code corresponding to the rightmost bit set to 1 in the inverted vector. The one-hot code corresponding to the rightmost 1 bit is bit-reversed to obtain the one-hot code corresponding to the most significant bit in the compressed vector.

10. The method according to claim 9, characterized in that, The method further includes: After subtracting 1 from the one-hot code corresponding to the most significant bit, all bits set to 1 in the result are accumulated, and the accumulated result is used as the binary number corresponding to the highest priority.

11. A queue scheduling device, characterized in that, The device includes: The request determination unit is used to determine the queue with the message to be sent as the valid request queue in each queue to be scheduled. The scheduling unit, connected to the request determination unit, is used to determine the queue with the highest priority among the valid request queues as a candidate queue within the same clock cycle according to the priority configured for each queue to be scheduled, and to perform round-robin arbitration on each candidate queue to determine the winning queue when the counters of each candidate queue are all negative, and to add their respective weight values ​​to the counters of each candidate queue. The dequeue processing unit, connected to the scheduling unit, is used to dequeue the messages from the arbitration winner queue and subtract the byte length of the dequeue message from the counter of the arbitration winner queue.

12. The apparatus according to claim 11, characterized in that, The scheduling unit includes a priority scheduling circuit, a parallel arbitration circuit, and a parallel weighting circuit. The priority scheduling circuit is used to determine the queue with the highest priority among the valid request queues as a candidate queue according to the priority configured for each queue to be scheduled. The parallel arbitration circuit, connected to the priority scheduling circuit, is used to poll and arbitrate each candidate queue when the counters of each candidate queue are all negative, so as to determine the winning queue. The parallel weighting circuit is used to add the corresponding weight value to the counter of each candidate queue within the same clock cycle as the parallel arbitration circuit when the counters of each candidate queue are all negative. The output of the priority scheduling circuit is connected to the input of the parallel arbitration circuit via a combinational logic path.

13. The apparatus according to claim 12, characterized in that, The parallel weighting circuit includes a register, which is used to latch the weighting result obtained by the parallel weighting circuit in the current clock cycle and write the latched weighting result into the counter of the corresponding queue in the next clock cycle.

14. The apparatus according to claim 12, characterized in that, The arbitration logic of the parallel arbitration circuit is a pure combinational logic circuit, and the critical path of the arbitration logic consists of polling arbitration operations.

15. A queue scheduling system, characterized in that, The system includes a priority scheduling subsystem and a polling arbitration subsystem; The priority scheduling subsystem includes: The request determination module is used to determine the queue with the message to be sent as the valid request queue in each queue to be scheduled. The candidate queue determination module, connected to the request determination module, is used to determine the queue with the highest priority among the valid request queues as the candidate queue based on the priority configured for each queue to be scheduled. The request bitmap output module, connected to the candidate queue determination module, is used to generate and output a request bitmap indicating each candidate queue; The input terminal of the polling arbitration subsystem is connected to the output terminal of the request bitmap output module. The polling arbitration subsystem includes: A parallel arbitration module is used to poll and arbitrate each of the candidate queues when the counters of each candidate queue are all negative, so as to determine the winning queue. The parallel weighting module is used to add the corresponding weight value to the counter of each candidate queue within the same clock cycle as the parallel arbitration module when the counters of each candidate queue are negative. The dequeue processing module, connected to the parallel arbitration module, is used to dequeue the messages from the arbitration winner queue and subtract the byte length of the dequeue message from the counter of the arbitration winner queue. The processing of the priority scheduling subsystem and the processing of the polling arbitration subsystem are completed within the same clock cycle.

16. The system according to claim 15, characterized in that, The output of the priority scheduling subsystem and the input of the polling arbitration subsystem are connected through a combinational logic path, so that the priority scheduling subsystem and the polling arbitration subsystem form a continuous combinational logic path within the same clock cycle.

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