Data transmission method, switching chip, device and electronic equipment
Patent Information
- Application Number
- CN202611308700.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-26
- Publication Date
- 2026-10-30
AI Technical Summary
[0004]有鉴于此，本申请提供了一种数据传输方法、交换芯片、装置及电子设备，以解决报文传输效率不高的问题
Smart Images
Figure CN123020511A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data transmission technology, specifically to data transmission methods, switching chips, devices, and electronic equipment. Background Technology
[0002] PCIe (Peripheral Component Interconnect Express) bus is a high-speed serial computer expansion bus standard widely used in connecting hardware devices such as graphics cards, network adapters, and storage in computers. With the rapid development of technologies such as cloud computing, artificial intelligence, and big data, the demand for large-scale heterogeneous parallel computing and high-throughput storage is constantly increasing. As the core component enabling interconnection between multiple PCIe devices, the performance of the PCIe switch chip directly affects the data transmission efficiency of the entire system. The PCIe switch chip's Crossbar is a hardware switching architecture that enables arbitrary direct connections between multiple ports. It performs data flow control, data buffering, and packet parsing on received PCIe packets. After matching the routing table entries to obtain the outgoing port information, it forwards the packet to the corresponding output port.
[0003] In existing PCIe switching chips, when the Crossbar sends TLP (Transaction Layer Packet) messages to downstream PCIe devices, the Header and Payload each use an independent channel for transmission. However, short packets, long packets, and TLP messages without Payload have much less effective data than the transmission capacity that can be carried in one clock cycle, yet they still need to occupy a clock cycle to be sent to the downstream PCIe, resulting in wasted bandwidth. Furthermore, the TLP message Header and Payload are each limited to only one channel for transmission, and the channel allocation method is fixed and rigid, preventing flexible interleaving of different messages and limiting further improvements in transmission efficiency. Summary of the Invention
[0004] In view of this, this application provides a data transmission method, a switching chip, a device, and an electronic device to solve the problem of low message transmission efficiency.
[0005] Firstly, this application provides a data transmission method, the method comprising: Retrieve the first and second adjacent packets in the transmission queue; At the moment when the first message is transmitted to the last frame, determine whether the payload data length of the second message is less than or equal to the first threshold. If the payload data length of the second message is less than or equal to the first threshold, then at the last beat time, in the period where the last beat time of the first message is located, the payload data of the second message is placed in the message header channel group. Before sending the first message and the second message to the receiving end, the payload data of the second message is switched from the message header channel group to the payload channel group to transmit the first message and the second message.
[0006] In one optional implementation, if the payload length of the first message is greater than or equal to a second threshold, the number of fragments of the first message is odd, and the number of fragments is greater than or equal to a third threshold, and the payload data length of the second message is greater than 0; the step of switching the payload data of the second message from the header channel group to the payload channel group before sending the first message and the second message to the receiving end to transmit the first message and the second message includes: At the tail time, the last fragment of the tail payload of the first message is allocated to the first channel of the payload channel group, and the payload data of the second message is allocated to the second channel of the payload channel group. Within the same cycle, the last fragment of the tail load of the first message is output through the first channel of the payload channel group, and the payload data of the second message is output through the second channel of the payload channel group. The header of the first message is located in the first channel of the header channel group.
[0007] In an optional implementation, if the payload length of the first message is greater than or equal to a second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to a third threshold, the payload data length of the second message is greater than 0, and the first message has a preceding message and the preceding message is concatenated with the first message, the step of switching the payload data of the second message from the header channel group to the payload channel group before sending the first message and the second message to the receiving end to transmit the first message and the second message further includes: At the tail time, the first fragment of the tail payload of the first message is allocated to the first channel of the payload channel group, the last fragment of the tail payload of the first message is allocated to the second channel of the payload channel group, and the payload data of the second message is allocated to the first channel of the payload channel group; the first fragment is adjacent to the last fragment. In the first cycle, the first and last segments of the tail load of the first message are output through the first channel of the payload channel group, and in the second cycle, the payload data of the second message is output through the first channel of the payload channel group. The second cycle is adjacent to the first cycle and follows the first cycle.
[0008] In an optional implementation, if the payload length of the first message is greater than or equal to a second threshold, the number of fragments of the first message is even, and the payload data length of the second message is greater than 0, then the step of switching the payload data of the second message from the header channel group to the payload channel group before sending the first message and the second message to the receiving end to transmit the first message and the second message includes: At the tail time, the first fragment of the tail payload of the first message is allocated to the first channel of the payload channel group, the last fragment of the tail payload of the first message is allocated to the second channel of the payload channel group, and the payload data of the second message is allocated to the first channel of the payload channel group; the first fragment is adjacent to the last fragment. In the first cycle, the first and last segments of the tail load of the first message are output through the first channel of the payload channel group, and in the second cycle, the payload data of the second message is output through the first channel of the payload channel group. The second cycle is adjacent to the first cycle and follows the first cycle.
[0009] In an optional implementation, if the payload length of the first message is greater than or equal to a second threshold, the number of fragments of the first message is even, the payload data length of the second message is greater than 0, and the first message has a preceding message that is concatenated with the first message, then the step of switching the payload data of the second message from the header channel group to the payload channel group before sending the first message and the second message to the receiving end to transmit the first message and the second message further includes: At the tail time, the last fragment of the tail payload of the first message is allocated to the first channel of the payload channel group, and the payload data of the second message is allocated to the second channel of the payload channel group. Within the same cycle, the last fragment of the tail load of the first message is output through the first channel of the payload channel group, and the payload data of the second message is output through the second channel of the payload channel group. The header of the first message is located in the first channel of the header channel group.
[0010] In an optional implementation, if the payload length of the first message is greater than or equal to a second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to a fourth threshold, and there is no second message concatenated with the first message, the method further includes: At the tail time, the last fragment of the tail payload of the first message is allocated to the first channel of the payload channel group, and the message header of the first message is located in the first channel of the message header channel group. At the tail time, the last fragment of the tail payload of the first message is switched from the message header channel group to the first channel output of the payload channel group.
[0011] In an optional implementation, if the payload length of the first message is greater than or equal to a second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to a fourth threshold, and there is a previous message concatenated with the first message, the method further includes: At the tail time, the first segment of the tail payload of the first message is allocated to the first channel of the payload channel group, and the last segment of the tail payload of the first message is allocated to the second channel of the payload channel group. Within the same cycle, the first slice is output through the first channel of the payload channel group, and the last slice is output through the second channel of the payload channel group. Wherein, if the tail data of the previous message is located in the second channel of the payload channel group, the message header of the first message is located in the first channel of the message header channel group; if the tail data of the previous message is located in the first channel of the payload channel group, the message header of the first message is located in the second channel of the message header channel group.
[0012] The data transmission method provided in this embodiment includes obtaining adjacent first and second messages in the transmission queue; determining whether the payload data length of the second message is less than or equal to a first threshold when the first message is transmitted to the end time; if the payload data length of the second message is less than or equal to the first threshold, then at the end time, in the period where the end time of the first message is located, placing the payload data of the second message in the message header channel group; before sending the first and second messages to the receiving end, switching the payload data of the second message from the message header channel group to the payload channel group to transmit the first and second messages.
[0013] This method utilizes the idle transmission resources during the tail time, enabling the parallel transmission of the first and second packets within the same clock cycle, thus improving data transmission efficiency without increasing additional bandwidth. Furthermore, the packet assembly process is primarily achieved through data path selection and switching, eliminating the need for large-capacity buffers or complex processing units. This results in simple hardware implementation, low chip resource consumption and power consumption, and excellent scalability and applicability, making it widely applicable to PCIe switching chips and various high-speed data transmission systems based on the PCIe bus.
[0014] Secondly, this application provides a switching chip, the switching chip including a crossbar switch output logic unit, the crossbar switch output logic unit including: The message buffer logic unit is used to temporarily store the first and second adjacent messages in the transmission queue; A message scheduling logic unit, connected to the message buffer logic unit, is used to schedule descriptors from the message buffer logic unit and generate a read signal; A message packet assembly logic unit, connected to the message scheduling logic unit, is used to perform the following actions: at the end of the transmission of the first message, determine whether the payload data length of the second message is less than or equal to a first threshold; if the payload data length of the second message is less than or equal to the first threshold, then at the end of the transmission, place the payload data of the second message in the message header channel group of the same period as the end of the transmission of the first message; before sending the first message and the second message to the receiving end, switch the payload data of the second message from the message header channel group to the payload channel group to transmit the first message and the second message. The message exit logic unit, connected to the message packet assembly logic unit, is used to send the first message and the second message to the receiving end.
[0015] Thirdly, this application provides a data transmission apparatus, the apparatus comprising: The message acquisition module is used to acquire the first and second adjacent messages in the transmission queue. The judgment module is used to determine whether the payload data length of the second message is less than or equal to a first threshold at the time when the first message is transmitted to the end of the transmission. The message placement module is used to place the payload data of the second message in the message header channel group at the tail time if the payload data length of the second message is less than or equal to the first threshold. The message transmission module is used to switch the payload data of the second message from the message header channel group to the payload channel group before sending the first message and the second message to the receiving end, so as to transmit the first message and the second message.
[0016] Fourthly, this application provides an electronic device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the data transmission method of the first aspect or any corresponding embodiment described above. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0018] Figure 1 This is a flowchart illustrating a data transmission method according to one embodiment; Figure 2 This is a schematic diagram of message placement in one embodiment; Figure 3 This is a schematic diagram of message placement in one embodiment; Figure 4 This is a schematic diagram of message placement in one embodiment; Figure 5 This is a schematic diagram of message placement in one embodiment; Figure 6 This is a schematic diagram of message placement in one embodiment; Figure 7 This is a timing diagram of message transmission in one embodiment; Figure 8 This is a schematic diagram of message placement in one embodiment; Figure 9 This is a schematic diagram of message placement in one embodiment; Figure 10 This is a schematic diagram of message placement in one embodiment; Figure 11 This is a schematic diagram of message placement in one embodiment; Figure 12 This is a schematic diagram of message placement in one embodiment; Figure 13 This is a schematic diagram of message placement in one embodiment; Figure 14 This is a schematic diagram of message placement in one embodiment; Figure 15 This is a schematic diagram of a cross switch output logic unit according to one embodiment; Figure 16 This is a schematic diagram of a message packet assembly logic unit in one embodiment; Figure 17 This is a structural block diagram of a data transmission device according to one embodiment; Figure 18 This is a schematic diagram of the hardware structure of an electronic device according to one embodiment. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0020] The data transmission method provided in this application can be applied to the Crossbar output logic unit of a PCIe switching chip to perform packet concatenation processing on multiple TLP messages before sending them to downstream PCIe devices. In practical applications, this method is applicable to PCIe 3.0, PCIe 4.0, PCIe 5.0 and higher versions of the PCIe bus protocol, as well as other high-speed serial bus switching chips compatible with the PCIe protocol.
[0021] According to an embodiment of this application, a data transmission method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.
[0022] This embodiment provides a data transmission method. Figure 1 This is a flowchart of a data transmission method according to an embodiment of this application, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain the first and second adjacent packets in the transmission queue.
[0023] The first and second messages are two adjacent messages to be sent in the transmission queue. The first message is the message about to be sent to the receiver, and the second message is the next message waiting to be sent after the first message. The process involves reading the first message to be sent from the message transmission queue, and simultaneously reading the second message that immediately follows the first message in the queue. This retrieval operation requires at least the basic information corresponding to both messages, including at least the transmission progress information and payload length information of both messages.
[0024] The first descriptor of the current message to be sent can be obtained from the sending end, and the second descriptor adjacent to the first descriptor can be prefetched. The corresponding message is read according to the first descriptor as the first message, and the corresponding message is read according to the second descriptor as the second message.
[0025] Step S102: At the time when the first message is transmitted to the end of the frame, determine whether the payload data length of the second message is less than or equal to the first threshold.
[0026] The tail time is the last clock cycle of a message transmission. During this cycle, the last part of the message data (i.e., the tail data) is sent to the receiving end, which can be used to pre-trigger the pre-scheduling operation of subsequent messages. Different types of messages have different effective data volumes at the tail time. The payload data length is the length of the effective payload in bytes after removing the message header. The first threshold is a preset length determination threshold, which can be configured according to the hardware channel width and single-cycle transmission capacity. It is used to determine whether the second message is a message that can be concatenated. Optionally, the first threshold is 32 bytes.
[0027] During the continuous transmission of the first message, the transmission progress is monitored in real time. When the first message enters its tail phase, the payload data length of the acquired second message is retrieved and compared with a first threshold. If the payload data length of the second message is less than or equal to the first threshold, it indicates that the data volume of the second message is small and can be combined with the tail phase of the first message. If the payload data length of the second message is greater than the first threshold, it indicates that the data volume of the second message is large and not suitable for combination. In this case, the first and second messages can be transmitted in the normal order.
[0028] Step S103: If the payload data length of the second message is less than or equal to the first threshold, then at the end time, in the period where the end time of the first message is located, the payload data of the second message is placed in the message header channel group.
[0029] The header channel group is used to transmit message header information, and the payload channel group is used to transmit message payload data. During message transmission, the header channel group and the payload channel group are two independent transmission channel groups. The header channel group carries the message header information, and the payload channel group carries the message payload data. Under normal transmission conditions, each message is sent to the receiving end according to the rule that the message header goes through the header channel group and the payload data goes through the payload channel group. However, at the tail time of the first message, the header of the first message has already been sent in the previous clock cycle, and the header channel group is idle. At this time, if the payload data length of the second message is less than or equal to a first threshold, it indicates that the second message meets the packet concatenation condition. Therefore, the payload data of the second message is temporarily placed in the header channel group used to carry the header of the first message, and it is in the same clock cycle as the tail data of the first message.
[0030] like Figure 2 As shown, the first message A is a long packet with an odd number of fragments, and the second message is B. Before the first message is transmitted to the end time, the payload data of the second message is temporarily stored in the message header channel group of the same period as the end data of the first message, i.e., the T3 period. In this example, the end data of the first message is A-5.
[0031] Similarly, such as Figure 3 As shown, the first message A is a long packet with an even number of fragments, and the second message is B. The payload data of the second message is placed in the message header channel of the same period as the tail data of the first message, i.e., the T3 period. In this example, the tail data of the first message are A-5 and A-6.
[0032] Step S104: Before sending the first message and the second message to the receiving end, the payload data of the second message is switched from the message header channel group to the payload channel group to transmit the first message and the second message.
[0033] The receiving end is a peer PCIe device that communicates with the sending end, used to receive and parse TLP messages sent by the sending end. To ensure the messages received by the receiving end conform to the standard message format, the payload data of the second message is switched from the header channel group to the payload channel group before the first and second messages are sent to the receiving end. After the switch, within the same clock cycle, the tail data of the first message and the payload data of the second message are output through the payload channel group in the same cycle.
[0034] In this embodiment, the first message is not limited and can be either a long packet or a short packet. When both the first and second messages are short packets, the two short packets can be output in parallel through the header channel group and the payload channel group within the same clock cycle, achieving simultaneous transmission of two short packets within one clock cycle. Optionally, when the second message is a TLP message without payload, the header of the second message can be sent directly through the header channel group.
[0035] The data transmission method provided in this embodiment utilizes the idle transmission resources at the tail time to achieve parallel transmission of the first message tail time and the second message within the same clock cycle, improving data transmission efficiency without increasing additional transmission bandwidth. Furthermore, the packet assembly process is mainly achieved through data path selection and switching, eliminating the need for large-capacity buffers or complex processing units. The hardware implementation is simple, with low chip resource consumption and power consumption, exhibiting good scalability and applicability. It can be widely applied to PCIe switching chips and various high-speed data transmission systems based on the PCIe bus.
[0036] In some optional implementations, if the payload length of the first message is greater than or equal to the second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to the third threshold, the payload data length of the second message is greater than 0. Step S104 above includes: at the end time, allocating the last fragment of the end-time payload of the first message to the first channel of the payload channel group, and allocating the payload data of the second message to the second channel of the payload channel group; within the same period, outputting the last fragment of the end-time payload of the first message through the first channel of the payload channel group, and outputting the payload data of the second message through the second channel of the payload channel group; wherein, the message header of the first message is located in the first channel of the message header channel group.
[0037] In this embodiment, the number of fragments is odd and greater than or equal to a third threshold to ensure that the first message has a tail time and that there are available idle transmission resources available at the tail time. Specifically, when the number of fragments in the first message is odd and at least 3, only one fragment needs to be sent at its tail time, while the other channel is idle, thereby providing reusable transmission resources for the payload data of the second message.
[0038] Furthermore, the payload length of the first message is greater than or equal to the second threshold, used to confirm that the first message is a long packet from the perspective of data volume. In this embodiment, the second threshold can be 32 bytes, that is, when the payload length of the first message is greater than or equal to 32 bytes, the first message is determined to be a long packet; the third threshold can be 3, that is, the number of fragments of the first message is at least 3. It should be noted that in practical applications, the specific value of the second threshold can be flexibly set according to the hardware channel bit width and single-cycle transmission capability, and is not limited to 32 bytes. Those skilled in the art can adjust it according to actual needs.
[0039] Since the number of fragments in the first message is odd and greater than or equal to the third threshold, the last fragment of the first message's tail time needs to occupy a separate clock cycle for transmission. In this case, the last fragment is assigned to the first channel of the payload channel group, which is the same channel as the header of the first message. That is, the header of the first message is located in the first channel of the header channel group, and the last fragment of its tail payload follows the header in the same channel (the first channel of the payload channel group), ensuring that the header and tail of the same message are transmitted on the same channel, facilitating correct message reassembly at the receiving end. Simultaneously, the payload data of the second message is assigned to the second channel of the payload channel group and transmitted in parallel with the last fragment of the first message within the same cycle. This compresses the transmission of the first message's tail time and the second message, which originally required two clock cycles, into one, saving one clock cycle and effectively improving bandwidth utilization.
[0040] like Figure 4 As shown, the last fragment of the tail payload of the first message is A-5, the payload data of the second message is B, and the message header of the first message is A-HD. The last fragment of the tail payload of the first message and the payload data of the second message are sent in cycle T3.
[0041] Furthermore, if the payload length of the first message is greater than or equal to the second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to the third threshold, the payload data length of the second message is greater than 0, and the first message has a preceding message and the preceding message is concatenated with the first message, the above step S104 further includes: At the tail time, the first fragment of the tail payload of the first message is assigned to the first channel of the payload channel group, the last fragment of the tail payload of the first message is assigned to the second channel of the payload channel group, and the payload data of the second message is assigned to the first channel of the payload channel group; the first fragment and the last fragment are adjacent; in the first cycle, the first fragment and the last fragment of the tail payload of the first message are output through the first channel of the payload channel group, and in the second cycle, the payload data of the second message is output through the first channel of the payload channel group; the second cycle is adjacent to the first cycle and follows the first cycle.
[0042] The concatenation of the previous message and the first message means that the previous message and the first message are sent to the same receiving port, and the tail data of the previous message and the header of the first message are transmitted in parallel within the same clock cycle. In this case, the tail data of the previous message occupies a certain channel at the start time of the first message, such as... Figure 5 and Figure 6 The checkmark in the text. For example... Figure 5 As shown, the tail data of the previous message is in the second channel (chnl1) of the payload channel group in cycle T1. The header of the first message is placed in the first channel (chnl0) of the header channel group. The first fragment (A-4) and the last fragment (A-5) of the tail payload of the first message are sent through the first and second channels in cycle T3 (cycle T1). The payload data of the second message B is sent through the first channel in cycle T4 (cycle T2). The first fragment refers to the penultimate segment of the last fragment. For example, A-4 in the figure is the first fragment of the tail payload, and A-5 is the last fragment of the tail payload.
[0043] like Figure 6 As shown, the tail data of the previous message is in the first channel (chnl 0) of the payload channel group in the T1 cycle, the message header of the first message is placed in the second channel (chnl 0) of the message header channel group, the first fragment (A-4) and the last fragment (A-5) of the tail payload of the first message are sent through the first and second channels in the T3 cycle (first cycle), and the payload data of the second message B is sent through the first channel in the T4 cycle (second cycle).
[0044] Figure 4 The corresponding timing diagram is as follows Figure 7 As shown, assume that the header of the first message A has 14 DW (double word, each DW is 4 bytes), and each fragment of the payload (e.g., A-1, A-2, etc.) has 16 DW. In period T3, the last fragment A-5 of the tail payload of the first message A is sent through the first channel of the payload channel group, and the payload data B of the second message B is sent through the second channel of the payload channel group. In period T3, the downstream receiver determines whether to retrieve the tail payload data of packet A from the first channel based on the data validity flag dwen0 of the first channel, and determines whether to retrieve the payload data of packet B from the second channel based on the data validity flag dwen1 of the second channel, thus achieving simultaneous reception of two messages within one period.
[0045] In some optional implementations, if the payload length of the first message is greater than or equal to the second threshold, the number of fragments of the first message is even, and the payload data length of the second message is greater than 0; the above step S104 includes: At the end of the clock, the first fragment of the end-of-clock payload of the first message is assigned to the first channel of the payload channel group, the last fragment of the end-of-clock payload of the first message is assigned to the second channel of the payload channel group, and the payload data of the second message is assigned to the first channel of the payload channel group; the first fragment and the last fragment are adjacent; in the first cycle, the first fragment and the last fragment of the end-of-clock payload of the first message are output through the first channel of the payload channel group, and in the second cycle, the payload data of the second message is output through the first channel of the payload channel group; the second cycle is adjacent to the first cycle and follows the first cycle.
[0046] In this embodiment, the number of fragments in the first message is even. Since the two fragments at the tail time have already occupied two channels of the payload channel group, the payload data of the second message cannot be sent at the tail time of the first message. Therefore, it needs to be sent in the next cycle (second cycle) after the tail time. Specifically, at the tail time (first cycle), the first fragment (i.e., the penultimate fragment) of the tail payload of the first message is allocated to the first channel of the payload channel group, and the last fragment of the tail payload of the first message is allocated to the second channel of the payload channel group. The two fragments are sent in parallel through the two channels in the same cycle, completing the transmission of the first message. At the same time, the payload data of the second message is allocated to the first channel of the payload channel group and output in the next cycle (second cycle) after the tail time. To ensure continuous busy transmission path, when the payload data of the second message is sent through the first channel in the second cycle, the header of the third message can be sent together in the second cycle through the header channel group (e.g., the second channel of the header channel group), realizing the parallel transmission of the two messages in the second cycle. It should be noted that the header of the first message is located in the first channel of the header channel group, and the tail payload of the first message is located in the same channel as the header (i.e., the payload channel corresponding to the first channel), ensuring that the header and tail of the same message are transmitted in the same channel.
[0047] like Figure 8As shown, taking the first message A (long packet, with an even number of fragments N=4) as an example, the message header A-HD of the first message A is located in the first channel of the message header channel group. In cycle T1, A-1 and A-2 are transmitted in parallel through the two channels of the payload channel group; in cycle T2, A-3 and A-4 are transmitted in parallel through the two channels of the payload channel group; in cycle T3 (the tail time, i.e., the first cycle), the first fragment A-5 of the tail payload of the first message is allocated to the first channel of the payload channel group, and the last fragment A-6 of the tail payload of the first message is allocated to the second channel of the payload channel group. Both fragments are transmitted simultaneously in cycle T3, completing the transmission of the first message A. The payload data of the second message B is transmitted through the first channel of the payload channel group in cycle T4 (the second cycle). Through this method, the two tail fragments of the first message are transmitted in parallel through two channels at the tail time, and the second message is transmitted in the next cycle. Compared with the prior art's method of sequentially transmitting tail fragments, this saves at least one clock cycle.
[0048] Furthermore, if the payload length of the first message is greater than or equal to the second threshold, the number of fragments of the first message is even, the payload data length of the second message is greater than 0, and the first message has a preceding message that is concatenated with the first message, the above step S104 further includes: At the end of the frame, the last fragment of the end-frame payload of the first message is assigned to the first channel of the payload channel group, and the payload data of the second message is assigned to the second channel of the payload channel group. Within the same cycle, the last fragment of the end-frame payload of the first message is output through the first channel of the payload channel group, and the payload data of the second message is output through the second channel of the payload channel group. The message header of the first message is located in the first channel of the message header channel group.
[0049] When a first message contains a preceding message and the preceding message is concatenated with the first message, the last fragment of the preceding message will occupy a channel at the start of the first message, compressing the overall transmission rhythm of the first message. Since the first message has an even number of fragments, the last fragment originally required transmission at the end of the transmission cycle should have two fragments. Due to the concatenation interference from the preceding message, the penultimate fragment of the first message is forced to merge with the preceding fragments and be transmitted prematurely. This results in only the last fragment remaining to be transmitted at the end of the transmission cycle, leaving the second channel of the payload channel group idle. This provides reusable transmission resources for the payload data of the second message. Therefore, at the end of the transmission cycle, the last fragment of the first message's payload is allocated to the first channel of the payload channel group, and the payload data of the second message is allocated to the second channel of the payload channel group. The data of both messages are transmitted in parallel within the same cycle. In this process, the header of the first message is located in the first channel of the header channel group, and the last fragment of its tail payload is located in the same channel (the first channel of the payload channel group) as the header, ensuring that the header and tail of the same message are transmitted in the same channel.
[0050] like Figure 9 As shown, taking the first message A (long packet, with an even number of fragments N=6) as an example, the tail data of the previous message (marked as "√" in the figure) is located in the second channel of the payload channel group during period T1. This causes the message header A-HD of the first message A to be placed in the first channel of the header channel group. The first payload fragment A-1 of A is sent through the first channel during period T1, while A-2 is postponed to period T2 and sent together with A-3. Due to the occupied start time, the transmission rhythm of A is compressed. A-5 is sent earlier in period T3 along with A-4, and A-6, as the last fragment, is sent through the first channel during period T4. The second channel of the payload channel group is idle during period T4. At this time, the payload data of the second message B is allocated to the second channel of the payload channel group and sent in parallel with A-6 during period T4, realizing the simultaneous transmission of the two messages at the tail time.
[0051] like Figure 10 As shown, the tail data of the previous message is located in the first channel of the payload channel group during period T1, which means that the message header A-HD of the first message A can only be placed in the second channel of the header channel group. The first payload fragment A-1 of A is sent through the second channel during period T1, while A-2 is postponed to period T2. The first message A sends the tail fragment A-6 through the first channel during period T4, and the payload data of the second message B is sent in parallel with A-6 through the second channel during period T3.
[0052] Even if the initial channel is occupied due to the previous message packet being assembled, this implementation method can still use the second channel that is idle at the end of the last frame to transmit the payload data of the second message. This compresses the transmission of the first message's last frame and the second message, which originally required two frames, into one frame, effectively improving bandwidth utilization.
[0053] In some optional implementations, if the payload length of the first message is greater than or equal to the second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to the fourth threshold, and there is no second message concatenated with the first message, the method further includes: Step S201: Before the tail beat time, the last fragment of the tail beat payload of the first message is allocated to the message header channel group.
[0054] If the number of fragments of the first message is odd and greater than or equal to the fourth threshold, it indicates that the first message is a long packet and there are idle transmission resources available at its tail time. The fourth threshold is greater than the third threshold, and optionally the fourth threshold is 5.
[0055] Before the tail beat time, the last fragment of the tail beat payload of the first message is allocated to the first message header channel group.
[0056] like Figure 11 As shown, taking the first message A (long packet, with an odd number of fragments N=5) as an example, the message header A-HD of the first message A is located in the first channel of the message header channel group. In cycle T1, A-1 and A-2 are transmitted in parallel through the two channels of the payload channel group; in cycle T2, A-3 and A-4 are transmitted in parallel through the two channels of the payload channel group; before the tail time T3 (i.e., cycle T2), the last fragment A-5 of the tail payload of the first message A is pre-assigned to the position of the message header channel group (head).
[0057] Step S202: At the tail time, the last fragment of the tail payload of the first message is switched from the message header channel group to the first channel output of the payload channel group.
[0058] Before sending the first and second messages to the receiving end, the last fragment, temporarily placed in the header channel group, is switched to the first channel output of the payload channel group. After the switch, the last fragment is finally sent through the first channel output of the payload channel group, allowing the receiving end to correctly identify and reassemble the fragment. Figure 12 As shown, the last fragment A-5 of the first message A is output through the first channel of the payload channel group in cycle T3.
[0059] In some optional implementations, if the payload length of the first message is greater than or equal to the second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to the fourth threshold, and there is a previous message and the first message being concatenated, the method further includes: at the end time, allocating the first fragment of the end time payload of the first message to the first channel of the payload channel group, and allocating the last fragment of the end time payload of the first message to the second channel of the payload channel group; within the same period, outputting the first fragment through the first channel of the payload channel group, and outputting the last fragment through the second channel of the payload channel group; Specifically, if the tail data of the previous message is located in the second channel of the payload channel group, the message header of the first message is located in the first channel of the header channel group; if the tail data of the previous message is located in the first channel of the payload channel group, the message header of the first message is located in the second channel of the header channel group.
[0060] In this implementation, if the number of fragments in the first message is odd and greater than or equal to the fourth threshold (e.g., N≥5), it indicates that the first message is a long packet. When the first message has a preceding message and the preceding message is concatenated with the first message, the tail data of the preceding message will occupy a channel at the start time of the first message. This causes the first payload fragment of the first message to be unable to be sent in parallel with the second payload fragment in the same cycle, but is postponed to the next cycle. This delay compresses the overall transmission rhythm of the first message. The two last fragments, which were originally sent separately in the penultimate and tail times, are merged and sent in parallel through two channels at the tail time. Therefore, at the tail time, the first fragment (i.e., the penultimate fragment) of the tail payload of the first message is assigned to the first channel of the payload channel group, and the last fragment of the tail payload of the first message is assigned to the second channel of the payload channel group. These two fragments are output in parallel through two channels in the same cycle.
[0061] Furthermore, the channel on which the header of the first message resides is determined by the channel on which the tail data of the previous message resides. Specifically, when the tail data of the previous message is located in the second channel of the payload channel group, since the same channel cannot transmit data from two different messages simultaneously within the same cycle, the header of the first message can only be placed in the first channel of the header channel group, and the tail payload of the first message follows the header in the first channel of the payload channel group (i.e., the first fragment is in the first channel, and the last fragment is in the second channel); when the tail data of the previous message is located in the first channel of the payload channel group, the header of the first message can only be placed in the second channel of the header channel group, and the tail payload of the first message follows the header in the second channel of the payload channel group (i.e., the first fragment is in the first channel, and the last fragment is in the second channel). It should be noted that regardless of which channel the tail data of the previous message is located in, the first fragment of the tail payload of the first message is always assigned to the first channel of the payload channel group, and the last fragment is always assigned to the second channel of the payload channel group. That is, the channel allocation of the first fragment and the last fragment at the tail time is fixed and has nothing to do with the interference channel of the previous message.
[0062] like Figure 13 As shown, taking the first message A (long packet, with an odd number of fragments N=5) as an example, the last frame data of the previous message (marked as "√" in the figure) is located in the second channel of the payload channel group in period T1. The message header A-HD of the first message A is placed in the first channel of the message header channel group. The first payload fragment A-1 of A is sent through the first channel of the payload channel group in period T1. Since the start time is occupied, the sending rhythm of A is compressed. A-4 and A-5, which were originally sent in T2 and T3 respectively, are finally merged in period T3. A-4 (the first fragment) is sent through the first channel of the payload channel group, and A-5 (the last fragment) is sent through the second channel of the payload channel group.
[0063] like Figure 14 As shown, the tail data of the previous message is located in the first channel of the payload channel group during cycle T1. The message header A-HD of the first message A is placed in the second channel of the header channel group. The first payload fragment A-1 of A is sent through the second channel of the payload channel group during cycle T1, while A-2 is postponed to cycle T2. In cycle T3, A-4 (the first fragment) is sent through the first channel of the payload channel group, and A-5 (the last fragment) is sent through the second channel of the payload channel group.
[0064] Even with the initial channel occupancy and transmission rhythm delay caused by the previous packet concatenation, this implementation method can still send the last two fragments of the first packet in parallel through two channels at the tail time, avoiding the generation of additional idle cycles due to rhythm delay and effectively improving transmission efficiency.
[0065] This embodiment also provides a switching chip, which includes a crossbar switch output logic unit, the crossbar switch output logic unit including: The message buffer logic unit is used to temporarily store the first and second adjacent messages in the transmission queue; A message scheduling logic unit, connected to the message buffer logic unit, is used to schedule descriptors from the message buffer logic unit and generate a read signal; A message packet assembly logic unit, connected to the message scheduling logic unit, is used to perform the following actions: at the end of the transmission of the first message, determine whether the payload data length of the second message is less than or equal to a first threshold; if the payload data length of the second message is less than or equal to the first threshold, then at the end of the transmission, place the payload data of the second message in the message header channel group of the same period as the end of the transmission of the first message; before sending the first message and the second message to the receiving end, switch the payload data of the second message from the message header channel group to the payload channel group to transmit the first message and the second message. The message exit logic unit, connected to the message packet assembly logic unit, is used to send the first message and the second message to the receiving end.
[0066] Cross switch output logic unit such as Figure 15 As shown, the message caching logic unit 101 temporarily stores the messages sent from the upstream. The message scheduling logic unit 102 retrieves the temporarily stored descriptors from the message caching logic unit 101, schedules the descriptors according to the ordering rules and the credit mechanism of the downstream and peer ends, and generates a read signal for the message caching logic unit 101. The descriptors scheduled by the message scheduling logic unit 102, along with the message header and payload read from the message caching logic unit 101, are sent to the message packet assembly logic unit 103. The message packet assembly logic unit 103 is as follows: Figure 16 As shown, the message concatenation logic unit 103 internally includes a descriptor prefetch FIFO queue (desc_2ptr_fifo), which can prefetch two descriptors simultaneously. The descriptor prefetch FIFO queue temporarily stores descriptors scheduled by the message scheduling logic unit 102. Based on the read descriptor, a read signal is generated for the message buffer FIFO queue (tlp_fifo). After aligning the descriptor with its corresponding message header and payload, the descriptor is sent to the concatenation module for concatenation. The message concatenation logic unit 103 judges based on the read descriptor. If the concatenation conditions are met, concatenation is performed according to the corresponding concatenation method. If the concatenation conditions are not met and the message corresponding to the read descriptor is a long packet, the second prefetched descriptor is read in advance at the tail time to predict whether the current message meets the concatenation conditions. If it does, concatenation is performed according to the corresponding concatenation method. The message output logic unit 104 sends data to the receiving end based on the downstream real-time backpressure.
[0067] like Figure 15 As shown, the crossbar switch output logic unit 100 is connected to the crossbar switch (CSB) and the PCIe interface, and is used to send the packets transmitted from the crossbar switch to the downstream PCIe device after packet concatenation. The packet buffer logic unit 101 can be implemented using a dual-port random access memory (DPRAM), while the packet scheduling logic unit 102 and the packet concatenation logic unit 103 can be implemented using a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The descriptor prefetch FIFO queue and the packet buffer FIFO queue can be implemented using a register file or static random access memory (SRAM). The packet concatenation module consists of sequential logic circuits (DFF, D flip-flops) and combinational logic circuits (comb), used to perform packet concatenation judgment and channel switching operations. The packet output logic unit 104 controls the data transmission rhythm according to the backpressure signal from the downstream device; transmission is paused when the backpressure signal is valid, and transmission continues when the backpressure signal is invalid. With the above hardware architecture, the switching chip can realize packet concatenation and transmission on the crossbar switch output side, effectively improving the bandwidth utilization and data transmission efficiency of the PCIe bus.
[0068] This embodiment also provides a data transmission device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.
[0069] This embodiment provides a data transmission device, such as... Figure 17 As shown, it includes: The message acquisition module is used to acquire the first and second adjacent messages in the transmission queue. The judgment module is used to determine whether the payload data length of the second message is less than or equal to a first threshold at the time when the first message is transmitted to the end of the transmission. The message placement module is used to place the payload data of the second message in the message header channel group at the tail time if the payload data length of the second message is less than or equal to the first threshold. The message transmission module is used to switch the payload data of the second message from the message header channel group to the payload channel group before sending the first message and the second message to the receiving end, so as to transmit the first message and the second message.
[0070] Further functional descriptions of the above modules are the same as those in the corresponding embodiments described above, and will not be repeated here.
[0071] In this embodiment, the data transmission device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.
[0072] Please see Figure 18 , Figure 18 This is a schematic diagram of the structure of an electronic device provided in an optional embodiment of this application, such as... Figure 18 As shown, the electronic device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 18 Take a processor 10 as an example.
[0073] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPRS), or any combination thereof.
[0074] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.
[0075] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
[0076] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.
[0077] The electronic device also includes a communication interface 30 for communicating with other devices or communication networks.
[0078] In the above embodiments, the functional modules in the switching chip, including the message buffering logic unit, message scheduling logic unit, message packet assembly logic unit, and message output logic unit, can be implemented entirely or partially through hardware circuits, firmware, or a combination of hardware and firmware. Specifically, the message buffering logic unit temporarily stores adjacent first and second messages in the transmission queue; the message scheduling logic unit schedules descriptors from the message buffering logic unit and generates read signals; the message assembly logic unit performs packet assembly judgment and assembly operations; and the message output logic unit sends the assembled data to the receiving end. The sub-units in the crossbar switch output logic unit, such as the buffer sub-unit, scheduling sub-unit, packet assembly sub-unit, and output sub-unit, can also be implemented in the above manner to complete message temporary storage, scheduling, packet assembly, and transmission processing operations.
[0079] Specifically, when implemented using hardware circuits, each functional module can utilize hardware logic devices such as Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs) to implement corresponding processing logic such as message buffering, descriptor scheduling, packet assembly judgment, channel switching, and data output. For example, the message buffering logic unit can be implemented using dual-port random access memory (DPRAM), and the message scheduling logic unit and message assembly logic unit can be implemented using ASICs or FPGAs. The descriptor prefetch FIFO queue and message buffer FIFO queue within the message assembly logic unit can be implemented using register files or static random access memory (SRAM). The assembly module consists of sequential logic circuits and combinational logic circuits, used to perform packet assembly judgment and channel switching operations. When implemented using firmware, the firmware configures logic according to the corresponding application scenario and business requirements. The configuration logic can be stored in the memory of the switching chip in the form of microcode or firmware programs, and executed by the processor or logic operation unit inside the chip, thereby generating all or part of the processes or functions according to the embodiments of this application, such as message length judgment, payload data placement, and channel switching.
[0080] Those skilled in the art will understand that the switching chip provided in this application can be a PCIe switching chip, applied to network switching equipment, high-speed network communication interface equipment, etc. It can be implemented through hardware logic circuit design within the chip, or by loading and executing firmware instructions within the chip to implement the various functional modules of the device provided in the specific embodiments of this application, as well as the method steps of the specific embodiments of this application. These firmware instructions can be stored in on-chip storage media such as read-only memory (ROM), static random access memory (SRAM), and tri-state content-addressable memory (TCAM) within the chip, or they can be stored in off-chip storage media. This allows the chip to implement the data transmission method steps of any of the above embodiments of this application when processing messages, thereby improving the bandwidth utilization and data transmission efficiency of the PCIe bus and reducing chip power consumption.
[0081] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.
Claims
1. A data transmission method, characterized in that, The method includes: Retrieve the first and second adjacent packets in the transmission queue; At the moment when the first message is transmitted to the last frame, determine whether the payload data length of the second message is less than or equal to the first threshold. If the payload data length of the second message is less than or equal to the first threshold, then at the last beat time, in the period where the last beat time of the first message is located, the payload data of the second message is placed in the message header channel group. Before sending the first message and the second message to the receiving end, the payload data of the second message is switched from the message header channel group to the payload channel group to transmit the first message and the second message.
2. The method according to claim 1, characterized in that, If the payload length of the first message is greater than or equal to a second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to a third threshold, and the payload data length of the second message is greater than 0; the step of switching the payload data of the second message from the header channel group to the payload channel group before sending the first message and the second message to the receiving end to transmit the first message and the second message includes: At the tail time, the last fragment of the tail payload of the first message is allocated to the first channel of the payload channel group, and the payload data of the second message is allocated to the second channel of the payload channel group. Within the same cycle, the last fragment of the tail load of the first message is output through the first channel of the payload channel group, and the payload data of the second message is output through the second channel of the payload channel group. The header of the first message is located in the first channel of the header channel group.
3. The method according to claim 1, characterized in that, If the payload length of the first message is greater than or equal to a second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to a third threshold, the payload data length of the second message is greater than 0, and the first message has a preceding message and the preceding message is concatenated with the first message, the step of switching the payload data of the second message from the header channel group to the payload channel group before sending the first message and the second message to the receiving end to transmit the first message and the second message further includes: At the tail time, the first fragment of the tail payload of the first message is allocated to the first channel of the payload channel group, the last fragment of the tail payload of the first message is allocated to the second channel of the payload channel group, and the payload data of the second message is allocated to the first channel of the payload channel group; the first fragment is adjacent to the last fragment. In the first cycle, the first fragment and the last fragment of the tail load of the first message are output through the first channel of the payload channel group, and in the second cycle, the payload data of the second message are output through the first channel of the payload channel group. The second cycle is adjacent to the first cycle and follows the first cycle.
4. The method according to claim 1, characterized in that, If the payload length of the first message is greater than or equal to the second threshold, the number of fragments of the first message is even, and the payload data length of the second message is greater than 0, then the step of switching the payload data of the second message from the header channel group to the payload channel group before sending the first message and the second message to the receiving end to transmit the first message and the second message includes: At the tail time, the first fragment of the tail payload of the first message is allocated to the first channel of the payload channel group, the last fragment of the tail payload of the first message is allocated to the second channel of the payload channel group, and the payload data of the second message is allocated to the first channel of the payload channel group; the first fragment is adjacent to the last fragment. In the first cycle, the first fragment and the last fragment of the tail load of the first message are output through the first channel of the payload channel group, and in the second cycle, the payload data of the second message are output through the first channel of the payload channel group. The second cycle is adjacent to the first cycle and follows the first cycle.
5. The method according to claim 1, characterized in that, If the payload length of the first message is greater than or equal to the second threshold, the number of fragments of the first message is even, the payload data length of the second message is greater than 0, and the first message has a preceding message that is concatenated with the first message, then the step of switching the payload data of the second message from the header channel group to the payload channel group before sending the first message and the second message to the receiving end to transmit the first message and the second message further includes: At the tail time, the last fragment of the tail payload of the first message is allocated to the first channel of the payload channel group, and the payload data of the second message is allocated to the second channel of the payload channel group. Within the same cycle, the last fragment of the tail load of the first message is output through the first channel of the payload channel group, and the payload data of the second message is output through the second channel of the payload channel group. The header of the first message is located in the first channel of the header channel group.
6. The method according to claim 1, characterized in that, If the payload length of the first message is greater than or equal to the second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to the fourth threshold, and there is no second message concatenated with the first message, the method further includes: Before the tail time, the last fragment of the tail payload of the first message is allocated to the message header channel group; At the tail time, the last fragment of the tail payload of the first message is switched from the message header channel group to the first channel output of the payload channel group.
7. The method according to claim 1, characterized in that, If the payload length of the first message is greater than or equal to the second threshold, the number of fragments of the first message is odd and the number of fragments is greater than or equal to the fourth threshold, and there is a previous message concatenated with the first message, the method further includes: At the tail time, the first segment of the tail payload of the first message is allocated to the first channel of the payload channel group, and the last segment of the tail payload of the first message is allocated to the second channel of the payload channel group. Within the same cycle, the first slice is output through the first channel of the payload channel group, and the last slice is output through the second channel of the payload channel group. Wherein, if the tail data of the previous message is located in the second channel of the payload channel group, the message header of the first message is located in the first channel of the message header channel group; if the tail data of the previous message is located in the first channel of the payload channel group, the message header of the first message is located in the second channel of the message header channel group.
8. A switching chip, characterized in that, The switching chip includes a crossbar switch output logic unit, which includes: The message buffer logic unit is used to temporarily store the first and second adjacent messages in the transmission queue; A message scheduling logic unit, connected to the message buffer logic unit, is used to schedule descriptors from the message buffer logic unit and generate a read signal; A message packet assembly logic unit, connected to the message scheduling logic unit, is used to perform the following actions: at the end of the transmission of the first message, determine whether the payload data length of the second message is less than or equal to a first threshold; if the payload data length of the second message is less than or equal to the first threshold, then at the end of the transmission, place the payload data of the second message in the message header channel group of the same period as the end of the transmission of the first message; before sending the first message and the second message to the receiving end, switch the payload data of the second message from the message header channel group to the payload channel group to transmit the first message and the second message. The message exit logic unit, connected to the message packet assembly logic unit, is used to send the first message and the second message to the receiving end.
9. A data transmission device, characterized in that, The device includes: The message acquisition module is used to acquire the first and second adjacent messages in the transmission queue. The judgment module is used to determine whether the payload data length of the second message is less than or equal to a first threshold at the time when the first message is transmitted to the end of the transmission. The message placement module is used to place the payload data of the second message in the message header channel group at the tail time if the payload data length of the second message is less than or equal to the first threshold. The message transmission module is used to switch the payload data of the second message from the message header channel group to the payload channel group before sending the first message and the second message to the receiving end, so as to transmit the first message and the second message.
10. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the data transmission method of any one of claims 1 to 7.