3D dram-based address mapping and permutation method, system, medium, product and terminal

Abstract

The application provides a 3D DRAM-based address mapping and replacement method, system, medium, product and terminal. In a sequential mode, an address mapping table is configured based on a preset first mapping mode, and all normal DRAM resources are fully utilized. In a replacement mode, the system can lock the storage layer where the damaged storage block is located, different address mapping modes are adopted for different logical address ranges by combining the first mapping mode and a second mapping mode, the address mapping table can be dynamically adjusted, the use of other normal storage blocks is avoided due to the damage of part of the storage blocks, the expansion effect of the damaged storage blocks during interleaving is reduced, and the negative influence of the part of DRAM yield problems on the system capacity and bandwidth is reduced.

Description

Technical Field

[0001] This application relates to the field of 3D storage technology, and in particular to an address mapping and replacement method, system, medium, product and terminal based on 3D DRAM. Background Technology

[0002] With the continuous development of semiconductor technology, the bandwidth requirements of chip systems are increasing. To improve the bandwidth balance of chip systems, existing technical solutions typically employ interleaving and decoding to optimize the use of DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). By distributing data across multiple memory cells, interleaving and decoding schemes can effectively improve data access efficiency and the overall system bandwidth.

[0003] In traditional 2D systems, DRAM and SOC (System-on-a-Chip) are discrete devices. DRAM has a relatively limited impact on the yield of the SOC chip. However, if DRAM and SOC are integrated on the same chip, their larger area and complexity can have a greater impact on the overall yield.

[0004] However, with the rise of 3D integration technology, 3D DRAM and SoC are integrated together via direct bonding. This tight integration method brings new challenges. Although 3D DRAM still has internal repair logic, due to the complexity of the 3D structure, some DRAM cells may be irreparable during manufacturing. Especially in the case of multi-layer DRAM stacking, irreparable cells accumulate layer by layer, leading to a significant decrease in overall yield.

[0005] Furthermore, in 3D systems using conventional interleaving decoding schemes, if a DRAM cell fails, due to the limitations of the interleaving range, the failed DRAM cell will cause all other normal DRAM cells (N-1 blocks) interleaved with it to also become unusable. This amplification effect of damage significantly reduces effective storage capacity and bandwidth. Specifically, the damaged DRAM cell will be amplified by a factor of N (N being the number of interleavings) or M (M being the number of memory blocks within a single interleaving group), thus severely impacting system performance and reliability.

[0006] In summary, while interleaving decoding schemes can effectively improve bandwidth equalization in 2D systems, in 3D systems, due to the direct bonding between DRAM and the SoC and the yield issues caused by multi-layer stacking, conventional interleaving schemes may lead to an amplification effect of DRAM damage, thus significantly reducing the effective capacity and bandwidth of the system. Therefore, considering the characteristics of 3D systems, a new technical solution is urgently needed to address these issues and improve the yield and performance of 3D integrated chips. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method, system, medium, product and terminal based on 3D DRAM address mapping and replacement, to solve technical problems such as how to improve the yield and performance of 3D integrated chips.

[0008] To achieve the above and other related objectives, a first aspect of this application provides an address mapping and replacement method based on 3D DRAM, applied to a system-on-a-chip (SoC). The SoC is electrically connected to a 3D DRAM chip. The 3D DRAM-based address mapping and replacement method includes: determining the operating mode of the SoC based on a decoding enable signal; wherein the operating mode includes a sequential mode and a replacement mode; when the SoC is in the sequential mode, configuring an address mapping table of the 3D DRAM chip based on a preset first mapping mode; wherein the 3D DRAM chip includes multiple memory layers, each memory layer containing multiple memory groups; each memory group containing multiple memory blocks; when the SoC is in the replacement mode, locking the memory layer containing the damaged memory block, and configuring the address mapping table of the 3D DRAM chip based on the preset first mapping mode and a preset second mapping mode.

[0009] In some embodiments of the first aspect of this application, the method of configuring the address mapping table of the 3D DRAM chip based on a preset first mapping mode includes: interleaving consecutive logical address segments in turn to map them to the physical addresses of each memory block in each memory group, so as to configure the address mapping table of the 3D DRAM chip.

[0010] In some embodiments of the first aspect of this application, the method of configuring the address mapping table of the 3D DRAM chip based on a preset first mapping mode and a preset second mapping mode includes: first, swapping the logical address mapped by the damaged memory block with the logical address mapped by the preset target memory block; then, interleaving consecutive logical address segments in the low logical address range (excluding the last row) to the physical addresses of each memory block in the locked memory layer (excluding the last row); interleaving consecutive logical address segments in the high logical address range of the last row to the physical addresses of each memory block in the last row of the locked memory layer (excluding the preset target memory block); or, non-interleaving consecutive logical address segments in the high logical address range of the last row to the physical addresses of each memory block in the last row of the locked memory layer.

[0011] In some embodiments of the first aspect of this application, the method of configuring the address mapping table of the 3D DRAM chip based on a preset first mapping mode and a preset second mapping mode includes: first, swapping the logical address mapped by the damaged memory block with the logical address mapped by the preset target memory block; then, interleaving and mapping consecutive logical address segments in the low logical address range of the first row to the physical addresses of each memory block in the first row of the locked memory layer, excluding the preset target memory block; or, interleaving and mapping consecutive logical address segments in the low logical address range of the first row to the physical addresses of each memory block in the first row of the locked memory layer; and interleaving and mapping consecutive logical address segments in the high logical address range, excluding the first row, to the physical addresses of each memory block in the locked memory layer, excluding the first row.

[0012] In some embodiments of the first aspect of this application, the method of mutually exchanging the logical address mapped to the damaged storage block and the logical address mapped to the preset target storage block includes: locking the storage layer and storage group where the damaged storage block is located based on the location signal of the damaged storage block; in the locked storage layer, after performing inter-group exchange between the storage group where the damaged storage block is located and the preset target storage group, performing intra-group exchange of the preset target storage block in the preset target storage group, so as to mutually exchanging the logical address mapped to the damaged storage block and the logical address mapped to the preset target storage block.

[0013] In some embodiments of the first aspect of this application, the method further includes: accessing the 3D DRAM chip according to the address mapping table of the 3D DRAM chip and based on the input address signal.

[0014] To achieve the above and other related objectives, a second aspect of this application provides an address mapping and replacement system based on 3D DRAM, comprising:

[0015] System-on-a-chip (SoC);

[0016] A 3D DRAM chip, wherein the system-on-a-chip is electrically connected to the 3D DRAM chip; the 3D DRAM chip includes multiple memory layers, each memory layer includes multiple memory groups, and each memory group includes multiple memory blocks;

[0017] The system-on-a-chip (SoC) is used to determine its operating mode based on a decoding enable signal; the operating mode includes a sequential mode and a replacement mode; when the SoC is in the sequential mode, the address mapping table of the 3D DRAM chip is configured based on a preset first mapping mode; when the SoC is in the replacement mode, the memory layer where the damaged memory block is located is locked, and the address mapping table of the 3D DRAM chip is configured based on the preset first mapping mode and the preset second mapping mode.

[0018] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the 3D DRAM-based address mapping and replacement method as described above.

[0019] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product comprising computer program code that, when executed on a computer, causes the computer to implement the 3D DRAM-based address mapping and replacement method as described above.

[0020] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the 3D DRAM-based address mapping and replacement method as described above.

[0021] As described above, the address mapping and replacement method, system, medium, product, and terminal based on 3D DRAM of this application have the following beneficial effects:

[0022] (1) In sequential mode, the address mapping table is configured based on the preset first mapping mode, making full use of all normal DRAM resources, ensuring that the system can run in the most optimized way without damaged memory blocks, while simplifying the software's access to and management of memory.

[0023] (2) In replacement mode, the system can lock the storage layer where the damaged memory block is located. By combining the first and second mapping modes, different address mapping methods are used for different logical address ranges, which can dynamically adjust the address mapping table. This avoids the inability of other normal memory blocks to be used due to the damage of some memory blocks, thereby reducing the amplification effect of partial DRAM yield loss on system capacity and bandwidth. It ensures that all normal memory blocks can be effectively utilized, keeping the logical address space continuous. This not only improves the utilization rate of storage resources but also reduces the impact of partial DRAM failure on the overall system performance. At the same time, the normalization of the mapped addresses reduces the types of software configurations, making the system easier to use.

[0024] (3) By reducing the amplification effect of damaged memory blocks during interleaving, the negative impact on system capacity and bandwidth caused by partial DRAM yield problems is reduced. Attached Figure Description

[0025] Figure 1 The diagram shown is a flowchart of an address mapping and replacement method based on 3D DRAM in one embodiment of this application.

[0026] Figure 2 The diagram shown is a schematic diagram of the grouping layout of the storage layer in one embodiment of this application.

[0027] Figure 3 The diagram shows a flowchart of address mapping for a damaged storage block in one embodiment of this application.

[0028] Figure 4 The diagram shown is a schematic representation of the layout mapping between the SOC logical address and the memory block after the damaged memory block is replaced, according to one embodiment of this application.

[0029] Figure 5 The diagram shown is a schematic of the SOC logical address layout after the damaged storage block is replaced, according to one embodiment of this application.

[0030] Figure 6 The diagram shown is a schematic block diagram of an address mapping and replacement system based on 3D DRAM in one embodiment of this application.

[0031] Figure 7 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this application. Detailed Implementation

[0032] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0033] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0034] <1> DRAM (Dynamic Random Access Memory): A type of computer memory used to store data for fast access by the central processing unit.

[0035] <2> SRAM (Static Random-Access Memory): Static random access memory is a common type of semiconductor memory widely used in computer systems, embedded systems, and caches.

[0036] <3> SOC (System on Chip): A system-on-a-chip is a technology that integrates the functions of multiple electronic systems onto a single chip.

[0037] <4> 3D DRAM: Three-dimensional dynamic random access memory, is an emerging storage technology that significantly improves storage density and performance by vertically stacking storage cells on multiple levels.

[0038] <5> 2D system: refers to the traditional planar architecture, where all components (such as storage units, logic circuits, etc.) are laid out on a single two-dimensional plane.

[0039] <6> 3D system: refers to an architecture that integrates multiple components (such as storage units, logic circuits, etc.) on multiple layers through vertical stacking technology.

[0040] <7> TSV (Through-Silicon Via): A silicon via is an advanced semiconductor packaging technology that enables vertical interconnection within or between chips by creating vertical through-holes on silicon chips.

[0041] While interleaving decoding schemes can effectively improve bandwidth equalization in 2D systems, in 3D systems, due to the direct bonding between DRAM and the SoC and the yield issues caused by multi-layer stacking, conventional interleaving schemes may lead to an amplification effect of DRAM damage, thus significantly reducing the effective capacity and bandwidth of the system. Therefore, considering the characteristics of 3D systems, a new technical solution is urgently needed to address these issues and improve the yield and performance of 3D integrated chips.

[0042] To facilitate understanding of the embodiments of this application, firstly, in conjunction with Figure 1 Detailed explanation. Figure 1 This document illustrates a flowchart of an address mapping and replacement method based on 3D DRAM, as described in an embodiment of the present invention. The 3D DRAM-based address mapping and replacement method is applied to a system-on-a-chip (SoC). The SoC is electrically connected to a 3D DRAM chip. The 3D DRAM chip includes multiple memory layers, each memory layer includes multiple memory groups, and each memory group includes multiple memory blocks. The address mapping and replacement method mainly includes the following steps:

[0043] S101: Determine the operating mode of the system-on-a-chip based on the decoding enable signal; wherein the operating mode includes sequential mode and replacement mode.

[0044] In this embodiment, the operating mode of the system-on-a-chip is controlled by the decoding enable signal (en), specifically divided into sequential mode and replacement mode. In the 3D DRAM chip, multiple DRAM chips are stacked together using vertical interconnect technology (such as TSV). Each memory layer's DRAM chip is a complete DRAM chip, and each memory layer's DRAM chip has multiple memory blocks, divided into multiple memory groups. The DRAM chip in each memory layer is damaged at the block level.

[0045] S102: When the system-on-a-chip is in the sequential mode, configure the address mapping table of the 3D DRAM chip based on the preset first mapping mode.

[0046] In this embodiment, as Figure 2 The diagram shown illustrates the grouped layout of the storage layer in an embodiment of the present invention. Exemplarily, the storage layer includes 16 storage blocks, divided into four storage groups: storage group B1, storage group B2, storage group B3, and storage group B4. Each storage group includes four storage blocks: storage group B1 includes storage blocks B1a, B1b, B1c, and B1d; storage group B2 includes storage blocks B2a, B2b, B2c, and B2d; storage group B3 includes storage blocks B3a, B3b, B3c, and B3d; and storage group B4 includes storage blocks B4a, B4b, B4c, and B4d.

[0047] In this embodiment, when en = 0, the operating mode of the system-on-a-chip is sequential mode. In sequential mode, based on a preset first mapping mode, the method of configuring the address mapping table of the 3D DRAM chip includes: interleaving and mapping consecutive logical address segments to the physical addresses of each memory block in each memory group in turn, so as to configure the address mapping table of the 3D DRAM chip. Thus, consecutive logical address segments are mapped to each memory block in each memory group in turn to achieve efficient continuous access and improve the parallel access capability and bandwidth utilization of the storage system.

[0048] It's important to note that logical address segments are divisions of the system-on-a-chip (SoC) logical address space, with each logical address segment corresponding to a memory block. Logical address segments are contiguous and represent the address range used by the SoC to access the 3D DRAM chip. Physical addresses, on the other hand, are determined based on the physical layout of the memory block and directly reflect its actual location within the 3D DRAM chip.

[0049] In this embodiment, for example, it is assumed that the interleaving granularity is 1KB and the number of interleaved memory groups is 4. The configured address mapping table in storage layer 1 is shown in Table 1:

[0050] Table 1

[0051] 0 0 B1 B1a 0 1 B2 B2a 0 2 B3 B3a 0 3 B4 B4a 1 0 B1 B1b 1 1 B2 B2b 1 2 B3 B3b 1 3 B4 B4b 2 0 B1 B1c 2 1 B2 B2C 2 2 B3 B3c 2 3 B4 B4c 3 0 B1 B1d 3 1 B2 B2d 3 2 B3 B3d 3 3 B4 B4d

[0052] It should be noted that in sequential mode, the configuration of address mapping tables for other storage layers is similar to that described above, and will not be repeated here. Table 1. Figure 2 This is merely one embodiment of the storage layer of the present invention, used only to explain the invention and not to limit the scope of protection of the invention. In practical applications, storage groups are divided according to the number of storage blocks, and address mapping is performed.

[0053] In this embodiment, in sequential mode, consecutive logical address segments are mapped in turn to the physical addresses of each memory block in each memory group to configure the address mapping table of the 3D DRAM chip. This is performed by the decoder in the system-on-a-chip according to a preset first mapping mode. That is, the decoder in the system-on-a-chip performs full interleaving by group, mapping consecutive logical address segments in turn to the memory blocks of each memory group. When accessing a certain memory layer, the memory group to be accessed is determined according to the input address signal, and the memory blocks in that memory group are accessed sequentially. For example, when accessing memory group B1 in the memory layer, the access sequence is: B1a→B1b→B1c→B1d.

[0054] S103: When the system-on-a-chip is in replacement mode, lock the storage layer where the damaged storage block is located, and configure the address mapping table of the 3D DRAM chip based on the preset first mapping mode and the preset second mapping mode.

[0055] In this embodiment, the method for configuring the address mapping table of the 3DDRAM chip based on a preset first mapping mode and a preset second mapping mode includes:

[0056] (1) First, swap the logical address mapped by the damaged storage block with the logical address mapped by the preset target storage block. Then, interleave the continuous logical address segments in the low logical address range (excluding the last row) to the physical addresses of each storage block in the locked storage layer (excluding the last row).

[0057] (2) The continuous logical address segments in the high logical address range of the last row are alternately mapped to the physical addresses of each storage block in the last row of the locked storage layer, except for the preset target storage block; or, the continuous logical address segments in the high logical address range of the last row are alternately mapped to the physical addresses of each storage block in the last row of the locked storage layer without being interleaved.

[0058] In this embodiment, the method for configuring the address mapping table of the 3DDRAM chip based on a preset first mapping mode and a preset second mapping mode includes:

[0059] (1) First, swap the logical address mapped by the damaged storage block with the logical address mapped by the preset target storage block. Then, interleave the continuous logical address segments in the lower logical address range of the first row with the physical addresses of each storage block in the first row of the locked storage layer, except for the preset target storage block. Alternatively, interleave the continuous logical address segments in the lower logical address range of the first row with the physical addresses of each storage block in the first row of the locked storage layer.

[0060] (2) Map consecutive logical address segments in the high logical address range other than the first line to the physical addresses of each memory block in the locked memory layer other than the first line in turn.

[0061] In this embodiment, as Figure 3 The diagram illustrates a process for logical address replacement of a damaged storage block in an embodiment of the present invention. The method of mutually replacing the logical address mapped to the damaged storage block and the logical address mapped to a preset target storage block includes:

[0062] S1031: Based on the location signal of the damaged storage block, locate the storage layer and storage group where the damaged storage block is located.

[0063] In this embodiment, when en=1, the operating mode of the system-on-a-chip is the replacement mode, which indicates that there is a damaged memory block in the 3D DRAM chip. Based on the received location signal (sel signal) of the damaged memory block, the memory layer and memory group where the damaged memory block is located are locked. Then, the logical address of the damaged memory block is replaced to map the damaged memory block to a location that does not affect the overall address space (e.g., the highest bit of the address space), thereby avoiding the discontinuity of the address space.

[0064] S1032: In the locked storage layer, after performing inter-group replacement between the storage group where the damaged storage block is located and the preset target storage group, the preset target storage block in the preset target storage group is replaced within the group, so as to replace the logical address mapped by the damaged storage block and the logical address mapped by the preset target storage block with each other.

[0065] In this embodiment, as Figure 4 The diagram shown illustrates the layout mapping between the SOC logical address and the memory block after the damaged memory block is replaced, as described in an embodiment of the present invention. Figure 5 The diagram shown illustrates the SOC logical address layout after replacing a damaged memory block in an embodiment of the present invention. Figure 2 As shown, assuming Figure 2 If memory block B2b is corrupted, and memory block B4d is the preset target memory block, after logical address replacement of the corrupted memory block B2b, the logical address of the corrupted memory block B2b is mapped to the physical address of the preset target memory block B4d. Thus, the corrupted memory block B2b is mapped to a location that does not affect the overall address space. Figure 4-5 As shown.

[0066] In this embodiment, as Figure 2 As shown, assuming each memory block is 1MB, totaling 16MB, and memory block B2b has a physical location error, if we still map consecutive address segments to memory blocks in different memory groups in a staggered manner, the memory blocks corresponding to row b will be unusable, leaving only 12MB of usable address space. Furthermore, the address space is discontinuous: 0-3MB is usable, 4-7MB is unusable, and 8-15MB is usable. Different chips may have errors in different physical units, resulting in different usable physical addresses for each chip, requiring multiple versions of software for address mapping, which is unreliable. This capacity loss and address space discontinuity significantly impact yield, reduce the system's effective capacity and bandwidth, amplify DRAM damage, and increase manufacturing defects and testing / repair costs. After mapping, for the system-on-a-chip (SoC), all individually damaged memory blocks can be mapped to memory block B4d.

[0067] In this embodiment, to reduce the impact of damaged memory blocks on the overall address space, the memory group containing the damaged memory block is first swapped with a preset target memory group. The preset target memory group can be either the memory group located at the highest bit of the logical address segment or the memory group located at the lowest bit of the logical address segment. This moves the memory group containing the damaged memory block to the edge of the logical address space, thereby reducing its impact on the overall address space. Then, the preset target memory blocks within the preset target memory group are swapped within the same group. The preset target memory blocks can be either the memory block located at the highest bit of the logical address segment or the memory block located at the lowest bit of the logical address segment, so that the logical address of the damaged memory block is mapped to the physical address of the preset target memory block.

[0068] In this embodiment, for example, the preset target storage group is the storage group located in the highest bit of the address segment. If storage block B2b is damaged, the decoding logic first performs inter-group swapping between storage groups B2 and B4, and then swaps B4d and B4b, thereby mapping the damaged storage block B2b to the SOC logical address B4d. Figure 5 As shown.

[0069] In this embodiment, for example, a preset target storage group is a storage group located in the highest bit of the logical address segment, and a preset target storage block is a storage block located in the highest bit of the logical address segment. Figure 4 As shown, the logical address mapped to the damaged storage block and the logical address mapped to the preset target storage block are swapped. For example... Figure 5As shown, the locked logical address space is 16MB, which is divided into different logical address ranges: 0-11MB (lower 12MB) and 12MB-15MB (higher 4MB). Within the 0-11MB logical address range, according to the preset first mapping mode (full interleaving), consecutive logical address segments within this range are interleaved and mapped to the first three rows of memory blocks, i.e., the first three memory blocks of the four memory groups, as shown in Table 2. Within the 12MB-15MB address range, according to the preset second mapping mode (triple interleaving or no interleaving), if the preset second mapping mode is triple interleaving, consecutive logical address segments within this range are interleaved and mapped to the last row of memory blocks except for memory block B4d, i.e., the last memory block of the first three memory groups, skipping the preset target memory block B4d, as shown in Table 3. If the preset second mapping mode is non-interleaving, consecutive logical address segments within the 12MB-15MB logical address range are mapped in turn to the memory blocks in the last row, i.e., the last memory block of the four memory groups, as shown in Table 4. Furthermore, the preset target memory group is the memory group located at the least significant bit of the logical address segment, and the preset target memory block is the memory block located at the least significant bit of the logical address segment. The address mapping method is similar to that described above and will not be repeated here.

[0070] Table 2 (Low-level full interleaving)

[0071] 0 0 B1 B1a 0 1 B2 B2a 0 2 B3 B3a 0 3 B4 B4a 1 0 B1 B1b 1 1 B2 B2b 1 2 B3 B3b 1 3 B4 B4b 2 0 B1 B1c 2 1 B2 B2C 2 2 B3 B3c 2 3 B4 B4c

[0072] Table 3 (High-level 3 intertwined)

[0073]

[0074] Table 4 (High-level positions do not intertwine)

[0075] 3 0 Full space B1 B1d 3 1 Full space B2 B2d 3 2 Full space B3 B3d 3 3 Unavailable Unavailable Unavailable

[0076] In this embodiment, the method further includes: accessing the 3D DRAM chip based on its address mapping table and the input address signal. When an input address signal is received, the corresponding address mapping table is first selected according to the current operating mode (sequential mode or permutation mode). The input address signal is then parsed to obtain the address segment or range of the memory layer to be accessed, and the logical address is converted into an actual physical address using the address mapping table. Finally, the 3D DRAM chip is accessed based on the parsed physical address.

[0077] It is worth noting that the address mapping and replacement method based on 3D DRAM of the present invention has the following advantages:

[0078] (1) In sequential mode, the address mapping table is configured based on the preset first mapping mode, making full use of all normal DRAM resources, ensuring that the system can run in the most optimized way without damaged memory blocks, while simplifying the software's access to and management of memory.

[0079] (2) In replacement mode, the system can lock the storage layer where the damaged memory block is located. By combining the first and second mapping modes, different address mapping methods are used for different logical address ranges, which can dynamically adjust the address mapping table. This avoids the inability of other normal memory blocks to be used due to the damage of some memory blocks, thereby reducing the amplification effect of partial DRAM yield loss on system capacity and bandwidth. It ensures that all normal memory blocks can be effectively utilized, keeping the logical address space continuous. This not only improves the utilization rate of storage resources but also reduces the impact of partial DRAM failure on the overall system performance. At the same time, the normalization of the mapped addresses reduces the types of software configurations, making the system easier to use.

[0080] (3) By reducing the amplification effect of damaged memory blocks during interleaving, the negative impact on system capacity and bandwidth caused by partial DRAM yield problems is reduced.

[0081] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first mapping mode and the preset second mapping mode are only used to distinguish different mapping modes and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that terms such as "first" and "second" do not necessarily imply that they are different.

[0082] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0083] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0084] Figure 6 This is a schematic block diagram of an address mapping and replacement system based on 3D DRAM provided in an embodiment of this application. Figure 6 As shown, the 3D DRAM-based address mapping and replacement system 600 includes:

[0085] System-on-a-chip 601;

[0086] The system-on-a-chip is electrically connected to the 3D DRAM chip 602; the 3D DRAM chip includes multiple memory layers, each memory layer includes multiple memory groups, and each memory group includes multiple memory blocks.

[0087] The system-on-a-chip (SoC) is used to determine its operating mode based on a decoding enable signal; the operating mode includes a sequential mode and a replacement mode; when the SoC is in the sequential mode, the address mapping table of the 3D DRAM chip is configured based on a preset first mapping mode; when the SoC is in the replacement mode, the memory layer where the damaged memory block is located is locked, and the address mapping table of the 3D DRAM chip is configured based on the preset first mapping mode and the preset second mapping mode.

[0088] In this embodiment, the system-on-a-chip is electrically connected to the 3D DRAM chip via a vertical interconnect technology (such as TSV).

[0089] It should be understood that the specific process of each module performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0090] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0091] Figure 7 This is a schematic block diagram of an electronic terminal provided in an embodiment of this application. The electronic terminal includes a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the 3DDRAM-based address mapping and replacement method described above. Figure 7 As shown, the electronic terminal includes at least one processor 701, a memory 702, at least one network interface 703, and a user interface 705. The various components in the device are coupled together via a bus system 704. It is understood that the bus system 704 is used to implement communication between these components. In addition to a data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 7 The general will label all buses as bus systems.

[0092] The user interface 705 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0093] It is understood that memory 702 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0094] In this embodiment of the invention, the memory 702 is used to store various types of data to support the operation of the electronic terminal 700. Examples of this data include: any executable program for operation on the electronic terminal 700, such as the operating system 7021 and application programs 7022; the operating system 7021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 7022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The address mapping and replacement method based on 3D DRAM provided in this embodiment of the invention can be included in the application program 7022.

[0095] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by processor 701. Processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 701 or by instructions in software form. The processor 701 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 701 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 701 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0096] In an exemplary embodiment, the electronic terminal 700 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to execute the aforementioned method.

[0097] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute... Figures 1 to 3The method of any of the embodiments shown.

[0098] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when executed on a computer, causes the computer to perform... Figures 1 to 3 The method of any of the embodiments shown.

[0099] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0100] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0101] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0102] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0103] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0104] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0105] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs, etc.).

[0106] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0107] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0108] In summary, this application provides a method, system, medium, product, and terminal for address mapping and replacement based on 3D DRAM. In sequential mode, the address mapping table is configured based on a preset first mapping mode, fully utilizing all normal DRAM resources. In replacement mode, the system can lock the memory layer where the damaged memory block is located. By combining the first and second mapping modes, different address mapping methods are used for different logical address ranges, dynamically adjusting the address mapping table to avoid the inability of other normal memory blocks to be used due to the damage of some memory blocks, reducing the amplification effect of damaged memory blocks during interleaving, and mitigating the negative impact on system capacity and bandwidth caused by partial DRAM yield issues. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0109] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. An address mapping and permutation method based on 3D DRAM, characterized in that, Applied to a system-on-a-chip (SoC), wherein the SoC is electrically connected to a 3D DRAM chip, the 3D DRAM-based address mapping and replacement method includes: The operating mode of the system-on-a-chip is determined based on the decoding enable signal; wherein the operating mode includes sequential mode and replacement mode; When the system-on-a-chip is in the sequential mode, the address mapping table of the 3D DRAM chip is configured based on a preset first mapping mode; wherein, the 3D DRAM chip includes multiple memory layers, each memory layer contains multiple memory groups, and each memory group contains multiple memory blocks; When the system-on-a-chip is in replacement mode, the memory layer where the damaged memory block is located is locked, and the address mapping table of the 3D DRAM chip is configured based on the preset first mapping mode and the preset second mapping mode.

2. The address mapping and replacement method based on 3D DRAM according to claim 1, characterized in that, Based on a preset first mapping mode, the method for configuring the address mapping table of the 3D DRAM chip includes: interleaving consecutive logical address segments in turn to map them to the physical addresses of each memory block in each memory group, so as to configure the address mapping table of the 3D DRAM chip.

3. The address mapping and replacement method based on 3D DRAM according to claim 1, characterized in that, The address mapping table of the 3D DRAM chip can be configured in the following ways, based on a preset first mapping mode and a preset second mapping mode: First, the logical address mapped by the damaged storage block and the logical address mapped by the preset target storage block are swapped. Then, the continuous logical address segments in the low logical address range (excluding the last row) are interleaved and mapped to the physical addresses of each storage block in the locked storage layer (excluding the last row). The continuous logical address range within the high logical address range of the last row is alternately interleaved and mapped to the physical addresses of each storage block in the last row of the locked storage layer, excluding the preset target storage block; or, the continuous logical address range within the high logical address range of the last row is alternately non-interleaved and mapped to the physical addresses of each storage block in the last row of the locked storage layer.

4. The address mapping and replacement method based on 3D DRAM according to claim 1, characterized in that, The address mapping table of the 3D DRAM chip can be configured in the following ways, based on a preset first mapping mode and a preset second mapping mode: First, the logical addresses mapped to the damaged storage block and the logical addresses mapped to the preset target storage block are interchanged. Then, the continuous logical address segments in the lower logical address range of the first row are alternately mapped to the physical addresses of each storage block in the first row of the locked storage layer, excluding the preset target storage block; or, the continuous logical address segments in the lower logical address range of the first row are alternately mapped to the physical addresses of each storage block in the first row of the locked storage layer without being interleaved. The consecutive logical address segments within the high logical address range (excluding the first line) are alternately mapped to the physical addresses of the various memory blocks in the locked memory layer (excluding the first line).

5. The address mapping and replacement method based on 3D DRAM according to claim 3, characterized in that, Methods for swapping the logical address mapped to the damaged memory block and the logical address mapped to the preset target memory block include: Based on the location signal of the damaged storage block, the storage layer and storage group where the damaged storage block is located are identified; In the locked storage layer, after the storage group containing the damaged storage block is swapped with the preset target storage group, the preset target storage block in the preset target storage group is swapped with the preset target storage block within the same group, so that the logical address mapped by the damaged storage block and the logical address mapped by the preset target storage block are swapped with each other.

6. The address mapping and replacement method based on 3D DRAM according to claim 1, characterized in that, Also includes: The 3D DRAM chip is accessed based on its address mapping table and the input address signal.

7. An address mapping and replacement system based on 3D DRAM, characterized in that, include: System-on-a-chip (SoC); A 3D DRAM chip, wherein the system-on-a-chip is electrically connected to the 3D DRAM chip; the 3D DRAM chip includes multiple memory layers, each memory layer includes multiple memory groups, and each memory group includes multiple memory blocks; The system-on-a-chip (SoC) is used to determine its operating mode based on a decoding enable signal; the operating mode includes a sequential mode and a replacement mode; when the SoC is in the sequential mode, the address mapping table of the 3D DRAM chip is configured based on a preset first mapping mode; when the SoC is in the replacement mode, the memory layer where the damaged memory block is located is locked, and the address mapping table of the 3D DRAM chip is configured based on the preset first mapping mode and the preset second mapping mode.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the address mapping and replacement method based on 3D DRAM as described in any one of claims 1 to 6.

9. A computer program product, characterized in that, The computer program product includes computer program code, which, when run on a computer, causes the computer to implement the address mapping and replacement method based on 3D DRAM as described in any one of claims 1 to 6.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the address mapping and replacement method based on 3D DRAM as described in any one of claims 1 to 6.

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