Address allocation method, controller and system

Abstract

The application discloses an address allocation method, a controller and a system, and relates to the technical field of communication, and comprises the following steps: since the hierarchical coding of a board card can indicate the uniqueness of the board card in an address allocation system, the device information and the mounting sequence can both indicate the uniqueness of a service device in the board card, therefore, when the address of the service device is allocated based on the hierarchical coding, the device information and the mounting sequence, the bus address of different service devices of different board cards can be made unique, and the problem of address conflict can be avoided. Moreover, the present scheme does not need to burn the addresses of all service devices included in the board card, and thus does not need manual configuration, is more efficient, and can avoid the error problem caused by manual configuration.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to address allocation methods, controllers and systems. Background Technology

[0002] In the field of communication technology, a single device is typically configured with multiple boards. Generally, cascading can be used to increase the transmission distance of bus signals and the number of devices that can be connected. However, current bus addresses usually use pre-configured static addresses. Using this method, when expanding the device through multi-backplane cascading or replacing different models of backplanes or modules, there is a risk of address conflicts between the new boards and the existing boards, potentially leading to problems such as device offline and loss of monitoring data. Furthermore, differences in the factory address settings for different models and manufacturers of devices further exacerbate the risk of address conflicts. Summary of the Invention

[0003] This application provides address allocation methods, controllers, systems, devices, electronic devices, storage media, and program products to solve the problem of address conflicts that occur when static addresses are used in related technologies.

[0004] This application provides an address allocation method, which is executed by a controller in an address allocation system, and the method includes: The hierarchical encoding of the cascaded hierarchy corresponding to at least one board in the address allocation system is identified. Based on the hierarchical code of the target board, obtain the device information and mounting order of the service devices mounted under the target board, wherein the target board is any one of at least one board; Based on the hierarchical code corresponding to at least one board, and the device information and / or mounting order of the service devices mounted under at least one board, a bus address is assigned to the service devices mounted under at least one board.

[0005] This application also provides a controller, including: a memory for storing a computer program; and a processor for implementing any of the above-described address allocation methods when executing the computer program.

[0006] This application provides an address allocation system, including a controller and at least one board, the board being used to mount one or more service devices, and the controller being connected to at least one board respectively; The controller is used to execute the steps of any of the above address allocation methods.

[0007] This application also provides an address allocation device, including: The identification module is used to identify the hierarchical encoding of the cascaded layers corresponding to at least one board in the address allocation system. The acquisition module is used to obtain the device information and mounting order of the service devices mounted under the target board according to the hierarchical code of the target board, wherein the target board is any one of at least one board; The allocation module is used to allocate bus addresses to the service devices connected to at least one board according to the hierarchical code corresponding to at least one board, and the device information and / or mounting order of the service devices connected to at least one board.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described address allocation methods.

[0009] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described address allocation methods.

[0010] This application allows for the identification of the hierarchical codes of each board, followed by the acquisition of device information and mounting order of the service devices connected to each board. Then, based on the hierarchical codes corresponding to multiple boards and the device information and mounting order of the service devices connected to each board, bus addresses can be allocated to each service device. Since the hierarchical codes of the boards indicate their uniqueness in the address allocation system, and the device information and mounting order both indicate the uniqueness of the service devices within the boards, allocating addresses to service devices based on hierarchical codes, device information, and mounting order ensures the uniqueness of bus addresses for different service devices on different boards, avoiding address conflicts. Furthermore, this solution eliminates the need to program the addresses of each service device onto the boards, thus eliminating manual configuration, improving efficiency, and avoiding errors caused by manual configuration. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart illustrating the first address allocation method provided in this application embodiment; Figure 2 A flowchart illustrating the second address allocation method provided in this application embodiment; Figure 3 A schematic diagram of the architecture of a controller provided in an embodiment of this application; Figure 4This is a schematic diagram of the architecture of a first address allocation system provided in an embodiment of this application; Figure 5 This is a schematic diagram of the architecture of a first address allocation system provided in an embodiment of this application; Figure 6 This is a schematic diagram of the architecture of a second address allocation system provided in an embodiment of this application; Figure 7 This is a schematic diagram of the internal logic of the cascaded hierarchy provided in the embodiments of this application; Figure 8 This is a schematic diagram of an address allocation device provided in an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0014] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] In the hardware architectures of multi-node servers, rack servers, and distributed storage servers, the I2C bus is a crucial low-speed bus for device status monitoring, hardware management, fault alarms, and link control. The primary function of the I2C bus is data exchange between low-speed integrated circuits such as temperature sensors, voltage monitors, and electrically erasable programmable read-only memory (EEPROM). It forms the core link for the Baseboard Management Controller (BMC) in the server to achieve overall hardware monitoring.

[0017] As server storage density continues to increase, single servers are typically equipped with multiple hard drive backplanes, multi-node computing modules, and numerous monitoring circuits. The traditional single-segment I2C bus architecture is clearly insufficient to meet the expansion needs of multiple nodes. To adapt to hardware layouts with multiple backplanes and modules, the industry commonly uses cascading to increase the transmission distance of bus signals and the number of devices that can be mounted. In multi-level cascading applications, devices and modules mounted on the backplane usually use static addresses. That is, during the R&D phase, the addresses of the devices mounted on the backplanes are planned and fixed in advance based on the number of server hardware backplanes, and the device addresses are locked through firmware burning, hardware configuration, etc. This approach typically has the following drawbacks: First, there is poor compatibility, making address conflicts a common problem. Once a device address is fixed, it cannot be changed. When expanding server capacity through multi-backplane cascading or replacing backplanes and modules with different models, there is a risk of address conflicts between the new cards and the existing ones, potentially leading to device offline issues or loss of monitoring data. Furthermore, differences in factory address settings between different models and manufacturers further exacerbate the risk of address conflicts.

[0018] Second, manual configuration and debugging are costly. The relevant technologies rely on manual planning and configuration of addresses in advance. For high-density servers with multiple backplanes and modules, the workload of address planning is large. At the same time, manual configuration is prone to problems such as address configuration errors and duplicate configurations, which can cause hardware debugging failures and prolong the product development cycle.

[0019] Third, bus cascading has limited scalability and poor signal stability. Multi-level backplane cascading significantly increases bus wiring length, easily leading to signal attenuation, crosstalk from reflections, and ground bounce noise, causing signal jitter and failing to meet bus communication requirements. Fixed relay cascading solutions can only achieve signal isolation, cannot adapt to dynamic changes in the number of devices, have a fixed number of cascading levels, cannot be expanded as needed, and have extremely low hardware adaptability.

[0020] To address the aforementioned technical problems, embodiments of this application provide an address allocation method, which can be executed by a controller in an address allocation system. The address allocation system can be applied in a server, and the controller can be a baseboard management controller, such as... Figure 1 As shown, the specific processing steps of the address allocation method may include: Step S101: Identify the hierarchical encoding of the cascaded layers corresponding to at least one board in the address allocation system.

[0021] Specifically, after the server is powered on, the controller can scan all the boards mounted on the server to directly identify the hierarchical code of each board. Alternatively, it can first obtain the board's identification information (the identification information can be a number, for example, the number can be the number of the slot where the board is located), and then find the board's hierarchical code based on the board's identification information from the pre-built mapping relationship between board identification information and hierarchical codes.

[0022] Step S102: Based on the hierarchical code of the target board, obtain the device information and mounting order of the service devices mounted under the target board.

[0023] The target board can be any one of multiple boards. Device information may include identification information, device model, original static address, device type, etc.

[0024] Specifically, a smaller hierarchical code indicates that the board is closer to the controller in terms of physical location or logical depth. After obtaining the hierarchical codes of each board, the controller can traverse each board from smallest to largest hierarchical code. Upon traversing each board, the controller can scan the service devices mounted on that board to obtain the device information and mounting order of each service device mounted on that board. After completing the traversal of all boards, the controller can obtain the device information and mounting order of each service device mounted on each board in the address allocation system.

[0025] For example, when the controller traverses a board, it can first open the communication channel corresponding to that board to avoid address conflicts between different boards. Then, it can send traversal commands to each address in the preset address range. For any address (here, the address is the physical bus address stored by the service device itself, i.e., the original static address), if a response is received for that address, it means that a corresponding service device exists at that address. At this time, the device information of the service device attached to that address can be read from that address. If no response is received for that address, it means that no service device exists at that address, and the controller can continue to probe the next address. In this way, the device information of each service device attached to that board can be obtained. At the same time, the order in which each service device is scanned can also be determined, for example, by the order of responses, which can be used as the attachment order of the service devices.

[0026] Step S103: Assign bus addresses to the service devices connected to the at least one board according to the hierarchical code corresponding to each of the at least one board, and the device information and / or mounting order of the service devices connected to the at least one board.

[0027] Specifically, hierarchical coding indicates the uniqueness of a board, while device information and mounting order indicate the uniqueness of a device on a board. Therefore, based on the hierarchical coding of each board, as well as the device information and mounting order of the service devices mounted on each board, the bus address of each service device can be determined and allocated to the service device. For example, the allocation operation can be to send the selected bus address to the service device, which can then store the bus address.

[0028] In this way, the motherboard's controller and service devices can communicate using the assigned bus address, eliminating the need for the original static address. Upon receiving a message, the service device can determine if the address carried in the message matches its own stored bus address. If so, it can assume the message was sent to it and perform corresponding service processing. Alternatively, when sending a message to the controller, the service device can add its own stored bus address to the message so the controller can identify the message source. For example, the controller can establish communication with various levels of service devices using the assigned bus address, reading temperature data from temperature sensors and voltage data from voltage monitors.

[0029] In addition, each time a bus address is assigned, it can be marked as allocated. This allows unmarked bus addresses to be identified as free addresses and allocated when adding new boards, thus improving the efficiency of bus address allocation.

[0030] The address allocation method in this application first identifies the hierarchical code of each board, then obtains the device information and mounting order of the service devices connected to each board. Then, based on the hierarchical codes corresponding to multiple boards, and the device information and mounting order of the service devices connected to each board, bus addresses are allocated to each service device. Since the hierarchical code of a board indicates its uniqueness in the address allocation system, and the device information and mounting order both indicate the uniqueness of the service device within the board, allocating addresses to service devices based on the hierarchical code, device information, and mounting order ensures that the bus addresses of different service devices on different boards are unique, thus avoiding address conflicts.

[0031] Furthermore, this solution eliminates the need to program the addresses of each included service device onto the board, thus avoiding manual address planning, resulting in higher efficiency, shorter product iteration cycles, and the prevention of errors caused by manual configuration. It is also adaptable to server models with different backplane numbers and peripheral configurations, requiring no specific modifications to the bus configuration, significantly improving hardware versatility.

[0032] In some optional implementations, in step S101 above, different methods can be used to determine the hierarchical encoding of each board depending on the different connection methods between the controller and the board. These methods may include the following: Method 1 involves identifying the level signal status of the hierarchy identification pin in the target repeater, where the target repeater is a repeater connected to the target board in the address allocation system. The hierarchy code of the target board is determined based on the level signal status of the hierarchy identification pin in the target repeater.

[0033] Specifically, when the target board is connected to the controller via a repeater, the repeater can be equipped with multiple level identification pins. After power-on, the combination of the level signals of these multiple level identification pins can indicate the level code of the connected board. For example, if the number of level identification pins is 3 and the combination of the level signals is "010", then the corresponding level code of the board is 2.

[0034] Taking the target board as an example, the state of the level signal of each level identification pin in the target repeater can be identified. Then, the state of the level signal of each level identification pin in the target repeater is combined into a binary code. After converting the code into decimal, the level code of the target board is obtained.

[0035] In this way, repeaters can isolate signals, avoiding problems such as signal attenuation, crosstalk from reflections, and noise interference even with a significant increase in bus wiring length, thus ensuring the accuracy and stability of transmitted signals. Furthermore, when expanding, the hierarchical identification pin of the newly added repeater can be directly set; the controller can directly identify the hierarchical code, allowing for on-demand expansion and high hardware adaptability.

[0036] Method 2: Identify the level signal status of the layer identification pins on the target board. Based on the level signal status of the layer identification pins on the target board, determine the layer code of the target board.

[0037] Specifically, when the target board is directly connected to the controller, the target board can be equipped with multiple level identification pins. After power-on, the combination of the level signals of the multiple level identification pins can indicate its own level code.

[0038] Taking the target board as an example, the controller can identify the status of the level signals of the identification pins of each level of the target board, and then combine the status of the level signals of the identification pins of each level of the target board into a code, and determine the code as its own level code.

[0039] In this way, resources can be saved when the cascading hierarchy is low.

[0040] In some alternative implementations, in step S103 above, the bus address can be allocated in the following manner: Step 1: Determine the number of levels in the address allocation system based on the level codes corresponding to at least one board.

[0041] Step 2: Based on the number of levels, divide the preset bus address range into multiple sub-address ranges, which is the same number as the number of levels.

[0042] Step 3: Assign a sub-address range to a board corresponding to a certain level.

[0043] Step 4: Based on the target sub-address range, the device type and mounting order of the service devices mounted on the target board, assign a bus address to each service device mounted on the target board.

[0044] The target sub-address range is the sub-address range allocated to the target board.

[0045] Specifically, in step one, the controller can count the number of acquired hierarchical codes, and then determine the number of hierarchical codes as the number of cascaded levels included in the address allocation system.

[0046] In step two, the controller can count the total number of addresses within a preset bus address range, then calculate the ratio between the total number of addresses and the number of levels, and round down to obtain the number of sub-addresses. Then, the controller can divide the bus address range into consecutive address ranges equal to the number of sub-addresses, according to the hierarchical encoding from low to high.

[0047] Optionally, in step two, for each cascade level, the target number of service devices connected to the board under the cascade level can be counted first, and a sub-address range containing the target number of consecutive addresses can be selected from the free addresses in the bus address range that have not been allocated to other boards.

[0048] In step three, the sub-address range can be directly allocated to the corresponding board.

[0049] In step four, for any given board, the device type and mounting order can indicate the uniqueness of the service device on the board. Therefore, the address of the target sub-address range can be allocated to each service device mounted on the board according to the device type and mounting order of each service device mounted on the board.

[0050] In this way, dividing the sub-address ranges by level can avoid address conflicts between different cascaded levels. Then, within the sub-address ranges, allocation is made according to device type and mounting order. The allocation logic is simple and can ensure the uniqueness of the bus address of the service device within the board, avoiding address conflicts between service devices at the same level.

[0051] In some alternative implementations, in step two above, the sub-address ranges of each cascade level can also be determined in the following way: The maximum number of cascading levels in the address allocation system is determined. Based on this maximum number of cascading levels, the bus address range is divided into multiple sub-address ranges, the same number as the maximum number of cascading levels. Each sub-address range is assigned to a cascading level. This ensures that the sub-address ranges of different cascading levels do not overlap. Consequently, when allocating bus addresses to service devices on a target board, the corresponding target sub-address range can be directly obtained based on the target board's level code.

[0052] In this way, each cascade level can have a fixed sub-address range. After adding a new board, there is no need to search for free addresses. Instead, the corresponding sub-address range can be directly obtained to perform the address allocation operation, which is more efficient.

[0053] In some optional implementations, in step four above, allocating a bus address to each service device connected to the target board based on the target sub-address range, the device type of the service device connected to the target board, and the connection order may include: Step 1: When multiple service devices are mounted on the target board, identify the service device group with the same device type among the multiple service devices mounted on the target board.

[0054] Step 2: Identify the unallocated free addresses within the target sub-address range.

[0055] Step 3: Based on the mounting order of the multiple service devices included in the service device group, allocate incrementally increasing free addresses to the multiple service devices in the service device group in sequence.

[0056] Specifically, if the target board has only one service device, an address from the target sub-address range (e.g., the first address, or a randomly selected address) can be assigned to that service device. If the target board has multiple service devices, the controller can first group the service devices on the target board according to their device types, assigning service devices of the same type to the same group. For example, temperature sensors can be grouped into one service device group, thus obtaining one or more service device groups.

[0057] In addition, each time the controller allocates a bus address, it can set the status of that bus address to allocated. Addresses that are not set to allocated are considered free addresses. In this way, before allocating a bus address each time, the unallocated free addresses in the target sub-address range can be determined.

[0058] For any group of service devices, free addresses in the target sub-address range can be allocated to the service device in order of mounting from smallest to largest. For example, if the mounting order of multiple service devices is 2, 3, and 4, then addresses 1, 2, and 3 can be allocated to these three service devices in ascending order.

[0059] In this way, for any given board, service devices of the same type can be assigned a unique bus address, avoiding address conflicts. Furthermore, since addresses for devices of the same type are assigned consecutively, technicians can quickly pinpoint the malfunctioning device when troubleshooting anomalies.

[0060] In some alternative implementations, step S103 above can also allocate the bus address in the following manner: For any target service device, a unique code can be obtained by concatenating the hierarchical code and mounting order of its associated board. The controller can set a mapping relationship between the unique code and the bus address, and then determine the corresponding bus address based on the unique code in the mapping relationship and allocate the bus address to the target service device.

[0061] In this way, hierarchical coding can indicate the uniqueness of the board, and the mounting order can indicate the uniqueness of the service device within the board. Therefore, the corresponding bus address determined based on this is also globally unique. Furthermore, this method is relatively simple.

[0062] In some alternative implementations, step S103 above can also allocate the bus address in the following manner: Step 1: Determine the number of levels in the address allocation system based on the level codes corresponding to at least one board.

[0063] Step 2: Based on the number of levels, divide the preset bus address range into multiple sub-address ranges, which is the same number as the number of levels.

[0064] Step 3: Assign a sub-address range to a board corresponding to a certain level.

[0065] Step 4: Based on the target sub-address range and the device information of the service devices connected to the target board, assign a bus address to each service device connected to the target board.

[0066] Specifically, the detailed processing of steps one through three can be referred to the aforementioned description, and will not be repeated here. In step four, the controller can traverse the device information of the service devices attached to the target board. For each device information traversed, the smallest address among the unallocated free addresses in the target sub-address range is assigned to the service device corresponding to the currently traversed device information.

[0067] In some alternative implementations, based on the above embodiments, after step S103, the controller may further perform the following specific operations: An address mapping table is generated and stored based on the hierarchical code corresponding to at least one board, as well as the device information and bus address of the service devices attached to at least one board.

[0068] Specifically, for any given service device, the hierarchical code of the board on which the service device is located, the device information of the service device, and the assigned bus address can be determined as an entry. Then, based on the entries of all service devices, an address mapping table is generated and stored.

[0069] When the bus address of the target service device is needed in the future, the controller can determine the corresponding bus address in the address mapping table based on the device information of the target service device (e.g., the identification information of the target service device) and the hierarchical code of the board it is on.

[0070] In some alternative implementations, after step S103 described above, the following operations may also be performed: The original static addresses of the service devices mounted on at least one board are blocked.

[0071] Specifically, the controller can directly mask the original static addresses of each service device. For example, it can mark the original static addresses of each service device to prevent communication with the service device using the original static addresses.

[0072] In this way, devices mounted on different boards may come from different manufacturers and different batches, and their factory static addresses may be duplicated. By masking the original static addresses and using globally unique mapped addresses for communication, address conflict issues can be avoided.

[0073] In some alternative implementations, after determining that a board hot-plug event has occurred in the address allocation system, address management operations can be performed promptly. Accordingly, the controller can execute the following steps: In scenario one, after detecting that the first cascade level board has been removed, the first entry corresponding to the first cascade level in the address mapping table is deleted.

[0074] The first cascade level is any one of the multiple cascade levels included in the address allocation system. The first entry includes the level code of the first cascade level, the device information and bus address of the service device connected to the board of the target cascade level.

[0075] Specifically, after the controller detects that the state of the presence signal of the first slot changes from present to absent (e.g., from low level to high level), it can assume that the board in the first slot has been removed. At this time, the corresponding first cascade level can be determined according to the number of the first slot, and then the first entry of all the level codes containing the first cascade level in the address mapping table can be deleted according to the first cascade level.

[0076] Scenario 2: After detecting the insertion of a second-level cascade card, obtain the device information and mounting order of the service devices connected to the second-level cascade card. Identify the set of unallocated addresses in the bus address range, which includes one or more free addresses. Based on the address set, and the device information and mounting order of the service devices connected to the second-level cascade card, allocate bus addresses to the service devices connected to the second-level cascade card. Add the cascade level code, the device information, and the bus addresses of the service devices connected to the second-level cascade card to the address mapping table.

[0077] Specifically, the controller can determine that a board has been inserted into the second slot after detecting that the state of the presence signal in the second slot has changed from absent to present (e.g., from high level to low level). At this time, the corresponding second cascade level can be determined based on the slot number. Then, following a similar process to step S102, the device information and mounting order of the service devices connected to the board in the second cascade level are obtained. Following the address allocation method described in step S103 above, the bus addresses in the address set are allocated to the service devices connected to the board in the second cascade level. Finally, based on the cascade level's level code, the device information of the service devices connected to the board in the second cascade level, and the bus address, a new entry is generated and added to the address mapping table.

[0078] In some optional implementations, based on the above embodiments, the board inserted into the second slot can be a board that does not exist during the initial scan operation after power-on, i.e., a newly added board. If the second cascade level has already been allocated a sub-address range, the corresponding sub-address range can be obtained directly according to the cascade encoding of the second cascade level, and the bus address therein can be used as the aforementioned unallocated address set to allocate bus addresses for the service devices of the boards in the second cascade level.

[0079] In some alternative implementations, based on the above embodiments, the first slot and the second slot can be the same slot, that is, replacing a board at a certain cascade level. Accordingly, the controller can perform the following operations: Step 1: After detecting that the target cascade level board has been removed, delete the target entry corresponding to the target cascade level in the address mapping table.

[0080] The target cascading level is any one of the multiple cascading levels included in the address allocation system. The target entry includes the level code of the target cascading level, the device information of the service devices connected to the board of the target cascading level, and the bus address.

[0081] Step 2: After detecting the re-insertion of the board in the target cascade layer, re-acquire the device information and mounting order of the service devices mounted on the board in the target cascade layer.

[0082] Step 3: Based on the sub-address range of the target cascade level, the device type and mounting order of the service devices mounted on the target cascade level boards, reallocate bus addresses to the service devices mounted on the target cascade level boards.

[0083] Step 4: Add the hierarchical code of the target cascade level, the device information and bus address of the service devices connected to the target cascade level board to the address mapping table.

[0084] Specifically, the controller can determine that a card in the target slot has been removed after detecting a change in the state of the target slot's presence signal from present to absent (e.g., from low to high). At this point, the controller can determine the corresponding target cascading level based on the target slot and delete all entries in the address mapping table that contain the target cascading level. Furthermore, the controller can retain the sub-address range corresponding to the target cascading level for a first preset duration to prevent it from being occupied by other service devices, and then release it after the first preset duration to ensure sufficient address space when adding new cards.

[0085] Within the first preset time after the target slot is determined to have a board removed, if the status of the target slot's presence signal changes from "not in" to "in", it is considered that the board in the target slot has been inserted, i.e., a hot-plug event has occurred in the target slot. At this time, the service devices attached to the target cascade level boards can be scanned again according to step S102 to obtain the device information and mounting order of the service devices attached to the target cascade level boards. The sub-address range corresponding to the target cascade level is then reassigned to the board. Based on the sub-address range, the target cascade level, and the device information and mounting order of each service device attached to the board, a bus address is assigned to the service device. For details, please refer to the description of step S103 above, which will not be repeated here.

[0086] This allows for the establishment of stable communication with a new configuration without server downtime or restart. When replacing a board, there's no need to search for free sub-addresses again; instead, the bus address within the originally allocated sub-address range can be directly allocated, resulting in higher efficiency.

[0087] In some alternative implementations, to avoid the problem of bus addresses being reclaimed when service devices are temporarily offline or malfunction (i.e., in an abnormal state), and the need to reallocate addresses after they come back online or return to normal, the controller can also directly perform the following operations: If the target service device is detected to be in an abnormal state, the bus address of the target service device will be marked as the target state.

[0088] The target status can be used to indicate the bus address of the target service device to be reserved. The target service device can be any service device mounted on any board.

[0089] Specifically, the controller can periodically send detection commands to the service devices corresponding to each bus address included in the address mapping table. If a response is received, the corresponding service device is considered online; if no response is received, the corresponding service device is considered offline or has malfunctioned. Alternatively, a service device can also proactively send a target signal to the controller when it malfunctions. Upon receiving the target signal, the controller can determine that the corresponding service device has malfunctioned.

[0090] At this point, the controller can mark the bus address corresponding to the service device in the address mapping table as a target state. This indicates that the bus address of the target service device should be retained to prevent it from being reclaimed. Once the service device returns to online or normal operation, the target state can be removed, and the bus address can continue to be used to communicate with the service device without needing to reallocate a bus address for a newly added service device. Alternatively, if the target service device is not detected to have recovered within a second preset time period after its bus address has been marked as a target state, the entry corresponding to the target service device can be directly removed from the address mapping table, indicating that the target service device has been deleted.

[0091] This can improve communication efficiency.

[0092] In some alternative implementations, based on the above embodiments, the controller may also perform the following operations: Step 1: After detecting the addition of a new service device to the target board, obtain the device information of the new service device.

[0093] Step 2: Based on the device information of the newly added service device, the hierarchical code of the target board, and the address mapping table, determine whether the newly added service device is the target service device that has been restored to normal status.

[0094] Step 3: If the newly added service device is determined to be the target service device, cancel the target status of the bus address of the target service device.

[0095] Step 4: If it is determined that the newly added service device is not the target service device, allocate the unallocated free addresses in the target sub-address range to the newly added service device.

[0096] Step 5: Add the target board's hierarchical code, as well as the device information and bus address of the newly added service device, to the address mapping table.

[0097] Specifically, after detecting that the presence signal of the third slot on the target board changes from absent to present, it can be determined that a new service device has been inserted into the third slot. At this point, the newly added service device may have been previously offline or faulty. The device information of the newly added service device can be read first, and it can be determined whether the device information of the new service device exists in the address mapping table, and whether a target entry matching the hierarchical code of the board containing the new service device is found, and whether the bus address in the target entry is marked as a target status. If so, the target status can be directly canceled to indicate that the new service device is being generated and used. If not, it can be considered that the newly added service device is not a target service device that has been restored to normal. In this case, the smallest unallocated free address in the sub-address range corresponding to the target board can be selected and allocated to the new service device. Finally, based on the hierarchical code of the board, the device information of the new service device, and the bus address, a new entry can be generated and added to the address mapping table.

[0098] The following example will illustrate the execution process of the address allocation method described above in detail.

[0099] like Figure 2 As shown, firstly, the BMC performs a hierarchical scan to read the hierarchical codes of each repeater level. Then, it performs a traversal scan of the bus devices to obtain the device information of each service device. Further, the BMC can assign bus addresses to each service device based on the hierarchical code, device information, and mounting order. Finally, an address mapping table can be generated. The BMC can then communicate with the bus devices using the bus addresses in the address mapping table.

[0100] In addition, the BMC can monitor the real-time status of service devices. Upon detecting an offline service device, it can mark the device and retain its bus address. After adding a new service device, a bus address can be assigned, and the address mapping table can be updated. After removing a board, the corresponding entry in the address mapping table is deleted. After inserting a board, the bus address is rescanned and reassigned, and the address mapping table is updated.

[0101] Embodiments of this application also provide a controller, such as Figure 3As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the above-described address allocation method embodiments.

[0102] Embodiments of this application also provide an address allocation system, such as Figure 4 As shown, the address allocation system may include a controller and at least one board, which can be used to mount one or more service devices.

[0103] The controller can be a BMC (Browser Control Center) that executes the address allocation method steps in any of the above embodiments. The controller can be located on the motherboard; for example, it can be the BMC that originally performs management operations on the motherboard. Alternatively, it can be a newly added BMC on the motherboard specifically for performing address allocation operations, avoiding impact on the original BMC services. Alternatively, a main control backplane can be set up in the first cascade level, with a BMC specifically configured on the main control backplane to perform address allocation operations. This reduces the motherboard design workload, increases the number of downlink service devices, and enhances scalability. Correspondingly, after completing the address allocation operation, the address mapping table can be sent to the BMC on the motherboard so that the BMC can communicate with each service device based on the information in the address mapping table.

[0104] The board can be various types of backplanes, such as main control backplanes, expansion backplanes, etc., and the attached business devices can be fan controllers, temperature sensors, storage devices, monitoring devices, etc.

[0105] The controller is connected to multiple boards, for example, each board is connected to the controller via an I2C bus.

[0106] In the address allocation system of this application, the controller first identifies the hierarchical code of each board, and then obtains the device information and mounting order of the service devices connected to each board. Then, based on the hierarchical codes corresponding to multiple boards, and the device information and mounting order of the service devices connected to each board, a bus address is allocated to each service device. Since the hierarchical code of the board indicates its uniqueness in the address allocation system, and the device information and mounting order both indicate the uniqueness of the service device within the board, allocating addresses to service devices based on the hierarchical code, device information, and mounting order ensures that the bus addresses of different service devices on different boards are unique, thus avoiding address conflicts. Furthermore, this solution eliminates the need to program the addresses of each service device onto the board, thereby eliminating the need for manual configuration, resulting in higher efficiency and avoiding errors caused by manual configuration.

[0107] In some alternative implementations, such as Figure 5As shown, the address allocation system also includes at least one repeater, which is connected to a board, and the at least one repeater is connected to the controller to realize the connection between the controller and at least one board.

[0108] When there are multiple repeaters, they are connected in series on the bus, which is connected to the controller. Repeaters can be used to interface with the buses of upper-level and lower-level boards, achieving isolation of bus signals, eliminating signal crosstalk and attenuation caused by cascading, and ensuring signal stability.

[0109] The repeater includes a signal buffer and a signal conditioning circuit. The signal buffer can be used to isolate the load, and the signal conditioning circuit can be used to repair, amplify, etc., the signal. The repeater can be deployed in the board it is connected to; for example, repeater 1 can be located in board 1. Alternatively, the repeater can be a separate circuit, connected to the board and controller separately, outside the board. When used as a separate circuit with different boards, the number of components on the board can be reduced, costs can be saved, and scalability can be increased.

[0110] In some alternative implementations, the controller is located on the lowest cascaded board among multiple boards, which is directly connected to the controller. The other boards in the multiple cascaded boards, excluding the lowest cascaded board, are connected to the controller via repeaters.

[0111] Specifically, a master control backplane can be added to the first cascading level added to the server, such as... Figure 6 The primary controller backplane shown has a dedicated controller on it that performs address allocation. This eliminates the need to utilize the resources of the controller on the motherboard. Furthermore, the controller can directly connect to the lowest cascade level board without requiring a repeater, saving hardware costs. Other boards further from the motherboard controller on the bus can connect to the motherboard controller via repeaters to avoid inaccurate information transmission caused by signal attenuation and interference.

[0112] In some alternative implementations, it can be pre-specified that when the cascading level is less than or equal to a preset cascading level (e.g., the first cascading level, the second cascading level), no repeater is set, and instead, the board and controller are directly connected. When the cascading level is greater than the preset cascading level, a repeater is set at that cascading level. Figure 6 As shown in the address allocation system, the primary control backplane can be directly connected to the controller without needing to connect to the controller through a repeater.

[0113] In this way, for cascaded levels that are close to the controller, the signal error is small, and repeaters are not needed. However, for boards that have been cascaded through multiple layers, the signal error increases, and repeaters can be set up to ensure the accuracy of the signal.

[0114] In some alternative implementations, each repeater may include a hierarchy identification pin, and correspondingly, a controller, specifically for: The status of the level identification pins in the target repeater is identified, where the target repeater is a repeater connected to the target board in the address allocation system. Based on the status of the level identification pins in the target repeater, the level code of the target board is determined.

[0115] Specifically, when the target board is connected to the controller via a repeater, the repeater can be equipped with multiple level identification pins. After power-on, the combination of the level signals of these pins indicates the level code of the connected board. For example, if there are 3 level identification pins and the combination of their level signals is "010", then the corresponding level code of the board is 2. Taking the target board as an example, the level signals of each level identification pin in the target repeater can be identified. Then, the level signals of each level identification pin in the target repeater can be combined into a binary code, which is then converted to decimal to obtain the level code of the target board.

[0116] In some alternative implementations, each board may include a hierarchy identification pin. Accordingly, the controller is specifically used for: Identify the level signal status of the target board's level identification pins. Determine the target board's level code based on the level signal status of the target board's level identification pins.

[0117] Specifically, when the target board is directly connected to the controller, the target board can be equipped with multiple level identification pins. After power-on, the combination of the level signals of these multiple level identification pins can indicate its own level code. Taking the target board as an example, the controller can identify the level signal status of each level identification pin on the target board, and then combine the level signal status of its own level identification pins into a code, which is then determined as its own level code.

[0118] For example, the internal logic of a cascaded hierarchy can be as follows: Figure 7 As shown, repeaters or boards can provide hierarchical coding, and monitoring devices, sensors, memory, etc. can be connected to the board via the I2C bus, from which device information can be read.

[0119] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0120] Embodiments of this application also provide an address allocation device, such as... Figure 8 As shown, it includes: The identification module 810 is used to identify the hierarchical encoding of the cascaded layers corresponding to at least one board in the address allocation system. The acquisition module 820 is used to acquire the device information and mounting order of the service devices respectively mounted under the target board according to the hierarchical code of the target board, wherein the target board is any one of at least one board; The allocation module 830 is used to allocate bus addresses to the service devices connected to at least one board according to the hierarchical code corresponding to at least one board, and the device information and / or mounting order of the service devices connected to at least one board.

[0121] In some alternative implementations, the identification module 810 is specifically used for: Identify the level signal status of the hierarchical identification pin in the target repeater, where the target repeater is the repeater connected to the target board in the address allocation system; The hierarchical encoding of the target board is determined based on the level signal of the hierarchical identification pin in the target repeater.

[0122] In some alternative implementations, the identification module 810 is specifically used for: Identify the level signal status of the pins of the target board's hierarchy; The layer code of the target board is determined based on the state of the level signal of the layer identification pin of the target board.

[0123] In some optional implementations, the device information includes the device type; the allocation module 830 is specifically used for: The number of levels in the address allocation system is determined based on the level code corresponding to at least one board. Based on the number of levels, the preset bus address range is divided into multiple sub-address ranges, which are equal to the number of levels. Assign a sub-address range to a board corresponding to a certain level; Based on the target sub-address range, the device type and mounting order of the service devices mounted on the target board, bus addresses are assigned to the service devices mounted on the target board. The target sub-address range is the sub-address range assigned to the target board.

[0124] In some alternative implementations, the allocation module 830 is used for: When multiple service devices are mounted on the target board, service devices with the same device type are grouped into a service device group according to the device type of each service device mounted on the target board. Identify unallocated free addresses within the target sub-address range; Based on the mounting order of the multiple service devices included in the service device group, incrementally increasing free addresses are allocated to the multiple service devices in the service device group in sequence.

[0125] In some alternative implementations, the apparatus further includes a generation module for: An address mapping table is generated and stored based on the hierarchical code corresponding to at least one board, as well as the device information and bus address of the service devices attached to at least one board.

[0126] In some alternative implementations, the device further includes a shielding module for: The original static addresses of the service devices mounted on at least one board are blocked.

[0127] In some alternative implementations, the device further includes a detection module for: After detecting that the target cascade level board has been removed, the target entry corresponding to the target cascade level in the address mapping table is deleted. The target cascade level is any one of the multiple cascade levels included in the address allocation system. The target entry includes the level code of the target cascade level, the device information of the service device connected to the target cascade level board, and the bus address.

[0128] In some alternative implementations, the detection module is further configured to: After detecting the reinsertion of the board at the target cascade level, the device information and mounting order of the service devices attached to the board at the target cascade level are re-acquired. Based on the sub-address range of the target cascade level, the device type and mounting order of the service devices mounted on the target cascade level boards, the bus addresses are reassigned to the service devices mounted on the target cascade level boards. Add the hierarchical encoding of the target cascade level, the device information and bus address of the service devices connected to the target cascade level board to the address mapping table.

[0129] In some alternative implementations, the detection module is further configured to: If the target service device is detected to be in an abnormal state, the bus address of the target service device is marked as the target state. The target state is used to indicate that the bus address of the target service device is reserved. The target service device is any service device connected to any board in the address allocation system.

[0130] In some alternative implementations, the detection module is further configured to: After detecting a new service device on the target board, obtain the device information of the new service device; Based on the equipment information of the newly added service equipment, the hierarchical code of the target board, and the address mapping table, determine whether the newly added service equipment is the target service equipment that has been restored to normal status. If the newly added service device is determined to be the target service device, the target status of the bus address of the target service device is cancelled.

[0131] In some alternative implementations, the detection module is further configured to: If it is determined that the newly added service device is not the target service device, the unallocated free addresses in the target sub-address range will be allocated to the newly added service device. Add the target board's hierarchical encoding, as well as the device information and bus address of the newly added service device, to the address mapping table.

[0132] For a description of the features in the embodiment corresponding to the address allocation device, please refer to the relevant description in the embodiment corresponding to the address allocation method, which will not be repeated here.

[0133] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described address allocation method embodiments when it is run.

[0134] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0135] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described address allocation method embodiments.

[0136] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described address allocation method embodiments.

[0137] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (fixed logic circuit systems), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microcontroller unit (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination thereof. The aforementioned computer program (also known as a program, software, software application, App, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0138] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0139] The foregoing has provided a detailed description of the address allocation method, controller, system, apparatus, storage medium, and program product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An address allocation method, characterized in that, The method is executed by a controller in an address allocation system, and the method includes: Identify the hierarchical encoding of the cascaded hierarchy corresponding to at least one board in the address allocation system; Based on the hierarchical coding of the target board, obtain the device information and mounting order of the service devices respectively mounted under the target board, wherein the target board is any one of the boards; Based on the hierarchical code corresponding to at least one of the boards, and the device information and / or mounting order of the service devices mounted under at least one of the boards, a bus address is assigned to the service devices mounted under at least one of the boards.

2. The address allocation method according to claim 1, characterized in that, The step of identifying the hierarchical encoding of the cascaded levels corresponding to at least one board in the address allocation system includes: The state of the level signal of the hierarchical identification pin in the target repeater is identified, wherein the target repeater is the repeater connected to the target board in the address allocation system; The hierarchical encoding of the target board is determined based on the state of the level signal of the hierarchical identification pin in the target repeater.

3. The address allocation method according to claim 1, characterized in that, The step of identifying the hierarchical encoding of the cascaded levels corresponding to at least one board in the address allocation system includes: Identify the state of the level signal of the layer identification pin of the target board; The layer code of the target board is determined based on the state of the level signal of the layer identification pin of the target board.

4. The address allocation method according to any one of claims 1 to 3, characterized in that, The device information includes the device type; the process of allocating bus addresses to the service devices connected to at least one of the boards based on the hierarchical codes corresponding to at least one of the boards, and the device information and / or mounting order of the service devices connected to at least one of the boards, includes: The number of levels in the address allocation system is determined based on the level code corresponding to at least one of the aforementioned boards. Based on the number of levels, the preset bus address range is divided into multiple sub-address ranges, which are equal to the number of levels. Assign one of the sub-address ranges to a board corresponding to a level; Based on the target sub-address range, the device type and mounting order of the service devices mounted on the target board, a bus address is allocated to the service devices mounted on the target board, wherein the target sub-address range is the range to which the service devices are allocated.

5. The address allocation method according to claim 4, characterized in that, The step of allocating bus addresses to the service devices connected to the target board based on the target sub-address range, the device type and connection order of the service devices connected to the target board includes: When the target board is equipped with multiple service devices, the service devices with the same device type are divided into a service device group according to the device type of each service device. Identify the unallocated free addresses within the target sub-address range; Based on the mounting order of the multiple service devices included in the service device group, incrementally increasing free addresses are allocated to the multiple service devices in the service device group in sequence.

6. The address allocation method according to claim 5, characterized in that, After allocating bus addresses to the service devices connected to at least one of the boards based on the hierarchical codes corresponding to at least one of the boards, and the device information and connection order of the service devices connected to at least one of the boards, the method further includes: An address mapping table is generated and stored based on the hierarchical code corresponding to at least one of the boards, and the device information and bus address of the service devices respectively attached to at least one of the boards.

7. The address allocation method according to any one of claims 1 to 3, characterized in that, After allocating bus addresses to the service devices connected to at least one of the boards based on the hierarchical codes corresponding to at least one of the boards, and the device information and connection order of the service devices connected to at least one of the boards, the method further includes: The original static addresses of at least one of the service devices mounted on the aforementioned board are blocked.

8. The address allocation method according to claim 6, characterized in that, The method further includes: After detecting that the target cascade level board has been removed, the target entry corresponding to the target cascade level in the address mapping table is deleted. The target cascade level is any one of the multiple cascade levels included in the address allocation system. The target entry includes the level code of the target cascade level, the device information of the service device connected to the board of the target cascade level, and the bus address.

9. The address allocation method according to claim 8, characterized in that, The method further includes: After detecting the reinsertion of the board in the target cascade layer, the device information and mounting order of the service devices attached to the board in the target cascade layer are re-acquired. Based on the sub-address range of the target cascade level, the device type and mounting order of the service devices mounted on the boards of the target cascade level, the bus address is reassigned to the service devices mounted on the boards of the target cascade level. The hierarchical encoding of the target cascade level, the device information and bus address of the service devices connected to the board under the target cascade level are added to the address mapping table.

10. The address allocation method according to claim 6, characterized in that, After generating and storing an address mapping table based on the hierarchical encoding corresponding to at least one of the boards, and the device information and bus address of the service devices respectively connected to at least one of the boards, the method further includes: If the target service device is detected to be in an abnormal state, the bus address of the target service device is marked as the target state. The target state is used to indicate that the bus address of the target service device is reserved. The target service device is any service device connected to any board in the address allocation system.

11. The address allocation method according to claim 10, characterized in that, The method further includes: After detecting the addition of a new service device to the target board, obtain the device information of the new service device; Based on the device information of the newly added service device, the hierarchical code of the target board, and the address mapping table, determine whether the newly added service device is the target service device that has been restored to normal status; If the newly added service device is determined to be the target service device, the target status of the bus address of the target service device is cancelled.

12. The address allocation method according to claim 11, characterized in that, The method further includes: If it is determined that the newly added service device is not the target service device, the unallocated free address in the target sub-address range will be allocated to the newly added service device; The hierarchical encoding of the target board, as well as the device information and bus address of the newly added service device, are added to the address mapping table.

13. A controller, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the address allocation method as described in any one of claims 1 to 12 when executing the computer program.

14. An address allocation system, characterized in that, The address allocation system includes a controller and at least one board, the board being used to mount one or more service devices, and the controller being connected to at least one of the boards respectively; The controller is configured to perform the steps of the address allocation method as described in any one of claims 1 to 12.

15. The address allocation system according to claim 14, characterized in that, The address allocation system further includes at least one repeater, which is connected to one of the boards, and at least one of the repeaters is connected to the controller to realize the connection between the controller and at least one of the boards.

16. The address allocation system according to claim 15, characterized in that, When there are multiple repeaters, the multiple repeaters are connected in series on a bus, and the bus is connected to the controller.

17. The address allocation system according to claim 15 or 16, characterized in that, The repeater is deployed in a board connected to it.

18. The address allocation system according to claim 16, characterized in that, The controller is located on the lowest cascaded board among the plurality of boards. The lowest cascaded board is directly connected to the controller. The other boards in the plurality of boards, excluding the lowest cascaded board, are all connected to the controller through repeaters.

19. The address allocation system according to claim 15 or 16, characterized in that, The repeater includes a hierarchy identification pin; The controller is specifically used for: The state of the level signal of the hierarchical identification pin in the target repeater is identified, wherein the target repeater is the repeater connected to the target board in the address allocation system; The hierarchical encoding of the target board is determined based on the state of the level signal of the hierarchical identification pin in the target repeater.

20. The address allocation system according to claim 15 or 16, characterized in that, The board includes a hierarchy identification pin; The controller is specifically used for: Identify the state of the level signal of the layer identification pin of the target board; The layer code of the target board is determined based on the state of the level signal of the layer identification pin of the target board.

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