Method for decoding a serial protocol signal without a synchronization pattern

Abstract

A method for decoding serial protocol signals without a synchronization pattern. A test and measurement instrument that can identify a bypassed control block within data during a capture interval is described. Further, the test and measurement instrument can determine a state value of a linear feedback shift register (LFSR) based on the bypassed control block and a location of the bypassed control block within the capture interval. The test and measurement instrument can determine an LFSR state corresponding to an earlier location in the capture interval based on the state value of the LFSR and the location of the bypassed control block by accounting for a relative positional relationship within the data. Further, the test and measurement instrument can use the LFSR state corresponding to the earlier location in the capture interval to de-scramble at least a portion of the data to generate decoded data for data preceding the bypassed control block.

Description

[0001] Cross-references to related applications This disclosure claims priority to Indian Provisional Patent Application No. 202521041012, filed April 28, 2025, entitled “method for Decoding Serial Protocol Signals Without Sync Patterns”, which is incorporated herein by reference in its entirety, pursuant to 35 USC §119. Technical Field

[0002] Examples of this disclosure generally relate to high-speed serial communication systems, and particularly to efficient data decoding and synchronization techniques for high-speed serial communication. Background Technology

[0003] High-speed serial protocols are communication protocols that transmit data at high data rates through serial interfaces. These protocols are commonly used for communication between electronic devices such as computers, servers, and networked equipment.

[0004] The key advantages of these serial communication protocols are reliable communication, low latency, and high bandwidth, making them ideal for high-performance computing applications. Different high-speed protocol standards on the market include Universal Standard Bus (USB), Fast Peripheral Component Interconnect (PCI), Serial Advanced Technology Accessories (SATA), High Definition Multimedia Interface (HDMI), and Ethernet.

[0005] To increase bandwidth to support higher data rates, high-speed serial standards employ different line codes and data formats, such as 8b / 10b, 64b / 66b, 128b / 130b, and 128b / 132b. Attached Figure Description

[0006] To gain a more detailed understanding of the features described above, please refer to the example implementations (briefly outlined above), some of which are illustrated in the accompanying figures. However, it should be noted that the accompanying figures only illustrate typical example implementations and should not be considered as limiting their scope.

[0007] Figure 1 The test and measurement instruments in the test setup are shown, which use probes to receive data from the device under test (DUT).

[0008] Figure 2 The different states of data transmission in Universal Serial Bus (USB) 3.2 Gen 2 are shown.

[0009] Figure 3This illustrates different states of data transfer in USB 3.2 Gen 2 using a 23-bit scrambler on the transmitter side.

[0010] Figure 4 The illustration shows a flowchart of a proposed solution for decoding data from the start of acquisition after the SKP control block is detected, implemented according to an exemplary embodiment of the present disclosure.

[0011] Figure 5 and Figure 6 The illustration shows a plotted image of the decoded data for idle mode after applying the proposed solution, as exemplarily implemented according to this disclosure.

[0012] For ease of understanding, the same reference numerals have been used where possible to designate common elements in the various figures. It is envisioned that elements of one example can be beneficially incorporated into other examples. Detailed Implementation

[0013] Various features are described below with reference to the figures. It should be noted that the figures may or may not be drawn to scale, and throughout the figures, elements with similar structures or functions are indicated by the same reference numerals. It should be noted that the figures are intended only to facilitate the description of features. They are not intended as an exhaustive description of the specification or a limitation on the scope of the claims. Furthermore, the illustrated examples do not need to possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so illustrated or explicitly described.

[0014] This disclosure relates to advanced methods and systems for decoding and synchronizing high-speed serial protocol data streams, particularly where conventional synchronization modes may be missing or compromised. As modern serial communication protocols continue to increase in speed and complexity, maintaining reliable synchronization between transmitters and receivers is both crucial and challenging. To address these challenges, the disclosed techniques provide mechanisms for robust and flexible decoding of serial data without exclusively relying on conventional synchronization modes. This invention supports improved system reliability and a wider range of applications by enabling accurate data recovery even when explicit synchronization cues are unavailable. The following detailed description, supported by illustrative figures and exemplary implementations, outlines the structure, processes, and advantages associated with the proposed solution, highlighting its applicability to high-speed protocols such as USB and PCIe.

[0015] This document describes test and measurement instruments and methods for descrambling and decoding Universal Serial Bus (USB) 3.2 Gen 2 waveforms after the standard-defined link initialization and training process. The embodiments demonstrate the decoding and synchronization of high-speed serial protocol data streams. The following discussion focuses on USB 3.2 Gen 2; however, the embodiments described herein can be applied to future USB standards or other serial data communication protocols. Therefore, the standard will be referred to as USB 3.2 gen 2, and subsequent USB versions will be referred to as "USB 3.X".

[0016] Figure 1 An example scenario is illustrated in which USB communication may require descrambling (also referred to as decoding). Test and measurement instrument 10 is connected to test fixture 14, which in turn is connected to computing device 28 and storage device 26. This connection may involve one or more probes on the test fixture. Although both are referred to as DUTs, the descrambling operation applies to either computing device 28 or storage device 26 where data is being transmitted. Test fixture 14 transmits USB data through one or more channels 16 on test and measurement instrument 10. In some embodiments, test fixture 14 may include probes. As discussed above, the embodiments herein will typically use only one probe and one channel of test and measurement instrument 10, but more can be used.

[0017] Data from test fixture 14, if analog, is converted to digital by one or more analog-to-digital converters (ADCs), such as ADC 20. ADC 20 converts analog data into digital data for operation on the digital data by one or more processors, such as processor 24. If the received data includes digital data, the digital data may not need to pass through ADC 20. Test and measurement instrument 10 may include memory 22 to allow the one or more processors 24 to store digital and analog data, and may contain code to be executed by the one or more processors 24. User interface 18 allows test and measurement instrument 10 to display at least the obtained current measurement to a user, and may include controls such as buttons, knobs, sliders, trackballs, etc., to allow the user to perform operations on incoming signals, etc.

[0018] Currently, the USB 3.2 Gen2 standard implements link initialization and training modes to negotiate and establish links. For both modes, different training sequences are sent on the bus to negotiate / establish the link. Figure 2 At position 30, the sequence begins with a low-frequency pulse stimulus (LFPS). Training sequences TSEQ 32, TS1 34, and TS2 36 appear to train the link between USB device 26 and the computing device 28 to which it is connected, such as... Figure 1 As shown in the diagram. After the training sequence, the SYNC signal at position 38 indicates the data transmission (SDS) at position 40.

[0019] The problem arises along with the baseband signal because, although the training sequence involves sending consecutive 1s or 0s, electromagnetic induction (EMI) and peak emissions across the connection lines can cause errors. Therefore, data scrambling is used to reduce EMI or peak emissions.

[0020] In USB 3.2 Gen 2, data scrambling involves using a 23-bit scrambler on the transmitter side to overcome EMI using 128b / 132b encoding before the final data has been sent to the receiver. The terms "descrambling" and "decoding" are used interchangeably in this discussion, referring to the process of converting scrambled data into unscrambled data that is recognizable by the receiver.

[0021] Figure 3 A block diagram depicting the different steps involved in decoding a USB 3.2 Gen2 signal is shown. The first step of signal decoding occurs at 42, where the Gen2 signal operates at 10 Gbps (gigabits per second), and the received data contains 132 bits, with a 4-bit block identifier being either a control (1100) or data (0011) block, which is pre-set to 16 symbols (128 bits) to create 128b / 132b line encoding.

[0022] At position 44, the descrambler uses a 23-bit polynomial for data descrambling. This polynomial can be expressed as: X 23 + X 21 + X 16 + X 8 + X 5 + X 2 +1.

[0023] The descrambler logic uses the aforementioned Linear Feedback Shift Register (LFSR), a 23-bit register. The initial state of the LFSR is 0x1dbfbc. For descrambling and creating the bitstream at position 46, there are specific rules followed by 3.2 Gen2 communication, and the bitstream is then decoded and packed at position 48.

[0024] For high-speed protocols, some ordered blocks, such as TS1 and TS2 (1-13 symbols), each containing 16 symbols, are scrambled, while the remaining blocks, such as SKP, SYNC, FTS, SDS, and EIEOS, are bypassed.

[0025] Achieving high-speed decoding requires establishing synchronization, which means obtaining the scrambler key and using it to extract data from the encrypted data, and then decoding the extracted data. Decoding of the encrypted data cannot begin until the scrambler key is extracted from the incoming signal. To extract the scrambler key, the high-speed protocol defines a SYNC mode after the training sequence. During communication, an SKP sequence set is sent every forty (40) blocks for clock compensation, data alignment (by sending LFSR states together), and error prevention. The LFSR states can be used to re-acquire block alignment in the middle of the bitstream.

[0026] Since tracing tools cannot force the link into recovery, they can reacquire bit locks if needed and monitor the SKP ordered set to obtain block alignment and perform inter-channel de-skewing. The LFSR value from the SKP 5 ordered set can be loaded into its LFSR to begin interpreting the bitstream. It must be noted that, using the bitstream, one might alias the SKP ordered set at non-block boundaries. Tracing tools can verify their block alignment using implementation-specific means, such as receiving a fixed number of valid packets or sync headers or subsequent SKP ordered sets, as shown in Table 1 below.

[0027] However, synchronizing the Linear Feedback Shift Register (LFSR) in the ordered set of the SKP presents specific challenges due to the need for precise alignment and initialization to ensure correct data decoding. As previously mentioned, SKP symbols are used to re-acquire block alignment in the middle of the bitstream. Synchronization is required to decode the acquired data. In high-speed protocols such as USB and PCIe, the following mechanisms can be used for synchronization.

[0028] A synchronization mechanism involves the SYNC and EIEOS symbols. Here, the LFSR is initialized to its initial value. Decoding begins using this LFSR value.

[0029] Another synchronization mechanism involves obtaining an SKP symbol containing the seed value of the LFSR state for the last three symbols. This LFSR state can then be used to begin decoding. For example, in USB 3.2 Gen 2, training sequences such as TS1 and TS2 contain scrambled symbols. Decoding these scrambled symbols involves searching for the SKP symbol. Once the SKP symbol is received, the LFSR key is read.

[0030] However, decoding only begins after synchronization with SKP. Before synchronization, no data, regardless of its existence, can be decoded.

[0031] This disclosure provides a solution that decodes data from the start of acquisition after detecting the SKP control block.

[0032] Figure 4 An embodiment of a method for decoding data from acquisition onwards after the detection of an SKP control block is illustrated. This method is typically implemented by one or more processors in a test and measurement instrument, configured to execute code embodying the method. This embodiment begins by receiving data from the DUT at point 50. In some embodiments, receiving data from the DUT involves reading symbols. The process attempts to determine at point 52 whether there are any more symbols and / or data to be acquired from the DUT. If acquisition is complete, the process ends at point 54.

[0033] However, if more data needs to be read from the DUT, at point 56, the process determines whether the symbol read from the DUT is an SKP block. If the read symbol is not an SKP block, the process returns to point 50 to continue reading symbols from the DUT. At this point in the process, the test and measurement instruments are searching for a control header, followed by an SKP block of size 4*N + 3 (where N can be 1 to 5).

[0034] If the read symbol is an SKP block, the process continues to 58, where the process obtains the current seed. In some embodiments, the current seed can be determined by reading the last three symbols of the SKP block, which is the LFSR value.

[0035] Furthermore, the process obtains the index (SKPIndex) of the SKP block at position 60. Once the SKP is found, the index of the SKP block involves obtaining the bit index of the start of the SKP block.

[0036] In some examples, getting the current seed and getting the SKP index can be interchanged, allowing getting the current seed and getting the SKP index to be performed in any order.

[0037] The process then involves determining the LFSR offset at 62 based on the SKP index and the current index. Determining the LFSR offset may involve calculating the LFSR offset to know the change in the LFSR value from the initial LFSR value (i.e., initial LFSR value: 0x1dbfbc). Based on the SKP index and the current index from the start of acquisition, the process involves calculating the LFSR state using the change in the LFSR value from the initial LFSR value (initial LFSR value: 0x1dbfbc).

[0038] The process then involves determining the symbol offset at 64. The symbol offset is the total number of symbols preceding the SKP block (based on the SKP block index). In some examples, the symbol offset may be based on the following equation: SymbolOffset = (SKPIndex – CurrentIndex) / 8.

[0039] The process involves determining the seed location at 64 based on the LFSR offset and symbol offset. In some examples, obtaining the seed value at the start of acquisition involves the following equation: SeedPos = Offset - SymbolOffset.

[0040] Once the seed location is determined, the process involves advancing the LFSR from its initial value to the seed location at point 66. Doing so gives the LFSR value at the start of acquisition. Advancing the LFSR can involve shifting / rotating the LFSR multiple times based on the difference between the seed location and the initial LFSR value, using a known LFSR value.

[0041] Once the LFSR is locked, the process can begin data decoding at position 68.

[0042] Figure 5 and Figure 6 The image of the entire acquired decoded data is presented in tabular format after applying the solution proposed above.

[0043] The advantage of this disclosed solution lies in the performance of the decoding solution, ensuring that no bits are lost during the acquisition process. The method is fast enough to complete the decoding because it uses the last three SKP symbols and then calculates the seed value.

[0044] This also decodes the data acquired before the SKP symbol. According to contention analysis, the decoder does not decode before the SKP symbol. No additional probing of the sideband signal is needed because the existing signal is used for seed extraction. This solution does not require additional channels for sideband signal, sideband data decoding, etc. Decoding performance is improved because the proposed solution does not rely on scrambled incoming symbol data used for seed extraction. The solution uses unscrambled SKP symbols.

[0045] According to this disclosure, the uniqueness of this solution lies in using SKP to decode the data from the beginning of acquisition.

[0046] Various aspects of this disclosure can operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers (including processors that operate according to programmed instructions). As used herein, the terms controller or processor are intended to include microprocessors, microcomputers, application-specific integrated circuits (ASICs), and special-purpose hardware controllers. One or more aspects of this disclosure can be embodied in computer-usable data and computer-executable instructions, such as one or more program modules executed by one or more computers (including monitoring modules) or other devices. Typically, program modules include routines, programs, objects, components, data structures, etc., which perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. Computer-executable instructions can be stored on non-transitory computer-readable media, such as hard disks, optical disks, removable storage media, solid-state storage, random access memory (RAM), etc. As those skilled in the art will appreciate, the functionality of program modules can be combined or distributed in various ways as desired. Furthermore, this functionality can be wholly or partially embodied in firmware or hardware equivalents, such as integrated circuits, FPGAs, etc. Specific data structures can be used to more efficiently implement one or more aspects of this disclosure, and such data structures are envisioned within the scope of the computer-executable instructions and computer-available data described herein.

[0047] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried or stored thereon on one or more non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, a computer-readable medium means any medium that can be accessed by a computing device. By way of example and not limitation, a computer-readable medium may include computer storage media and communication media.

[0048] Computer storage media means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) or other optical disc storage devices, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media does not include the signal itself or the temporary form of signal transmission.

[0049] Communication medium means any medium that can be used for computer-readable information communication. By way of example and not limitation, communication medium may include coaxial cable, fiber optic cable, air, or any other medium suitable for electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signal communication.

[0050] Example Illustrative examples of the disclosed technology are provided below. Embodiments of the technology may include one or more of the examples below, and any combination thereof.

[0051] Example 1 is a test and measurement instrument that may include: one or more channels for receiving data from a device under test (DUT) via a test fixture, the data being transmitted by the DUT according to a serial data communication protocol; and one or more processors configured to execute code that causes the one or more processors to: identify a bypassed control block within data during an acquisition interval; determine a state value of a linear feedback shift register (LFSR) based on the bypassed control block and its position within the acquisition interval; determine an LFSR state corresponding to an earlier position within the acquisition interval, based on the LFSR state value and the position of the bypassed control block, taking into account relative positioning within the data; and descramble at least a portion of the data using the LFSR state corresponding to the earlier position within the acquisition interval to generate decoded data prior to the data bypassed by the control block.

[0052] Example 2 is the test and measurement instrument of Example 1, wherein the serial data communication protocol may include Universal Serial Bus (USB) protocol 3_prd_x_prd_.

[0053] Example 3 is a test and measurement instrument of Example 1 or Example 2, wherein the bypassed control block may include the SKP control block.

[0054] Example 4 is a test and measurement instrument for any of Examples 1-3, wherein determining the state value of the LFSR may include extracting the LFSR state from a subset of symbols within the bypassed control block.

[0055] Example 5 is a test and measurement instrument for any of Examples 1-4, wherein the subset of symbols may include multiple symbols of the bypassed control block that encode the LFSR state.

[0056] Example 6 is a test and measurement instrument for any of Examples 1-5, where symbol indexing or bit indexing is used to determine the location of the bypassed control block within the acquisition interval.

[0057] Example 7 is a test and measurement instrument of any of Examples 1-6, wherein taking into account relative positioning relationships may include determining the offset between the position of the bypassed control block and the start of the acquisition interval.

[0058] Example 8 is a test and measurement instrument for any of Examples 1-7, where the offset is based on the number of symbols that were bypassed before the control block was reached within the acquisition interval.

[0059] Example 9 is a test and measurement instrument for any of Examples 1-8, wherein determining the LFSR state corresponding to the start of the acquisition interval may include offset-driven or reversed LFSR.

[0060] Example 10 is a test and measurement instrument of any of Examples 1-9, wherein the LFSR has an initial state value specified by a serial data communication protocol.

[0061] Example 11 is a method for synchronizing serial communication data, which may include: receiving serial communication data from a device under test (DUT); identifying a bypassed control block within the data during an acquisition interval; determining the state value of a linear feedback shift register (LFSR) based on the bypassed control block and its position within the acquisition interval; determining an LFSR state corresponding to an earlier position within the acquisition interval based on the LFSR state value and the position of the bypassed control block, taking into account the relative positioning relationship within the data; and using the LFSR state corresponding to the earlier position within the acquisition interval to descramble at least a portion of the data to generate decoded data prior to the data of the bypassed control block.

[0062] Example 12 is the method of Example 11, wherein receiving serial communication data is according to Universal Serial Bus (USB) protocol 3_prd_x_prd_.

[0063] Example 13 is a method of Example 11 or Example 12, wherein the bypassed control block may include an SKP control block.

[0064] Example 14 is a method of any of Examples 11-13, wherein determining the state value of the LFSR may include extracting the LFSR state from a subset of symbols within the bypassed control block.

[0065] Example 15 is a method of any of Examples 11-14, wherein the subset of symbols may include multiple symbols of the bypassed control block that encode the LFSR state.

[0066] Example 16 is a method of any of Examples 11-15, wherein the location of the bypassed control block within the acquisition interval is determined using a symbol index or a bit index.

[0067] Example 17 is a method of any of Examples 11-16, wherein taking into account the relative positioning relationship may include determining the offset between the location of the bypassed control block and the start of the acquisition interval.

[0068] Example 18 is a method of any of Examples 11-17, where the offset is based on the number of symbols that were bypassed from the control block within the acquisition interval.

[0069] Example 19 is a method of any of Examples 11-18, wherein determining the LFSR state corresponding to the start of the acquisition interval may include offset-driven or reversed LFSR.

[0070] Example 20 is a method of any of Examples 11-19, wherein the LFSR has an initial state value specified by a serial data communication protocol.

[0071] The foregoing versions of the disclosed subject matter have many advantages, which have been described or will be apparent to those skilled in the art. Nevertheless, these advantages or features are not required in all versions of the disclosed apparatus, system, or method.

[0072] Furthermore, this written description refers to specific features. It should be understood that the disclosure in this specification includes all possible combinations of those specific features. Where a specific feature is disclosed in the context of a particular aspect or example, that feature may also be used to the extent possible in the context of other aspects and examples.

[0073] Furthermore, when this application refers to a method having two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context precludes those possibilities.

[0074] All features disclosed in the specification (including the claims, abstract, and drawings) and all steps in any disclosed method or process may be combined in any combination, except for at least some mutually exclusive combinations of such features and / or steps. Unless otherwise expressly stated, each feature disclosed in the specification (including the claims, abstract, and drawings) may be replaced by an alternative feature for the same, equivalent, or similar purpose.

[0075] While specific examples of the invention have been illustrated and described for illustrative purposes, it should be understood that various modifications may be made without departing from the spirit and scope of the invention. Therefore, the invention should not be limited to any aspects other than those stated in the appended claims.

Claims

1. A testing and measuring instrument, comprising: One or more channels are used to receive data from the device under test (DUT) via a test fixture, the data being transmitted by the DUT according to a serial data communication protocol; and One or more processors are configured to execute code that causes the one or more processors to: The identifier was bypassed from the control block during the data acquisition interval; Based on the bypassed control block and its position within the acquisition interval, the state value of the linear feedback shift register (LFSR) is determined. By taking into account the relative positioning relationship within the data, the LFSR state corresponding to the earlier positioning in the acquisition interval is determined based on the LFSR state value and the position of the bypassed control block. and At least a portion of the data is descrambled using the LFSR state corresponding to an earlier location in the acquisition interval to generate decoded data prior to the data being bypassed from the control block.

2. The test and measurement instrument according to claim 1, wherein the serial data communication protocol includes Universal Serial Bus (USB) protocol 3.x.

3. The test and measurement instrument of claim 1, wherein the bypassed control block includes the SKP control block.

4. The test and measurement instrument of claim 1, wherein determining the state value of the LFSR comprises extracting the LFSR state from a subset of symbols within the bypassed control block.

5. The test and measurement instrument of claim 4, wherein the subset of symbols comprises a plurality of symbols encoding the bypassed control block of the LFSR state.

6. The test and measurement instrument of claim 1, wherein a symbol index or a bit index is used to determine the location of the bypassed control block within the acquisition interval.

7. The test and measurement instrument of claim 1, wherein taking into account the relative positioning relationship includes determining the offset between the position of the bypassed control block and the start of the acquisition interval.

8. The test and measurement instrument of claim 7, wherein the offset is based on the number of symbols before the control block is bypassed within the acquisition interval.

9. The test and measurement instrument of claim 7, wherein determining the LFSR state corresponding to the start of the acquisition interval includes offset-driven or reversed LFSR.

10. The test and measurement instrument of claim 1, wherein the LFSR has an initial state value specified by a serial data communication protocol.

11. A method for synchronizing serial communication data, comprising: Receive serial communication data from the device under test (DUT); The identifier was bypassed from the control block during the data acquisition interval; Based on the bypassed control block and its position within the acquisition interval, the state value of the linear feedback shift register (LFSR) is determined. By taking into account the relative positioning relationship within the data, the LFSR state corresponding to the earlier positioning in the acquisition interval is determined based on the LFSR state value and the position of the bypassed control block. and At least a portion of the data is descrambled using the LFSR state corresponding to an earlier location in the acquisition interval to generate decoded data prior to the data being bypassed from the control block.

12. The method of claim 11, wherein receiving serial communication data is in accordance with Universal Serial Bus (USB) protocol 3.x.

13. The method of claim 11, wherein the bypassed control block includes the SKP control block.

14. The method of claim 11, wherein determining the state value of the LFSR comprises extracting the LFSR state from a subset of symbols within the bypassed control block.

15. The method of claim 14, wherein the subset of symbols comprises a plurality of symbols encoding the bypassed control block of the LFSR state.

16. The method of claim 11, wherein a symbol index or a bit index is used to determine the location of the bypassed control block within the acquisition interval.

17. The method of claim 11, wherein taking into account the relative positioning relationship includes determining the offset between the position of the bypassed control block and the start of the acquisition interval.

18. The method of claim 17, wherein the offset is based on the number of symbols that were bypassed from the control block within the acquisition interval.

19. The method of claim 17, wherein determining the LFSR state corresponding to the start of the acquisition interval includes offset-driven or reversed LFSR.

20. The method of claim 11, wherein the LFSR has an initial state value specified by a serial data communication protocol.

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