A PCM code stream data receiving method and device supporting frame-subframe two-level structure and inverse code subframe framing

Abstract

The application discloses a PCM code stream data receiving method and device supporting frame-subframe two-level structure and inverse code subframe framing, and belongs to the technical field of digital communication and integrated circuit design. The device is realized based on FPGA, and contains receiving control, receiving cache, DMA control and programmable sending path module. The method adopts frame-subframe two-level data structure, and inserts a synchronization word into the last subframe in the frame to form an inverse code subframe, and the positive and inverse code double matching automatically frames and checks; multi-stage progressive synchronization locking makes the false synchronization probability lower than 10-12; asynchronous FIFO cross clock domain safe transmission and automatic insertion of 64-bit hardware time stamp; double FIFO decoupling storage cooperates with AXI4-Stream to automatically package according to 4096 byte boundaries; the synchronization word value, bit width and mask full parameters are programmable, and in-chip loop self-checking is supported. The application realizes frame-subframe structured data hardware full-automatic analysis, and significantly reduces the processor analysis overhead.

Description

Technical Field

[0001] This invention relates to the fields of digital communication and integrated circuit design technology, and particularly to a PCM code stream data receiving method and apparatus based on FPGA programmable logic devices, supporting a two-level frame-to-subframe structure and inverse code subframe framing. Specifically, it relates to a protocol controller that supports a two-level frame-to-subframe data structure, programmable synchronization word detection (including bit width and mask), inverse code subframe framing and verification, multi-level progressive synchronization locking, dual FIFO decoupled storage, automatic hardware timestamp insertion, multi-level cross-clock domain secure transmission, and AXI4-Stream DMA automatic packet splitting. It is suitable for synchronous serial communication scenarios such as PCM telemetry, satellite communication, radar data transmission, industrial data acquisition, and multi-subframe structured data transmission. Background Technology

[0002] PCM (Pulse Code Modulation) streams are one of the most fundamental data forms in telemetry, telemetry, and broadband data transmission. In PCM telemetry systems, data is continuously transmitted as a serial bit stream along with the channel clock. The transmitting end digitizes the analog signals collected by multiple sensors and assembles them into a serial PCM stream according to a predetermined frame format. The receiving end needs to identify the frame header (synchronization word) in the bit stream, and then divide it into frames and subframes according to the agreed row and column structure. Finally, the payload is written to the memory for backend processing.

[0003] In practical engineering applications, especially in scenarios such as PCM telemetry, satellite data transmission, and industrial fieldbus, data transmission often adopts a multi-subframe structured data format—each frame consists of multiple subframes, each containing a synchronization word and the data payload immediately following it. Furthermore, some code patterns place the bitwise inverse of the synchronization word (i.e., a "inverse subframe") at a specific subframe position to identify frame boundaries. This multi-subframe structured data format is not fully supported in existing HDLC protocol standards and traditional PCM receiving schemes. A systematic analysis of existing technologies reveals the following six major technical shortcomings.

[0004]

Defect 1

[0005]

Defect 2

[0006]

Defect 3

[0007]

Defect 4

[0008]

Defect 5

[0009]

Defect 6

[0010] Cost limitations of existing solutions: Furthermore, due to the aforementioned functional limitations, existing solutions require high-frequency CPU participation in stream parsing and frame segmentation, necessitating high-performance processors (such as ARM Cortex-A series or DSPs) in industrial equipment, increasing hardware material costs by over 30%. This invention automates the entire hardware preprocessing chain, enabling system design with a low-cost MCU, resulting in significant economic and technological advantages.

[0011] A search of publicly available domestic patents related to PCM / HDLC controllers (CN117354387A, CN114629966B, CN110224789B, CN106411918A, CN111698271A, CN112073151A, CN121150882B) and academic literature ("Design of PCM Telemetry Frame Synchronizer with Variable Frame Structure", "High-Speed ​​Programmable PCM Telemetry Frame Synchronizer", "Implementation of HDLC Protocol Based on FPGA") revealed no complete solution simultaneously supporting all innovative features such as frame-subframe two-level data structure, programmable synchronization word (including bit width and mask), inverse code subframe framing and verification, multi-level progressive synchronization locking, dual FIFO decoupled storage, hardware timestamp insertion, multi-level cross-clock domain secure transmission, and AXI4-Stream DMA automatic packet splitting. This indicates a significant technological gap. Comparison of existing technical routes

[0012] To further clarify the non-obviousness of this invention, existing technical approaches are categorized and compared: Route 1: Pure Software PCM Analysis CPU + General Purpose Serial Port / Ethernet Port The software searches for synchronization words frame by frame, segments frames, and timestamps data. High processor overhead, poor time accuracy (millisecond level), inability to handle high-speed bitstreams, and high cost of high-performance processors. Route 2: Simplified Single-Stage Synchronous FPGA Patents CN117354387A, CN114629966B, etc. Hardware single / double matching synchronization word, fixed frame format, no inverse code recognition High probability of false synchronization, frame format cannot be configured, no timestamp, no DMA packet splitting Route 3: Multi-level hardware IP of this invention This application Frame-subframe two-level + inverse code subframe + multi-level synchronization + fully programmable parameters + dual FIFO + hardware timestamp + AXI4-Stream DMA + integrated transmit / receive loopback — (Full-chain hardware automation, can be paired with low-cost MCUs)

[0013] This invention belongs to route three, which realizes the complete processing from synchronization word detection to DMA packet splitting through hardware full-link automation, significantly reducing processor parsing overhead and reducing the amount of software frame parsing computation. There is no similar solution in the existing technology. Summary of the Invention

[0014] (a) Purpose of the invention To address all the aforementioned deficiencies in existing technologies, the present invention aims to provide a PCM code stream data receiving method and apparatus based on FPGA programmable logic devices, supporting a two-level frame-to-subframe structure and inverse code subframe framing. This method and apparatus achieves automatic identification and parsing of frame-to-subframe structured data, flexible configuration of programmable synchronization words (including bit width and mask), inverse code subframe framing and verification, multi-level progressive synchronization locking and configurable lock-out recovery, hardware automatic extraction of subframe counting and frame structure information, hardware timestamp insertion of received data, multi-level cross-clock domain secure transmission, and AXI4-Stream DMA automatic packet splitting. This significantly reduces processor parsing overhead, decreases software frame parsing computation, and improves the processing efficiency and transmission reliability of multi-subframe structured data.

[0015] (II) Technical Solution and Core Innovations To achieve the above objectives, the present invention adopts the following technical solution. The device is implemented as a single hardware IP core on an FPGA programmable logic device, employing a three-layer architecture with an AXI4-Lite configuration interface and a system clock domain data path, and a serial receive clock domain. The device includes a configuration register module, a receive control module, a receive buffer module, a DMA control module, a programmable transmit path module, and a reference timer module. The system is divided into two clock domains: the PCM receive clock domain (rx_clk, frequency determined by the code rate) and the system clock domain (sys_axi_aclk, 100MHz). Secure data transmission between the two domains is achieved through an asynchronous FIFO and a three-level synchronization register. The modules are labeled with Arabic numerals 1 to 10 in the accompanying drawings (see the accompanying drawings and detailed embodiments for details). The present invention possesses the following eight core innovations, each corresponding one-to-one with the deficiencies in the background technology.

[0016] Innovation Point 1: Two-level frame-subframe architecture and inverse code subframe frame determination verification (solving defects one and three) Existing defects: Traditional HDLC / PCM controllers only support single-layer frame structures, cannot recognize frame tail synchronization inverse code, require software to segment frames, and frame integrity cannot be verified by hardware; This solution uses a hardware-defined two-level data structure of frame and subframe. Each frame consists of a configurable number of subframes. The synchronization word is placed in the bitwise inverse code of the last subframe. The receiver uses dual comparators to simultaneously identify the positive code and the inverse code. The frame boundary is determined by hitting the inverse code. Beneficial effects: Hardware automatically defines frame boundaries, eliminating the need for processor parsing; the inverse subframe simultaneously provides dual verification functions for frame determination and data integrity. hit_pos = (recv_data & pcm_syn_bit_mask) == pcm_syn_word; hit_neg = (recv_data & pcm_syn_bit_mask) == ((~pcm_syn_word) & pcm_syn_bit_mask); sync_hit = hit_pos || hit_neg;.

[0017] Innovation Point 2: Synchronization word full parameter programmability (three degrees of freedom: numerical value + bit width + mask) (addressing defect 2) Existing drawback: The existing HDLC controller uses a fixed 0x7E synchronization word with a fixed bit width. Changing the code pattern requires re-synthesizing the bit stream. This solution supports three degrees of freedom programmable configuration for the synchronization word value register (pcm_syn_word, 32-bit), the bit width register (pcm_syn_bit_len, supporting 8 / 16 / 24 / 32 bits), and the mask register (pcm_syn_bit_mask, 32-bit). The mask can be 0x000000FF, 0x0000FFFF, 0x00FFFFFF, or 0xFFFFFFFF depending on the bit width. Beneficial effects: The same hardware can be adapted to multiple code types such as 0xEB90 / 16-bit and 0x9ABCB52C / 32-bit without resynthesis, enabling one machine to be used for multiple purposes.

[0018] Innovation Point 3: Multi-level progressive synchronous locking and configurable unlock recovery (addressing defect 4) Existing drawbacks: Existing technologies lock after one or two matches, resulting in a high probability of false synchronization; the number of protection levels is fixed and cannot be configured. This scheme employs a six-level state machine (IDLE→SYN_DETECT1→SYN_DETECT2→SYN_DETECT3→RECV_FRAME→RECV_END), requiring four consecutive matches before entering the receiving state (preferred implementation). The lock-loss tolerance threshold pcm_syn_unlock_err_times is configurable during runtime. Claim 1 uses the terms "multi-level progressive" and "predetermined number of times," while claim 4 further specifies it as four levels / four times. Beneficial effect: The probability of false synchronization is reduced from P in a single instance to P in a single instance. 4 The theoretical value for a 16-bit synchronization word is less than 10. -12 (See Example 2 for the derivation), improving upon the existing two-level protection scheme by 10%. 6 More than twice.

[0019] Innovation Point 4: Dual FIFO decoupled storage and hardware load separation (addressing defects five and six) Existing drawbacks: The existing solution mixes the synchronization word into the overall data stream cache, which requires software to filter the synchronization word, resulting in wasted bandwidth and high processor overhead; This solution employs a data FIFO (dma_data_fifo, block RAM, 32-bit wide, 4096-bit deep) to buffer the stripped payload; an information FIFO (dma_info_fifo, distributed RAM, 32-bit wide, 16-bit deep) to buffer frame metadata; and hardware discards synchronization subframes based on frame flags. Beneficial effects: Data and metadata are stored separately, allowing the upper layer to obtain frame structure information with zero overhead; hardware stripping of synchronization subframes saves backend bandwidth.

[0020] Innovation Point 5: Automatic Embedding of 64-bit Hardware Timestamps (Addressing Defect 5) Existing limitations: The existing solution lacks hardware timestamps, and software labeling suffers from millisecond-level uncertainty; This solution: The reference timer module is a 64-bit loadable free counter, and the receive buffer module automatically splits the data into two FIFOs, high 32 bits and low 32 bits, at the beginning of each frame; Beneficial effects: The timestamp accuracy is one system clock cycle (10ns@100MHz), which is 10% higher than software marking. 5 Multiples; time and data strictly correspond.

[0021] Innovation Point 6: Multi-level secure transmission across clock domains (addressing defect six) Existing shortcomings: Existing solutions mostly use two-level trigger synchronization or a single FIFO, and lack multi-level security handling for cross-domain configuration parameters; This scheme uses a three-level register synchronization chain for configuration parameters (system domain _d1 → receiver domain _d2 → receiver domain _d3); data transmission uses a 40-bit wide asynchronous FIFO (32-bit data + 6-bit subframe counter + 2-bit frame flag), Gray code read / write pointer + FWFT mode + afull backpressure + overflow flag. Beneficial effects: Effectively eliminates the risk of metastable propagation. The FIFO will back-pressure when full and report the overflow flag when back-pressure is continuous, avoiding implicit data loss and significantly improving the mean time between failures (MTBF).

[0022] Innovation Point 7: AXI4-Stream DMA Automatic Packet Splitting (Addressing Defect 6) Existing drawbacks: The existing solution transmits the entire frame after buffering, resulting in high latency, high memory consumption, and a lack of standard AXI4-Stream packet splitting capabilities; This solution: The DMA control module assembles AXI4-Stream data packets frame by frame. If the packet exceeds 4096 bytes (minus 8 bytes for the header), it is automatically split into multiple packets. The header contains pkt_id / valid_byte_cnt / frame_total_byte_len, and the interface outputs tdata / tvalid / tready / tlast / tuser. Beneficial effects: Streaming packet transmission eliminates the need for full frame buffering, significantly reducing latency; the standard AXI4-Stream interface connects to high-performance SoCs.

[0023] Innovation Point 8: Programmable transmission path and on-chip loopback self-test (solving the lack of testing capabilities) Existing shortcomings: The existing solution requires external equipment for testing and lacks built-in transmission path and loopback capability; This solution: The programmable transmit path module generates a transmit clock by dividing the system clock. It transmits a positive code of the synchronization word in each subframe, a negative code at the end of the frame, and fills in auto-incrementing test data between subframes; the loopback multiplexer inverts the transmit clock and uses it as the receive clock to form an on-chip self-closed loop. Beneficial effects: The entire receiving link (including inverse code subframe fixing) can be verified without external equipment, significantly improving debugging efficiency.

[0024] (III) Beneficial Effects Compared with the prior art, the present invention has the following beneficial effects: 1 Frame structure support Frame-subframe two-level system plus inverse code subframe for frame determination, with automatic hardware-level recognition. Standard HDLC single-layer frame, does not support multiple subframes (CN117354387A, CN114629966B). First time 2 Synchronous word programmable The numerical value, bit width, and mask are all configurable, supporting 8 / 16 / 24 / 32 bits. Fixed at 0x7E, fixed bit width (CN117354387A) Multi-functional 3 Inverse subframe Double matching of positive and negative codes, with dual functions of frame fixing and verification. This function is not available; it only recognizes a single synchronization word (CN110224789B). First time 4 Synchronization Reliability <![CDATA[Multi-level progressive locking, false synchronization probability P N (<10 -12 )]]> <![CDATA[Single-stage / two-stage protection, false synchronization probability P~P 2 (CN112073151A)]]> <![CDATA[Increase by 10 6 times]]> 5 Unlock recovery Configurable threshold, dynamically modified at runtime, automatic recapture. Fixed number of levels or software intervention required (CN111698271A) Adaptive 6 Frame structure information The information FIFO independently outputs the subframe count and the total number of frame bytes. Unstructured information output, requires software parsing (CN114629966B) Zero overhead 7 Time precision Subframe-level 64-bit hardware timestamp (10ns precision) Software-generated tags or no timestamps (millisecond-level uncertainty) <![CDATA[10 times higher 5 > 8 Load efficiency Hardware stripping of synchronization subframes, with only the payload written to the DMA. Synchronization words mixed into the data stream require software filtering. Bandwidth savings 9 Cross-clock domain security Three-level register synchronous + asynchronous FIFO dual mechanism Two-stage triggers or a single FIFO (CN110224789B) MTBF enhancement 10 DMA transfer efficiency AXI4-Stream streaming packet splitting eliminates the need for full-frame buffering. The entire frame is buffered before transmission, resulting in high latency. Latency reduction 11 Testability Built-in programmable transmit path + loopback multiplexer + self-generated inverse code pattern External equipment is required for testing. Improved debugging efficiency 12 Economic effects Hardware preprocessing reduces processor performance requirements, allowing for the pairing with low-cost MCUs and significantly lowering the overall hardware cost. High-frequency CPU-based bitstream parsing is required, necessitating a high-performance processor, which increases hardware material costs by over 30%. Cost reduction Attached Figure Description

[0025] Figure 1 This is a block diagram of the overall architecture of the PCM stream data receiving device of the present invention, showing the connection relationship of the configuration register module (labeled 1), the receive control module (labeled 2), the asynchronous FIFO (labeled 3), the three-level synchronization register (labeled 4), the receive buffer module (labeled 5), the DMA control module (labeled 6), the reference timer module (labeled 7), the programmable transmit path module (labeled 8), the polarity selection unit (labeled 9), and the loopback multiplexer (labeled 10), as well as the division of the two clock domains, the AXI4-Lite configuration interface, the AXI4-StreamDMA output interface, and the on-chip loopback path.

[0026] Figure 2 The flowchart shows the state machine for multi-level progressive synchronization locking and inverse code subframe fixing, illustrating the complete jump conditions for six states: IDLE → SYN_DETECT1 → SYN_DETECT2 → SYN_DETECT3 → RECV_FRAME → RECV_END (including the branch returning to IDLE upon loss of lock and the re-search branch from RECV_END to IDLE), as well as the frame flag generation and inverse code subframe verification logic for dual matching of positive and negative codes.

[0027] Figure 3 The diagram illustrates the data flow of the receive cache module's timestamp embedding, payload stripping, and DMA control module's automatic packet splitting. It shows the 64-bit timestamp high 32-bit / low 32-bit splitting and insertion process, the bit width and depth markings of the data FIFO (4096×32bit BRAM) and information FIFO (16×32bit distributed RAM), the AXI4-Stream automatic packet splitting mechanism, the packet header format [pkt_id|valid_byte_cnt|frame_total_byte_len], and the tdata / tvalid / tready / tlast / tuser signal markings.

[0028] Figure 4 This diagram illustrates multi-level cross-clock domain parameter synchronization and asynchronous FIFO data transmission, showing the three-level register synchronization chain of configuration parameters (first level _d1, second level _d2, and third level _d3 are respectively boxed) and the internal bit field splitting structure of the 40-bit wide asynchronous FIFO: {frame_flag[1:0], sub_frame_cnt[5:0], recv_data[31:0]}. Detailed Implementation

[0029] The numerical parameters given in the following specific embodiments (such as synchronization word value 0xEB90, subframe byte length 160, number of subframes per frame 16, FIFO depth 4096, system clock frequency 100MHz, etc.) are all exemplary values ​​used to illustrate the preferred embodiments of the present invention. Those skilled in the art can adjust the above parameters according to actual application needs, and such adjustments are all within the protection scope of the present invention.

[0030] Example 1: System Overall Architecture and Configuration Registers See Figure 1 The PCM stream data receiving device of this invention is deployed on a Xilinx Kintex-7 series FPGA (XC7K325), with a system clock of 100MHz AXI clock. The top layer of the device provides an AXI4-Lite slave interface (32-bit data) for processor configuration and status reading, an AXI4-Stream master interface (64-bit tdata) for outputting packetized data to the back-end DMA, and serial receive ports (rx_clk, rx_din) and serial transmit ports (tx_clk, tx_dout, used for loopback testing). The modules represented by labels 1 to 10 are described below: Label 1 – Configuration Register Module (pcm_cfg): Receives and stores all configurable parameters via the AXI4-Lite bus, and transmits them to the receive control module (label 2) via the three-level synchronization register (label 4). Label 2 – Receive Control Module (pcm_ctrl): Operates in the receive clock domain, and implements serial-to-parallel conversion, synchronization identification, multi-level progressive synchronization locking, inverse code subframe fixing and verification, frame flag generation, and data output; Label 3 – Asynchronous FIFO: Serves as a data bridge between the receive clock domain and the system clock domain. It is 40 bits wide and contains frame flags, subframe counts, and data. Label 4 – Level 3 Synchronization Register: Synchronizes the configuration parameters of the system clock domain to the receiving clock domain via a three-level DFF cascade, eliminating metastability; Label 5 – Receive buffer module (pcm_rx_buf): operates in the system clock domain and implements timestamp insertion, payload stripping, and frame description information generation; Label 6 – DMA control module (pcm_dma_ctrl): contains data FIFO and information FIFO, assembles AXI4-Stream data packets frame by frame and supports automatic packet splitting output; Label 7 – Reference Timer Module (ref_timer): A 64-bit loadable free counter that outputs a timestamp for use by Label 5; Label 8 – Programmable Transmit Path Module (pcm_tx): Generates test code patterns consistent with the receiver side structure, supports clock division, positive and negative code generation, and auto-incrementing test data; Label 9 – Polarity Selection Unit: Selects whether to sample data on the rising or falling edge of the receiving clock according to the polarity configuration; Label 10 – Loopback Multiplexer: This is a clock / data 2-to-1 multiplexer that selects either an external input or the output of label 8 as the receive clock and receive data based on the loopback test enable. The processed data is transmitted from label 2 to label 5 (receive buffer module) via label 3 (asynchronous FIFO); label 5 sends the payload and frame description information to label 6 (DMA control module's data FIFO and information FIFO respectively); label 7 (reference timer module) provides label 5 with a 64-bit timestamp; label 8 (programmable transmit path module) is connected to label 2 via label 10 (loopback multiplexer); label 9 (polarity selection unit) controls the sampling polarity. Configure the register module (labeled 1, pcm_cfg) to implement the standard AXI4-Lite read / write state machine. The register mapping is shown in the table below: 0x000 PCM_SYN_WORD 32 RW Synchronization word value 0x004 PCM_SYN_BIT_LEN 8 RW Synchronization word width: 8 / 16 / 24 / 32 0x008 PCM_SYN_BIT_MASK 32 RW Synchronization mask 0x00C PCM_SUB_FRAME_BYTE_LEN 16 RW Subframe byte length 0x010 PCM_FRAME_LEN 16 RW Number of subframes per frame 0x014 PCM_SYN_UNLOCK_ERR_TIMES 8 RW Number of times the lock is lost 0x018 PCM_STATUS 32 RO States: {Lockout Count, State Machine, Lock Indicator} 0x01C PCM_RX_EN 1 RW Receive Enable 0x020-0x024 PCM_TIME_INIT 64 RW Initial time value (high / low) 0x028 PCM_TIME_SET_EN 1 RW Time setting enabled 0x02C PCM_LOOP_TEST 1 RW Loopback test enable 0x030 PCM_TX_EN 1 RW Send Enable 0x034 PCM_RECV_32BIT_CNT 32 RO 32-bit word count received 0x038 PCM_POLAR_NEG 1 RW Falling edge sampling enable 0x03C PCM_TX_CLK_PERIOD 16 RW Transmit clock division factor 0x040 PCM_TX_RESET 1 RW Send Reset 0x044 PCM_RX_RESET 1 RW Receive reset The PCM_STATUS (read-only) bit fields of the status register are defined as follows: [31:24] error count, [23:16] current status, [1:0] lock status (00 = unlocked, 01 = searching, 11 = locked). All configuration registers are loaded with default values ​​upon reset and can be dynamically modified via the AXI4-Lite bus during operation.

[0031] Example 2: Multi-level progressive synchronization locking and inverse code subframe fixing See Figure 2 The receive control module (labeled 2, pcm_ctrl) operates in the receive clock domain rx_clk, implementing serial-to-parallel conversion, frame header identification, inverse code subframe fixing, row and column counting, and lockout management. The serial shift register recv_data[31:0] shifts the serial input rx_din into each valid edge of rx_clk, achieving MSB-priority serial-to-parallel conversion. The bit counter recv_bit_cnt periodically resets to zero to mark subframe boundaries according to the number of subframe bits pcm_sub_frame_byte_len × 8; the subframe counter sub_frame_cnt periodically resets to zero to mark frame boundaries according to the number of subframes per frame pcm_frame_len. Double comparisons are performed at the boundaries of each subframe. The following provides complete calculation examples for two synchronization word widths: Mask pcm_syn_bit_mask = 0x0000FFFF (value for 16-bit) Orthogonal code matching: recv_data & 0xFFFF == 0xEB90 → hit_pos Ones' complement calculation: ~0xEB90 = 0x146F → 0x146F & 0xFFFF = 0x146F Ones' complement matching: recv_data & 0xFFFF == 0x146F → hit_neg sync_hit = hit_pos || hit_neg Mask pcm_syn_bit_mask = 0xFFFFFFFF (value for 32-bit systems) Orthogonal code matching: recv_data & 0xFFFFFFFF == 0x9ABCB52C → hit_pos Ones' complement calculation: ~0x9ABCB52C = 0x65434AD3 → 0x65434AD3 & 0xFFFFFFFF = 0x65434AD3 Ones' complement matching: recv_data & 0xFFFFFFFF == 0x65434AD3 → hit_neg sync_hit = hit_pos || hit_neg Frame flag generation rules: Hitting the inverse code → frame_flag=2'b11 (force frame start, reset subframe counter); Hitting the positive code and the subframe count reaches the end of the frame → 2'b11; Hitting the positive code but not the end of the frame → 2'b01 (subframe start); others → 2'b10 (normal data); not locked → 2'b00. The level 4 synchronization detection state machine only enters the RECV_FRAME state after four consecutive synchronization hits (positive or negative code) at the subframe boundary. The derivation of the false synchronization probability is as follows: Taking a 16-bit synchronization word as an example, the probability of a single match in a random bitstream is P = 1 / 2. 16 = 1 / 65536 ≈ 6.1×10 -5 The probability of a fourth-level continuous matching = P 4 = (1 / 2 16 ) 4 = 1 / 2 64 = 1 / 1.8×10 19 ≈ 5.4 × 10 -20 With a bit error rate of 10 -3 Under actual channel conditions, considering bit errors in the synchronization word portion, the probability of a single synchronization hit increases to approximately P' = P×(1 + bit error correction factor) ≈ 10. -3 Order of magnitude, fourth-order continuous probability P' 4 ≈ 10 -12 That is, the probability of false synchronization is less than 10. -12 It is far superior to the existing two-level protection scheme. 2 ≈ 10 -6 Magnitude. In RECV_FRAME state, after receiving each subframe, the synchronization word is checked for a match: if a match is found, error_times is cleared; if a mismatch is found, error_times is incremented. Once pcm_syn_unlock_err_times is reached, RECV_END is entered, and IDLE is returned for a new search. The frame end position is expected to hit a one-bit subframe; if a one-bit subframe is actually hit, a frame boundary anomaly is determined, providing data integrity verification. Flexibility of Multi-Level Synchronization: Claim 1 summarizes synchronization locking as "multi-level progressive" and "predetermined number of levels," with this embodiment preferably having four levels. In channels with high signal-to-noise ratios, two or three levels of protection can be configured to accelerate synchronization establishment; in channels with strong interference, four levels of protection can be configured to maximize resistance to false synchronization. This flexibility is achieved by adding a synchronization protection level register, and the state machine transitions to the RECV_FRAME state after the corresponding level based on the configuration value.

[0032] Example 3: Receive Buffer, Timestamp Embedding, and Payload Stripping See Figure 3 In the upper part, the receive buffer module (labeled 5, pcm_rx_buf) operates in the system clock domain, and its buffer state machine is: IDLE → RD_FRAME_START → INSERT_TIME1 (write the high 32 bits of the timestamp time[63:32]) → INSERT_TIME2 (write the low 32 bits of the timestamp time[31:0]) → RD_FRAME_FIRST → RD_FRAME_DATA → RD_FRAME_END. In the RD_FRAME_DATA state, the synchronization subframes at the start of the frame (2'b11) and the start of the subframe (2'b01) are discarded according to the frame_flag, and only normal data (2'b10) is written to the downstream DMA data FIFO. When the start of the frame flag is encountered, the frame byte count reaches a threshold, or the subframe count reaches frame_len+1, it enters RD_FRAME_END and writes data to the information FIFO.<sub_frame_cnt, frame_byte_cnt> .

[0033] Example 4: DMA Packet Assembly and AXI4-Stream Automatic Packet Segmentation See Figure 3 In the lower half, the packet assembly state machine of the DMA control module (labeled 6, pcm_dma_ctrl) is: IDLE→WRITE_HEAD→READ_DATA_L→WRITE_DATA→WRITE_PKT (packet splitting)→WRITE_HEAD→…→WRITE_FINISH. It reads frame description information from the information FIFO to determine the packet type and length, and assembles a 64-bit header according to [63:48] packet identifier pkt_id, [47:32] valid byte count valid_byte_cnt, and [31:0] frame byte length frame_total_byte_len. When the payload of a single frame exceeds 4096−8=4088 bytes, it is automatically split into multiple AXI4-Stream packets. The first packet is marked with SOF (pkt_id=2'b10), the last packet is marked with EOF (pkt_id=2'b01), the middle packets are not marked (pkt_id=2'b00), and a complete single packet is marked with SOF+EOF (pkt_id=2'b11). The AXI4-Stream interface outputs tdata[63:0], tvalid, tready, tlast (valid at the end of the packet), and tuser (valid word count), and interfaces with the standard AXI4-Stream DMA.

[0034] The technical basis for selecting the dual FIFO capacity is as follows: The data FIFO depth is chosen to be 4096 because the maximum packet length of AXI4-Stream is 4096 bytes (including an 8-byte header, i.e., 4088 bytes of data). The data FIFO needs to be able to cache the data volume of at least one complete packet, and a depth of 4096 × 32 bits = 16384 bytes perfectly meets this requirement with a margin. The information FIFO depth is chosen to be 16 because the maximum number of subframes per frame is supported (configurable with 16 bits), but in actual engineering, the number of subframes per frame is usually no more than a few hundred. At a 100MHz system clock, the DMA speed for reading information from the information FIFO is much faster than the frame arrival speed, and a depth of 16 is sufficient to cache the continuously arriving frame description information queue without overflowing. If the application scenario requires a larger frame buffer queue, it can be expanded by modifying the distributed RAM depth parameter.

[0035] Example 5: Multi-level cross-clock domain secure transmission See Figure 4 The configuration parameters employ a three-level register synchronization chain: specifically, a three-level cascaded D flip-flop (DFF) structure—the first level latches the configuration parameters to register cfg_d1 on the valid edge of the system clock domain (sys_axi_aclk); the second level synchronizes cfg_d1 to register cfg_d2 on the valid edge of the receive clock domain (rx_clk); and the third level synchronizes cfg_d2 to register cfg_d3 on the next valid edge of the receive clock domain. cfg_d3 is the stable configuration value used by the receive control module. In this three-level DFF cascaded structure, the first level completes the initial latch across clock domains, while the second and third levels complete two synchronizations within the target clock domain, effectively eliminating the risk of metastability propagation.

[0036] Data transmission is implemented through a 40-bit wide asynchronous FIFO, with a data format of {frame_flag[1:0], sub_frame_cnt[5:0], recv_data[31:0]}. Internally, it uses Gray code read / write pointers and First Word Pass-Through (FWFT) mode. When the FIFO is full, it is back-pressurized through the afull signal, and the overflow flag is set during continuous back-pressurization to avoid implicit data loss.

[0037] Example 6: Typical Workflow Taking a 16-bit synchronization word 0xEB90, a subframe byte length of 160, 16 subframes per frame, and falling edge sampling as an example: (1) The processor writes parameters via AXI4-Lite and sets pcm_rx_en; (2) The bit stream is shifted into recv_data bit by bit on the falling edge of rx_clk; (3) Every 1280 bits (160 bytes) reaches the subframe boundary, and recv_data & 0xFFFF is compared to 0xEB90 or 0x146F; (4) After four consecutive hits, the receiver enters the receiving state, normal data is marked 2'b10, and the frame tail is marked when the 16th subframe hits the inverse code; (5) 40 bits of data are transferred to the system clock domain via asynchronous FIFO, a 64-bit timestamp is inserted at the beginning of the frame, and the synchronization subframe is stripped; (6) The frame ends when the frame bytes reach the threshold or when the next frame begins, and the information FIFO is written; (7) The DMA controller packets AXI4-Stream according to the frame group, and the long packet is automatically split and output, and the frame data is synchronously uploaded to the processor.

[0038] Example 7: Complete Test Procedure for Programmable Transmit Path and On-Chip Loopback Self-Test This embodiment describes the complete test process for the transmit-receive closed loop, verifying the entire receiving link, including inverse code subframe fixing: (1) Register configuration: The processor writes the synchronization word 0xEB90, bit width 16, mask 0xFFFF, subframe byte length 160, number of subframes per frame 16, number of times to recover from lock failure 3, and transmit clock division factor 100 (1MHz transmit rate) via AXI4-Lite. (2) Start the transmission path: Set pcm_tx_en=1, the programmable transmission path module generates a 1MHz transmission clock tx_clk by dividing the system clock 100MHz by 100, sends the synchronization word 0xEB90 at the beginning of each subframe, sends the inverse code 0x146F in the 16th subframe of each frame, and fills the inter-subframe space with auto-incrementing test data 0x00000001, 0x00000002, ...; (3) Loopback connection: Set pcm_loop_test=1, the loopback multiplexer inverts tx_clk and uses it as rx_clk, and tx_dout as rx_din, forming an on-chip self-closing loop; (4) Receive synchronization lock: The receive control module performs serial-to-parallel conversion and four-level synchronization detection in the rx_clk field. After matching 0xEB90 or 0x146F four times in a row, it enters the RECV_FRAME state. (5) Timestamp and payload stripping: The receive buffer module inserts a 64-bit timestamp at the beginning of the frame, discards the synchronization subframe according to the frame flag, and only writes the effective payload into the DMA data FIFO; (6) DMA output and data comparison: The DMA control module outputs the data packets to AXI4-Stream. The processor reads the data packets from DDR, verifies the timestamp value, the correctness of the payload auto-increment sequence, and the inverse code subframe tail identifier, and completes the functional verification of the entire link.

[0039] Example 8: Performance and Resource Indicators Supports synchronized word width 8 / 16 / 24 / 32-bit Register configurable Supported subframe byte length 1~65535 bytes 16-bit configurable Supported number of intra-frame subframes 1~65535 16-bit configurable Supported sending rate 100bps~50Mbps Depends on the frequency division coefficient Timestamp precision 10ns 100MHz system clock False synchronization probability <![CDATA[<10 -12 ]]> <![CDATA[Fourth-level detection@10 -3 bit error rate]]> DMA maximum packet length 4096 bytes Includes an 8-byte header Data FIFO 4096×32bit Block RAM Information FIFO 16×32bit Distributed RAM LUT resource usage Around 1850 XC7K325 typical value FF resource usage Approximately 2100 XC7K325 typical value BRAM resource usage 1 36Kb Data FIFO usage .

[0040] To verify the technical effectiveness of this invention, system performance tests were conducted under different code rates and synchronization word widths. The measured data are as follows: Test 1 1Mbps 16-bit 0 (72h no false synchronization) 0.98Mbps 1832 / 2087 / 1 Test 2 10Mbps 16-bit 0 (72h no false synchronization) 9.82Mbps 1851 / 2103 / 1 Test 3 10Mbps 32-bit 0 (72h no false synchronization) 9.81Mbps 1868 / 2125 / 1 Test 4 50Mbps 16-bit 0 (No false synchronization in 48 hours) 48.95Mbps 1895 / 2156 / 1 The test data above show that the present invention maintains zero false synchronization under various code rates and synchronization word widths, with throughput approaching the theoretical limit and resource usage remaining stable at approximately 1850 LUTs / 2100 FFs / 1 36Kb BRAM.

[0041] Example 10: Alternative Implementation Variation Variation 1: Dynamic Real-Time Switching of Synchronization Mask. In another embodiment of the present invention, the synchronization mask pcm_syn_bit_mask can be dynamically modified by the processor at runtime without resetting the receiving link. When the link code pattern changes online, the processor first pauses reception (pcm_rx_en=0), modifies the mask register, and the changes take effect after three-level synchronization, before resuming reception. This variation is applicable to adaptive communication scenarios where the code pattern switches midway, demonstrating that the scope of protection of the present invention can be extended to dynamic code pattern adaptation. Variation 2: Configurable Synchronization Protection Levels. In another embodiment of the invention, the multi-level progressive synchronization locking can be configured via registers to provide 1, 2, 3, or 4 levels of protection. In channels with high signal-to-noise ratios, 2-level protection can be configured to accelerate synchronization establishment; in channels with strong interference, 4-level protection can be configured to maximize resistance to false synchronization. This variation is achieved by adding a synchronization protection level register. The state machine transitions to the RECV_FRAME state after the corresponding level based on the configured value, demonstrating that the synchronization locking mechanism of the present invention can adapt to channel conditions with different signal-to-noise ratios. Variation 3: ASIC and Hardware Accelerator Porting Implementation. Except for FPGA programmable logic devices, the entire hardware architecture of this invention can be ported to ASIC application-specific integrated circuits or MCU hardware accelerators. In the ASIC implementation, the data first-in-first-out memory with dual FIFO decoupled storage can be replaced by embedded SRAM or eDRAM instead of the FPGA's block RAM, and the information first-in-first-out memory can be replaced by register arrays or distributed storage instead of the FPGA's distributed RAM. The multi-level progressive synchronous locking state machine, the positive / negative code dual matching comparator, the 64-bit timestamp insertion logic, and the AXI4-Stream automatic packet splitting controller can all be directly mapped to ASIC standard cell logic, requiring only timing constraints to be adjusted according to the process node. In the MCU hardware accelerator implementation, this invention can be used as a peripheral IP core of the MCU, connected to the MCU processor core via the AHB or APB bus. The MCU only needs to configure parameters and read DMA data, without participating in code stream parsing. The above variations demonstrate that the core synchronization, dual FIFO, timestamp, and DMA packet splitting logic of this invention are completely reusable, and the protected object is not limited to FPGAs, but can be extended to ASIC application-specific integrated circuits and MCU hardware accelerators, broadening the scope of patent protection.

[0042] Example 11: Industrial Implementation Case After a certain type of satellite telemetry equipment adopted the IP core of this invention to replace the traditional HDLC controller, the measured data are as follows: Under a code rate of 10 Mbps, a 16-bit synchronization word of 0xEB90, and a configuration of 16 subframes per frame, the received packet loss rate decreased from 2.3 × 10⁻⁶ in the traditional scheme. -4 The performance degradation rate was reduced to 0 (no packet loss during 72 hours of continuous testing); processor utilization decreased from 35% to 0.1% (only requiring reading DMA interrupts and parsing the FIFO information); timestamp accuracy improved from ±1ms to ±10ns; synchronization setup time decreased from an average of 1.2 seconds to an average of 0.8 milliseconds. This device has been deployed in batches at multiple satellite ground stations, accumulating over 10,000 hours of stable and reliable operation. This example demonstrates the significant technical effectiveness and commercial application value of this invention in practical engineering, and its commercial success further attests to the inventiveness of this invention. Comparative analysis with existing technologies

[0043] (a) Determination of the closest prior art According to the "three-step method" for determining inventiveness in the Patent Examination Guidelines, the closest prior art is first identified. Analysis revealed that patent CN117354387A (an HDLC protocol controller FPGA module) and the academic document "Design of a PCM telemetry frame synchronizer with a variable frame structure" are the closest prior art. CN117354387A discloses an FPGA-based HDLC protocol controller, which belongs to the same technical field as this invention, both involving hardware reception and processing of serial code streams. The academic document discloses a PCM frame synchronizer with a variable frame structure, which, like this invention, involves frame synchronization of PCM telemetry data. However, neither of them discloses the core distinguishing features of this invention.

[0044] (ii) Non-obviousness argument (three-step method) Step 1: Identify the closest existing technology. As mentioned above, CN117354387A and the academic paper "Design of PCM Telemetry Frame Synchronizer with Variable Frame Structure" are considered the closest existing technologies. CN117354387A discloses an FPGA implementation of HDLC frames, using a fixed 0x7E synchronization word, a single-layer frame structure, and no inverse code recognition; the academic paper discloses that the frame length and synchronization word value can be configured through host computer software, but the synchronization word width is still fixed, there is no masking mechanism, no inverse code subframe recognition, no timestamp, and no DMA automatic packet splitting. Step 2: Identify the distinguishing technical features and the actual technical problem solved by this invention. The distinguishing technical features of this invention from the closest prior art and the actual technical problem solved by them are as follows: Frame-subframe two-level data structure + inverse code subframe frame determination and verification Multi-subframe structured data cannot be recognized by hardware and frame integrity verification is not possible. Synchronous word value + bit width + mask three degrees of freedom fully programmable Different code types require reassembly of the bitstream, resulting in low flexibility. Multi-level progressive synchronization locking (configurable number of levels) The probability of false synchronization is high in single / double matching, and the protection level cannot be configured. 64-bit hardware timestamps are automatically embedded. The software's marking time accuracy is poor (millisecond level). Dual FIFO decoupled storage + hardware load stripping Synchronization words mixed into the data stream require processor filtering, resulting in wasted bandwidth. AXI4-Stream DMA Automatic Packet Segmentation Large frame buffer latency, no standard DMA interface Programmable transmit path + on-chip loopback self-test External equipment is required for testing; it lacks built-in transceiver capabilities. Step 3: Demonstrate that no combined instruction exists. There is no technical instruction in the prior art to combine the aforementioned distinguishing features, for the following reasons: (1) The HDLC controller patents such as CN117354387A focus on the FPGA implementation of the standard HDLC frame format. Their technical teachings point to a fixed 0x7E synchronization word and a single-layer frame structure, which are different from the multi-subframe two-level structure and inverse code subframe identification technology of this invention. There is no motivation to combine them. (2) Although the academic paper "Design of PCM Telemetry Frame Synchronizer with Variable Frame Structure" proposes programmable configuration of frame length and synchronization word value, its synchronization word width is still fixed (hard-coded in hardware), does not support masking mechanism, and does not disclose features such as inverse code subframe recognition, hardware timestamp, dual FIFO decoupling, and AXI4-Stream DMA automatic packet splitting. The technical teaching of this paper points to "software configuration of frame parameters" rather than "hardware full parameter programmability + full-link automation", which is fundamentally different from the technical direction of this invention; (3) The multi-mode HDLC controllers such as CN110224789B focus on the compatibility of multiple HDLC modes and are still based on a single-layer frame structure. They do not provide technical inspiration for the two-level architecture of frame-subframe and inverse code subframe. (4) Each comparative document focuses on different technical issues and does not provide technical guidance on combining features such as frame-to-subframe two-level architecture, programmable synchronization word, multi-level synchronization, inverse code recognition, hardware timestamp, dual FIFO decoupling, AXI4-Stream DMA, and integrated transceiver loopback. The distinguishing feature combination of the present invention is not obvious.

[0045] (III) Comparison Table of Existing Technical Features The following is a systematic comparison of this invention with published related patents and documents: Technical Field PCM Receive Processing (Transmit / Receive Ends) HDLC Module FPGA Design HDLC protocol FPGA implementation Multi-mode HDLC controller PCM data reception Data synchronization device PCM-BPSK decoding synchronization PCM editor dynamic framing PCM Frame Synchronizer Frame structure Frame-subframe two-level + inverse code subframe Standard HDLC single layer Standard HDLC single layer Standard HDLC multimode Single-layer PCM frame Not involved Single-layer PCM frame Sending end framing Single-layer PCM frame Synchronous word programmable Values, bit width, and mask are all configurable. Fixed 0x7E Fixed 0x7E Fixed 0x7E fixed Not involved fixed Not involved Numerical values ​​are configurable, bit width is fixed. Inverse subframe Double matching and frame verification of positive and negative codes none none none none none None (modulation domain inversion) none none Synchronous locking Multi-level progressive (configurable number of levels) No multi-level No multi-level No multi-level No multi-level No multi-level No multi-level Not involved Front and rear protection (fixed) Unlock recovery Runtime configurable threshold Software intervention is required. Software intervention is required. Not involved Not involved fixed Not configurable Not involved Fixed series Timestamp Subframe-level 64-bit hardware timestamp none none none none none none none none Load stripping Hardware discarding synchronization subframes none none none none none none none none Double FIFO Data FIFO + Information FIFO Decoupling Multiple FIFOs but no information separation Dual-port RAM without separation none none none none none none Cross-clock domain Level 3 register + asynchronous FIFO Not involved Not involved Two-stage trigger Not involved Not involved Not involved Not involved Not involved DMA interface AXI4-Stream Automatic Packet Splitting none none none none none none AXI4-Lite (Specifications Only) none Loopback test Built-in programmable transmission path + loopback MUX + self-generated inverse code pattern none none none none none none none none

[0046] A detailed comparison of academic literature: While the paper "Design of a PCM Telemetry Frame Synchronizer with Variable Frame Structure" proposes that "users can configure parameters such as frame length and frame synchronization word through host computer software according to actual needs," which overlaps somewhat with the "programmable" feature of this invention, there are the following essential differences: the synchronization word width in that paper is still fixed (hard-coded in hardware), it does not support a masking mechanism (cannot mask invalid high bits), it lacks inverse code subframe recognition, hardware timestamps, DMA automatic packet splitting, and integrated transmit / receive loopback. Therefore, this invention represents a substantial improvement over that paper in terms of "fully programmable parameters (numerical value + bit width + mask three degrees of freedom)."

[0047] Creative Conclusion: None of the existing comparative documents simultaneously implement the complete hardware link of "hardware framing with inverse code + multi-level programmable synchronization + three-degree-of-freedom synchronization word + hardware subframe timestamp + dual FIFO metadata decoupling + integrated transmit / receive loopback self-test". The distinguishing feature combination of this invention is not obvious. Specifically, existing PCM / HDLC controller patents and documents are all based on a standard single-layer frame structure, with a fixed and non-programmable synchronization word (or only the value is configurable while the bit width is fixed). They lack the ability to frame and verify inverse code subframes, and lack innovative features such as multi-level progressive synchronization locking, dual FIFO decoupling storage, hardware timestamp insertion, payload stripping, multi-level cross-clock domain secure transmission, and AXI4-Stream DMA automatic packet splitting. This invention presents for the first time a complete receiving and processing scheme for PCM multi-subframe structured data. Its core innovations—a two-level data structure (frame-subframe) and inverse code subframe framing verification, a programmable synchronization word (including bit width and mask), multi-level progressive synchronization locking and configurable lock-out recovery, dual FIFO decoupled storage and payload stripping, subframe-level 64-bit hardware timestamps, multi-level cross-clock domain secure transmission, AXI4-Stream DMA automatic packet splitting, programmable transmission paths, and on-chip loopback self-testing—are not disclosed in existing technologies and do not offer any related inspiration. This invention solves long-standing technical problems in PCM telemetry and multi-subframe data acquisition applications, possessing outstanding substantive features and significant progress, and meeting the novelty, inventiveness, and industrial applicability requirements stipulated in the Patent Law.

[0048] Further evidence of the lack of technical inspiration: Existing HDLC patents and PCM literature address individual pain points, and none of the existing documents provide a complete technical inspiration for "simultaneously integrating two-level frames + positive and negative code recognition + three-degree-of-freedom synchronization word + multi-level synchronization + hardware timestamp + dual FIFO + AXI packet splitting + built-in loopback". Specifically, the technical approaches of the various comparative documents are independent of each other: HDLC controller patents such as CN117354387A focus on the FPGA implementation of the standard HDLC frame format, and their technical direction points to fixed synchronization word and single-layer frame structure; although academic literature proposes configurable frame parameters, the technical direction points to "software configuration of frame parameters" rather than "hardware full parameter programmability + full-link automation"; multi-mode HDLC controllers such as CN110224789B focus on multi-mode compatibility, but are still based on a single-layer frame structure. There is no motivation for those skilled in the art to combine all of the above eight differentiated innovations, and the combination produces unexpected technical effects such as low CPU usage (processor utilization rate reduced from 35% to 0.1%), zero packet loss (no packet loss in 72 hours of continuous testing), and low cost (can be paired with a low-cost MCU, reducing hardware material costs by more than 30%), which further strengthens the non-obviousness of the present invention.

Claims

1. A PCM bitstream data receiving method based on FPGA programmable logic devices, supporting a two-level frame-subframe structure and inverse code subframe framing, characterized in that, Includes the following steps: S1: Receive and store configurable parameters through the AXI4-Lite bus interface. The configurable parameters include synchronization word value, synchronization word width, synchronization word mask, subframe byte length, number of subframes per frame, number of times to recover from loss of lock, and sampling polarity. S2: In the receiving clock domain of the selected sampling polarity, the serial input bit stream is shifted into the parallel shift register one by one, and the subframe boundary is marked by bit counting with the subframe byte length multiplied by eight as the modulus, and the frame boundary is marked by frame counting with the number of subframes per frame as the modulus. S3: At the subframe boundary, perform a bitwise AND operation between the shift register content and the synchronization word mask, and then compare it with the synchronization word and its bitwise complement. If either the positive code or the complement is matched, it is determined that the synchronization is matched. S4: A multi-level progressive synchronization locking state machine is used for frame synchronization. After passing through the idle state and multi-level synchronization detection in sequence, it enters the frame receiving state. Each level of synchronization detection requires that the synchronization word positive code or negative code be hit again after a complete subframe period before it can enter the next level. Otherwise, it returns to the idle state. The multi-level refers to a predetermined number of levels greater than or equal to two. S5: Continuously receive data in frame receiving state, detect synchronization word at each subframe boundary, and exit frame receiving state and return to idle state to search again when the number of consecutive synchronization word misses reaches the configured number of lock loss tolerances; expect to hit bit-inverted code at the last subframe position in the frame, and if the positive code is actually hit, determine that the frame boundary is abnormal and trigger resynchronization, realizing the dual functions of inverted code subframe positioning and verification. S6: Parallel data with frame flags is transmitted from the receiving clock domain to the system clock domain via asynchronous first-in-first-out memory. 64-bit timestamp data is automatically inserted at the beginning of each frame. Synchronization subframes are discarded according to the frame flags, and only the payload is retained and written to the downstream data first-in-first-out memory. S7: Assemble AXI4-Stream data packets by frame. When the total length of the frame data exceeds the preset maximum packet length, it is automatically split into multiple data packets and the start packet identifier and end packet identifier are set respectively. The packets are output to the back-end DMA through the AXI4-Stream port. At the same time, the frame data is synchronously uploaded to the AXI4-Lite register through the information first-in-first-out memory for the processor to read. S8: In addition to the normal data transmission and reception process, an on-chip closed-loop self-test loopback step is included. When the loopback test is enabled, the programmable transmit path module generates a test code pattern that is consistent with the receiver side structure. After the loopback multiplexer flips the polarity of the transmit clock and uses it as the receive clock, the transmit data is used as the receive data, thus forming an on-chip self-closed-loop test. The loopback multiplexer is located before the polarity selection unit. In loopback mode, the clock source selection is completed first, and then the sampling polarity configuration is performed.

2. The method according to claim 1, characterized in that, The bitwise inverse code mentioned in step S3 is the result of inverting the bits of the synchronization word and then performing a bitwise AND operation with the synchronization word mask. When the bitwise inverse code is hit at the subframe boundary, it is determined as the start of a frame and the subframe counter is reset to form an inverse code subframe for frame fixing. When the synchronization word positive code is hit and the subframe count reaches the number of subframes per frame, it is determined as the start of a frame. A subframe is considered to begin when the synchronization word is hit and the subframe count has not reached the number of subframes per frame.

3. The method according to claim 1, characterized in that, The synchronization word width is one of 8 bits, 16 bits, 24 bits, or 32 bits, and is configured by the synchronization word width register; the synchronization word mask takes the corresponding mask value according to the bit width, which is used to mask the invalid high bits of the parallel register during comparison, so that the same hardware can switch between multiple synchronization word widths without resynthesis.

4. The method according to claim 1, characterized in that, The predetermined number of levels mentioned in step S4 is four levels. The multi-level progressive synchronization locking state machine is a four-level progressive synchronization locking state machine. After passing through the idle state, the first level of synchronization detection, the second level of synchronization detection, and the third level of synchronization detection, it enters the frame receiving state. It can only enter the frame receiving state after hitting the positive code or the negative code of the synchronization word at the subframe boundary four times in a row.

5. The method according to claim 1, characterized in that, The timestamp insertion and payload stripping described in step S6 specifically include: At the beginning of each frame, a 64-bit time counter is split into two blocks of high 32 bits and low 32 bits and written to the data first-in-first-out memory, so that the payload of each frame is prefixed with an 8-byte timestamp. The time counter runs freely in the system clock domain and supports setting the initial value through the configuration interface to achieve synchronization with the external time system. The buffer state machine inside the receive buffer module includes an idle state, a frame start read state, a timestamp insertion high bit state, a timestamp insertion low bit state, an initial data read state, a data read state, and a frame end state. In the data read state, the synchronization subframes of the frame start and subframe start are discarded according to the frame flag, and only normal data is written to the downstream data first-in-first-out memory. In the frame end state, the subframe count and frame byte count are written as frame description information to the information first-in-first-out memory.

6. The method according to claim 1, characterized in that, When the configurable parameters are transferred from the system clock domain to the receiving clock domain, a three-level register synchronization chain is used: the first level is latched in the system clock domain, and the second and third levels are synchronized sequentially in the receiving clock domain to eliminate the risk of metastability across clock domains; when data is transferred from the receiving clock domain to the system clock domain, it is implemented through a 40-bit wide asynchronous first-in-first-out memory. The data width of the asynchronous first-in-first-out memory includes data bits, frame flag bits, and subframe count values, and it internally uses Gray code read / write pointers and first-word pass-through mode.

7. The method according to claim 1, characterized in that, The automatic packet splitting process described in step S7 specifically includes: The system employs a data first-in-first-out (FIFO) memory to cache the payload and an information first-in-first-out (FIFO) memory to cache the frame description information, thereby achieving decoupled storage of data and metadata. The frame description information is read from the information first-in-first-out (FIFO) memory to determine the packet type and packet length, and the packet identifier, effective byte count, and frame byte length are written into the packet header. When the payload of a single frame exceeds the maximum packet length, it is automatically split into multiple AXI4-Stream packets, with the first packet having a start packet identifier, the last packet having an end packet identifier, and the middle packets having no identifier. The data FIFO memory is implemented using block RAM with a depth of 4096 and a width of 32 bits. The depth of 4096 is adapted to the maximum packet length of 4096 bytes in AXI4-Stream. The information FIFO memory is implemented using distributed RAM with a depth of 16 and a width of 32 bits. The depth of 16 is adapted to the frame buffer queue requirements in scenarios with a maximum of 65535 subframes per frame. The tlast of the AXI4-Stream interface is valid at the end of the packet, and tuser outputs the number of valid words, interfacing with the standard AXI4-Stream DMA.

8. The method according to claim 1, characterized in that, The loopback test described in step S8 specifically includes: The programmable transmission path module generates a transmission clock by dividing the system clock, and the division coefficient is programmable. The synchronization word positive code is output at the beginning of each subframe, and the bitwise inverse code of the synchronization word is output as the frame tail inverse code subframe at the last subframe of each frame. The subframes are filled with auto-incrementing test data. The loopback multiplexer is a clock / data 2-to-1 multiplexer. According to the loopback test enable, it selects an external input or the output of the programmable transmission path module as the receiving clock and receiving data. In loopback mode, the polarity of the transmission clock is reversed and used as the receiving clock.

9. A PCM stream data receiving device based on an FPGA programmable logic device for implementing the PCM stream data receiving method according to any one of claims 1 to 8, characterized in that, include: The configuration register module is used to receive and store configurable parameters via the AXI4-Lite bus; The receiving control module operates in the receiving clock domain and is used for serial-to-parallel conversion, synchronization identification, multi-level progressive synchronization locking, inverse code subframe fixing and verification, frame flag generation, and data output. The receive buffer module operates in the system clock domain and is used for cross-clock domain data reception, timestamp insertion, and payload stripping. The DMA control module is used for decoupled storage of dual first-in-first-out (FIFO) memories and automatic packet output of AXI4-Stream. The data FIFO memory is implemented using block RAM hardware resources, and the information FIFO memory is implemented using distributed RAM hardware resources. Reference timer module for providing 64-bit timestamps; A programmable transmit path module is used to generate a test code pattern that is consistent with the receiver side structure; A loopback multiplexer is used to select the output of an external input or a programmable transmit path module to form an on-chip self-closed-loop test path. The device is equipped with serial receiving ports rx_clk and rx_din, and serial transmitting ports tx_clk and tx_dout, for inputting and outputting external PCM code streams.

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