Electronic device

Abstract

The present disclosure relates to electronic devices. An electronic device comprising first circuitry for converting a first data transmission protocol to a second data transmission protocol. The first circuitry comprises a first-in-first-out storage element for receiving data transmitted using the first data transmission protocol. A first frequency of a first clock signal used by the first circuitry for converting the data is based at least on a second frequency of a second clock signal of the second data transmission protocol and information about a fill of the first-in-first-out storage element.

Description

Priority Statement

[0001] This application claims priority to European Patent Application No. 25315153.4, filed on April 30, 2025; and to French Patent Application No. FR2511305, filed on October 1, 2025, the contents of which are hereby incorporated in their entirety by reference to the fullest extent permitted by law. Technical Field

[0002] This disclosure generally relates to electronic devices and methods for transmitting data from such electronic devices. Background Technology

[0003] Transmitting a standard high-speed communication protocol through different channels (e.g., physically different and non-standard channels) typically requires three steps: first, protocol conversion (usually digital) from the standard protocol to the different protocol (e.g., non-standard protocol); second, transmission through the different channel (e.g., non-standard channel, such as using a radio frequency channel); and third, reverse conversion to reconstruct the original standard protocol.

[0004] Transmission via non-standard channels may introduce jitter or require complex implementation.

[0005] There is a need to improve the transmission of standard communication protocols (such as high-speed protocols) over non-standard channels.

[0006] It is necessary to address all or part of the known shortcomings of electronic devices. Summary of the Invention

[0007] One embodiment provides an electronic device comprising: a first circuit for converting a first data transmission protocol to a second data transmission protocol; the first circuit including a first-in-first-out (FIFO) storage element for transmitting data using the first data transmission protocol, wherein a first frequency of a first clock signal used by the first circuit for converting the data is based at least on a second frequency of a second clock signal of the second data transmission protocol and information regarding the filling of the FIFO storage element.

[0008] One embodiment provides a method for transmitting data from an electronic device, comprising: converting a first data transmission protocol to a second data transmission protocol via a first conversion circuit; the first conversion circuit including a first-in-first-out (FIFO) storage element for transmitting data using the first data transmission protocol; and adjusting the frequency of the first clock signal used by the first conversion circuit based at least on the frequency of a second clock signal of the second data transmission protocol and information regarding the filling of the FIFO storage element.

[0009] According to one embodiment, the device includes a second circuit and a generator of a first clock signal; wherein the generator is configured to generate the first clock signal based on a setpoint from the second circuit; and wherein the second circuit is configured to determine information regarding the filling of first-in-first-out (FIFO) memory elements and generate a setpoint based on the information regarding the filling of FIFO memory elements.

[0010] According to one embodiment, information about the filling rate of a first-in-first-out (FIFO) memory element is determined based on the fill rate and output rate of the FIFO memory element.

[0011] According to one embodiment, first-in-first-out (FIFO) memory elements are configured to be half-filled during the initialization phase.

[0012] According to one embodiment, information about the filling of a first-in-first-out (FIFO) memory element is determined based on changes in filling over a given time period.

[0013] According to one embodiment, information about the filling of a first-in-first-out (FIFO) memory element is determined based on the read pointer of the FIFO memory element.

[0014] According to one embodiment, when the fill value of the first-in-first-out (FIFO) memory element is higher than a first threshold, the first frequency is adapted to be higher than a second frequency, and when the fill value of the FIFO memory element is lower than the second threshold, the first frequency is adapted to be lower than the second frequency.

[0015] According to one embodiment, the second frequency is configured to change periodically.

[0016] According to one embodiment, when the second frequency is configured to vary according to the spread spectrum clock protocol, the first frequency is adapted according to the spread spectrum clock protocol.

[0017] According to one embodiment, the first frequency is based on a second frequency plus or minus a value based on information about the filling of the first-in-first-out memory element.

[0018] According to one embodiment, a first frequency is updated when the value of information about the filling of a first-in-first-out (FIFO) memory element changes beyond a threshold.

[0019] According to one embodiment, after updating the first frequency, a given time period is elapsed, and then information regarding the filling of the first-in-first-out memory elements is determined again.

[0020] According to one embodiment, the first-in-first-out (FIFO) storage element is a memory or a set of registers.

[0021] According to one embodiment, the second data transmission protocol is a protocol from the group consisting of: USB3®, USB4®, DisplayPort®, and Ethernet®.

[0022] According to one embodiment, the first data transmission protocol is implemented by a radio frequency channel, or optical channel, or waveguide coupled to the input of the first-in-first-out storage element.

[0023] According to one embodiment, the first frequency is also based on measurement information, determination information, or predetermined information related to the second data transmission protocol.

[0024] According to one embodiment, a first frequency is adjusted such that the first-in-first-out (FIFO) memory element is never empty and never full.

[0025] According to one embodiment, the device includes a first means and a second means; the first means includes: a first physical interface that implements a second data transmission protocol and is configured to be coupled to a connector compatible with the second data transmission protocol; a third circuit that is coupled to the first physical interface and configured to perform a conversion from the second data transmission protocol to the first data transmission protocol; and an RF transmitter for an RF channel that is coupled to the second circuit and uses the first data transmission protocol; the second means includes: an RF receiver for the RF channel that uses the first data transmission protocol; a first circuit that is coupled to the RF receiver; and a second physical interface that implements the second data transmission protocol and is configured to be coupled to a connector compatible with the second data transmission protocol.

[0026] According to one embodiment, measurement information related to a second data transmission protocol is measured in a first device and transmitted via a channel to a second device for use by a first circuit. Attached Figure Description

[0027] The above-described features and advantages, as well as other features and advantages, will be described in detail below with reference to the accompanying drawings, which are given by way of illustration rather than limitation, in which:

[0028] Figure 1 An example of a data transmission chain to which the embodiments can be applied is schematically shown in the form of a functional circuit;

[0029] Figure 2 The functional circuit is schematically shown. Figure 1 One embodiment of the data transmission chain shown;

[0030] Figure 3 The illustration shows that Figure 2 The data transmission method implemented in [the document / platform]; and

[0031] Figure 4 The functional circuit is schematically shown. Figure 1 An example of a data transmission chain is shown. Detailed Implementation

[0032] The same features are indicated by the same reference numerals in the various figures. Specifically, structural and / or functional features common to the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0033] For clarity, only the operations and elements useful for understanding the embodiments described herein are illustrated and described in detail.

[0034] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be directly connected or can be coupled through one or more other elements.

[0035] In the following disclosure, unless otherwise stated, reference is made to the orientation shown in the accompanying drawings when referring to absolute position qualifiers (such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc.) or relative position qualifiers (such as the terms “above,” “below,” “higher,” “lower,” etc.) or direction qualifiers (such as “horizontal,” “vertical,” etc.).

[0036] Unless otherwise stated, the expressions “approximately,” “about,” “approximately,” “substantially,” and “about the order of magnitude of” indicate within 10% or 10°, preferably within 5% or 5°.

[0037] In this paper: a serial link is defined as a communication channel in which information is sent sequentially, one bit at a time; jitter is defined as the time variation of a set of signal edges relative to their ideal value (i.e., aligned with a reference clock signal); a retimer is defined as a standardized component capable of retransmitting serial signals (e.g., USB3® / USB4® types) to improve signal quality and enable longer communication distances; and a phase-locked loop (PLL) is defined as a component or circuit used to generate a clock signal with the desired frequency from a reference clock signal and a multiplication factor.

[0038] Figure 1 An example of a data transmission chain 101 to which this implementation can be applied is shown schematically in the form of a functional circuit. The data transmission chain 101 is implemented, for example, within device 100.

[0039] Figure 1The transmission chain 101 includes the transmission of high-speed communication protocols 110 (standard protocols (raw)) via different channels 130, such as high-speed serial links (~10 Gbps), USB3®, USB3.2®, USB4®, DisplayPort®, and Ethernet®. Channels 130 may be physically different from protocol 110 and / or use, for example, non-standard (or non-standard) data protocols or standard data protocols different from communication protocol 110. For simplicity, channel 130 is also referred to herein as non-standard channel 130. Non-standard channels 130 may be, for example, radio frequency channels, optical channels, or waveguides.

[0040] Standard protocols refer to protocols that are standardized or widely used and documented, as opposed to proprietary or custom protocols, which may represent a type of non-standard or non-standard protocol.

[0041] In this article, the term "protocol" also refers to the data transmitted by that protocol.

[0042] exist Figure 1 In the example, the transmission of communication protocol 110, in other words, the data transmission according to communication protocol 110, includes the step of converting protocol 110 into a non-standard protocol (non-standard channel) used by channel 130. This conversion is implemented, for example, by conversion circuit 120 (protocol conversion). This conversion is implemented, for example, using digital, analog, or mixed signal processing.

[0043] In the example shown, once the conversion is complete, the converted protocol, in other words, the data converted from the standard protocol to the non-standard protocol used by channel 130, is transmitted through channel 130.

[0044] The transmission protocol, in other words, the data transmitted using a non-standard protocol, is reconstructed 150 (standard protocol (reconstruction)) by a reconversion circuit 140 (inverse protocol conversion), in other words, reconverted to obtain the original standard protocol 110, in other words, the data transmitted using the standard protocol.

[0045] Common serial protocols, such as USB3®, USB3.2®, USB4®, DisplayPort®, Ethernet®, etc., allow data to be transmitted one bit at a time. However, these protocol data streams do not transmit the original clock signal used to generate the transmitted data.

[0046] To correctly reconstruct the data bits, the original clock signal used to generate the data transmission must be reconstructed, for example, by the receiver using a clock signal reconstruction component called a CDR (Clock Data Recovery) circuit. However, the reconstructed clock signal is typically degraded compared to the original clock signal used to generate the data transmission.

[0047] For example, channel 130 using a non-standard protocol transmits only data without transmitting the associated clock signal. This may require using a CDR clock signal reconstruction circuit.

[0048] Channel 130 may also introduce additional jitter, which will further degrade the quality of the reconstructed clock signal.

[0049] The quality of the clock signal is specified for each standard protocol—USB3®, USB3.2®, USB4®, DisplayPort®, Ethernet®, etc.—with jitter being a key parameter. The clock signal used for re-conversion is reconstructed from the input data via channel 130; therefore, jitter introduced by channel 130 will degrade the jitter of the reconstructed clock signal. If the associated jitter becomes too large, the reconstructed signal will become incompatible with the maximum jitter level required by the relevant standard.

[0050] One possible solution could be to use USB3® / USB3.2® / USB4® resynchronizers or DisplayPort® repeaters. However, this solution is not compatible with the use of channel 130.

[0051] Other possible solutions could be: using a reconstructed version of the original clock signal obtained through the CDR reconstruction component to perform the conversion; or using a separate, undegraded clock signal with the same nominal frequency (as specified in the standard) as the original clock signal; in this case, residual differences between the clock signals are compensated for by adding or removing specific SKIP symbols defined in the standard for this purpose.

[0052] In the case of audio data embedded in a video stream, the clock signal associated with the audio data is unavailable at the receiver of channel 130 and cannot be directly reconstructed from the data transmitted through channel 130. To overcome this, a digital algorithm is used to generate an audio clock signal from a faster reference clock signal, and a timestamp injected into the audio stream is used. However, this solution is only possible because the frequency of the audio signal is relatively low.

[0053] In the case of the RF channel, where standard protocols use spread spectrum clocks (SSC), this degrades the RF jitter budget, leading to increased complexity and power consumption.

[0054] These methods are not "agnostic" to different types of standards and are only effective if the SKIP symbol defined in the standard exists.

[0055] To overcome these problems, the described embodiments are based on a procedure that allows dynamic control over the generation of the clock signal used for conversion. Therefore, the described embodiments provide an electronic device including a first circuit (140) for converting a first data transmission protocol to a second data transmission protocol (110, 150); the first circuit (140) includes a first-in-first-out (FIFO) storage element for transmitting data using the first (non-standard) data transmission protocol; the frequency of the first clock signal (Retransmission_Clock) used by the first circuit (140) for converting the data is at least based on the frequency of the second clock signal (Source_Clock) of the second data transmission protocol (110, 150) and information regarding the filling of the storage element.

[0056] In the following text, the first data transmission protocol is also referred to as a non-standard protocol, or a non-standard data transmission protocol, or a channel protocol, or a non-standard channel protocol. Furthermore, the second data transmission protocol is also referred to as a standard protocol, or a rebuilt standard protocol.

[0057] Therefore, the embodiment is based on a negative feedback loop whose feedback varies according to the fill state of the memory element. Thus, this feedback loop allows the frequency of the first clock signal to be modified based on information about the fill state of the memory element.

[0058] This further allows for handling situations where data is transmitted in bursts.

[0059] Another advantage is that the clock signal used in the non-standard channel 130 can have a higher frequency than the clock signal used in the standard protocol. This allows multiple data streams to be time-division multiplexed.

[0060] The described embodiments further allow for improvements in the quality of the clock signal used by circuit 140 to reconstruct the data received through channel 130.

[0061] Figure 2 The circuit is schematically shown in the form of a functional circuit. Figure 1 An embodiment of the data transmission chain shown.

[0062] In the example shown, the conversion circuit 120 includes functional circuit 204 (Tx Digital Processing, transmit digital processing) and functional circuit 206 (Tx FIFO, transmit FIFO).

[0063] In the example shown, circuit 204 is configured to receive data using a standard data transmission protocol 110 (e.g., one of USB3 / USB4 / DisplayPort / Ethernet protocols). Circuit 204 is also configured to process (e.g., digitally) the conversion from the standard serial protocol 110 to a non-standard protocol used by channel 130.

[0064] Circuit 204 includes, for example, a clock signal reconstruction sub-circuit or component (CDR) capable of recovering the source clock signal (Source_Clock) used to generate the input data stream of standard protocol 110. The raw or source clock signal detected by the CDR component is provided to circuit 206. Circuit 206 also receives, as input, a channel clock signal (Channel_Clock) specific to non-standard channel 130.

[0065] Circuit 206 implements the transition from the source clock signal (Source_Clock) to the channel 130 clock signal. The source clock signal (Source_Clock) and the channel 130 clock signal (Channel_Clock) are independent. In one example, the channel 130 clock signal is faster than the source clock signal, which prevents data loss.

[0066] Circuit 206 is, for example, a storage element, such as a register set, register, or first-in-first-out memory. If the channel 130 clock signal is faster than the source clock signal, storage element 206 may be temporarily empty because the rate at which input data fills it will be slower than the rate at which data is output.

[0067] In the example shown, the non-standard channel 130 includes, for example, a transceiver and a physical transmission device. In one example, the transceiver is an RF transceiver for wireless communication or an optical transceiver for fiber optic communication. Channel 130 is implemented independently of circuit 204, for example; that is, the standard protocols used at the input of circuit 120 or circuit 204 are not used by channel 130. Specifically, the clock signal of channel 130 and the source clock signal are, for example, independent of each other.

[0068] In the example where storage element 206 becomes empty, channel 130 is configured to not corrupt data, for example, when attempting to read the contents of storage element 206.

[0069] In one example, the transmitter circuitry of channel 130 can insert symbols, such as idle symbols, which are then removed by the receiver circuitry of channel 130 at the end of channel transmission. The transmitter circuitry of channel 130 can also, for example, insert data from a low-speed channel. In other words, if channel 130 has a sufficiently high frequency (e.g., higher than the frequency of the source clock signal (Source_Clock), additional data, such as data not included in standard protocol 110, can be transmitted through channel 130. This additional data is then removed by the receiver of channel 130, for example, before entering circuitry 140.

[0070] In the example shown, circuit 140 includes storage element 208 (Rx FIFO receive FIFO) that receives data from channel 130 at the rate of the channel clock signal (Channel_Clock). Storage element 208 is, for example, a register set, a register, or a first-in-first-out memory. Data enters storage element 208 at the rate of the channel 130 clock signal and is output at the rate of a clock signal called the retransmission clock (Retransmission_Clock).

[0071] Circuit 140 includes, for example, a clock signal generator 212 (Clk synthesis), which is configured to generate a retransmission clock signal (Retransmission_Clock) based on a frequency setpoint f. Generator 212 includes, for example, an oscillator, and / or a phase-locked loop, and / or a fractional phase-locked loop, and / or a phase interpolation circuit based on a fixed clock signal.

[0072] In the example shown, circuit 140 includes functional circuit 210 (FIFO monitor) which is configured to determine the value of the frequency setpoint f to be sent to generator 212 based on information about the filling of storage element 208, such as fill level or fill rate.

[0073] In one example, circuit 210 is coupled to or forms part of generator 212. Circuit 210 is configured, for example, to modify, and / or modulate, and / or adjust the value of frequency setpoint f or the setpoint of frequency f based on information about the fill level or rate of storage element 208 (which may contain multiple data items) and other information or values.

[0074] In one example, information about the filling of storage element 208 is determined based on the rate or throughput of data input to storage element 208 and the rate or throughput of data output from storage element 208.

[0075] In one example, information about the fill level of storage element 208 is determined based on the change in the fill level of storage element 208 over a given time period.

[0076] In one example, information about the filling of storage element 208 is determined based on the read pointer of storage element 208.

[0077] In one example, the retransmission clock signal (Retransmission_Clock) is at a higher frequency than the channel 130 clock signal (Channel Clk).

[0078] In another example, the retransmission clock signal (Retransmission_Clock) operates at a lower frequency than the channel clock signal (Channel Clk). In this case, more data can be transmitted via channel 130 than is required by the standard protocol 110.

[0079] In one example, storage element 208 is half-filled during the initialization phase.

[0080] In one example, the frequency setpoint f is based on the frequency of the channel 130 clock signal (Channel Clk) plus or minus a value based on information about the fill level of memory element 208. For example, if the fill level of memory element 208 increases, circuit 210 increases the frequency setpoint f such that the frequency of the retransmission clock signal (Retransmission_Clock) generated by generator 212 is higher than the frequency of the channel 130 clock signal (Channel Clk). Conversely, if the fill level of memory element 208 decreases, and optionally becomes less than half the size of memory element 208, circuit 210 decreases the frequency setpoint f such that generator 212 decreases the frequency of the retransmission clock signal (Retransmission_Clock).

[0081] In one example, when the change in the fill level value of storage element 208 is greater than a threshold, circuit 210 updates the frequency setpoint f.

[0082] In one example, in addition to the fill level of storage element 208, the frequency setpoint f is also based on information extracted or measured from a standard data transmission protocol, such as information about the maximum bit transfer rate. In one example, this information from the standard data transmission protocol is transmitted via channel 130 and optionally updated dynamically. In one example, the source clock signal is modulated by a frequency that varies over time according to a spread spectrum clock (SSC), and information about the frequency modulation of the source clock signal can be transmitted via channel 130 to adjust the frequency setpoint f.

[0083] In one example, the frequency setpoint f is adjusted so that storage element 208 is never empty and never full.

[0084] In one example, circuit 210 updates the frequency setpoint f based on information about the fill level of storage element 208, and then a given time period passes before circuit 210 again determines the information about the fill level of the storage element and sends it to generator 212. This allows for a settling time.

[0085] In one example, circuit 210 receives from storage element 208 information indicating the fill level "C" of storage element 208, and one or more fill thresholds, such as a fill threshold called "F" (indicating that storage element 208 is almost full) or a fill threshold called "E" (indicating that storage element 208 is almost empty). The fill level "C" of storage element 208 is obtained, for example, by evaluating the number and size of elements or data stored in storage element 208 at a given time and comparing it to the total size of storage element 208.

[0086] In one example, circuit 210 transmits the value of the setpoint frequency f to generator 212, for example, based on the element "C", "F" or "E", and the frequency f of the source clock signal (Source_Clock). DEFAULT This causes the latter to generate a re-conversion clock signal with that setpoint f value. By default, for example during the initialization phase, the frequency f is equal to the frequency f of the source clock signal (Source_Clock). DEFAULT The frequency is known because it is specified in the standard protocol. The frequency f is dynamically updated, for example, by circuit 210 to compensate for residual differences between the source clock signal (Source_Clock) and the retransmission clock signal (Retransmission_Clock).

[0087] The combination of circuit 210 and generator 212 allows control of the data output rate of storage element 208 based on data related to its fill level, ultimately enabling it to accommodate the inherent jitter or other interference of non-standard channel 130. Therefore, the retransmission clock signal (Retransmission_Clock) has low jitter. In fact, the retransmission clock signal (Retransmission_Clock) is independent of the channel 130 clock signal and therefore does not inherit its jitter.

[0088] In the illustrated example, the output of circuit 208 and the output of generator 212 are coupled to a functional circuit 214 (RxDigital Processing, receive digital processing) for standard protocol reconstruction, for example via digital or analog or mixed signal processing operations. Circuit 214 receives data from the output of storage element 208 as well as a re-conversion clock signal (Retransmission_Clock, retransmission clock). Based on these elements, circuit 214 reconstructs the standard protocol, in other words, circuit 214 reconstructs the output data from storage element 208 in standard protocol format.

[0089] Circuit 214 outputs data 150 (standard protocol (reconstructed)), which is in the format of a serial link compatible with the original standard protocol 110 (e.g., USB3 / USB4 / DisplayPort / Ethernet).

[0090] Figure 3 The figure illustrates, according to one embodiment, in Figure 2 the implemented data transmission method. More specifically, the illustrated example represents an example operation of circuit 210 and generator 212.

[0091] In optional step 300 (f := f DEFAULT ), the frequency setpoint f indicated by circuit 210 to generator 212 corresponds to the frequency f of the source clock signal (Source_Clock, source clock) DEFAULT , which is known because it is specified in the standard protocol.

[0092] In step 302 (monitor C input), for example after step 300, circuit 210 acquires the current fill level "C" of storage element 208. In one example, this fill level is determined based on a read pointer.

[0093] In steps 304 (E<C<F?), 308 (E ≤ C?), and 310 (C ≥ F) after step 302, circuit 210 compares the determined C value with thresholds E and / or F.

[0094] In step 304, if the fill level "C" of storage element 208 is strictly between thresholds E and F (branch Y), the current value of frequency setpoint f is not changed, and thus the output frequency of generator 214 is not changed either, then (e.g., after waiting for a period of time) step 302 is executed.

[0095] In step 308, if the fill level "C" of storage element 208 is less than or equal to threshold E, then (branch Y) step 312 (f := f - Δf) is executed.

[0096] In step 310, if the fill level “C” of storage element 208 is greater than or equal to the threshold F, then (branch Y) proceeds to step 314 (f := f + Δf).

[0097] In step 312, the current value f is subtracted by a value Δf, which is predetermined, for example, through programming. This allows the generator's output frequency to be reduced, thereby reducing the data output rate of storage element 208.

[0098] In step 314, the current value f is added to a value Δf, which may be equal to or different from the value in step 312, and is predetermined, for example, by programming. This increases the data output rate of storage element 208, causing the fill level of storage element 208 to be closer to or further away from half.

[0099] After step 312 or 314, an optional step 316 (waiting time Δt) is performed. In step 316, after circuit 210 updates the value f, step 302 is performed, but with a waiting time Δt, ensuring that the frequency variation of the clock signal output by the generator does not exceed Δf / Δt. This is necessary for many applications because, for example, the maximum value of this parameter is defined by the original standard. Another reason is that an excessively high Δf / Δt value may cause clock re-establishment problems in the downstream CDR circuit (i.e., the standard protocol circuit 150 that receives the reconstructed signal).

[0100] Figure 2 and Figure 3 The example shown allows the frequency of the retransmission clock signal (Retransmission_Clock) to be synchronized with the frequency at which data arrives at the input of storage element 208.

[0101] Figure 2 and Figure 3 The example shown further allows the use of non-standard channels that are completely independent of the standard 110 protocol; in other words, they are called "orthogonal".

[0102] Figure 2 and Figure 3 The example shown also allows standard protocols to implement spread spectrum clocks (SSC).

[0103] Figure 2 and Figure 3 The example shown also has the advantage of providing a parameterized solution, because parameters such as the size of storage element 208, thresholds E and F, and element Δf and Δt are configurable. These parameters can be adjusted to modify the transmission delay of the transmission chain or the characteristics of the re-conversion clock signal.

[0104] Figure 2 and Figure 3The example shown allows for robust reconstruction of the reconverted clock signal, even if the Channel 130 clock signal (Channel Clk) is faster than the standard protocol clock signal (Source_Clock), which opens the door to new applications such as time-division multiplexing of multiple data streams.

[0105] Figure 4 A schematic diagram of one embodiment is shown in the form of a functional circuit. Figure 1 An example of data transmission chain 101 is shown. Figure 4 The data transmission chain 101 shown ensures data transmission between electronic device 400 (here, a computer) and electronic device 430 (here, a smartphone).

[0106] Figure 4 The data transmission chain 101 shown includes two electronic devices 401 and 403, which communicate wirelessly with each other via radio frequency channel 130.

[0107] In the example shown, computer 400 is coupled to the USB-C- (or USB-3-) type physical interface 402 (USB-C PHY) of electronic device 401 via a USB cable of type USB3 (or USB-C), which implements the standard USB3 protocol.

[0108] In the example shown, physical interface 402 is coupled to conversion circuit 120, which is... Figure 1 or Figure 2 The conversion circuits shown are similar or identical.

[0109] exist Figure 4 In transmission chain 101, non-standard channel 130 includes transmitter circuit 410 (RF transmitter), implemented in device 401, which modulates and transmits modulated RF waves while taking into account the non-standard protocol after protocol conversion implemented by circuit 120. Non-standard channel 130 also includes receiver circuit 420 (RF receiver), implemented in device 403, which receives, demodulates, and processes RF waves received from device 401.

[0110] In the example shown, circuit 420 is coupled to circuit 140 implemented in device 403. At the output of conversion circuit 140, the standard protocol USB-C, which was originally present at the input of device 401, is reconstructed and sent to the USB-C- (or USB-3-) type physical interface 450 (USB-C PHY) of electronic device 403, which implements the standard protocol USB3.

[0111] In the example shown, a USB-C or USB3 type cable couples the physical interface 450 to the electronic device 430.

[0112] Figure 4 Examples of this allow for fast and robust data transfer between two electronic devices that use standard serial protocols, for instance, using non-standard protocols.

[0113] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variations exist. Specifically, circuit 210 and generator 212 can be implemented as a single circuit.

[0114] Finally, based on the functional description provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art. Specifically, those skilled in the art will be able to adjust the frequency setpoint f not only based on information about the filling of storage element 208, but also based on other information about the operation of non-standard channels or standard protocol 110.

[0115] Applications of the described embodiments include, for example, the automotive field, or any application that requires the transmission of standard protocols over non-standard protocols.

Claims

1. An electronic device, comprising: A first circuit is configured to convert data transmitted according to a first data transmission protocol into data transmitted according to a second data transmission protocol, wherein the first circuit includes: A first-in, first-out (FIFO) storage element having an input configured to receive data transmitted according to the first data transmission protocol; The first frequency of the first clock signal used by the first circuit to convert the data is based at least on the second frequency of the second clock signal of the second data transmission protocol and information about the filling of the first-in-first-out memory element.

2. The device according to claim 1, further comprising: Second circuit; as well as A generator for the first clock signal, wherein the generator is configured to generate the first clock signal based on a setpoint generated by the second circuit; as well as The second circuit is configured to determine the information regarding the filling of the first-in-first-out (FIFO) memory element and generate the set point based on the information regarding the filling of the FIFO memory element.

3. The device of claim 1, wherein the information regarding the filling of the first-in-first-out (FIFO) memory element is determined based on the fill rate and the output rate of the FIFO memory element.

4. The device of claim 3, wherein the first-in-first-out storage element is configured to be half-filled during the initialization phase.

5. The device of claim 1, wherein the information regarding the fill of the first-in-first-out (FIFO) memory element is determined based on the change in fill over a given time period.

6. The device of claim 1, wherein the information regarding the filling of the first-in-first-out (FIFO) memory element is determined based on the read pointer of the memory element.

7. The device of claim 1, wherein the first frequency is greater than the second frequency when the value of the fill of the first-in-first-out memory element is greater than a first threshold, and the first frequency is less than the second frequency when the value of the fill of the first-in-first-out memory element is less than the second threshold.

8. The device of claim 7, wherein the second frequency is configured to vary periodically.

9. The device of claim 8, wherein the second frequency is configured to vary according to a spread spectrum clock protocol, and wherein the first frequency is adapted according to the spread spectrum clock protocol.

10. The device of claim 1, wherein the first frequency is based on the second frequency plus or minus a value based on the information about the filling of the first-in-first-out memory element.

11. The device of claim 10, wherein the first frequency is adjusted such that the first-in-first-out storage element is never empty and never full.

12. The device of claim 10, wherein the first frequency is updated when the value change based on the information regarding the filling of the first-in-first-out memory element exceeds a threshold.

13. The device according to claim 12, wherein, After updating the first frequency, a given time delay is applied, and then the information regarding the filling of the first-in-first-out memory element is determined again.

14. The device of claim 1, wherein the first-in-first-out storage element is one of the following: a memory or a set of registers.

15. The device of claim 1, wherein the second data transmission protocol is a protocol selected from the group consisting of: USB3®, USB4®, DisplayPort®, and Ethernet®.

16. The device of claim 1, wherein the first data transmission protocol is implemented by one of the following coupled to an input of the first-in-first-out storage element: a radio frequency channel, an optical channel, or a waveguide.

17. The device of claim 1, wherein the first frequency is further based on measurement information, determination information, or predetermined information related to the second data transmission protocol.

18. An apparatus comprising: A first device, the first device comprising: The first physical interface implements a standard data transmission protocol and is configured to be coupled to a connector compatible with the standard data transmission protocol; A first conversion circuit, coupled to the first physical interface and configured to perform conversion from the standard data transmission protocol to a non-standard data transmission protocol; and A transmitter for a non-standard channel, coupled to the output of the first conversion circuit and configured to use the non-standard data transmission protocol; and A second device, the second device comprising: The receiver for the non-standard channel is configured to use the non-standard data transmission protocol; A second conversion circuit is coupled to the receiver and configured to perform the conversion from the non-standard data transmission protocol to the standard data transmission protocol; The second physical interface implements the standard data transmission protocol and is configured to be coupled to a connector compatible with the standard data transmission protocol; The second conversion circuit includes circuitry for conversion, the conversion circuitry being configured to convert data transmitted according to the non-standard data transmission protocol into data transmitted according to the standard data transmission protocol, wherein the conversion circuitry includes: A first-in, first-out (FIFO) storage element having an input configured to receive data transmitted according to the non-standard data transmission protocol; The first frequency of the first clock signal used by the circuit configured for conversion is based at least on the second frequency of the clock signal of the non-standard data transmission protocol and information regarding the filling of the first-in-first-out memory element.

19. The device of claim 18, wherein the first frequency is further based on measurement information, determination information, or predetermined information related to the standard data transmission protocol, and wherein the measurement information related to the standard data transmission protocol is measured in the first device and transmitted to the second device via the non-standard channel for use by the circuit configured for conversion.

20. A method for transmitting data from an electronic device, comprising: The first conversion circuit converts data transmitted according to the first data transmission protocol into data transmitted according to the second data transmission protocol. The first conversion circuit includes a first-in-first-out (FIFO) storage element configured to receive the data transmitted according to the first data transmission protocol. as well as The first frequency of the first clock signal used by the first conversion circuit is adjusted based at least on the second frequency of the second clock signal of the data transmitted according to the second data transmission protocol and information about the filling of the first-in-first-out memory element.

21. The method of claim 20, further comprising: The information regarding the filling rate of the first-in-first-out (FIFO) memory element is determined based on the fill rate and output rate of the FIFO memory element. Wherein, when the value of the fill of the first-in-first-out memory element is greater than a first threshold, the first frequency is greater than the second frequency, and wherein when the value of the fill of the first-in-first-out memory element is less than a second threshold, the first frequency is less than the second frequency.

22. The method of claim 20, wherein the first frequency is based on the second frequency plus or minus a value based on the information about the filling of the first-in-first-out memory element.

23. The method of claim 20, wherein the first frequency is adjusted such that the first-in-first-out memory element is never empty and never full.

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