A communication method and apparatus

Abstract

The application provides a communication method applied to a MAC module. The MAC module comprises a first interface connected with a first PHY chip and a second PHY chip. The MAC module sends a first clock signal to the first PHY chip and the second PHY chip through the first interface, and the first clock signal is used for determining a first time slot and a second time slot. The MAC module sends first data to the first PHY chip and the second PHY chip through the first interface, and the first data comprises a first part of data and a second part of data, the first part of data is data sent by the MAC module in the first time slot, and the second part of data is data sent by the MAC module in the second time slot. By using the method, the interconnection between the first interface and the plurality of PHY chips is realized, and the MAC module can normally communicate with the plurality of PHY chips connected with the first interface, so that the requirement of the MAC chip and the plurality of PHY chips is met.

Description

Technical Field

[0001] This application relates to the field of communications, and in particular to a communication method and apparatus. Background Technology

[0002] With the increasing prevalence of low-speed Ethernet technologies, such as single-pair Ethernet (SPE), in industrial, IoT, and automotive applications, there is a growing demand for media access control (MAC) chips to interface with multiple Ethernet physical layer (PHY) chips.

[0003] Currently, the need for the aforementioned MAC chip to interface with multiple Ethernet PHY chips cannot be met.

[0004] Therefore, a solution is urgently needed to address the above problems. Summary of the Invention

[0005] This application provides a communication method that enables the MAC chip to interface with multiple PHY chips.

[0006] Firstly, this application provides a communication method applied to a MAC module, wherein the MAC module can be a MAC chip or a component (e.g., circuitry) on the MAC chip. The MAC module includes a first interface, which connects to a first PHY chip and a second PHY chip. That is, the first interface connects to both the first and second PHY chips, enabling interconnection between the first interface and multiple PHY chips. This allows the MAC chip to connect to more PHY chips based on a limited number of interfaces, satisfying the need for the MAC chip to interface with multiple PHY chips. When the first interface connects to both the first and second PHY chips, the MAC module can send a first clock signal to both the first and second PHY chips through the first interface. The first clock signal is used to determine a first time slot and a second time slot. Furthermore, the MAC module sends first data to both the first and second PHY chips through the first interface. The first data includes a first portion of data and a second portion of data. The first portion of data is the data sent by the MAC module in the aforementioned first time slot, and the second portion of data is the data sent by the MAC module in the aforementioned second time slot. In this configuration, the first part of the data is destined for the first PHY chip, and the second part of the data is destined for the second PHY chip. In other words, when the first interface is connected to both the first and second PHY chips, the MAC module can send the first part of the data, destined for the first PHY chip, through the first interface in the first time slot, and send the second part of the data, destined for the second PHY chip, through the first interface in the second time slot. This enables the MAC module to send data to both the first and second PHY chips connected to the first interface, thus ensuring that the MAC module can communicate normally with both the first and second PHY chips.

[0007] In one possible implementation, the first interface includes a clock pin, which is connected to the clock pins of the first PHY chip and the second PHY chip. In this scenario,

[0008] The MAC module can send the first clock signal to the clock pins of the first PHY chip and the second PHY chip through the clock pin of the first interface. That is, the first interface can send clock signals to multiple PHY chips through its own clock pin, instead of sending clock signals to different PHY chips separately through multiple clock pins. This solution effectively saves the number of pins of the first interface and correspondingly reduces the cost of the MAC module.

[0009] In one possible implementation, the first interface includes a transmit data pin, which connects to the transmit data pins of the first PHY chip and the second PHY chip. In this scenario, the MAC module can transmit the first data to the transmit data pins of both the first and second PHY chips via the transmit data pin of the first interface. That is, the first interface can transmit data to multiple PHY chips via its own transmit data pin, instead of transmitting data to different PHY chips separately via multiple transmit data pins. This solution effectively reduces the number of pins on the first interface, thereby lowering the cost of the MAC module.

[0010] In one possible implementation, the first clock signal is further used to determine a third time slot. Correspondingly, the aforementioned first data also includes management data, which is the data transmitted by the MAC module in the third time slot. In the scenario where the MAC module transmits the first data through the transmit data pin of the first interface, this transmit data pin, in addition to transmitting the aforementioned first and second parts of data, can also be used to transmit management data. In this way, the first interface does not need to reserve a pin for transmitting management data; by transmitting management data through the transmit data pin, in-band transmission of management data is achieved, further saving the number of pins on the first interface and reducing the cost of the MAC module.

[0011] In one possible implementation, the first clock signal is further used to determine a fourth time slot, and the first data includes time slot synchronization data, which is data sent by the MAC module in the fourth time slot. The time slot synchronization data is used by the PHY chip connected to the first interface to determine its corresponding time slot. For example, the time slot synchronization data is used by the first PHY chip to determine the first time slot and by the second PHY chip to determine the second time slot, thereby enabling normal communication between the MAC module and its connected PHY chips.

[0012] In one possible implementation, the MAC module can also send a first data validity indication message to the first PHY chip and the second PHY chip through the first interface. The first data validity indication message is used to indicate valid data in the first data, so that the first PHY chip and the second PHY chip can perform corresponding data processing operations according to the received data validity indication message, so as to correctly receive the data sent by the first interface with themselves as the destination receiving end.

[0013] In one possible implementation, the first interface includes a transmit enable pin, which connects to the transmit enable pins of the first PHY chip and the second PHY chip. In this scenario, the MAC module can send first data valid indication information to the transmit enable pins of the first PHY chip and the second PHY chip via the transmit enable pin of the first interface. That is, the first interface can send first data valid indication information to multiple PHY chips via its own transmit enable pin, instead of sending corresponding data valid indication information to different PHY chips separately via multiple transmit enable pins. This solution effectively saves the number of pins on the first interface, thereby reducing the cost of the MAC module.

[0014] In one possible implementation, the first part of the data can be obtained from data sent via a second interface, and the second part of the data can be obtained from data sent via a third interface. Both the second and third interfaces are MII, RMII, GMII, or RGMII. The second interface is an interface that requires communication with the first PHY chip, and the destination receiving end of the data sent via the second interface is the first PHY chip. Similarly, the third interface is an interface that requires communication with the second PHY chip, and the destination receiving end of the data sent via the third interface is the second PHY chip. Both the second and third interfaces can be logical interfaces. In scenarios where both the second and third interfaces require communication with the first PHY chip, this application allows the first interface to connect to both the first and second PHY chips, enabling the MAC chip to connect to more PHY chips while saving MAC chip pins.

[0015] In one possible implementation, to obtain the first part of data based on data sent by the second interface, the data sent by the second interface can be directly identified as the first part of data. Similarly, to obtain the second part of data based on data sent by the third interface, the data sent by the third interface can be directly identified as the second part of data.

[0016] In one possible implementation, if the second interface is MII, the data sent by the second interface can be converted into RMII-corresponding data to obtain the first part of the data. In this case, the first part of the data is the RMII-corresponding data. Similarly, if the third interface is MII, the data sent by the third interface can be converted into RMII-corresponding data to obtain the second part of the data. In this case, the second part of the data is the RMII-corresponding data. In this case, since RMII has fewer pins than MII, this method reduces the number of pins on the first interface compared to directly identifying the data sent by the second interface as the first part of the data, thereby reducing the cost of the MAC module.

[0017] In one possible implementation, if the second interface is GMII, the data sent by the second interface can be converted into data corresponding to RGMII to obtain the first part of the data. In this case, the first part of the data is the data corresponding to RGMII. Similarly, if the third interface is GMII, the data sent by the third interface can be converted into data corresponding to RGMII to obtain the second part of the data. In this case, the second part of the data is the data corresponding to RGMII. In this case, since RGMII has fewer pins than GMII, this solution can reduce the number of pins on the first interface compared to directly determining the data sent by the second interface as the first part of the data, thereby reducing the cost of the MAC module.

[0018] In one possible implementation, if the first PHY chip and the second PHY chip are incompatible with the first interface, the first data, after being sent via the first interface and processed by serial-to-parallel conversion, is then sent to the first PHY chip and the second PHY chip. In this case, the target data received by the first PHY chip through its own transmit data pin includes the aforementioned first part of the data, and the target data received by the second PHY chip through its own transmit data pin includes the aforementioned second part of the data. In this scenario, the first PHY chip and the second PHY chip can be standard chips, thereby enabling the first interface to interface with standard PHY chips.

[0019] In one possible implementation, if the first PHY chip and the second PHY chip are incompatible with the first interface, the first clock signal, after being sent via the first interface, undergoes multi-phase frequency division to obtain a first divided clock and a second divided clock. The first divided clock is sent to the first PHY chip, and the second divided clock is sent to the second PHY chip. The first divided clock is used by the first PHY chip to obtain the first portion of data from the received data, and the second divided clock is used by the second PHY chip to obtain the second portion of data from the received data. In this scenario, the first PHY chip and the second PHY chip can be standard chips, thereby enabling the first interface to interface with standard PHY chips.

[0020] In one possible implementation, the MAC module can also receive second data sent by the first PHY chip and the second PHY chip through the first interface. The second data includes a third part and a fourth part, where the third part is data received by the first interface in a fifth time slot, and the fourth part is data received by the first interface in a sixth time slot. In this application, in scenarios where the first interface is connected to both the first and second PHY chips, the first interface can receive data sent to it by different PHY chips through different time slots, thereby enabling the first interface to normally receive data sent to it by multiple PHY chips.

[0021] In one possible implementation, the first interface includes a receive data pin, which is connected to the receive data pins of the first PHY chip and the second PHY chip. The MAC module can receive the second data sent by the receive data pins of the first PHY chip and the second PHY chip through the receive data pin of the first interface. That is, the first interface can receive data sent by multiple PHY chips through its own receive data pin, instead of receiving data sent by different PHY chips separately through multiple receive data pins. This solution effectively saves the number of pins of the first interface and correspondingly reduces the cost of the MAC module.

[0022] In one possible implementation, if the first PHY chip and the second PHY chip are compatible with the first interface, then the third part of the data is the data transmitted by the first PHY chip in the fifth time slot, and / or, the fourth part of the data is the data transmitted by the second PHY chip in the sixth time slot. That is, for multiple PHY chips connected to the first interface, different PHY chips transmit data to the receive data pin of the first interface in different time slots, thereby enabling the first interface to correctly receive data from different PHY chips. Furthermore, each of the multiple PHY chips can control its receive data pin to be in a high-impedance state in a time slot not corresponding to its own.

[0023] In one possible implementation, if the first PHY chip and the second PHY chip are standard chips, they are not compatible with the first interface. In this scenario, the data sent by the first PHY chip and the data sent by the second PHY chip are sent to the first interface after parallel-to-serial conversion; or, the data sent by the first PHY chip is processed by a first tri-state buffer and then sent to the first interface in the fifth time slot, and the data sent by the second PHY chip is processed by a second tri-state buffer and then sent to the first interface in the sixth time slot, thereby achieving the interface between the first interface and the standard PHY chip.

[0024] In one possible implementation, the first PHY chip may further send a fourth data validity indication message to the first interface, the fourth data validity indication message being used to indicate valid data in the data sent by the first PHY chip. Similarly, the second PHY chip may further send a fifth data validity indication message to the first interface, the fifth data validity indication message being used to indicate valid data in the data sent by the second PHY chip. Correspondingly, the first interface can receive a second data validity indication message, wherein the second data validity indication message is obtained based on the fourth and fifth data validity indication messages, and the second data validity indication message can indicate valid data in the second data received by the receive data pin of the first interface. As described above, the second data includes a third part of data and a fourth part of data; therefore, the second data validity indication message can indicate whether the third part of data is valid and whether the fourth part of data is valid.

[0025] In one possible implementation, the first interface includes a receive data valid pin, which is connected to the receive data valid pins of the first PHY chip and the second PHY chip. In this scenario, the MAC module receives second data valid indication information sent by the first PHY chip and the second PHY chip through the receive data valid pin of the first interface. That is, the first interface can receive data valid indication information sent by multiple PHY chips through its own receive data valid pin, instead of receiving data valid indication information sent by different PHY chips separately through multiple receive data valid pins. This solution effectively saves the number of pins of the first interface and correspondingly reduces the cost of the MAC module.

[0026] Secondly, this application provides a communication method applied to a first PHY chip. The first PHY chip receives a target clock signal, which is obtained based on a first clock signal sent by a first interface of a MAC module. The first interface is connected to the first PHY chip, and the first clock signal is used to determine a first time slot. Additionally, the first PHY chip also receives target data, which is obtained based on first data sent by the first interface. The first data includes a first portion of data, which is data sent by the MAC module in the first time slot. The destination receiver of the first portion of data is the first PHY chip. The first PHY chip obtains the first portion of data based on the target clock signal and the target data. In one example, the first interface is also connected to a second PHY chip. In this scenario, the first PHY chip can also obtain the first portion of data based on the received target clock signal and target data. In scenarios where the first interface is connected to both the first and second PHY chips, the first PHY chip can communicate normally with the MAC module.

[0027] In one possible implementation, the first clock signal is further used to determine a third time slot, and the first data further includes management data, which is data sent by the MAC module in the third time slot.

[0028] In one possible implementation, the first clock signal is further used to determine a fourth time slot, and the first data further includes time slot synchronization data, which is data sent by the MAC module in the fourth time slot.

[0029] In one possible implementation, the method further includes: receiving third data validity indication information sent by the MAC module, the third data validity indication information being obtained based on first data validity indication information sent by the MAC module, the first data validity indication information being used to indicate valid data in the first data, and the third data validity information being used to indicate valid data in the target data.

[0030] In one possible implementation, the target clock signal is the first clock signal, the target data is the first data, and the step of obtaining the first part of the data based on the target clock signal and the target data includes: determining a first time slot based on the first clock signal, and extracting data corresponding to the first time slot from the first data to obtain the first part of the data.

[0031] In one possible implementation, the target data is the data that was sent to the first PHY chip after the first data was sent via the first interface and then processed by serial-to-parallel conversion.

[0032] In one possible implementation, the target clock is a first frequency-divided clock obtained after the first clock signal is sent via the first interface and then processed by multi-phase frequency division. The first frequency-divided clock is used by the first PHY chip to obtain the first part of the data from the received target data.

[0033] In one possible implementation, the method further includes: sending data to the first interface in the fifth time slot.

[0034] In one possible implementation, the method further includes: sending data to the first interface, wherein the data sent by the first PHY chip and the data sent by the second PHY chip are sent to the first interface after being processed by parallel-to-serial conversion; or, the data sent by the first PHY chip is processed by a first tri-state buffer and then sent to the first interface in a fifth time slot, wherein the first interface is also connected to the second PHY chip.

[0035] In one possible implementation, the method further includes: sending a fourth data validity indication message to the first interface, the fourth data validity indication message being used to indicate valid data in the data sent by the first PHY chip.

[0036] In one possible implementation, the fourth data valid indication information sent by the first PHY chip and the fifth data valid indication information sent by the second PHY chip are sent to the first interface after being processed by parallel-to-serial conversion; or, the fourth data valid indication information sent by the first PHY chip is processed by a first tri-state buffer and the fifth data valid indication information sent by the second PHY chip is processed by a second tri-state buffer before being sent to the first interface.

[0037] Thirdly, this application provides a communication device applied to a MAC module. The MAC module includes a first interface, which is connected to a first physical layer PHY chip and a second PHY chip. The first interface is used to send a first clock signal to the first PHY chip and the second PHY chip, and the first clock signal is used to determine a first time slot and a second time slot. The first interface is also used to send first data to the first PHY chip and the second PHY chip. The first data includes a first part of data and a second part of data. The first part of data is the data sent by the MAC module in the first time slot, and the second part of data is the data sent by the MAC module in the second time slot.

[0038] In one possible implementation, the first interface includes a clock pin, which is connected to the clock pins of the first PHY chip and the second PHY chip. The clock pin of the first interface is used to send the first clock signal to the clock pins of the first PHY chip and the second PHY chip.

[0039] In one possible implementation, the first interface includes a transmit data pin, which is connected to the transmit data pins of the first PHY chip and the second PHY chip. The transmit data pin is used to transmit the first data to the transmit data pins of the first PHY chip and the second PHY chip.

[0040] In one possible implementation, the first clock signal is further used to determine a third time slot, and the first data further includes management data, which is data sent by the MAC module in the third time slot.

[0041] In one possible implementation, the first clock signal is further used to determine a fourth time slot, and the first data further includes time slot synchronization data, which is data sent by the MAC module in the fourth time slot.

[0042] In one possible implementation, the first interface is further configured to send first data validity indication information to the first PHY chip and the second PHY chip, the first data validity indication information being used to indicate valid data in the first data.

[0043] In one possible implementation, the first interface includes a transmit enable pin, which is connected to the transmit enable pins of the first PHY chip and the second PHY chip. The transmit enable pin of the first interface is used to send first data valid indication information to the transmit enable pins of the first PHY chip and the second PHY chip.

[0044] In one possible implementation, the apparatus further includes a processing unit configured to: obtain the first portion of data based on data sent from a second interface, wherein the second interface is: a Media Independent Interface (MII), or a Reduced Media Independent Interface (RMII), or a Gigabit Media Independent Interface (GMII), or a Reduced Gigabit Media Independent Interface (RGMII); and obtain the second portion of data based on data sent from a third interface, wherein the third interface is MII, RMII, GMII, or RGMII.

[0045] In one possible implementation, the processing unit is configured to: determine the data sent by the second interface as the first part of the data; or, if the second interface is MII, convert the data sent by the second interface into data corresponding to a simplified Media Independent Interface (RMII) to obtain the first part of the data; or, if the second interface is GMII, convert the data sent by the second interface into data corresponding to a simplified Gigabit Media Independent Interface (RGMII) to obtain the first part of the data.

[0046] In one possible implementation, the first data is sent via the first interface, then processed by serial-to-parallel conversion, and finally sent to the first PHY chip and the second PHY chip.

[0047] In one possible implementation, after the first clock signal is sent via the first interface, it is processed by multi-phase frequency division to obtain a first divided clock and a second divided clock. The first divided clock is sent to the first PHY chip, and the second divided clock is sent to the second PHY chip. The first divided clock is used by the first PHY chip to obtain the first part of the data from the received data, and the second divided clock is used by the second PHY chip to obtain the second part of the data from the received data.

[0048] In one possible implementation, the first interface is further configured to receive second data sent by the first PHY chip and the second PHY chip. The second data includes a third part of data and a fourth part of data. The third part of data is data received by the first interface in a fifth time slot, and the fourth part of data is data received by the first interface in a sixth time slot.

[0049] In one possible implementation, the first interface includes a receive data pin, which is connected to the receive data pins of the first PHY chip and the second PHY chip. The receive data pin of the first interface is used to receive the second data sent by the receive data pins of the first PHY chip and the second PHY chip.

[0050] In one possible implementation, the third portion of the data is the data transmitted by the first PHY chip in the fifth time slot, and / or the fourth portion of the data is the data transmitted by the second PHY chip in the sixth time slot.

[0051] In one possible implementation, the data sent by the first PHY chip and the data sent by the second PHY chip are sent to the first interface after being processed by parallel-to-serial conversion; or, the data sent by the first PHY chip is sent to the first interface in the fifth time slot after being processed by a first tri-state buffer, and the data sent by the second PHY chip is sent to the first interface in the sixth time slot after being processed by a second tri-state buffer.

[0052] In one possible implementation, the first interface is further configured to receive second data validity indication information sent by the first PHY chip and the second PHY chip, wherein the second data validity indication information is used to indicate valid data in the second data.

[0053] In one possible implementation, the first interface includes a receive data valid pin, which is connected to the receive data valid pin of the first PHY chip and the receive data valid pin of the second PHY chip. The receive data valid pin of the first interface is used to receive second data valid indication information sent by the first PHY chip and the second PHY chip.

[0054] Fourthly, this application provides a communication device applied to a first physical layer PHY chip. The device includes: a receiving unit for receiving a target clock signal, the target clock signal being obtained based on a first clock signal sent by a first interface of a MAC module, the first interface being connected to the first PHY chip, and the first clock signal being used to determine a first time slot; the receiving unit is further configured to receive target data, the target data being obtained based on first data sent by the first interface, the first data including a first portion of data, the first portion of data being data sent by the MAC module in the first time slot; and a processing unit for acquiring the first portion of data based on the target clock signal and the target data.

[0055] In one possible implementation, the first clock signal is further used to determine a third time slot, and the first data further includes management data, which is data sent by the MAC module in the third time slot.

[0056] In one possible implementation, the first clock signal is further used to determine a fourth time slot, and the first data further includes time slot synchronization data, which is data sent by the MAC module in the fourth time slot.

[0057] In one possible implementation, the receiving unit is further configured to receive third data validity indication information sent by the MAC module. The third data validity indication information is obtained based on first data validity indication information sent by the MAC module. The first data validity indication information is used to indicate valid data in the first data, and the third data validity information is used to indicate valid data in the target data.

[0058] In one possible implementation, the target clock signal is the first clock signal, the target data is the first data, and the processing unit is configured to: determine a first time slot based on the first clock signal, and extract data corresponding to the first time slot from the first data to obtain the first part of the data.

[0059] In one possible implementation, the target data is the data that was sent to the first PHY chip after the first data was sent via the first interface and then processed by serial-to-parallel conversion.

[0060] In one possible implementation, the target clock is a first frequency-divided clock obtained after the first clock signal is sent via the first interface and then processed by multi-phase frequency division. The first frequency-divided clock is used by the first PHY chip to obtain the first part of the data from the received target data.

[0061] In one possible implementation, the apparatus further includes a transmitting unit for transmitting data to the first interface in a fifth time slot.

[0062] In one possible implementation, the apparatus further includes: a transmitting unit for transmitting data to the first interface, wherein the data transmitted by the first PHY chip and the data transmitted by the second PHY chip are transmitted to the first interface after being processed by parallel-to-serial conversion; or, the data transmitted by the first PHY chip is transmitted to the first interface in a fifth time slot after being processed by a first tri-state buffer, wherein the first interface is also connected to the second PHY chip.

[0063] In one possible implementation, the sending unit is further configured to: send a fourth data validity indication information to the first interface, the fourth data validity indication information being used to indicate valid data in the data sent by the first PHY chip.

[0064] In one possible implementation, the fourth data valid indication information sent by the first PHY chip and the fifth data valid indication information sent by the second PHY chip are sent to the first interface after being processed by parallel-to-serial conversion; or, the fourth data valid indication information sent by the first PHY chip is processed by a first tri-state buffer and the fifth data valid indication information sent by the second PHY chip is processed by a second tri-state buffer before being sent to the first interface.

[0065] Fifthly, this application provides a Media Access Control (MAC) module, the MAC module including a first interface, the first interface being connected to a first physical layer PHY chip and a second PHY chip.

[0066] In one possible implementation, the first interface includes a clock pin, which is connected to the clock pins of the first PHY chip and the second PHY chip.

[0067] In one possible implementation, the first interface includes a transmit data pin, which is connected to the transmit data pins of the first PHY chip and the second PHY chip.

[0068] In one possible implementation, the first interface includes a transmit enable pin, which is connected to the transmit enable pin of the first PHY chip and the transmit enable pin of the second PHY chip.

[0069] In one possible implementation, the first interface includes a receive data pin, which is connected to the receive data pins of the first PHY chip and the second PHY chip.

[0070] In one possible implementation, the first interface includes a receive data valid pin, which is connected to the receive data valid pin of the first PHY chip and the receive data valid pin of the second PHY chip.

[0071] Sixthly, embodiments of this application provide a communication device, including a communication interface and a processor connected to the communication interface. The communication interface is used to perform transmit / receive operations as described in the first aspect and any one of the methods described in the first aspect above, and the processor is used to perform other operations as described in the first aspect and any one of the methods described in the first aspect above, excluding the transmit / receive operations. Alternatively, the communication interface is used to perform transmit / receive operations as described in the second aspect and any one of the methods described in the second aspect above, and the processor is used to perform other operations as described in the second aspect and any one of the methods described in the second aspect above, excluding the transmit / receive operations.

[0072] In a seventh aspect, this application provides a chip including an interface circuit and a processing circuit, the chip being configured to perform the method described in the first aspect and any one of the first aspects above; wherein the interface circuit is configured to receive and / or transmit data, and the processing circuit is configured to perform data processing. Alternatively, the chip is configured to perform the method described in the second aspect and any one of the second aspects above; wherein the interface circuit is configured to receive and / or transmit data, and the processing circuit is configured to perform data processing.

[0073] Eighthly, embodiments of this application provide a computer-readable storage medium, including instructions or a computer program that, when executed on a processor, implements the method described in the first aspect and any one of the first aspects above. Alternatively, when executed on a processor, the instructions or computer program implements the method described in the second aspect and any one of the first aspects above.

[0074] Ninthly, embodiments of this application provide a computer program product, including a computer program product that, when run on a processor, implements the method described in the first aspect and any one of the first aspects above. Alternatively, when run on a processor, it implements the method described in the second aspect and any one of the second aspects above. Attached Figure Description

[0075] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0076] Figure 1a A schematic diagram illustrating a scenario where a network device extends low-speed Ethernet access is shown.

[0077] Figure 1b A schematic diagram of an Ethernet access scenario for an MCU chip is shown.

[0078] Figure 2 A flowchart illustrating a communication method provided in an embodiment of this application;

[0079] Figure 3 A flowchart illustrating yet another communication method provided in an embodiment of this application;

[0080] Figure 4a This is a schematic diagram illustrating the connection between a first interface and a PHY chip, provided in an embodiment of this application.

[0081] Figure 4b A schematic diagram illustrating the first interface providing data transmission to the PHY chip in an embodiment of this application;

[0082] Figure 4c A schematic diagram illustrating the first interface receiving data sent by the PHY chip, as provided in an embodiment of this application;

[0083] Figure 5a A schematic diagram showing another connection between the first interface and the PHY chip provided in an embodiment of this application;

[0084] Figure 5b A schematic diagram illustrating another instance of a first interface connected to a PHY chip, provided in an embodiment of this application.

[0085] Figure 6 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0086] Figure 7 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0087] Figure 8 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0088] Figure 9 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0089] This application provides a communication method that enables the MAC chip to interface with multiple PHY chips.

[0090] Currently, there is a need for MAC chips to interface with multiple PHY chips.

[0091] In one example, the MAC chip can be the MAC chip on a network device such as a switch. In smart park IoT access scenarios, there is a need for integrated office and IoT networking. Therefore, the MAC chip on the network device needs to support the connection of more PHY chips without affecting the traditional BASE-T chip access, thereby improving IoT access capabilities. Additionally, in the process industry, advanced physical layer (APL) switches use 10BASE-T1L PHY chips, requiring low complexity and small size to support placement within a chassis. Multiple PHY chips interface with the MAC chip to enable interconnection between more instruments and the MAC chip. (See reference...) Figure 1a To understand, Figure 1a This diagram illustrates a scenario where a network device extends low-speed Ethernet access. For example... Figure 1a As shown, the MAC chip on the switch needs to be interconnected with the traditional BASE-T chip. In addition, the MAC chip on the switch also needs to be interconnected with the 10BASE-T1L PHY chip to improve the IoT access capability of the switch.

[0092] Currently, the number of pins on MAC chips in network devices is limited. Therefore, switching chips in network devices generally use serial interfaces such as Serial Gigabit Media Independent Interface (SGMII) to interconnect with traditional BASE-T chips, effectively utilizing the limited number of pins on the MAC chip. Because the number of pins on a MAC chip is limited, and PHY chips typically use parallel interfaces such as Media Independent Interface (MII), Reduced Media-Independent Interface (RMII), or Reduced Gigabit Media Independent Interface (RGMII), which require more pins, MAC chips cannot support interconnection with a large number of PHY chips (such as 10BASE-T1L PHY chips). Furthermore, the number of pins on a MAC chip is related to its cost; more pins mean higher costs. Therefore, using a MAC chip with more pins to achieve interconnection with the PHY chip would result in higher costs.

[0093] In another example, the MAC chip can be a core chip on an edge device. The edge device mentioned here can be a terminal device (e.g., an instrument) or a server; this application does not limit this. In this scenario, a typical implementation of the MAC chip is a microcontroller unit (MCU). MCUs typically support many traditional IoT interfaces, such as RS485, RS232, and Controller Area Network (CAN). However, due to limitations in chip complexity, pin count, power consumption, and cost, MCUs typically use parallel interfaces such as MII, RMII, or RGMII. Parallel interfaces require more pins than serial interfaces. Therefore, in Ethernet-based access scenarios for MCU chips, an MCU typically only supports one Ethernet port, meaning it can only interface with one PHY chip and cannot interface with multiple PHY chips. (See reference...) Figure 1b To understand, such as Figure 1b As shown, Figure 1b This diagram illustrates an Ethernet-based access scenario for an MCU chip. (For example...) Figure 1bAs shown, MCU chips have the requirement to interface with multiple PHY chips, but currently, MCU chips only support interface with one PHY chip, and their requirement to interface with multiple PHY chips cannot be met.

[0094] Based on this, this application provides a communication method and apparatus that can satisfy the need for a MAC chip to interface with multiple PHY chips even when the number of pins on the MAC chip is limited. The multiple PHY chips mentioned herein include, but are not limited to, low-speed Ethernet PHY chips.

[0095] See Figure 2 , Figure 2 This is a flowchart illustrating a communication method provided in an embodiment of this application.

[0096] Figure 2 The method shown is applied to a MAC module, which can be a MAC chip or a component on a MAC chip. For example, the MAC module is a part of the circuitry on the MAC chip. The MAC chip can be a MAC chip on a network device such as a switch, or a MAC chip on an end-side device; this application does not specifically limit the application to this method.

[0097] In this application, the MAC module includes a first interface. The connection method of this first interface differs from conventional technology. In conventional technology, one interface on a MAC chip can only connect to one PHY chip. However, in this application, the first interface can connect to multiple PHY chips simultaneously. The first PHY chip and the second PHY chip are two of these multiple PHY chips. That is, the first interface connects to both the first and second PHY chips, or in other words, the first interface connects to both the first and second PHY chips.

[0098] Figure 2 The method shown includes S101 and S102 as follows. Although S101 is described before S102 below, this does not mean that S101 is executed before S102. In practice, S101 and S102 can be considered to be executed almost simultaneously.

[0099] S101: The MAC module sends a first clock signal to the first PHY chip and the second PHY chip through the first interface. The first clock signal is used to determine the first time slot and the second time slot.

[0100] In one example, the first interface includes a clock pin, which is an output pin used to transmit a clock signal. Similarly, both the first PHY chip and the second PHY chip have clock pins; the clock pin of the first PHY chip is an input pin used to receive a clock signal, and similarly, the clock pin of the second PHY chip is also an input pin used to receive a clock signal. In this application, the clock pin of the first interface is connected to both the clock pin of the first PHY chip and the clock pin of the second PHY chip.

[0101] When the clock pin of the first interface is connected to both the clock pin of the first PHY chip and the clock pin of the second PHY chip, in a specific implementation of S101, the MAC module can send a first clock signal to the clock pin of the first PHY chip through the clock pin of the first interface. Similarly, the MAC module can send a first clock signal to the clock pin of the second PHY chip through the clock pin of the first interface.

[0102] In this application, the clock pin of the first interface is connected to the clock pin of the first PHY chip. This connection can be direct, or it can be achieved through other devices. For example, a multi-phase frequency divider may be included between the clock pin of the first interface and the clock pin of the first PHY chip. The clock pin of the first interface is connected to the input of this multi-phase frequency divider, and the clock pin of the first PHY chip is connected to the first output of the multi-phase frequency divider.

[0103] Similarly, the clock pin of the first interface is connected to the clock pin of the second PHY chip. This connection can be direct, or it can be achieved through other devices. For example, a multi-phase frequency divider may be included between the clock pin of the first interface and the clock pin of the second PHY chip. The clock pin of the first interface is connected to the input of this multi-phase frequency divider, and the clock pin of the second PHY chip is connected to the second output of the multi-phase frequency divider.

[0104] In a scenario where the clock pin of the first interface is directly connected to the clock pin of the first PHY chip, after the MAC module sends the first clock signal through the first interface, the target clock signal received by the first PHY chip is the first clock signal. Similarly, in a scenario where the clock pin of the first interface is directly connected to the clock pin of the second PHY chip, after the MAC module sends the first clock signal through the first interface, the target clock signal received by the second PHY chip is the first clock signal.

[0105] In a scenario where the clock pin of the first interface is connected to the clock pin of the first PHY chip via other devices, after the MAC module sends a first clock signal through the first interface, the first clock signal is processed by the device between the clock pin of the first interface and the clock pin of the first PHY chip before being sent to the clock pin of the first PHY chip. In a specific example, after the MAC module sends the first clock signal through the first interface, the first clock signal is processed by the aforementioned multi-phase frequency divider to obtain a first frequency-divided clock, which is then sent to the first PHY chip. The clock frequency of the first frequency-divided clock is lower than the clock frequency of the first clock signal. For example, in a scenario where the first interface connects to M PHY chips, the clock frequency of the first clock signal is, for example, greater than or equal to M times the clock frequency of the first frequency-divided clock, where M is an integer greater than or equal to 2.

[0106] Similarly, in a scenario where the clock pin of the first interface is connected to the clock pin of the second PHY chip via other devices, after the MAC module sends a first clock signal through the first interface, this clock signal is processed by the device between the clock pin of the first interface and the second PHY chip before being sent to the clock pin of the second PHY chip. In a specific example, after the MAC module sends the first clock signal through the first interface, the first clock signal is processed by the aforementioned multi-phase frequency divider to obtain a second frequency-divided clock, which is then sent to the second PHY chip. The clock frequency of the second frequency-divided clock is lower than the clock frequency of the first clock signal, and the clock frequency of the second frequency-divided clock is the same as the clock frequency of the first frequency-divided clock. The phase of the first frequency-divided clock and the phase of the second frequency-divided clock differ by N clock cycles of the first clock signal, where N is a positive integer less than or equal to M-1.

[0107] S102: The MAC module sends first data to the first PHY chip and the second PHY chip through the first interface. The first data includes a first part of data and a second part of data. The first part of data is the data sent by the MAC module in the first time slot, and the second part of data is the data sent by the MAC module in the second time slot.

[0108] In one example, the first interface includes a transmit data pin for transmitting data. Similarly, both the first PHY chip and the second PHY chip have transmit data pins. In this application, the transmit data pin of the first interface is connected to both the transmit data pins of the first PHY chip and the transmit data pin of the second PHY chip. It should be noted that the transmit data pin of the first interface is an output pin, through which the first interface transmits data. The transmit data pin of the first PHY chip is an input pin for receiving data. Similarly, the transmit data pin of the second PHY chip is an input pin for receiving data.

[0109] When the transmit data pin of the first interface is connected to both the transmit data pin of the first PHY chip and the transmit data pin of the second PHY chip, in a specific implementation of S102, the MAC module can send first data to the transmit data pin of the first PHY chip through the transmit data pin of the first interface. Similarly, the MAC module can send first data to the transmit data pin of the second PHY chip through the transmit data pin of the first interface.

[0110] In this application, the transmit data pin of the first interface is connected to the transmit data pin of the first PHY chip. This connection can be direct, or it can be achieved through other devices. For example, a serial-to-parallel converter may be included between the transmit data pin of the first interface and the transmit data pin of the first PHY chip. The transmit data pin of the first interface is connected to the first input terminal of this converter, and the transmit data pin of the first PHY chip is connected to the first output terminal of the converter.

[0111] Similarly, the transmit data pins of the first interface are connected to the transmit data pins of the second PHY chip. This connection can be direct, or it can be achieved through other devices. For example, a serial-to-parallel converter may be included between the transmit data pins of the first interface and the second PHY chip. The transmit data pins of the first interface are connected to the first input of this converter, and the transmit data pins of the second PHY chip are connected to the second output of the converter.

[0112] In a scenario where the transmit data pin of the first interface is directly connected to the transmit data pin of the first PHY chip, after the MAC module transmits the first data through the first interface, the target data received by the first PHY chip is the first data. Similarly, in a scenario where the transmit data pin of the first interface is directly connected to the transmit data pin of the second PHY chip, after the MAC module transmits the first data through the first interface, the target data received by the second PHY chip is the first data.

[0113] In a scenario where the transmit data pin of the first interface is connected to the transmit data pin of the first PHY chip via other devices, after the MAC module transmits first data through the first interface, the first data is processed by the device between the transmit data pin of the first interface and the transmit data pin of the first PHY chip before being transmitted to the transmit data pin of the first PHY chip. Similarly, in a scenario where the transmit data pin of the first interface is connected to the transmit data pin of the second PHY chip via other devices, after the MAC module transmits first data through the first interface, the first data is processed by the device between the transmit data pin of the first interface and the transmit data pin of the second PHY chip before being transmitted to the transmit data pin of the second PHY chip. In a specific example, after the MAC module transmits the first data through the first interface, the first data is processed by the aforementioned serial-to-parallel conversion processing device to obtain a serial first part of data and a second part of data, wherein the first part of data is transmitted to the transmit data pin of the first PHY chip, and the second part of data is transmitted to the transmit data pin of the second PHY chip. In this scenario, the target data received by the first PHY chip through its own transmit data pin includes the aforementioned first part of the data, and the target data received by the second PHY chip through its own transmit data pin includes the aforementioned second part of the data. In this scenario, the first PHY chip can acquire the received data based on the aforementioned received first divided clock to obtain the first part of the data; similarly, the second PHY chip can acquire the received data based on the aforementioned received second divided clock to obtain the second part of the data.

[0114] Regarding the first part of the data and the second part of the data, they may be data generated by the MAC module based on the communication requirements between the first PHY chip and the second PHY chip.

[0115] In one example, the first part of the data may be obtained from data sent via a second interface, and the second part of the data may be obtained from data sent via a third interface. Both the second and third interfaces are either MII, RMII, GMII, or RGMII. The second interface is the interface that needs to communicate with the first PHY chip, and the destination receiving end of the data sent via the second interface is the first PHY chip. Similarly, the third interface is the interface that needs to communicate with the second PHY chip, and the destination receiving end of the data sent via the third interface is the second PHY chip. Both the second and third interfaces can be logical interfaces. In scenarios where both the second and third interfaces need to communicate with the first PHY chip, conventional technologies require deploying separate interfaces for communication with the first and second PHY chips on the MAC chip. However, in this application, the first interface can connect to both the first and second PHY chips, allowing the MAC chip to connect to more PHY chips while saving MAC chip pins.

[0116] In one example, to obtain the first part of data based on data sent by the second interface, in a specific implementation, the data sent by the second interface can be directly identified as the first part of data. Similarly, to obtain the second part of data based on data sent by the third interface, in a specific implementation, the data sent by the third interface can be directly identified as the second part of data. In this scenario:

[0117] If both the second and third interfaces are MIIs, then the first interface can be considered as a multi-MII obtained by fusing multiple MIIs. Multi-MII can be used to transmit data transmitted by multiple MIIs (such as the second and third interfaces), but the number of pins in multi-MII is close to the number of pins in a single MII, effectively reducing the cost of the MAC module.

[0118] If both the second and third interfaces are RMII, then the first interface can be considered as a multi-RMII obtained by fusing multiple RMIIs. The multi-RMII can be used to transmit data transmitted by multiple RMIIs (such as the second and third interfaces), but the number of pins in the multi-RMII is close to the number of pins in a single RMII, effectively reducing the cost of the MAC module.

[0119] If both the second and third interfaces are GMII, then the first interface can be considered as a multi-GMII obtained by fusing multiple GMIIs. The multi-GMII can be used to transmit data transmitted by multiple GMIIs (such as the second and third interfaces), but the number of pins in the multi-GMII is close to the number of pins in a single GMII, effectively reducing the cost of the MAC module.

[0120] If both the second and third interfaces are RGMIIs, then the first interface can be considered as a multi-RGMII obtained by fusing multiple RGMIIs. The multi-RGMII can be used to transmit data transmitted by multiple RGMIIs (such as the second and third interfaces), but the number of pins in the multi-RGMII is close to the number of pins in a single RGMII, effectively reducing the cost of the MAC module.

[0121] In another example, if the second interface is an MII, the data sent by the second interface can be converted into RMII-corresponding data to obtain the first part of the data. In this case, the first part of the data is the RMII-corresponding data. Similarly, if the third interface is an MII, the data sent by the third interface can be converted into RMII-corresponding data to obtain the second part of the data. In this case, the second part of the data is the RMII-corresponding data. In this scenario, the first interface can be considered as a multi-RMII obtained by fusing multiple RMIIs. In this case, since RMII has fewer pins than MII, this solution can reduce the number of pins on the first interface compared to directly determining the data sent by the second interface as the first part of the data, thereby reducing the cost of the MAC module.

[0122] In another example, if the second interface is GMII, the data sent by the second interface can be converted into data corresponding to RGMII, thus obtaining the first part of the data. In this case, the first part of the data is the data corresponding to RGMII. Similarly, if the third interface is GMII, the data sent by the third interface can be converted into data corresponding to RGMII, thus obtaining the second part of the data. In this case, the second part of the data is the data corresponding to RGMII. In this scenario, the first interface can be considered as a multi-RGMII obtained by fusing multiple RGMIIs. In this case, since RGMII has fewer pins than GMII, this solution can reduce the number of pins on the first interface compared to directly determining the data sent by the second interface as the first part of the data, thereby reducing the cost of the MAC module.

[0123] In one example, the first clock signal is also used to determine a third time slot. Correspondingly, the aforementioned first data also includes management data, which is the data sent by the MAC module in the third time slot. In a scenario where the MAC module sends the first data through the transmit data pin of the first interface, this transmit data pin, in addition to sending the aforementioned first and second parts of data, can also be used to send management data. In this way, the first interface does not need to reserve a pin for transmitting management data; by transmitting management data through the transmit data pin, in-band transmission of management data is achieved, further saving the number of pins on the first interface and reducing the cost of the MAC module. This application does not specifically limit the management data; the management data can be determined according to actual circumstances.

[0124] In one example, the first clock signal is further used to determine a fourth time slot, and the first data also includes time slot synchronization data, which is data sent by the MAC module in the fourth time slot. The time slot synchronization data is used by the first PHY chip to determine the first time slot and by the second PHY chip to determine the second time slot. Specifically, in a scenario where the clock pin of the first interface is directly connected to the clock pin of the first PHY chip, and the clock pin of the first interface is directly connected to the clock pin of the second PHY chip, the time slot synchronization data is used by the first PHY chip to determine the first time slot and by the second PHY chip to determine the second time slot.

[0125] This application does not specifically limit the time slot synchronization data; the time slot synchronization data can be determined according to actual conditions. For example, the MAC module sends data through the first interface according to a certain transmission cycle, wherein each transmission cycle includes several time slots, and these several time slots include at least the aforementioned first time slot, second time slot, and time slot synchronization time slot. For example, the MAC module can send different time slot synchronization data in the time slot synchronization time slots of any two adjacent transmission cycles, so that the first PHY chip and the second PHY chip can locate the transmission cycle, and thus determine the first time slot or the second time slot based on the located transmission cycle. For example, the MAC module sends time slot synchronization data 00 in the time slot synchronization time slot of the current transmission cycle, and sends time slot synchronization data 01 in the time slot synchronization time slot of the next transmission cycle.

[0126] In one example, the MAC module can also send first data validity indication information to the first PHY chip and the second PHY chip through the first interface. The first data validity indication information is used to indicate valid data in the first data. As mentioned above, the first data includes a first part of data and a second part of data. Therefore, the first data validity indication information can indicate whether the first part of data is valid and whether the second part of data is valid. For example, if the value of the first data validity indication information corresponding to the first time slot is 1, it indicates that the first part of data is valid; if the value of the first data validity indication information corresponding to the first time slot is 0, it indicates that the first part of data is invalid. If the value of the first data validity indication information corresponding to the second time slot is 1, it indicates that the second part of data is valid; if the value of the first data validity indication information corresponding to the second time slot is 0, it indicates that the second part of data is invalid.

[0127] Optionally, in a scenario where the first data also includes management data, the first data validity indication information is further used to indicate whether the management data is valid.

[0128] As described above, the aforementioned first data also includes time slot synchronization data. In one example, considering that the function of the time slot synchronization data is to enable the first PHY chip and the second PHY chip to locate the aforementioned transmission cycle, and that it is somewhat different from specific service data such as the first part of data and the second part of data, in one example, in a scenario where the first data also includes time slot synchronization data, the value of the first data validity indication information in the fourth time slot is 0. In another example, the value of the first data validity indication information in the fourth time slot can also be 1. The value of the first data validity indication information in the fourth time slot can be flexibly set according to the actual situation, and this application embodiment does not impose specific limitations.

[0129] In one example, the first interface includes a transmit enable pin, which indicates whether the data transmitted by the transmit data pin of the first interface is valid. Similarly, both the first PHY chip and the second PHY chip have transmit enable pins. In this application, the transmit enable pin of the first interface is connected to both the transmit enable pin of the first PHY chip and the transmit enable pin of the second PHY chip. The transmit enable pin of the first interface is an output pin used to transmit signals. The transmit enable pin of the first PHY chip is an input pin used to receive signals. Similarly, the transmit enable pin of the second PHY chip is an input pin used to receive signals.

[0130] When the transmit enable pin of the first interface is connected to both the transmit enable pin of the first PHY chip and the transmit enable pin of the second PHY chip, the MAC module sends the first data valid indication information to both the first PHY chip and the second PHY chip through the first interface. In specific implementation, the MAC module can send the first data valid indication information to the transmit enable pin of the first PHY chip through the transmit enable pin of the first interface. Similarly, the MAC module can send the first data valid indication information to the transmit enable pin of the second PHY chip through the transmit enable pin of the first interface.

[0131] In this application, the transmit enable pin of the first interface is connected to the transmit enable pin of the first PHY chip. This connection can be direct, or it can be achieved through other devices. For example, a serial-to-parallel converter may be included between the transmit enable pin of the first interface and the transmit enable pin of the first PHY chip. The transmit enable pin of the first interface is connected to the second input of this converter, and the transmit enable pin of the first PHY chip is connected to the third output of the converter.

[0132] Similarly, the transmit enable pin of the first interface is connected to the transmit enable pin of the second PHY chip. This connection can be direct, or it can be achieved through other devices. For example, a serial-to-parallel converter may be included between the transmit enable pins of the first and second PHY chips. The transmit enable pin of the first interface is connected to the second input of this converter, and the transmit enable pin of the second PHY chip is connected to the fourth output of the converter.

[0133] In a scenario where the transmit enable pin of the first interface is directly connected to the transmit enable pin of the first PHY chip, after the MAC module sends the first data valid indication information through the first interface, the third data valid indication information received by the first PHY chip is the first data valid indication information. Similarly, in a scenario where the transmit enable pin of the first interface is directly connected to the transmit enable pin of the second PHY chip, after the MAC module sends the first data valid indication information through the first interface, the sixth data valid indication information received by the second PHY chip is the first data valid indication information.

[0134] In a scenario where the transmit enable pin of the first interface is connected to the transmit enable pin of the first PHY chip via other devices, after the MAC module sends a first data valid indication message through the first interface, this first data valid indication message is processed by the device between the transmit enable pin of the first interface and the transmit enable pin of the first PHY chip before being sent to the transmit enable pin of the first PHY chip. In this scenario, the third data valid indication message received by the first PHY chip is different from the first data valid indication message. The third valid indication message is used to indicate whether the target data received by the transmit data pin of the first PHY chip is valid.

[0135] Similarly, in a scenario where the transmit enable pin of the first interface is connected to the transmit enable pin of the second PHY chip via other devices, after the MAC module sends the first data valid indication information through the first interface, this first data valid indication information is processed by the device between the transmit enable pin of the first interface and the transmit enable pin of the second PHY chip before being sent to the transmit enable pin of the second PHY chip. In this scenario, the sixth data valid indication information received by the second PHY chip is different from the first data valid indication information. The sixth valid indication information is used to indicate whether the target data received by the transmit data pin of the second PHY chip is valid.

[0136] The process of the MAC module sending data to the first PHY chip and the second PHY chip through the first interface has been described above. Next, the data receiving operation performed by the first PHY chip and the second PHY chip will be explained. The data receiving operation performed by the first PHY chip and the second PHY chip follows the same principle. The following explanation will take the first PHY chip as an example.

[0137] For ease of description, the first interface will be referred to as "multi-xMII". As described above, multi-xMII can be multi-MII, multi-RMII, multi-GMII, or multi-RGMII.

[0138] In this application, the first PHY chip and the second PHY chip can be chips compatible with multi-xMII. In this scenario, the first interface can be directly connected to the first PHY chip and the second PHY chip.

[0139] The phrase "the first interface is directly connected to the first PHY chip" means that the pins on the first interface are directly connected to the corresponding pins on the first PHY chip. No other devices are involved in connecting these pins. For example, the clock pin of the first interface is directly connected to the clock pin of the first PHY chip, the transmit data pin of the first interface is directly connected to the transmit data pin of the first PHY chip, and so on. These examples are not listed here. Similarly, the direct connection between the first interface and the second PHY chip will not be repeated here.

[0140] In this application, the first PHY chip and the second PHY chip can also be chips compatible with standard interfaces. For example, the first PHY chip and the second PHY chip can be compatible with standard MII, standard RMII, standard GMII, or standard RGMII. In this scenario, other devices can also be included between the first interface and the first PHY chip. Similarly, other devices can also be included between the first interface and the second PHY chip. In this scenario, this solution does not require modification of the PHY chip, thereby enabling the first interface to interface with multiple standard PHY chips.

[0141] The phrase "other devices between the first interface and the first PHY chip" refers to the connection between pins on the first interface and corresponding pins on the first PHY chip via other devices. For example, the clock pin of the first interface might be connected to the clock pin of the first PHY chip via a multi-phase divider, and the transmit data pin of the first interface might be connected to the transmit data pin of the first PHY chip via a serial-to-parallel converter, and so on. These examples are not listed here. Similarly, the connection between the first interface and the second PHY chip, including other devices, will not be repeated here.

[0142] See Figure 3 This figure is a flowchart illustrating another communication method provided in an embodiment of this application. Figure 3 The method shown is applied to the first PHY chip. Figure 3 The method shown includes the following steps S201-S203.

[0143] S201: The first PHY chip receives a target clock signal, which is obtained based on a first clock signal sent by a first interface of the MAC module. The first interface is connected to the first PHY chip, and the first clock signal is used to determine a first time slot.

[0144] S202: The first PHY chip receives target data, which is obtained based on the first data sent by the first interface. The first data includes a first part of data, which is the data sent by the MAC module in the first time slot.

[0145] For details regarding the connection between the first PHY chip and the MAC module, the target clock signal, and the target data, please refer to the relevant descriptions above; they will not be described in detail here.

[0146] S203: The first PHY chip acquires the first part of the data based on the target clock signal and the target data.

[0147] In one example, if the target clock signal is the first clock signal and the target data is the first data, then in the specific implementation of S203, the first PHY chip can determine the first time slot based on the first clock signal. For example, it can determine the start position of the transmission cycle based on the time slot synchronization data, and determine the first time slot based on the first clock signal and the start position of the transmission cycle. Furthermore, it can extract the data corresponding to the first time slot from the first data to obtain the first part of the data.

[0148] In another example, if the target clock signal is a first frequency divider clock, the first PHY chip can collect the data received by its own transmit data pin based on the first frequency divider clock to obtain the aforementioned first part of the data.

[0149] In a scenario where the first PHY chip also receives a third data valid indication, the first PHY chip can further determine, based on the third data valid indication, whether to acquire the data received by its own transmit data pin based on the target clock signal. As a specific example, if the third data valid indication indicates that the target data received by the first PHY chip is valid, the first PHY chip can acquire the first portion of data based on the target clock signal and the target data. If the third data valid indication indicates that the target data received by the first PHY chip is invalid, the first PHY chip may not perform the operation of acquiring the first portion of data.

[0150] In this application, in addition to sending data to the PHY chip (e.g., the first PHY chip and the second PHY chip) connected to the first interface through the first interface, the MAC module can also receive data sent by the PHY chip connected to the first interface through the first interface.

[0151] As a specific example, the MAC module receives second data sent by a first PHY chip and a second PHY chip through a first interface. The second data includes a third part and a fourth part, wherein the third part is data received by the first interface in a fifth time slot, and the fourth part is data received by the first interface in a sixth time slot. In this application, the third part is data sent by the first PHY chip to the first interface, and the fourth part is data sent by the second PHY chip to the first interface. In this application, in a scenario where the first interface is connected to both the first and second PHY chips, the first interface can receive data sent to it by different PHY chips through different time slots, thereby enabling the first interface to normally receive data sent to it by multiple PHY chips.

[0152] In one example, the first interface includes a receive data pin for receiving data. Similarly, both the first PHY chip and the second PHY chip have receive data pins. In this application, the receive data pin of the first interface is connected to both the receive data pin of the first PHY chip and the receive data pin of the second PHY chip. It should be noted that the receive data pin of the first interface is an input pin used to receive data. The receive data pin of the first PHY chip is an output pin used to transmit data. Similarly, the receive data pin of the second PHY chip is an output pin used to transmit data.

[0153] When the receive data pin of the first interface is connected to both the receive data pin of the first PHY chip and the receive data pin of the second PHY chip, the MAC module can receive and send second data through the receive data pin of the first interface and the receive data pin of the second PHY chip.

[0154] In this application, the receive data pin of the first interface is connected to the receive data pin of the first PHY chip, which can be a direct connection between the receive data pin of the first interface and the receive data pin of the first PHY chip. For example, if the first PHY chip is compatible with multi-xMII, the receive data pin of the first interface is directly connected to the receive data pin of the first PHY chip.

[0155] The receive data pin of the first interface can be connected to the receive data pin of the first PHY chip, or the receive data pin of the first interface can be connected to the receive data pin of the first PHY chip through other devices. For example, when the first PHY chip is a chip compatible with a standard interface, the receive data pin of the first interface can be connected to the receive data pin of the first PHY chip through other devices. As an example, a parallel-to-serial conversion processing device is also included between the receive data pin of the first interface and the receive data pin of the first PHY chip. The receive data pin of the first interface is connected to the first output terminal of the parallel-to-serial conversion processing device, and the receive data pin of the first PHY chip is connected to the first input terminal of the parallel-to-serial conversion processing device. As another example, a first tri-state buffer is included between the receive data pin of the first interface and the receive data pin of the first PHY chip. The tri-state buffer will not be described in detail here.

[0156] Similarly, in this application, the data receiving pin of the first interface is connected to the data receiving pin of the second PHY chip, which can be a direct connection between the data receiving pin of the first interface and the data receiving pin of the second PHY chip. For example, if the second PHY chip is compatible with multi-xMII, the data receiving pin of the first interface can be directly connected to the data receiving pin of the second PHY chip.

[0157] The receive data pin of the first interface can be connected to the receive data pin of the second PHY chip, or the receive data pin of the first interface can be connected to the receive data pin of the second PHY chip through other devices. For example, when the second PHY chip is a chip compatible with a standard interface, the receive data pin of the first interface can be connected to the receive data pin of the second PHY chip through other devices. As an example, a parallel-to-serial conversion processing device is also included between the receive data pin of the first interface and the receive data pin of the second PHY chip. The receive data pin of the first interface is connected to the first output terminal of the parallel-to-serial conversion processing device, and the receive data pin of the second PHY chip is connected to the second input terminal of the parallel-to-serial conversion processing device. As another example, a second tri-state buffer is included between the receive data pin of the first interface and the receive data pin of the second PHY chip.

[0158] In a scenario where the receive data pin of the first interface is directly connected to the receive data pins of both the first and second PHY chips, the third part of the data is the data transmitted by the first PHY chip in the fifth time slot, and the fourth part of the data is the data transmitted by the second PHY chip in the sixth time slot. In this scenario, the first PHY chip can control its receive data pin to be in a high-impedance state in a time slot not corresponding to its own, and the second PHY chip can also control its receive data pin to be in a high-impedance state in a time slot not corresponding to its own. Using this method, different PHY chips transmit data to the receive data pin of the first interface in different time slots, thus enabling the first interface to correctly receive data from different PHY chips.

[0159] In a scenario where the receive data pin of the first interface is connected to the receive data pin of the first PHY chip through other devices, and the receive data pin of the first interface is connected to the receive data pin of the second PHY chip through other devices, the data sent by the first PHY chip through its own receive data pin and the data sent by the second PHY chip through its own receive data pin both need to be processed before being sent to the first interface.

[0160] In one example, if a parallel-to-serial conversion processing device is included between the receive data pins of the first PHY chip and the receive data pins of the first interface, and between the receive data pins of the second PHY chip and the receive data pins of the first interface, then the data sent by the first PHY chip and the data sent by the second PHY chip are sent to the first interface after parallel-to-serial conversion. That is, the parallel-to-serial conversion processing device can convert the parallel data sent by the receive data pins of the first PHY chip and the receive data pins of the second PHY chip into parallel data sent by the second PHY chip.

[0161] In another example, if a first tri-state buffer is included between the receive data pin of the first interface and the receive data pin of the first PHY chip, and a second tri-state buffer is included between the receive data pin of the first interface and the receive data pin of the second PHY chip, then the data sent by the first PHY chip is processed by the first tri-state buffer and sent to the first interface in the fifth time slot, and the data sent by the second PHY chip is processed by the second tri-state buffer and sent to the first interface in the sixth time slot. In this way, the first interface can receive the aforementioned third part of the data in the fifth time slot and the aforementioned fourth part of the data in the sixth time slot.

[0162] In one example, the first PHY chip can also send a fourth data validity indication to the first interface, which indicates valid data in the data sent by the first PHY chip. Alternatively, the fourth data validity indication indicates whether the data sent by the first PHY chip is valid. Similarly, the second PHY chip can also send a fifth data validity indication to the first interface, which indicates valid data in the data sent by the second PHY chip. Correspondingly, the first interface can receive a second data validity indication, which is derived from the fourth and fifth data validity indications. This second data validity indication indicates valid data in the second data received by the receive data pin of the first interface. As described above, the second data includes a third part and a fourth part; therefore, the second data validity indication indicates whether the third part is valid and whether the fourth part is valid.

[0163] In one example, the first interface includes a valid data receive pin, which indicates whether the data received by the first interface's valid data receive pin is valid. Similarly, both the first PHY chip and the second PHY chip have valid data receive pins. In this application, the valid data receive pin of the first interface is connected to both the valid data receive pin of the first PHY chip and the valid data receive pin of the second PHY chip. In this application, the valid data receive pin of the first interface is an input pin used to receive signals. The valid data receive pin of the first PHY chip is an output pin used to transmit signals. Similarly, the valid data receive pin of the second PHY chip is also an output pin used to transmit signals.

[0164] In some scenarios, the receive data valid pin can also be called the carrier sense / receive data valid (CRS_DV) pin.

[0165] In this application, the first PHY chip can send a fourth data validity indication message to the first interface through its own receive data validity pin, and the second PHY chip can send a fifth data validity indication message to the first interface through its own receive data validity pin. Correspondingly, the first interface can receive the second data validity indication message through its own receive data validity pin.

[0166] In this application, the valid data receiving pin of the first interface is connected to the valid data receiving pin of the first PHY chip, or the valid data receiving pin of the first interface is directly connected to the valid data receiving pin of the first PHY chip. For example, if the first PHY chip is compatible with multi-xMII, the valid data receiving pin of the first interface is directly connected to the valid data receiving pin of the first PHY chip.

[0167] The valid data receive pin of the first interface is connected to the valid data receive pin of the first PHY chip, or the valid data receive pin of the first interface can be connected to the valid data receive pin of the first PHY chip through other devices. For example, when the first PHY chip is a chip compatible with a standard interface, the valid data receive pin of the first interface is connected to the valid data receive pin of the first PHY chip through other devices. As an example, a parallel-to-serial conversion processing device is also included between the valid data receive pin of the first interface and the valid data receive pin of the first PHY chip. The valid data receive pin of the first interface is connected to the second output terminal of the serial-to-parallel conversion processing device, and the valid data receive pin of the first PHY chip is connected to the third input terminal of the parallel-to-serial conversion processing device. As another example, a first tri-state buffer is also included between the valid data receive pin of the first interface and the valid data receive pin of the first PHY chip.

[0168] Similarly, the valid data receiving pin of the first interface is connected to the valid data receiving pin of the second PHY chip. This connection can be direct, or it can be achieved through other devices. For example, a parallel-to-serial conversion device may be included between the valid data receiving pin of the first interface and the valid data receiving pin of the second PHY chip. The valid data receiving pin of the first interface is connected to the second output of this device, and the valid data receiving pin of the second PHY chip is connected to the fourth input of the same device. Another example is a second tri-state buffer may also be included between the valid data receiving pin of the first interface and the valid data receiving pin of the second PHY chip.

[0169] In scenarios where the valid data receiving pin of the first interface is directly connected to the valid data receiving pin of the first PHY chip, and the valid data receiving pin of the first interface is directly connected to the valid data receiving pin of the second PHY chip, the second valid data indication information includes the aforementioned fourth valid data indication information and fifth valid data indication information.

[0170] In a scenario where the valid data receiving pin of the first interface is connected to the valid data receiving pins of the first PHY chip and the second PHY chip via a parallel-to-serial conversion processor, the fourth valid data indication information and the fifth valid data indication information are both sent to the valid data receiving pin of the first interface after being processed by the parallel-to-serial conversion processor. That is, in this scenario, the second valid data indication information is obtained by processing the fourth valid data indication information and the fifth valid data indication information through parallel-to-serial conversion.

[0171] In a scenario where the valid data receive pin of the first interface is connected to the valid data receive pin of the first PHY chip via a first tri-state buffer, and the valid data receive pin of the first interface is connected to the valid data receive pin of the second PHY chip via a second tri-state buffer, the fourth valid data indication information is processed by the first tri-state processor and then sent to the valid data receive pin of the first interface, and the fifth valid data indication information is processed by the second tri-state processor and then sent to the valid data receive pin of the first interface. That is, in this scenario, the second valid data indication information includes the information obtained by the first tri-state buffer processing the fourth valid data indication information, and the information obtained by the second tri-state buffer processing the fifth valid data indication information.

[0172] The communication method provided in the embodiments of this application has been described above. Next, several possible connection methods between the first interface and the PHY chip will be introduced.

[0173] See Figure 4a This figure is a schematic diagram of a first interface connected to a PHY chip according to an embodiment of this application. Figure 4a In this example, we will use a multi-RMII interface as the first interface. When the first interface is another type of interface, the connection method between the first interface and the PHY chip is different. Figure 4a Similarly, these will not be explained in detail here.

[0174] like Figure 4a As shown, the first interface includes: a clock pin M_REF_CLK, a transmit enable pin M_TX_EN, transmit data pins M_TXD[1:0], receive data valid pin M_CRS_DV, and receive data pins M_RXD[1:0]. In Figure 4a In the scenario shown, all PHY chips connected to the first interface are compatible with multi-RMII. Figure 4a The example described uses eight connected PHY chips. In practice, the number of PHY chips connected to the first interface can be other than that. The first and second PHY chips in the above embodiment can be... Figure 4a Any two different PHY chips among the eight PHY chips shown.

[0175] like Figure 4a As shown, there are no other devices between the first interface and the multiple PHY chips. The clock pin M_REF_CLK, the transmit enable pin M_TX_EN, the transmit data pin M_TXD[1:0], the receive data valid pin M_CRS_DV, and the receive data pin M_RXD[1:0] of the first interface are all directly connected to the multiple PHY chips.

[0176] against Figure 4a The scenario shown illustrates how the first interface sends data to multiple PHY chips connected to it. (The method described can be referenced.) Figure 4b To understand, Figure 4b This is a schematic diagram of the first interface provided in this application sending data to the PHY chip.

[0177] like Figure 4b As shown:

[0178] The clock pin M_REF_CLK is used to transmit the first clock signal, the transmit data pins M_TXD[1:0] are used to transmit the first data, and the transmit enable pin M_TX_EN is used to transmit the first data valid indication information. The first interface divides the 10 clock cycles corresponding to M_REF_CLK into one transmit cycle, which includes 10 time slots, with one time slot corresponding to one clock cycle corresponding to M_REF_CLK. Wherein:

[0179] The data transmitted via the M_TXD[1:0] pin can be understood as data transmitted through eight RMII channels, each corresponding to one of the eight PHY chips mentioned above. Specifically:

[0180] The data sent by RMII channel 0 is the data sent by the first interface through M_TXD[1:0] in the first of the aforementioned 10 time slots. The destination receiver of the data sent by RMII channel 0 is PHY chip 0.

[0181] The data sent by RMII channel 1 is the data sent by the first interface through M_TXD[1:0] in the second time slot of the aforementioned 10 time slots. The destination receiver of the data sent by RMII channel 0 is PHY chip 1.

[0182] The data sent by RMII channel 2 is the data sent by the first interface through M_TXD[1:0] in the third time slot of the aforementioned 10 time slots. The destination receiver of the data sent by RMII channel 2 is PHY chip 2.

[0183] Similarly, the data sent by RMII channel 7 is the data sent by the first interface through M_TXD[1:0] in the 8th time slot of the aforementioned 10 time slots, and the destination receiver of the data sent by RMII channel 7 is PHY chip 7.

[0184] The first and second parts of the data mentioned above are data carried by any two different RMII channels among the eight RMII channels, from RMII channel 0 to RMII channel 7.

[0185] Similarly, the first data valid indication information sent by the transmit enable pin M_TX_EN can also be decomposed into data valid indication information corresponding to each RMII channel.

[0186] according to Figure 4b It can be seen that in the first data: the data carried by RMII channel 0, RMII channel 2, RMII channel 5 and RMII channel 6 is valid data, while the data carried by RMII channel 1, RMII channel 3, RMII channel 4 and RMII channel 7 is invalid data.

[0187] In addition, the last two time slots of the aforementioned 10 time slots are respectively used to carry management data (i.e., the third time slot in the above embodiment) and to carry time slot synchronization data (i.e., the fourth time slot in the above embodiment).

[0188] In this scenario, after receiving the first clock signal sent by M_REF_CLK, the PHY chip can determine its corresponding time slot based on this first clock signal and extract the corresponding time slot data from the first data, thereby obtaining the data sent to it by the first interface. For example, PHY chip 0 extracts the data corresponding to the first time slot from the first data, PHY chip 1 extracts the data corresponding to the second time slot from the first data, PHY chip 2 extracts the data corresponding to the third time slot from the first data, and so on, with PHY chip 7 extracting the data corresponding to the eighth time slot from the first data.

[0189] against Figure 4aThe scenario shown illustrates how the first interface receives data from multiple PHY chips connected to it. (The method can be referenced in the original text.) Figure 4c To understand, Figure 4c This is a schematic diagram of the first interface receiving data sent by the PHY chip, as provided in an embodiment of this application.

[0190] like Figure 4c As shown:

[0191] Each PHY chip sends its corresponding data validity indication information to the first interface (corresponding to...). Figure 4c (CRS_DV transmission) and data (corresponding to) Figure 4c (RXD in) Figure 4c In the diagram, RXD[1:0] represents the data received by the first interface through each RMII channel, which is the data sent by each PHY chip to the first interface. Similarly, CRS_DV represents the valid data indication information received by the first interface through each RMII channel, which is the valid data indication information sent by each PHY chip to the first interface. Specifically, each PHY chip sends data to the first interface in its corresponding time slot. In time slots not corresponding to its own, it controls its own receive data pin to be in a high-impedance state, thereby enabling the receive data pin M_RXD[1:0] of the first interface to receive data from different PHY chips in different time slots.

[0192] like Figure 4c As shown: PHY chip 0 corresponds to RMII channel 0. PHY chip 0 sends data to the receive data pins M_RXD[1:0] of the first interface in the first time slot of the transmission cycle. Similarly, the receive data pins M_RXD[1:0] can receive the data sent by PHY chip 0 in the first time slot. PHY chip 1 corresponds to RMII channel 1. PHY chip 1 sends data to the receive data pins M_RXD[1:0] of the first interface in the second time slot of the transmission cycle. Similarly, the receive data pins M_RXD[1:0] can receive the data sent by PHY chip 1 in the second time slot. PHY chip 2 corresponds to RMII channel 2. PHY chip 2 sends data to the receive data pins M_RXD[1:0] of the first interface in the third time slot of the transmission cycle. Similarly, the receive data pins M_RXD[1:0] can receive the data sent by PHY chip 2 in the third time slot. And so on, PHY chip 7 corresponds to RMII channel 1. 7. PHY chip 7 sends data to the receive data pins M_RXD[1:0] of the first interface in the 8th time slot of the transmission cycle. Similarly, the receive data pins M_RXD[1:0] can receive the data sent by PHY chip 7 in the 8th time slot.

[0193] In addition, the data validity indication information sent by each PHY chip is sent to the receive data validity pin M_CRS_DV of the first interface. The signal received by the receive data validity pin M_CRS_DV of the first interface is as follows: Figure 4c As shown, no further details are provided here.

[0194] See Figure 5a This figure is a schematic diagram of a first interface connected to a PHY chip according to an embodiment of this application. Figure 5a In this example, we will use a multi-RMII interface as the first interface. When the first interface is another type of interface, the connection method between the first interface and the PHY chip is different. Figure 5a Similarly, these will not be explained in detail here.

[0195] Regarding the pins included in the first interface, please refer to the previous section. Figure 4a The description will not be repeated here.

[0196] exist Figure 5a In the scenario shown, all PHY chips connected to the first interface support the standard RMII. Figure 5a The example described uses eight connected PHY chips. In practice, the number of PHY chips connected to the first interface can be other than that. The first and second PHY chips in the above embodiment can be... Figure 5a Any two different PHY chips among the eight PHY chips shown.

[0197] like Figure 5a As shown, other devices are also included between the first interface and the plurality of PHY chips. Specifically:

[0198] A multi-phase frequency divider is also included between the clock pin M_REF_CLK of the first interface and the clock pin of the PHY chip. This multi-phase frequency divider can perform multi-phase frequency division on the first clock signal received through the clock pin M_REF_CLK of the first interface, and send the resulting divided clock to the corresponding PHY chip. In one example, the multi-phase frequency divider processes the first clock signal to obtain 8 divided clocks, and these 8 divided clocks correspond one-to-one with the 8 PHY chips. As an example, the phase difference between the divided clocks corresponding to PHY chip i and PHY chip i+1 corresponds to one clock cycle of the first clock signal.

[0199] The transmit enable pin M_TX_EN and the transmit data pins M_TXD[1:0] of the first interface are both connected to a serial-to-parallel converter. The serial-to-parallel converter is used to convert the serial data corresponding to the aforementioned 8 RMII channels carried by M_TXD[1:0] into parallel data. Correspondingly, the first data validity indication information carried by the transmit enable pin M_TX_EN is also converted into data validity indication information corresponding to each RMII channel. In this way, the signals received by each PHY chip are standard RMII signals, and the PHY chip can receive data according to the data reception logic corresponding to the standard RMII.

[0200] For information regarding the clock pin M_REF_CLK, transmit enable pin M_TX_EN, and transmit data pins M_TXD[1:0] of the first interface, please refer to the previous text. Figure 4b The description of that section will not be repeated here.

[0201] The valid data receiving pins M_CRS_DV and M_RXD[1:0] of the first interface are both connected to a parallel-to-serial converter. This converter receives standard RMII signals sent by multiple PHY chips and performs parallel-to-serial conversion on these signals before sending them to the first interface. In this scenario, the data received by the valid data receiving pins M_CRS_DV and M_RXD[1:0] of the first interface is described in detail below. Figure 4c The relevant parts are not described in detail here.

[0202] See Figure 5b This figure is a schematic diagram illustrating another type of connection between a first interface and a PHY chip provided in an embodiment of this application. Figure 5b In this example, we will use a multi-RMII interface as the first interface. When the first interface is another type of interface, the connection method between the first interface and the PHY chip is different. Figure 5b Similarly, these will not be explained in detail here.

[0203] Figure 5b and Figure 5a The difference is: in Figure 5b In the first interface, the valid data receiving pin M_CRS_DV and the data receiving pins M_RXD[1:0] of the first interface are both connected to a tri-state buffer. Figure 5bIn this scenario, the data sent by each PHY chip and its corresponding data validity indication information are connected to its own tri-state buffer. After processing by the tri-state buffer, the data is sent to the valid data receive pin M_CRS_DV and the receive data receive pins M_RXD[1:0] of the first interface. In this scenario, each PHY chip only needs to send a standard RMII signal. The standard RMII signal is processed by the tri-state buffer and then sent to the first interface, enabling the first interface to receive data sent by different PHY chips in different time slots. The data received by the valid data receive pin M_CRS_DV and the receive data receive pins M_RXD[1:0] of the first interface in this scenario can also be referenced... Figure 4c The relevant parts are not described in detail here.

[0204] Based on the communication method provided in the above embodiments, this application also provides a corresponding device, which will be described below with reference to the accompanying drawings.

[0205] See Figure 6 This figure is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Figure 6 The communication device 600 shown is applied to the MAC module and is used to execute the method steps provided by the MAC module in the above embodiments.

[0206] like Figure 6 As shown, the device 600 includes a first interface 610. Optionally, the MAC module further includes a processing unit 620. The first interface 610 connects to a first physical layer PHY chip and a second PHY chip. The first interface 610 is used to send a first clock signal to the first PHY chip and the second PHY chip. The first clock signal is used to determine a first time slot and a second time slot.

[0207] The first interface 610 is also used to send first data to the first PHY chip and the second PHY chip. The first data includes a first part of data and a second part of data. The first part of data is the data sent by the MAC module in the first time slot, and the second part of data is the data sent by the MAC module in the second time slot.

[0208] In one possible implementation, the first interface 610 includes a clock pin, which is connected to the clock pins of the first PHY chip and the second PHY chip. The clock pin of the first interface 610 is used to send the first clock signal to the clock pins of the first PHY chip and the second PHY chip.

[0209] In one possible implementation, the first interface 610 includes a transmit data pin, which is connected to the transmit data pins of the first PHY chip and the second PHY chip. The transmit data pin is used to transmit the first data to the transmit data pins of the first PHY chip and the second PHY chip.

[0210] In one possible implementation, the first clock signal is further used to determine a third time slot, and the first data further includes management data, which is data sent by the MAC module in the third time slot.

[0211] In one possible implementation, the first clock signal is further used to determine a fourth time slot, and the first data further includes time slot synchronization data, which is data sent by the MAC module in the fourth time slot.

[0212] In one possible implementation, the first interface 610 is further configured to send first data validity indication information to the first PHY chip and the second PHY chip, the first data validity indication information being used to indicate valid data in the first data.

[0213] In one possible implementation, the first interface 610 includes a transmit enable pin, which is connected to the transmit enable pin of the first PHY chip and the transmit enable pin of the second PHY chip. The transmit enable pin of the first interface 610 is used to send first data valid indication information to the transmit enable pin of the first PHY chip and the transmit enable pin of the second PHY chip.

[0214] In one possible implementation, the apparatus further includes a processing unit 620, configured to: obtain the first portion of data based on data sent from a second interface, wherein the second interface is: a Media Independent Interface (MII), or a Reduced Media Independent Interface (RMII), or a Gigabit Media Independent Interface (GMII), or a Reduced Gigabit Media Independent Interface (RGMII); and obtain the second portion of data based on data sent from a third interface, wherein the third interface is MII, RMII, GMII, or RGMII.

[0215] In one possible implementation, the processing unit 620 is configured to: determine the data sent by the second interface as the first part of the data; or, if the second interface is MII, convert the data sent by the second interface into data corresponding to a simplified Media Independent Interface (RMII) to obtain the first part of the data; or, if the second interface is GMII, convert the data sent by the second interface into data corresponding to a simplified Gigabit Media Independent Interface (RGMII) to obtain the first part of the data.

[0216] In one possible implementation, the first data is sent via the first interface 610, and after being processed by serial-to-parallel conversion, it is sent to the first PHY chip and the second PHY chip.

[0217] In one possible implementation, after the first clock signal is sent via the first interface 610, it is processed by multi-phase frequency division to obtain a first divided clock and a second divided clock. The first divided clock is sent to the first PHY chip, and the second divided clock is sent to the second PHY chip. The first divided clock is used by the first PHY chip to obtain the first part of the data from the received data, and the second divided clock is used by the second PHY chip to obtain the second part of the data from the received data.

[0218] In one possible implementation, the first interface 610 is further configured to receive second data sent by the first PHY chip and the second PHY chip. The second data includes a third part of data and a fourth part of data. The third part of data is data received by the first interface 610 in a fifth time slot, and the fourth part of data is data received by the first interface 610 in a sixth time slot.

[0219] In one possible implementation, the first interface 610 includes a receive data pin, which is connected to the receive data pins of the first PHY chip and the second PHY chip. The receive data pin of the first interface 610 is used to receive the second data sent by the receive data pins of the first PHY chip and the second PHY chip.

[0220] In one possible implementation, the third portion of the data is the data transmitted by the first PHY chip in the fifth time slot, and / or the fourth portion of the data is the data transmitted by the second PHY chip in the sixth time slot.

[0221] In one possible implementation, the data sent by the first PHY chip and the data sent by the second PHY chip are sent to the first interface 610 after being processed by parallel-to-serial conversion; or, the data sent by the first PHY chip is sent to the first interface 610 in the fifth time slot after being processed by the first tri-state buffer, and the data sent by the second PHY chip is sent to the first interface 610 in the sixth time slot after being processed by the second tri-state buffer.

[0222] In one possible implementation, the first interface 610 is further configured to receive second data validity indication information sent by the first PHY chip and the second PHY chip, the second data validity indication information being used to indicate valid data in the second data.

[0223] In one possible implementation, the first interface 610 includes a receive data valid pin, which is connected to the receive data valid pin of the first PHY chip and the receive data valid pin of the second PHY chip. The receive data valid pin of the first interface 610 is used to receive second data valid indication information sent by the first PHY chip and the second PHY chip.

[0224] See Figure 7 This figure is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Figure 7 The communication device 700 shown is applied to the first PHY chip and is used to execute the method steps provided in the above embodiments by the first PHY chip.

[0225] like Figure 7 As shown, the communication device 700 includes a receiving unit 710 and a processing unit 720. Optionally, the communication device 700 further includes a transmitting unit 730.

[0226] The receiving unit 710 is used to receive a target clock signal, which is obtained based on a first clock signal sent by a first interface of the MAC module. The first interface is connected to the first PHY chip, and the first clock signal is used to determine a first time slot. As an example, the receiving unit 710 includes a clock pin for receiving the target clock signal.

[0227] The receiving unit 710 is further configured to receive target data, which is obtained based on first data sent by the first interface. The first data includes a first portion of data, which is data sent by the MAC module in the first time slot. As an example, the receiving unit 710 includes a transmit data pin, which is used to receive the target data.

[0228] The processing unit 720 is used to acquire the first part of the data based on the target clock signal and the target data.

[0229] In one possible implementation, the first clock signal is further used to determine a third time slot, and the first data further includes management data, which is data sent by the MAC module in the third time slot.

[0230] In one possible implementation, the first clock signal is further used to determine a fourth time slot, and the first data further includes time slot synchronization data, which is data sent by the MAC module in the fourth time slot.

[0231] In one possible implementation, the receiving unit 710 is further configured to receive third data validity indication information sent by the MAC module. The third data validity indication information is obtained based on first data validity indication information sent by the MAC module. The first data validity indication information indicates valid data in the first data, and the third data validity information indicates valid data in the target data. As an example, the receiving unit 710 includes a transmit enable pin, which is used to receive the third data validity indication information sent by the MAC module.

[0232] In one possible implementation, the target clock signal is the first clock signal, the target data is the first data, and the processing unit 720 is configured to: determine a first time slot based on the first clock signal, and extract data corresponding to the first time slot from the first data to obtain the first part of the data.

[0233] In one possible implementation, the target data is the data that was sent to the first PHY chip after the first data was sent via the first interface and then processed by serial-to-parallel conversion.

[0234] In one possible implementation, the target clock is a first frequency-divided clock obtained after the first clock signal is sent via the first interface and then processed by multi-phase frequency division. The first frequency-divided clock is used by the first PHY chip to obtain the first part of the data from the received target data.

[0235] In one possible implementation, the transmitting unit 730 is configured to transmit data to the first interface in a fifth time slot. As an example, the transmitting unit 730 includes a receive data pin for transmitting data to the first interface in the fifth time slot.

[0236] In one possible implementation, the transmitting unit 730 is configured to transmit data to the first interface, wherein data transmitted by the first PHY chip and data transmitted by the second PHY chip are transmitted to the first interface after parallel-to-serial conversion; or, data transmitted by the first PHY chip is transmitted to the first interface in a fifth time slot after being processed by a first tri-state buffer, wherein the first interface is also connected to the second PHY chip. As an example, the transmitting unit 730 includes a receive data pin, which is used to transmit data to the first interface.

[0237] In one possible implementation, the transmitting unit 730 is further configured to: transmit a fourth data validity indication message to the first interface, the fourth data validity indication message being used to indicate valid data in the data transmitted by the first PHY chip. As an example, the transmitting unit 730 includes a receive data validity pin, the receive data validity pin being used to transmit the fourth data validity indication message to the first interface.

[0238] In one possible implementation, the fourth data valid indication information sent by the first PHY chip and the fifth data valid indication information sent by the second PHY chip are sent to the first interface after being processed by parallel-to-serial conversion; or, the fourth data valid indication information sent by the first PHY chip is processed by a first tri-state buffer and the fifth data valid indication information sent by the second PHY chip is processed by a second tri-state buffer before being sent to the first interface.

[0239] This application embodiment also provides a first interface. Regarding the first interface, please refer to the description of the first interface in the previous section on the communication device 600, which will not be repeated here.

[0240] This application embodiment also provides a first PHY chip. For the first PHY chip, please refer to the description of the communication device 700 above, which will not be repeated here.

[0241] In addition, this application also provides a communication device 800, see [link to relevant documentation]. Figure 8 As shown, Figure 8 This is a schematic diagram of a communication device provided in an embodiment of this application. The communication device 800 includes a communication interface 801 and a processor 802 connected to the communication interface 801.

[0242] In one example, the communication device 800 can be applied to the MAC module mentioned in the above embodiments to execute the methods executed by the MAC module in the above embodiments.

[0243] Communication interface 801 is used to perform the receiving and / or sending operations in the method executed by the MAC module. Processor 802 is used to perform other operations in the method executed by the MAC module besides the receiving and / or sending operations. For example, communication interface 801 is used to send a first clock signal to the first PHY chip and the second PHY chip, the first clock signal being used to determine a first time slot and a second time slot, and to send first data to the first PHY chip and the second PHY chip, the first data including a first part of data and a second part of data, the first part of data being data sent by the MAC module in the first time slot, and the second part of data being data sent by the MAC module in the second time slot. Optionally, processor 802 is used to obtain the first part of data based on data sent by a second interface, the second interface being: Media Independent Interface (MII), or, Reduced Media Independent Interface (RMII), or, Gigabit Media Independent Interface (GMII), or, Reduced Gigabit Media Independent Interface (RGMII); and to obtain the second part of data based on data sent by a third interface, the third interface being MII, RMII, GMII, or RGMII. In one example, the communication interface 801 mentioned here may correspond to the first interface in the above embodiments.

[0244] In another example, the communication device 800 can be applied to the first PHY chip mentioned in the above embodiments to perform the methods executed by the first PHY chip in the above embodiments.

[0245] Communication interface 801 is used to perform the receiving and / or transmitting operations in the method executed by the first PHY chip. Processor 802 is used to perform other operations in the method executed by the first PHY chip besides the receiving and / or transmitting operations. For example: communication interface 801 is used to receive a target clock signal, which is obtained according to a first clock signal sent by a first interface of the MAC module, the first interface being connected to the first PHY chip, and the first clock signal being used to determine a first time slot; and to receive target data, which is obtained according to first data sent by the first interface, the first data including a first part of data, which is data sent by the MAC module in the first time slot. Processor 802 is used to obtain the first part of data according to the target clock signal and the target data.

[0246] See Figure 9 The figure is a schematic diagram of the structure of a chip provided in an embodiment of this application. Figure 9 The chip 900 shown includes an interface circuit 901 and a processing circuit 902. The interface circuit 901 is used to receive and / or transmit data, and the processing circuit 902 is used to perform data processing.

[0247] In one example, the chip 900 can be applied to the MAC module described above to execute the methods provided in the above method embodiments. For this situation:

[0248] Interface circuit 901 is used to perform the receive and / or transmit operations in the method executed by the MAC module. Processing circuit 902 is used to perform other operations in the method executed by the MAC module besides the receive and / or transmit operations. For example, interface circuit 901 is used to send a first clock signal to the first PHY chip and the second PHY chip, the first clock signal being used to determine a first time slot and a second time slot, and to send first data to the first PHY chip and the second PHY chip, the first data including a first part of data and a second part of data, the first part of data being data sent by the MAC module in the first time slot, and the second part of data being data sent by the MAC module in the second time slot. Optionally, processing circuit 902 is used to obtain the first part of data based on data sent from a second interface, the second interface being: Media Independent Interface (MII), or, Reduced Media Independent Interface (RMII), or, Gigabit Media Independent Interface (GMII), or, Reduced Gigabit Media Independent Interface (RGMII); and to obtain the second part of data based on data sent from a third interface, the third interface being MII, RMII, GMII, or RGMII. In one example, the interface circuit 901 mentioned here can correspond to the first interface in the above embodiments.

[0249] In another example, the chip 900 can be applied to the first PHY chip described above to execute the method provided in the above method embodiments, which is executed by the first PHY chip. In this case:

[0250] Interface circuit 901 is used to perform the receiving and / or transmitting operations in the method executed by the first PHY chip. Processing circuit 902 is used to perform other operations in the method executed by the first PHY chip besides the receiving and / or transmitting operations. For example: interface circuit 901 is used to receive a target clock signal, which is obtained according to a first clock signal sent by a first interface of the MAC module, the first interface being connected to the first PHY chip, and the first clock signal being used to determine a first time slot; and to receive target data, which is obtained according to first data sent by the first interface, the first data including a first part of data, which is data sent by the MAC module in the first time slot. Processing circuit 902 is used to obtain the first part of data according to the target clock signal and the target data.

[0251] For details regarding the specific steps performed by the interface circuit 901 and the processing circuit 902, please refer to the relevant descriptions in the above embodiments; they will not be repeated here.

[0252] This application also provides a computer-readable storage medium storing instructions or computer programs that, when executed on a processor, can perform any one or more of the operations described in the foregoing embodiments.

[0253] This application also provides a computer program product, including a computer program that, when run on a processor, can implement any one or more of the operations described in the foregoing embodiments.

[0254] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0255] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0256] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical business division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0257] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0258] Furthermore, the various business units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software business unit.

[0259] If the integrated unit is implemented as a software business unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0260] Those skilled in the art will recognize that, in one or more of the examples above, the services described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these services can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media can be any available medium accessible to general-purpose or special-purpose computers.

[0261] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention.

[0262] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A communication method, characterized in that, An application is made in a media access control (MAC) module, the MAC module including a first interface, the first interface being connected to a first physical layer (PHY) chip and a second PHY chip, the method comprising: The MAC module sends a first clock signal to the first PHY chip and the second PHY chip through the first interface. The first clock signal is used to determine the first time slot and the second time slot. The MAC module sends first data to the first PHY chip and the second PHY chip through the first interface. The first data includes a first part of data and a second part of data. The first part of data is the data sent by the MAC module in the first time slot, and the second part of data is the data sent by the MAC module in the second time slot.

2. The method according to claim 1, characterized in that, The first interface includes a clock pin, which is connected to the clock pins of the first PHY chip and the second PHY chip. The MAC module sends a first clock signal to the first PHY chip and the second PHY chip through the first interface, including: The MAC module sends the first clock signal to the clock pins of the first PHY chip and the second PHY chip through the clock pin of the first interface.

3. The method according to claim 1 or 2, characterized in that, The first interface includes a transmit data pin, which is connected to the transmit data pins of the first PHY chip and the second PHY chip. The MAC module transmits first data to the first PHY chip and the second PHY chip through the first interface, including: The MAC module sends the first data to the transmit data pins of the first PHY chip and the second PHY chip through the transmit data pin of the first interface.

4. The method according to any one of claims 1-3, characterized in that, The first clock signal is also used to determine the third time slot, and the first data also includes management data, which is the data sent by the MAC module in the third time slot.

5. The method according to any one of claims 1-4, characterized in that, The first clock signal is also used to determine the fourth time slot, and the first data also includes time slot synchronization data, which is the data sent by the MAC module in the fourth time slot.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: The MAC module sends a first data validity indication message to the first PHY chip and the second PHY chip through the first interface. The first data validity indication message is used to indicate valid data in the first data.

7. The method according to claim 6, characterized in that, The first interface includes a transmit enable pin, which is connected to the transmit enable pins of the first PHY chip and the second PHY chip. The MAC module sends first data validity indication information to the first PHY chip and the second PHY chip through the first interface, including: The MAC module sends a first data valid indication message to the transmit enable pins of the first PHY chip and the second PHY chip through the transmit enable pin of the first interface.

8. The method according to any one of claims 1-7, characterized in that, The method further includes: The first part of the data is obtained based on the data sent by the second interface, wherein the second interface is: Media Independent Interface MII, or, Simplified Media Independent Interface RMII, or, Gigabit Media Independent Interface GMII, or, Simplified Gigabit Media Independent Interface RGMII; The second part of the data is obtained based on the data sent by the third interface, which is MII, RMII, GMII, or RGMII.

9. The method according to claim 8, characterized in that, The process of obtaining the first part of the data based on the data sent from the second interface includes: The data sent by the second interface is identified as the first part of the data; or... If the second interface is MII, then the data sent by the second interface is converted into data corresponding to a simplified Media Independent Interface (RMII) to obtain the first part of the data; or, If the second interface is GMII, the data sent by the second interface is converted into data corresponding to the simplified Gigabit Media Independent Interface (RGMII) to obtain the first part of the data.

10. The method according to any one of claims 1-9, characterized in that, After the first data is sent via the first interface, it is processed by serial-to-parallel conversion and then sent to the first PHY chip and the second PHY chip.

11. The method according to claim 10, characterized in that, After the first clock signal is sent through the first interface, it is processed by multi-phase frequency division to obtain a first frequency-divided clock and a second frequency-divided clock. The first frequency-divided clock is sent to the first PHY chip, and the second frequency-divided clock is sent to the second PHY chip. The first frequency-divided clock is used by the first PHY chip to obtain the first part of the data from the received data, and the second frequency-divided clock is used by the second PHY chip to obtain the second part of the data from the received data.

12. The method according to any one of claims 1-11, characterized in that, The method includes: The MAC module receives second data sent by the first PHY chip and the second PHY chip through the first interface. The second data includes a third part of data and a fourth part of data. The third part of data is the data received by the first interface in the fifth time slot, and the fourth part of data is the data received by the first interface in the sixth time slot.

13. The method according to claim 12, characterized in that, The first interface includes a receive data pin, which is connected to the receive data pins of the first PHY chip and the second PHY chip. The MAC module receives second data sent by the first PHY chip and the second PHY chip through the first interface, including: The MAC module receives the second data sent by the first PHY chip and the second PHY chip through the receive data pin of the first interface.

14. The method according to claim 12 or 13, characterized in that, The third part of the data is the data sent by the first PHY chip in the fifth time slot, and / or the fourth part of the data is the data sent by the second PHY chip in the sixth time slot.

15. The method according to claim 12 or 13, characterized in that, The data sent by the first PHY chip and the data sent by the second PHY chip are sent to the first interface after being processed by parallel-to-serial conversion; or, the data sent by the first PHY chip is sent to the first interface in the fifth time slot after being processed by the first tri-state buffer, and the data sent by the second PHY chip is sent to the first interface in the sixth time slot after being processed by the second tri-state buffer.

16. The method according to any one of claims 12-15, characterized in that, The method further includes: The MAC module receives second data validity indication information sent by the first PHY chip and the second PHY chip through the first interface. The second data validity indication information is used to indicate valid data in the second data.

17. The method according to claim 16, characterized in that, The first interface includes a receive data valid pin, which is connected to the receive data valid pin of the first PHY chip and the receive data valid pin of the second PHY chip. The MAC module receives second data valid indication information sent by the first PHY chip and the second PHY chip through the first interface, including: The MAC module receives the second data validity indication information sent by the first PHY chip and the second PHY chip through the data validity pin of the first interface.

18. A communication method, characterized in that, The method, applied to a first physical layer PHY chip, includes: Receive a target clock signal, which is obtained based on a first clock signal sent by a first interface of the MAC module. The first interface is connected to the first PHY chip, and the first clock signal is used to determine a first time slot. Receive target data, which is obtained based on the first data sent by the first interface. The first data includes a first part of data, which is the data sent by the MAC module in the first time slot. The first part of the data is obtained based on the target clock signal and the target data.

19. The method according to claim 18, characterized in that, The first clock signal is also used to determine the third time slot, and the first data also includes management data, which is the data sent by the MAC module in the third time slot.

20. The method according to claim 18 or 19, characterized in that, The first clock signal is also used to determine the fourth time slot, and the first data also includes time slot synchronization data, which is the data sent by the MAC module in the fourth time slot.

21. The method according to any one of claims 18-20, characterized in that, The method further includes: The system receives a third data validity indication message sent by the MAC module. The third data validity indication message is obtained based on the first data validity indication message sent by the MAC module. The first data validity indication message is used to indicate valid data in the first data, and the third data validity indication message is used to indicate valid data in the target data.

22. The method according to any one of claims 18-21, characterized in that, The target clock signal is the first clock signal, the target data is the first data, and the step of obtaining the first portion of data based on the target clock signal and the target data includes: The first time slot is determined based on the first clock signal, and the data corresponding to the first time slot is extracted from the first data to obtain the first part of the data.

23. The method according to any one of claims 18-21, characterized in that, The target data is the data that is sent to the first PHY chip after the first data is sent via the first interface, and after being processed by serial-to-parallel conversion.

24. The method according to claim 23, characterized in that, The target clock is the first frequency-divided clock obtained after the first clock signal is sent through the first interface and undergoes multi-phase frequency division processing. The first frequency-divided clock is used by the first PHY chip to obtain the first part of the data from the received target data.

25. The method according to any one of claims 18-24, characterized in that, The method further includes: Data is sent to the first interface in the fifth time slot.

26. The method according to any one of claims 18-24, characterized in that, The method further includes: Data is sent to the first interface, wherein the data sent by the first PHY chip and the data sent by the second PHY chip are sent to the first interface after being processed by parallel-to-serial conversion; or, the data sent by the first PHY chip is sent to the first interface in the fifth time slot after being processed by the first tri-state buffer, wherein the first interface is also connected to the second PHY chip.

27. The method according to claim 25 or 26, characterized in that, The method further includes: A fourth data validity indication message is sent to the first interface, the fourth data validity indication message being used to indicate valid data in the data sent by the first PHY chip.

28. The method according to claim 27, characterized in that, The fourth data validity indication information sent by the first PHY chip and the fifth data validity indication information sent by the second PHY chip are sent to the first interface after parallel-to-serial conversion; or, The fourth data validity indication information sent by the first PHY chip is processed by the first tri-state buffer, and the fifth data validity indication information sent by the second PHY chip is processed by the second tri-state buffer before being sent to the first interface.

29. A media access control (MAC) module, the MAC module including a first interface, the first interface being connected to a first physical layer PHY chip and a second PHY chip.

30. The MAC module according to claim 29, characterized in that, The first interface includes a clock pin, which is connected to the clock pin of the first PHY chip and the clock pin of the second PHY chip.

31. The MAC module according to claim 29 or 30, characterized in that, The first interface includes a transmit data pin, which is connected to the transmit data pin of the first PHY chip and the transmit data pin of the second PHY chip.

32. The MAC module according to any one of claims 29-31, characterized in that, The first interface includes a transmit enable pin, which is connected to the transmit enable pin of the first PHY chip and the transmit enable pin of the second PHY chip.

33. The MAC module according to any one of claims 29-32, characterized in that, The first interface includes a data receiving pin, which is connected to the data receiving pin of the first PHY chip and the data receiving pin of the second PHY chip.

34. The MAC module according to any one of claims 29-33, characterized in that, The first interface includes a valid data receiving pin, which is connected to the valid data receiving pin of the first PHY chip and the valid data receiving pin of the second PHY chip.

35. A communication device, characterized in that, It includes a processor and a communication interface, the communication interface being used to perform the receiving operation and / or transmitting operation as described in any one of claims 1-28, and the processor being used to perform other operations as described in any one of claims 1-28 besides the receiving operation and the transmitting operation.

36. A chip, characterized in that, It includes a processing circuit and an interface circuit, wherein the interface circuit is used to perform the receiving operation and / or transmitting operation as described in any one of claims 1-28, and the processing circuit is used to perform other operations as described in any one of claims 1-28 besides the receiving operation and the transmitting operation.

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