A high-speed multi-channel star-sensor image data transmission system and method based on PolarFire SoC

Abstract

A multi-channel star sensor image data high-speed transmission system and method based on PolarFire SoC belong to the technical field of high-speed data transmission of satellite-borne computers, and solve the technical problem that in the prior art, in the scene of multi-channel star sensor image data high-speed transmission and centralized processing, it is difficult to balance high-speed transmission, unified scheduling of multi-channel asynchronous data and high reliability requirements. The system comprises a star sensor high-speed receiving, data caching and scheduling and DMA storage link, and can further comprise a high-speed forwarding link. High-speed serial image data is received and restored to parallel data, valid image frames are identified through a frame header, cross-clock domain caching and bit width conversion are completed, a transmission ready signal and a channel polling order are selected according to the transmission channel to be transmitted, and the star sensor image data is written into the MSS side DDR memory through DMA. The application is used for realizing centralized reception, reliable caching, efficient storage and optional high-speed forwarding of multi-channel star sensor original image data in a satellite-borne computer.

Description

Technical Field

[0001] This invention relates to the field of high-speed data transmission technology for spaceborne computers, and specifically to a high-speed transmission system and method for multi-channel star-sensor image data based on PolarFire SoC. Background Technology

[0002] Star-sensor cameras are crucial sensing devices in satellite attitude determination systems, typically used to acquire star images and provide fundamental data for star image recognition, attitude calculation, and attitude control. As high-resolution remote sensing satellites increasingly demand higher accuracy in attitude determination, real-time data processing, and on-orbit maintainability, the volume and transmission rate of star-sensor image data continue to rise. Traditional star-sensor data transmission architectures are gradually becoming insufficient to meet the needs of centralized processing and high-speed transmission of multiple star-sensor image data streams.

[0003] In existing technologies, star-aware single-unit systems typically have an independent processor or processing board. The star-aware single-unit completes star map recognition and attitude calculation locally, and then sends the attitude results or a small amount of processed data to the onboard central computer via a low-speed bus such as RS422. This solution can meet basic usage requirements in traditional low-speed data application scenarios. However, in scenarios involving high-speed transmission and centralized processing of multi-channel star-aware image data, the traditional solution of general-purpose processor plus low-speed bus is difficult to simultaneously meet the requirements of high-speed transmission, unified scheduling of multi-channel asynchronous data, and high reliability.

[0004] In summary, existing technologies struggle to simultaneously address the technical challenges of high-speed transmission, unified scheduling of multiple asynchronous data streams, and high reliability requirements in scenarios involving high-speed transmission and centralized processing of multi-channel star-sensor image data. Summary of the Invention

[0005] This invention solves the technical problem that existing technologies struggle to balance high-speed transmission, unified scheduling of multiple asynchronous data streams, and high reliability requirements in scenarios involving high-speed transmission and centralized processing of multi-channel star-sensor image data.

[0006] The present invention discloses a high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC, the system comprising a PolarFire SoC controller and DDR memory; The PolarFire SoC controller includes an FPGA logic area and an MSS processor subsystem; The FPGA logic area includes an XCVR receiving channel, a buffer scheduling module 1, and a DMA write module; The XCVR receiving channel is used to receive high-speed serial star-sensor image data output from multiple star-sensor cameras, and recover parallel data and recover the clock. The cache scheduling module 1 is used to perform frame header detection, cross-clock domain buffering, bit width conversion and channel scheduling on parallel data and recovery clock, and output star-sensor image data. The DMA write module is used to write the star-sensor image data output by the cache scheduling module 1 into the DDR memory. The MSS processor subsystem is used to configure the transmission parameters of the DMA write module, manage the buffer status in the DDR memory, and mark the corresponding buffer as readable after the DMA write module writes the star-sensor image data into the DDR memory, so that the star-sensor processing algorithm can read it. The DDR memory is used to store star-sensor image data.

[0007] Furthermore, in one embodiment of the present invention, the MSS processor subsystem includes a DMA configuration unit, an interrupt management unit, a star-aware algorithm unit, an exception management unit, and a DDR controller; The DMA configuration unit is used to configure the control and status register group of the DMA write module through the AXI bus interface to set the destination address and transmission length, and to trigger the DMA write module to start. The interrupt management unit is used to receive the transmission completion interrupt generated by the DMA write module and update the buffer state in the DDR memory according to the transmission completion interrupt. The star-sensor algorithm unit is used to read star-sensor image data marked as readable from DDR memory and perform star map recognition and attitude calculation. The anomaly management unit is used to receive the anomaly status reported by the cache scheduling module 1 and perform a reset or rebuild cache operation on the corresponding star channel. The DDR controller is used to control read and write access to the DDR memory.

[0008] Furthermore, in one embodiment of the present invention, the cache scheduling module 1 includes multiple star-sensor data cache sub-modules and channel scheduling sub-modules configured corresponding to multiple star-sensor cameras; The star-sensitive data cache submodule includes a write control module and an asynchronous FIFO module; The write control module includes a frame header detection module and a frame length counting module, which are used to write the star image data of the corresponding star channel into the asynchronous FIFO module after detecting a preset frame header, and stop writing the current frame when the preset frame length is reached. The asynchronous FIFO module is used to realize cross-clock domain processing from the recovery clock domain of the XCVR receiving channel to the system clock domain of the PolarFire SoC controller, and to perform bit width adaptation to adapt to the data interface bit width of the DMA write module. The channel scheduling submodule is used to select the star-sensitive channel to be transmitted based on the transmission ready signal output by each asynchronous FIFO module. When multiple transmission ready signals are valid at the same time, one of the star-sensitive channels is selected for transmission according to the polling order.

[0009] Furthermore, in one embodiment of the present invention, the write-side data width of the asynchronous FIFO module is 16-bit, and the read-side data width is 64-bit.

[0010] Furthermore, in one embodiment of the present invention, the DMA write module includes an interface conversion module and a DMA controller; The interface conversion module is connected between the cache scheduling module 1 and the DMA controller, and is used to receive the star-sensor image data and corresponding channel identifiers output by the cache scheduling module 1, and adapt the star-sensor image data to the data input format of the DMA controller; The DMA controller is used to write the star-sensor image data input via the interface conversion module into the DDR memory according to the configuration in the control and status register group.

[0011] Furthermore, in one embodiment of the present invention, the control and status register group includes a stream descriptor register, a transfer start register, and an interrupt status register.

[0012] Furthermore, in one embodiment of the present invention, the DDR memory is provided with at least two independent buffers for each star channel; When each star-sensor channel is equipped with two independent buffers, a ping-pong buffer structure is formed; When each star-sensor channel is equipped with no fewer than three independent buffers, a circular buffer queue is formed.

[0013] Furthermore, in one embodiment of the present invention, the system further includes an XCVR high-speed forwarding unit, which includes a buffer scheduling module 2, a framing module, and an XCVR transmission channel; The cache scheduling module 2 is used to cache the parallel data recovered by the XCVR receive channel according to the channel enable information configured in the MSS processor subsystem, and to perform polling arbitration among the enabled star channels to select the current star channel to be forwarded. The framing module is used to frame the selected current star-sensor channel to be forwarded, and generate star-sensor image data transmission frames. The XCVR transmission channel is used to send star-sensor image data transmission frames to the downstream device.

[0014] Furthermore, in one embodiment of the present invention, the star-sensor image data transmission frame includes at least a frame header, a channel identifier, and a payload.

[0015] The present invention discloses a high-speed transmission method for multi-channel star-sensor image data based on PolarFire SoC. The method is used to implement any of the aforementioned systems and is characterized by comprising the following steps: Step 1: Receive high-speed serial star-sensor image data output from multiple star-sensor cameras through the XCVR receiving channel, and recover the parallel data and clock. Step 2: Frame header detection is performed on the parallel data. When a preset frame header is detected, the star sensor image data of the corresponding star sensor channel is written into the asynchronous FIFO module. Step 3: The asynchronous FIFO module completes the cross-clock domain processing from the recovery clock domain of the XCVR receiving channel to the system clock domain of the PolarFire SoC controller, and completes the data bit width conversion. Step 4: The buffer scheduling module 1 selects the star channel to be transmitted based on the transmission ready signal output by each asynchronous FIFO module. When multiple transmission ready signals are valid at the same time, one of the star channels is selected for transmission according to the polling order. Step 5: The MSS processor subsystem configures the control and status register group of the DMA write module through the AXI bus interface to set the destination address and transmission length, and triggers the DMA write module to start. The DMA write module writes the star image data of the star channel to be transmitted into the DDR memory according to the transmission parameters. Step 6: The MSS processor subsystem updates the buffer status of the corresponding star channel based on the transfer completion interrupt generated by the DMA write module, and marks the buffer that has been written as readable so that the star processing algorithm can read it.

[0016] This invention solves the technical problem of existing technologies in scenarios involving high-speed transmission and centralized processing of multi-channel star-sensor image data, which makes it difficult to simultaneously meet the requirements of high-speed transmission, unified scheduling of multi-channel asynchronous data, and high reliability. Specific beneficial effects of this invention include: 1. This invention proposes a high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC. Through the coordinated operation of XCVR high-speed reception, asynchronous FIFO cross-clock domain processing, polling arbitration scheduling, DMA CPU-free writing, and multi-buffer management, it realizes centralized high-speed reception, unified scheduling, and reliable storage of multi-channel star-sensor raw image data, taking into account the requirements of high-speed transmission, unified scheduling of multi-channel asynchronous data, and high reliability. 2. This invention proposes a high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC. The system uses the XCVR high-speed forwarding unit to frame and forward star-sensor image data in a time-division manner, thereby improving the system's data service capabilities for downstream devices. Attached Figure Description

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a diagram of the high-speed transmission system architecture for multi-channel star-sensor image data as described in Implementation Method 3; Figure 2 This is a schematic diagram of the cache scheduling module 1 described in Implementation Method 3; Figure 3 This is a schematic diagram of the DMA write module described in Embodiment 3; Figure 4 This is a flowchart of the MSS configuration DMA controller and buffer management as described in Implementation Method 3; Figure 5 This is the flowchart of the high-speed transmission method and anomaly handling method for multi-channel star-sensor image data described in Implementation Method 3. Detailed Implementation

[0018] Various embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. The embodiments described with reference to the drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0019] Implementation Method 1: Currently, existing technologies struggle to simultaneously meet the requirements of high-speed transmission, unified scheduling of multiple asynchronous data streams, and high reliability in scenarios involving high-speed transmission and centralized processing of multi-channel star-sensor image data. This is mainly reflected in the following aspects: 1. Low-speed buses such as RS422 have limited bandwidth, making it difficult to transmit complete original star-sensor image data; 2. The onboard central computer can usually only acquire the attitude results processed by the star sensor alone, making it difficult to centrally acquire multiple channels of raw star map data, which is not conducive to unified processing, fusion analysis and playback verification; 3. The star-sensor algorithms are distributed across individual star-sensor machines, making algorithm upgrades, unified maintenance, and on-orbit adjustments inconvenient; 4. Multiple StarSense standalone machines are configured with independent processing resources, resulting in redundant hardware resource configuration and low system integration. 5. The output clocks of multiple star-sensor cameras are usually independent of each other and asynchronous with the clock of the central computer system, making cross-clock domain buffering and unified scheduling of multi-channel data quite difficult; 6. Spaceborne environments place higher demands on low power consumption, resistance to single-event effects, and high reliability. The traditional general-purpose processor plus low-speed bus transmission method is difficult to meet the requirements of high-speed transmission and high reliability.

[0020] To address the aforementioned technical problems, this embodiment proposes a high-speed transmission system and method for multi-channel star-aware image data suitable for spaceborne computers. This system enables the spaceborne central computer to directly receive raw image data output from multiple star-aware cameras and efficiently writes the star-aware image data into memory through reliable caching, unified scheduling, and DMA writing methods for subsequent algorithm processing or on-demand high-speed forwarding. Specifically, it includes the following: The multi-channel star-sensor image data high-speed transmission system includes a PolarFire SoC controller and DDR memory connected to the MSS processor subsystem of the PolarFire SoC controller.

[0021] The PolarFire SoC controller includes an MSS processor subsystem and an FPGA logic area.

[0022] The MSS processor subsystem is used to configure DMA transfer parameters, manage the buffer status in the DDR memory, and mark the corresponding buffer as readable after the DMA write is completed, so that the star-sensor processing algorithm can read it.

[0023] Specifically, the MSS processor subsystem includes a DMA configuration unit, an interrupt management unit, a star-aware algorithm unit, an exception management unit, and a DDR controller; The DMA configuration unit is used to configure the control and status register group of the DMA write module through the AXI bus interface to set the destination address and transmission length, and to trigger the DMA write module to start. The interrupt management unit is used to receive the transmission completion interrupt generated by the DMA write module and update the buffer state in the DDR memory according to the transmission completion interrupt. The star-sensor algorithm unit is used to read star-sensor image data marked as readable from DDR memory and perform star map recognition and attitude calculation. The anomaly management unit is used to receive the anomaly status reported by the cache scheduling module 1 and perform a reset or rebuild cache operation on the corresponding star channel. The DDR controller is used to control read and write access to the DDR memory.

[0024] The FPGA logic area includes an XCVR receiving channel, a buffer scheduling module 1, and a DMA write module, specifically: I. XCVR Receiving Channel The FPGA logic area includes at least an XCVR receiving channel for receiving high-speed serial star-sensor image data output from multiple star-sensor cameras and recovering parallel data and clock signals.

[0025] II. Cache Scheduling Module 1 The cache scheduling module 1 is used to complete frame header detection, cross-clock domain caching, bit width adaptation and channel scheduling of each star-sensor image data, and output the star-sensor image data to be written to the DDR memory.

[0026] Specifically, the cache scheduling module includes a star data cache submodule that is configured one-to-one with multiple star cameras and a channel scheduling submodule that is connected to multiple star data cache submodules; The star-sensitive data cache submodule includes a write control module and an asynchronous FIFO module; The write control module includes a frame header detection module and a frame length counting module, which are used to write the star image data of the corresponding star channel into the asynchronous FIFO module after detecting a preset frame header, and stop writing the current frame when the preset frame length is reached. The frame header detection module is used to detect the preset frame header in the corresponding star-sensor channel; The frame length counting module is used to count the length of the currently written star-sensor image frame and stop writing the current frame when the preset frame length is reached.

[0027] The asynchronous FIFO operates on the XCVR recovery clock domain of the corresponding star sensor camera on the write side and on the system clock domain on the read side. It is used to convert the data under the star sensor recovery clock domain to the system clock domain and to perform bit width adaptation according to the data interface requirements of the DMA write module, so as to adapt to the data interface bit width of the DMA write module.

[0028] The XCVR receiving channel restores the high-speed serial star-sensor image data output by each star-sensor camera into 16-bit parallel data. The asynchronous FIFO has a 16-bit data width on the write side and a 64-bit data width on the read side.

[0029] The cache scheduling module 1 starts frame header search of multiple star-sensor channels according to a preset scheduling cycle. When one of the star-sensor channels detects a valid frame header, the cache scheduling module locks the star-sensor channel and pauses the frame header search of other unlocked star-sensor channels. After the current star-sensor channel completes the caching of one frame of star-sensor image data, the cache scheduling module restarts the frame header search of other star-sensor channels.

[0030] The cache scheduling module 1 selects the star-sensitive channel to be transmitted based on the transmission ready signals output by each asynchronous FIFO and the channel polling order. The transmission ready signal indicates that the data cached in the asynchronous FIFO of the corresponding star-sensitive channel meets the DMA write condition. When a star-sensitive channel meets the transmission condition, the cache scheduling module uses that channel as a candidate transmission channel; when multiple star-sensitive channels simultaneously meet the transmission condition, the cache scheduling module selects one of them for transmission using a polling arbitration method.

[0031] III. DMA Write Module The DMA write module is used to write the star-sensor image data output by the cache scheduling module into the MSS-side DDR memory according to the DMA transfer parameters configured in the MSS.

[0032] The DMA write module includes an interface conversion module and a DMA controller; The interface conversion module is connected between the cache scheduling module 1 and the DMA controller, and is used to receive the star-sensor image data and corresponding channel identifiers output by the cache scheduling module 1, and adapt the star-sensor image data to the data input format of the DMA controller; The DMA controller includes a control and status register group, which includes a stream descriptor register, a transfer start register, and an interrupt status register. The stream descriptor register is used to configure one or more transmission parameters among the destination address, transmission length, and channel number; The DMA controller is used to write the star-sensor image data input via the interface conversion module into the DDR memory according to the configuration in the control and status register group.

[0033] Once a frame of star-sensor image data has been written, the DMA controller updates the interrupt status register and generates a transmission completion interrupt to the MSS.

[0034] Specifically, the MSS processor subsystem configures the control / status register group of the DMA write module through the AXI bus interface to set DMA transfer parameters and initiate DMA transfer. After the DMA write is completed, the DMA write module generates a transfer completion interrupt to the MSS. The MSS updates the DDR buffer status of the corresponding star-sensor channel according to the interrupt information and marks the buffer that has been written as readable for the star-sensor processing algorithm to read.

[0035] Furthermore, in this embodiment, at least two independent buffers can be set in the DDR memory for each star-sensor channel. The MSS manages the status of each buffer through a buffer status table, enabling DMA writes and star-sensor processing algorithm reads to be performed in parallel, avoiding data conflicts caused by both accessing the same buffer.

[0036] The buffer's state includes one or more of the following: idle, DMA writing, write complete, algorithm reading, and exception. When each star channel has two buffers, a ping-pong buffer structure can be formed; when each star channel has at least three buffers, a circular buffer queue can be formed.

[0037] Furthermore, in this embodiment, when any star-sensor channel fails to detect a valid frame header within a preset time, or when the corresponding asynchronous FIFO overflows, the buffer scheduling module 1 can mark the channel as abnormal and report it to the MSS. The MSS can perform anomaly counting, telemetry recording, FIFO clearing, channel reset, or restart the frame header search based on the abnormal status, thereby improving the maintainability and reliability of the system in a spaceborne environment.

[0038] Furthermore, the system may also include an XCVR high-speed forwarding unit. The XCVR high-speed forwarding unit is used to poll and arbitrate among the enabled star-sensor channels according to the channel enable information configured in the MSS, frame the selected star-sensor image data, and send it to the subsequent equipment through the XCVR transmission channel.

[0039] The XCVR high-speed forwarding unit is located in the FPGA logic area and includes a transmission buffer scheduling module 2, a framing module, and an XCVR transmission channel; The MSS is used to configure the channel enable information of the star-sensitive channel to be forwarded; The cache scheduling module 2 is used to cache the restored parallel data and perform polling arbitration among the enabled star channels according to the channel enable information. The framing module is used to frame the star-sensor image data selected by polling arbitration and generate star-sensor image data transmission frames. The XCVR transmission channel is used to send the framed star-sensor image data to the subsequent equipment.

[0040] The star-sensor image data transmission frame may include a frame header, channel identifier, and payload, as well as one or more fields such as data length, frame sequence number, timestamp, CRC check field, and frame tail.

[0041] The channel identifier is used to distinguish different star-sensor channels, the frame sequence number is used to determine the continuity of star-sensor image data, the time tag is used to align multiple star-sensor image data with the whole satellite time, and the CRC check field is used to detect transmission errors.

[0042] MSS can configure the star channels participating in forwarding based on the available transmission bandwidth of the downstream equipment, the number of star channels, and the data rate of each star channel.

[0043] When the available transmission bandwidth of the downstream device meets the total bandwidth required for time-division forwarding of all star-sensor channels, the MSS enables all star-sensor channels; when the available transmission bandwidth of the downstream device is insufficient to meet the total bandwidth required for time-division forwarding of all star-sensor channels, the MSS enables some star-sensor channels.

[0044] Therefore, this embodiment solves the problems existing in the prior art by constructing a high-speed transmission system for multi-channel star-sensor image data: 1. By receiving multiple channels of raw star sensor image data at high speed via XCVR, the bandwidth of star sensor data transmission is significantly improved compared to the traditional method of transmitting processed results via low-speed buses such as RS422. 2. By writing the star-aware image data to the MSS-side DDR memory via DMA, it is convenient for unified processing, fusion analysis and playback verification, which reduces the data handling burden of the MSS processor and improves the real-time performance of the system. At the same time, the original data is centrally stored on the central computer side, and the star-aware algorithm can be uniformly deployed on the MSS. Algorithm upgrades and maintenance do not need to involve each individual star-aware machine. 3. The multi-channel star-sensor image data high-speed transmission system is implemented based on the PolarFire SoC platform. It does not require each star-sensor to be configured with an independent processor. It has both FPGA real-time logic processing capabilities and MSS software configuration management capabilities, making it suitable for low-power and high-reliability applications of spaceborne computers. 4. By using asynchronous FIFO to complete cross-clock domain buffering and bit width adaptation of multiple star-sensitive data, the reliability of receiving multiple asynchronous high-speed data is improved; 5. Fair scheduling of multiple star-sensor channels is achieved through the transmission of ready signals and polling arbitration, making it suitable for scenarios with concurrent input of multiple star-sensor data. 6. Through the DDR buffer state management mechanism, DMA writing and star-sensor algorithm reading can be executed in parallel, avoiding data access conflicts and achieving highly reliable storage.

[0045] Implementation Method Two: This implementation method also provides a high-speed transmission method for multi-channel star-sensor image data based on a PolarFire SoC. The method includes: S1. Receive high-speed serial star-sensor image data output from multiple star-sensor cameras through the XCVR receiving channel, and recover the parallel data and clock. S2. Perform frame header detection on each star sensor image data. When a valid frame header is detected, write the current star sensor image frame into the corresponding asynchronous FIFO. S3. The asynchronous FIFO completes the cross-clock domain processing from the star-sensor recovery clock domain to the system clock domain, and completes the data bit width conversion. S4. The cache scheduling module polls and arbitrates among the star channels that meet the transmission conditions based on whether each star channel meets the transmission conditions, and selects the star channel to be transmitted. The transmission conditions are met, including the asynchronous FIFO output transmission ready signal of the corresponding star-sensor channel; the transmission ready signal includes the FIFO being full signal; when the transmission ready signals of multiple star-sensor channels are valid at the same time, the buffer scheduling module selects one of the star-sensor channels for transmission according to the polling order.

[0046] S5 and MSS configure the control / status register group of the DMA write module through the AXI bus interface to set DMA transfer parameters and start DMA transfer; the DMA write module writes the star image data of the star channel to be transferred into the DDR memory according to the DMA transfer parameters.

[0047] S6 and MSS update the DDR buffer status of the corresponding star channel based on the DMA transfer completion interrupt, and mark the buffer that has been written as readable for the star processing algorithm to read.

[0048] Furthermore, in one embodiment of this implementation, the method further includes a high-speed forwarding step of star-sensor image data: S71, MSS configures the channel enable information of the star-sensitive channel to be forwarded, and sends the channel enable information to the FPGA logic area; S72. The cache scheduling module in the FPGA logic area performs polling arbitration among the enabled star channels according to the channel enable information and selects the current star channel to be forwarded. S73. The framing module adds a frame header, channel identifier, and payload to the star-sensor image data corresponding to the current star-sensor channel to be forwarded, and adds one or more fields among data length, frame sequence number, time tag, CRC check field, and frame tail to generate a star-sensor image data transmission frame. S74, the XCVR transmission channel sends the star-sensor image data transmission frame to the downstream device.

[0049] Implementation Method 3: This implementation method is a specific embodiment proposed based on the system described in Implementation Method 1 and the method described in Implementation Method 2.

[0050] 1. System Overall Structure like Figure 1 As shown, the high-speed multi-channel star-sensor image data transmission system provided in this embodiment is built on the PolarFire SoC platform. The system mainly includes a PolarFire SoC controller, MSS-side DDR memory, XCVR high-speed transceiver, cache scheduling module, and DMA write module. The PolarFire SoC controller includes an MSS processor subsystem and an FPGA logic area. The MSS is mainly responsible for parameter configuration, buffer state management, interrupt handling, and algorithm scheduling, while the FPGA logic area is mainly responsible for the high-speed real-time data path.

[0051] Multiple star-sensors are connected to the XCVR receiving channel via a high-speed serial interface. The XCVR receiving channel recovers the input serial data and outputs parallel data and a recovered clock. Since the output clocks of each star-sensor are independent and do not have a fixed phase relationship with the system clock, an asynchronous FIFO is set after each star-sensor channel to perform cross-clock domain buffering.

[0052] In one specific embodiment, the system receives data from three star-sensor cameras, each with an output line rate of 2Gbps. The XCVR receive channel restores each serial data stream to 16-bit parallel data. This parameter is only one specific implementation; the number of star-sensor channels, input rate, and parallel data bit width can be adjusted according to the actual star-sensor interface protocol.

[0053] 2. Star-Sensitive Data Reception and Buffer Scheduling like Figure 2 As shown, the cache scheduling module 1 includes multiple star-sensor data cache submodules and channel scheduling submodules. Each star-sensor data cache submodule corresponds to one star-sensor channel and includes a frame header detection module, a write control module, an asynchronous FIFO, and a frame length counting module.

[0054] During system operation, the frame header detection module continuously monitors the parallel data stream of the corresponding channel. Upon detecting a preset frame header, the write control module begins writing the star-sensor image data for that channel into the asynchronous FIFO, while the frame length counting module starts counting. When the count reaches the preset frame length, the write control module stops writing the current frame. This method completes star-sensor image frame buffering based on frame header recognition and fixed frame length counting, without relying on frame tail detection.

[0055] The asynchronous FIFO operates on the star-sensitive recovery clock domain for writing and on the system clock domain for reading. Through the asynchronous FIFO, the system can safely transfer data from different star-sensitive recovery clock domains to a unified system clock domain for processing. Simultaneously, the asynchronous FIFO can also adapt its bit width according to the data interface requirements of the DMA write module. In one specific embodiment, the asynchronous FIFO's write side is 16-bit and its read side is 64-bit to improve the efficiency of subsequent DMA writes.

[0056] The cache scheduling module 1 initiates frame header searches for multiple star-sensor channels according to a preset scheduling period. In one specific embodiment, the scheduling period is 250ms, corresponding to a star-sensor image frame extraction frequency of 4Hz. When a star-sensor channel detects a valid frame header first, the cache scheduling module locks that channel and pauses frame header searches for other unlocked channels, ensuring that the current channel completes the buffering of one frame of star-sensor image data. After the current channel has completed buffering, the cache scheduling module restarts frame header searches for other channels.

[0057] When an asynchronous FIFO outputs a transmission ready signal, it indicates that the channel has met the DMA write conditions. In one specific embodiment, the transmission ready signal is a FIFO nearing full signal. When the transmission ready signals of multiple star channels are simultaneously valid, the channel scheduling submodule selects one star channel using a round-robin arbitration method and sends the data buffered in that channel to the DMA write link. In this way, multiple star channels can fairly share DMA write resources.

[0058] 3. DMA write, MSS configuration, and DDR buffer management like Figure 3 As shown, the DMA write module is used to write the star-sensor image data output by the cache scheduling module into the MSS-side DDR memory. The DMA write module includes a DMA controller and a control / status register group. The MSS accesses this control / status register group through the AXI bus interface to configure DMA transfer parameters and initiate DMA transfer.

[0059] The control / status register group may include a stream descriptor register, a transfer start register, and an interrupt status register. The stream descriptor register is used to configure transfer parameters such as destination address, transfer length, and channel number; the transfer start register is used to initiate DMA writes; and the interrupt status register is used to record the DMA transfer completion status or abnormal status.

[0060] The DMA controller receives the star-sensor image data and corresponding channel identifier from the buffer scheduling module, selects the DMA transfer parameters for the corresponding star-sensor channel based on the channel identifier, and writes the star-sensor image data for that channel into the corresponding buffer in the DDR memory. After one frame of star-sensor image data is written, the DMA write module updates the interrupt status register and generates a transfer completion interrupt to the MSS. Upon responding to the interrupt, the MSS updates the buffer status of the corresponding star-sensor channel.

[0061] like Figure 4 As shown, during system initialization, the MSS establishes a DDR buffer status table and configures DMA transfer parameters for each star-sensor channel. The DMA controller waits for the cache scheduling module to output data and channel identifiers. When a star-sensor data meets the transfer conditions, it selects the corresponding DMA transfer parameters based on the channel identifier and initiates the DMA write for that channel. After the DMA transfer is completed, the DMA controller generates an interrupt to the MSS. The MSS reads the interrupt status register to obtain the completed channel number and updates the buffer status and the next DMA destination address for that channel accordingly. To avoid conflicts between DMA writes and star-sensor processing algorithm reads, each star-sensor channel has at least two independent buffers in the DDR memory. The MSS manages the status of each buffer through a buffer status table, which can include idle, DMA write in progress, write complete, algorithm read in progress, and exception.

[0062] When each star-sensor channel is configured with two buffers, a ping-pong buffer structure is formed. For example, when DMA writes to buffer A, the star-sensor processing algorithm can read the data from the previous frame that has already been read in buffer B. When buffer A has finished writing and buffer B has finished reading by the algorithm, the MSS marks buffer A as readable, and the next frame of data can be switched to be written to buffer B. If buffer B is currently being read by the algorithm, the MSS does not change the state of buffer A, and the next frame of data is still written to buffer A.

[0063] In another implementation, each star-sensor channel can be configured with three or more buffers, forming a circular buffer queue. The MSS selects an idle buffer as the destination buffer for the next DMA write based on the buffer status table, and provides buffers that have been written to but not occupied by the algorithm for reading by the star-sensor processing algorithm. This method is suitable for scenarios where algorithm processing time fluctuates.

[0064] 4. Exception Handling In one implementation, the buffer scheduling module also performs anomaly detection on the star-sensor receiving link. When any star-sensor channel fails to detect a valid frame header within a preset time, or when the corresponding asynchronous FIFO overflows, the buffer scheduling module marks the channel as abnormal and reports the abnormal status to the MSS.

[0065] Upon receiving an anomaly, the MSS can record the anomaly count and telemetry status. For recoverable anomalies, the MSS can reinitialize the corresponding star-sensor channel's buffer state, clear the corresponding FIFO, or restart the frame header search. For persistent anomalies, the MSS can maintain the anomaly marker for that channel and wait for further processing by ground control or upper-level missions. This anomaly handling mechanism is not a necessary step for normal star-sensor data transmission, but rather serves to improve the system's maintainability and reliability in a spaceborne environment.

[0066] 5. Optional XCVR high-speed forwarding like Figure 1 As shown, in one optional embodiment, the system further includes an XCVR high-speed forwarding unit. This unit includes a transmission buffer scheduling module 2, a framing module, and an XCVR transmission channel.

[0067] MSS configures the channel enable information for the star-sensor channels to be forwarded. The cache scheduling module 2, based on this channel enable information, performs frame header search and data caching, and conducts round-robin arbitration among the enabled star-sensor channels to select the current star-sensor channel to be forwarded. The framing module frames the selected star-sensor image data, generating a star-sensor image data transmission frame. The XCVR transmission channel sends the framed star-sensor image data transmission frame to the subsequent devices.

[0068] The transmission frame includes at least a frame header, a channel identifier, and a payload. Depending on the parsing and reliability requirements of downstream equipment, the transmission frame may also include one or more of the following: data length, frame sequence number, timestamp, CRC check field, and frame trailer. The channel identifier distinguishes different star-sensor channels, the frame sequence number determines data continuity, the timestamp aligns the star-sensor image data with the overall satellite time, and the CRC check field detects transmission errors.

[0069] MSS can configure channel enabling information based on the available transmission bandwidth of the downstream devices, the number of star channels, and the data rate of each star channel. When the available transmission bandwidth of the downstream devices is insufficient to meet the total bandwidth required for time-division forwarding of all star channels, MSS can enable some star channels to participate in forwarding; when the available transmission bandwidth of the downstream devices meets the total bandwidth required for time-division forwarding of all star channels, MSS can enable all star channels to participate in forwarding. The transmission scheduling module performs round-robin transmission among the enabled channels.

[0070] It should be noted that the XCVR high-speed forwarding unit is an optional extension link, which is used to frame and transmit the star-sensor image data involved in the forwarding.

[0071] 6. System Workflow like Figure 5 As shown, after the system powers on, the MSS first completes the initialization configuration of the XCVR, cache scheduling module, DMA write module, and DDR buffer. Subsequently, the XCVR receive channel begins to receive high-speed serial star-sensor image data output from multiple star-sensor cameras and recovers the parallel data and clock.

[0072] After each star-sensor data stream enters its corresponding star-sensor data buffer submodule, the frame header detection module identifies valid frames. Upon detecting a valid frame header, the write control module writes the current frame data to the asynchronous FIFO and stops writing after reaching the preset frame length. The asynchronous FIFO converts the data to the system clock domain and outputs a transmission ready signal to the buffer scheduling module.

[0073] When one or more star-sensor channels meet the transmission conditions, the buffer scheduling module selects the star-sensor channel to be transmitted using a round-robin arbitration method. The MSS configures the control / status register group of the DMA write module via the AXI bus interface, setting transmission parameters such as destination address, transmission length, and channel number, and then initiates DMA writing. The DMA write module writes the star-sensor image data of the selected channel into the MSS-side DDR memory.

[0074] After the DMA write is complete, the MSS reads the interrupt status register to obtain the completion channel number and selects the next DMA write destination address based on the buffer status of that channel. If a free buffer exists, it is selected; otherwise, the previous write buffer for that channel is reused as the destination address. The star-sensor processing algorithm can then read the star-sensor image data in this buffer for further processing.

[0075] For scenarios requiring high-speed forwarding, MSS can also configure the channel enable information for the star-sensor channels to be forwarded. The transmission scheduling module performs polling arbitration among the enabled channels, the framing module frames the star-sensor image data of the selected channel, and sends it to the downstream device through the XCVR transmission channel.

[0076] Through the above implementation method, this embodiment enables high-speed reception, reliable caching, unified scheduling, and DMA writing of multiple star-aspect image data on the PolarFire SoC platform. Compared with the traditional scheme where attitude results are sent to the central computer via low-speed buses such as RS422 after processing within the star-aspect unit, this embodiment allows the onboard central computer to directly acquire multiple raw star-aspect image data, facilitating unified algorithm processing, unified data management, and on-orbit upgrades. It also reduces the processor's data handling burden and improves star-aspect data transmission bandwidth, real-time performance, and system integration.

[0077] The above provides a detailed description of a high-speed multi-channel star-sensor image data transmission system and method based on PolarFire SoC proposed in this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC, characterized in that, The system includes a PolarFire SoC controller and DDR memory; The PolarFire SoC controller includes an FPGA logic area and an MSS processor subsystem; The FPGA logic area includes an XCVR receiving channel, a buffer scheduling module 1, and a DMA write module; The XCVR receiving channel is used to receive high-speed serial star-sensor image data output from multiple star-sensor cameras, and recover parallel data and recover the clock. The cache scheduling module 1 is used to perform frame header detection, cross-clock domain buffering, bit width conversion and channel scheduling on parallel data and recovery clock, and output star-sensor image data. The DMA write module is used to write the star-sensor image data output by the cache scheduling module 1 into the DDR memory. The MSS processor subsystem is used to configure the transmission parameters of the DMA write module, manage the buffer status in the DDR memory, and mark the corresponding buffer as readable after the DMA write module writes the star-sensor image data into the DDR memory, so that the star-sensor processing algorithm can read it. The DDR memory is used to store star-sensor image data.

2. The high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC according to claim 1, characterized in that, The MSS processor subsystem includes a DMA configuration unit, an interrupt management unit, a star-aware algorithm unit, an exception management unit, and a DDR controller; The DMA configuration unit is used to configure the control and status register group of the DMA write module through the AXI bus interface to set the destination address and transmission length, and to trigger the DMA write module to start. The interrupt management unit is used to receive the transmission completion interrupt generated by the DMA write module and update the buffer state in the DDR memory according to the transmission completion interrupt. The star-sensor algorithm unit is used to read star-sensor image data marked as readable from DDR memory and perform star map recognition and attitude calculation. The anomaly management unit is used to receive the anomaly status reported by the cache scheduling module 1 and perform a reset or rebuild cache operation on the corresponding star channel. The DDR controller is used to control read and write access to the DDR memory.

3. The high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC according to claim 1, characterized in that, The cache scheduling module 1 includes multiple star data cache sub-modules and channel scheduling sub-modules configured corresponding to the multiple star cameras; The star-sensitive data cache submodule includes a write control module and an asynchronous FIFO module; The write control module includes a frame header detection module and a frame length counting module, which are used to write the star image data of the corresponding star channel into the asynchronous FIFO module after detecting a preset frame header, and stop writing the current frame when the preset frame length is reached. The asynchronous FIFO module is used to realize cross-clock domain processing from the recovery clock domain of the XCVR receiving channel to the system clock domain of the PolarFire SoC controller, and to perform bit width adaptation to adapt to the data interface bit width of the DMA write module. The channel scheduling submodule is used to select the star-sensitive channel to be transmitted based on the transmission ready signal output by each asynchronous FIFO module. When multiple transmission ready signals are valid at the same time, one of the star-sensitive channels is selected for transmission according to the polling order.

4. The high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC according to claim 3, characterized in that, The asynchronous FIFO module has a 16-bit data width on the write side and a 64-bit data width on the read side.

5. The high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC according to claim 1, characterized in that, The DMA write module includes an interface conversion module and a DMA controller; The interface conversion module is connected between the cache scheduling module 1 and the DMA controller, and is used to receive the star-sensor image data and corresponding channel identifiers output by the cache scheduling module 1, and adapt the star-sensor image data to the data input format of the DMA controller; The DMA controller is used to write the star-sensor image data input via the interface conversion module into the DDR memory according to the configuration in the control and status register group.

6. The high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC according to claim 5, characterized in that, The control and status register group includes a stream descriptor register, a transfer start register, and an interrupt status register.

7. The high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC according to claim 1, characterized in that, The DDR memory is configured with at least two independent buffers for each star channel; When each star-sensor channel is equipped with two independent buffers, a ping-pong buffer structure is formed; When each star-sensor channel is equipped with no fewer than three independent buffers, a circular buffer queue is formed.

8. The high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC according to claim 1, characterized in that, The system also includes an XCVR high-speed forwarding unit, which includes a buffer scheduling module 2, a frame assembly module, and an XCVR transmission channel. The cache scheduling module 2 is used to cache the parallel data recovered by the XCVR receive channel according to the channel enable information configured in the MSS processor subsystem, and to perform polling arbitration among the enabled star channels to select the current star channel to be forwarded. The framing module is used to frame the selected current star-sensor channel to be forwarded, and generate star-sensor image data transmission frames. The XCVR transmission channel is used to send star-sensor image data transmission frames to the downstream device.

9. The high-speed transmission system for multi-channel star-sensor image data based on PolarFire SoC according to claim 8, characterized in that, The star-sensor image data transmission frame includes at least a frame header, a channel identifier, and a payload.

10. A method for high-speed transmission of multi-channel star-sensor image data based on PolarFire SoC, the method being used to implement the system described in any one of claims 1 to 9, characterized in that, Includes the following steps: Step 1: Receive high-speed serial star-sensor image data output from multiple star-sensor cameras through the XCVR receiving channel, and recover the parallel data and clock. Step 2: Frame header detection is performed on the parallel data. When a preset frame header is detected, the star sensor image data of the corresponding star sensor channel is written into the asynchronous FIFO module. Step 3: The asynchronous FIFO module completes the cross-clock domain processing from the recovery clock domain of the XCVR receiving channel to the system clock domain of the PolarFire SoC controller, and completes the data bit width conversion. Step 4: The buffer scheduling module 1 selects the star channel to be transmitted based on the transmission ready signal output by each asynchronous FIFO module. When multiple transmission ready signals are valid at the same time, one of the star channels is selected for transmission according to the polling order. Step 5: The MSS processor subsystem configures the control and status register group of the DMA write module through the AXI bus interface to set the destination address and transmission length, and triggers the DMA write module to start. The DMA write module writes the star image data of the star channel to be transmitted into the DDR memory according to the transmission parameters. Step 6: The MSS processor subsystem updates the buffer status of the corresponding star channel based on the transfer completion interrupt generated by the DMA write module, and marks the buffer that has been written as readable so that the star processing algorithm can read it.

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