Opto-electric image transmission system and method

Abstract

The application discloses a photoelectric image transmission system and method, which comprises a photoelectric signal collection module, which receives photoelectric image data collected from the outside world and transmits the data to a photoelectric image coding transmission module; the photoelectric image coding transmission module converts the received image data into 32-bit UDP protocol AXI4-stream data, and then performs secondary coding through an Aurora 64b / 66b encoder and transmits the data to a UDP frame data exchange module through a GTX high-speed transceiver; the UDP frame data exchange module performs routing forwarding on the received image UDP frame according to a pre-configured routing table, transmits the data frame to a destination port, and a photoelectric image UDP frame receiving and restoring module receives serial data from the UDP frame data exchange module, writes the decoded image data into a large-capacity memory at a first clock frequency, reads out the image data from the large-capacity memory at a pixel clock frequency lower than the first clock frequency, and restores the image row field signal. The application realizes low-delay real-time transmission of various photoelectric images on an FPGA.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic image data transmission, and specifically relates to an optoelectronic image transmission system and method based on the UDP protocol.

[0002] Background technology.

[0003] With the rapid development of optoelectronic technology, the application of optoelectronic devices is becoming increasingly widespread. Optoelectronic devices are modern reconnaissance systems that use imaging devices such as visible light, television, and infrared thermal imagers as sensors. They integrate information monitoring, processing, countermeasures, interconnection, transmission, storage, and control, providing stable, high-resolution image data. Optoelectronic technology has evolved from distributed arrays to multifunctional, multi-band integrated arrays. Digital imaging technology supports high resolution and high frame rates, requiring optoelectronic devices to see more clearly and react faster. This places demands on image data transmission systems with high bandwidth, low latency, multipath support, and large storage space.

[0004] Image data transmission systems are a crucial component of optoelectronic equipment. In existing technologies, traditional image data transmission systems employ a fiber optic transmission + FPGA (Field-Programmable Gate Array) processing model. Fiber optic transmission is widely used due to its low power consumption and high bandwidth. The FPGA integrates a GTX (Gigabit Transceiver) serial high-speed transceiver, which can serve as the transmission and forwarding medium. Because of its high parallel processing speed, the FPGA is particularly suitable for embedding protocol stacks in high-speed transmission fields, improving system operating speed. This fiber optic transmission system uses a multi-channel image data combination codec + Aurora 8b / 10b encoding protocol solution. However, this system can only achieve point-to-point transmission, resulting in a single transmission path and significant bandwidth loss. Furthermore, the image data encoder and decoder consume a large amount of FIFO resources, creating resource constraints for the joint deployment of image processing algorithms such as image tracking, recognition, and early warning. 10 Gigabit Ethernet is widely used in high-speed image data transmission. UDP / IP protocols can achieve image on-demand and multicast transmission modes, but network switching leads to significant latency. 10 Gigabit Ethernet is suitable for image display and image data storage applications. Neither fiber optic transmission nor 10 Gigabit Ethernet transmission modes can meet the image data transmission performance requirements of integrated array optoelectronic equipment. Therefore, considering the real-time acquisition characteristics of photoelectric image signals, a photoelectric image transmission technology that balances real-time performance, low latency, and multi-path transmission is needed. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes a photoelectric image transmission system and method that enables low-latency real-time transmission of various photoelectric images on an FPGA.

[0006] The objective of this invention is achieved through the following technical solution: a photoelectric image transmission system, comprising: The photoelectric signal acquisition module receives photoelectric image data collected from the outside world and transmits it to the photoelectric image encoding and transmission module; The photoelectric image encoding and transmission module converts the received image data into 32-bit UDP protocol AXI4-stream data, then performs secondary encoding through an Aurora 64b / 66b encoder, and transmits it to the UDP frame data exchange module through a GTX high-speed transceiver. The UDP frame data exchange module routes and forwards the received image UDP frames according to the pre-configured routing table, transmitting the data frames to the destination port; The photoelectric image UDP frame receiving and recovery module receives serial data from the UDP frame data exchange module, writes the decoded image data into a large-capacity memory at a first clock frequency, and then reads the image data from the large-capacity memory at a pixel clock frequency lower than the first clock frequency to recover the image line and field signals.

[0007] Preferably, the photoelectric signal acquisition module uses a CMOS high-speed image sensor with a resolution of 4K, YUV format, and a frame rate of 30fps, and the sensor output interface is MIPI-CSI2.

[0008] Preferably, the input interface of the photoelectric image encoding and transmission module is the image line and field signals, and a three-line image buffering mechanism is adopted. The input image data is cyclically written into three FIFO spaces in sequence; the output interface of the photoelectric image encoding and transmission module adopts the AXI4-stream protocol.

[0009] Preferably, the photoelectric image encoding and transmission module includes: Image buffer controller, which buffers complete image data in FIFO; When the image buffer controller buffers a complete line of image data in the FIFO, the data encoding controller requests to read the image data in the FIFO. Based on the image input format type, it selects different encoding methods to convert the image data into 32-bit UDP protocol AXI4-stream data.

[0010] Preferably, the image buffer controller uses a line of images as a processing unit, packages image data in message format according to the image encoding protocol, and adds message headers and message trailers.

[0011] Preferably, the photoelectric image encoding and transmission module adopts a UDP frame uniformity method, which achieves uniform output of all UDP frames by controlling the UDP frame output interval.

[0012] Preferably, the UDP frame data exchange module is based on the OSI layered model, which divides the optical signal data transmission network into the physical layer, data link layer and transport layer. The data link layer and transport layer are implemented through the Aurora protocol and the UDP protocol, respectively. The 16 exchange nodes communicate with the data exchange module through the GTX transceiver to complete the reception, buffering and forwarding of UDP frames, and build a complete local area exchange network.

[0013] Preferably, the data transceiver channel of the UDP frame data exchange module completes the reception and transmission of UDP frame data between ports A and B, performs 64b / 66b protocol encoding / decoding and serial-to-parallel conversion, and transmits at high speed through a GTX transceiver. The UDP frame data exchange module is designed based on a crossbar structure for the switching network. By setting a switching routing table, it realizes the data exchange routing between ports B and C. Each port B has both receiving and sending functions. The exchanged cells adopt the UDP frame format. The cell header data includes the source port number, destination port number, effective length, and check information. The destination port number is configured as a point-to-point or multicast type address. The UDP frame data exchange module maps the cell address information to the data transmission path by looking up the routing table. The point-to-point data uses a point-to-point transmission mode, and multiple cells can be sent to the same port simultaneously to realize a multi-point transmission mode. The multicast data uses a point-to-multicast transmission mode.

[0014] Preferably, the photoelectric image UDP frame reception and recovery module includes: PL writes image data to DDR3 by autonomously controlling the AXI4 bus; The DDR3 SDRAM consists of two MT41K256M16 chips, with a storage capacity of 512MB and a data interface width of 16 bits. The Aurora 64b / 66b decoder receives image UDP frames transmitted by the UDP frame data exchange module. The timing conversion controller converts the AXI4-stream data stream into an AXI4 data stream. The PL writes the image data into DDR3 by autonomously controlling the AXI4 bus. DDR3 is configured with a 4-frame image buffer address space. The status controller controls the read and write operations of the IP core. When an image UDP frame enters the photoelectric image UDP frame receiving and recovery module, the IP core performs a DDR3 write operation. When the address space of the image buffer for that frame is full, the system automatically jumps to the address space of the next frame. The image controller recovers the image data by processing one line of image data as the smallest unit. When a line of image data UDP frame is written to DDR3, PL reads the image data in DDR3 through the AXI4 bus, and decodes and recovers the image line and field signals using the pixel clock according to the image encoding protocol.

[0015] In addition to providing a photoelectric image transmission system, this invention further provides a method for implementing photoelectric image transmission using the above system, the method comprising the following steps: The photoelectric signal acquisition module acquires the horizontal and vertical signals of the image. The image line and field signals are encapsulated into data frames conforming to the connectionless transmission protocol format to obtain a data stream in the streaming transmission protocol format. The photoelectric image encoding and transmission module transmits the data stream to the frame data exchange module via a high-speed serial transceiver after high-speed serial encoding. The UDP frame data exchange module routes and forwards the data frames according to the pre-configured routing table, transmitting the data frames to the destination port; The photoelectric image UDP frame receiving and recovery module receives serial data from the destination port and writes the decoded image data into a large-capacity memory at a first clock frequency; the photoelectric image UDP frame receiving and recovery module reads the image data from the large-capacity memory at a pixel clock frequency lower than the first clock frequency and recovers the image line and field signals.

[0016] The beneficial effects of this invention are as follows: As can be seen from the above scheme, the photoelectric image transmission system and method provided by this invention overcomes the limitations of the traditional point-to-point transmission mode of photoelectric image fiber optic transmission. It performs a lightweight modification of the UDP protocol and proposes a new photoelectric image transmission architecture based on the UDP protocol, realizing multiple transmission modes such as point-to-point, point-to-many, and many-to-point. It forms a local area switching network. UDP is a connectionless protocol, eliminating the need for the TCP protocol's "three-way handshake" to establish a connection, effectively reducing transmission latency.

[0017] This invention proposes a novel optoelectronic image data encoding protocol that covers all types of optoelectronic images, supports image formats such as RGB, GRAY, and YUV, and supports 1TAP, 2TAP, and 4TAP image data input methods. This invention uses DDR3 SDRAM to replace FIFO as the image UDP frame receiving buffer medium, reducing the FIFO resource occupancy rate, and utilizes the large storage space of DDR3 SDRAM to achieve low-frequency clock decoding to recover the image line and field signals.

[0018] The actual effective bandwidth of this invention reaches 8.04 Gbit / s, far exceeding the effective bandwidth of 6.6 Gbit / s of traditional optical fiber image transmission technology. It can transmit 4K (3840) When transmitting images at 2160 resolution, the total image transmission latency is as low as 60µs, avoiding large latency (usually 30ms) in wide area network environments.

[0019] This invention uses the Aurora 64b / 66b encoding protocol instead of the Aurora 8b / 10b encoding protocol, which theoretically reduces bandwidth loss by 17%. Attached Figure Description

[0020] Figure 1 This is a flowchart of the photoelectric image transmission method based on the UDP protocol in an embodiment of the present invention; Figure 2 This is a flowchart illustrating the design of the photoelectric image encoding and transmission module in an embodiment of the present invention. Figure 3 This is a schematic diagram of the photoelectric image encoding principle in an embodiment of the present invention; Figure 4 This is a schematic diagram of the UDP frame protocol AXI4-stream data format in an embodiment of the present invention; Figure 5 This is a UDP frame smoothing method in an embodiment of the present invention; Figure 6 This is a schematic diagram of the UDP frame data exchange path in an embodiment of the present invention; Figure 7 This is a flowchart illustrating the design of the photoelectric image UDP frame reception and recovery module in this embodiment of the invention. Figure 8 This is a schematic diagram of the DDR3 image data storage mode in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in this embodiment will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0022] like Figures 1 to 3As shown, the technical solution of this invention provides a photoelectric image transmission system and method. Addressing the limitations of traditional point-to-point transmission in optical fiber image transmission and avoiding high latency in network transmission, a photoelectric image data transmission system based on the UDP protocol is proposed. This system is based on the electrical architecture of a photoelectric signal processor using the VPX (Virtual Path Cross-Connect) chassis standard. Combining the advantages of high-speed optical fiber transmission and multi-mode transmission via 10 Gigabit Ethernet, the UDP protocol is lightweighted to construct a UDP frame image data transmission architecture, enabling on-demand and multicast transmission functions. A photoelectric image encoding and decoding protocol is designed, using Aurora 64b / 66b instead of Aurora 8b / 10b encoding protocol to improve transmission bandwidth and reduce transmission latency. DDR3 SDRAM is used instead of FIFO to store image data, reducing FIFO resource occupancy and enabling low-frequency clock decoding of image data. This system achieves low-latency, high-bandwidth, multi-path, real-time transmission of image data, solving the problems of multi-path transmission of multiple images and fusion of multiple image algorithms in the context of integrated array photoelectric equipment applications. The photoelectric image transmission system provided in this embodiment includes: The photoelectric signal acquisition module receives photoelectric image data acquired from the outside and transmits it to the photoelectric image encoding and transmission module. The photoelectric image encoding and transmission module converts the received image data into 32-bit UDP protocol AXI4-stream data, then performs secondary encoding using an Aurora 64b / 66b encoder, and transmits it to the UDP frame data exchange module via a GTX high-speed transceiver. The UDP frame data exchange module routes and forwards the received image UDP frames according to a pre-configured routing table, transmitting the data frames to the destination port. The photoelectric image UDP frame reception and recovery module receives serial data from the UDP frame data exchange module, writes the decoded image data to a large-capacity memory at a first clock frequency, and then reads the image data from the large-capacity memory at a pixel clock frequency lower than the first clock frequency to recover the image line and field signals. The objective of this invention can be achieved through three key technologies: photoelectric image encoding and transmission technology; UDP frame data exchange technology; and photoelectric image UDP frame reception, decoding, and image recovery technology. Figure 1 As shown, the system is configured as follows: (1) Hardware platform: The ZYNQ series FPGA chip is used as the core hardware processor. The internal hardware computing resources of the FPGA chip are used to quickly complete the image data protocol conversion. The GTX serial transceiver is used instead of the codec chip to realize the serial-to-parallel conversion function of the data.

[0023] (2) Optoelectronic Image Encoding and Transmission: Implement the function of converting the input signal of optoelectronic image to UDP data protocol and outputting image UDP frames, and design the image message encoding protocol. The input TV and infrared image signals are converted into AXI4-stream parallel data of UDP protocol. The Aurora 64b / 66b encoding module converts the AXI4-stream parallel data into serial data, and finally transmits it to the UDP data exchange system through the GTX high-speed transceiver. The AXI4-stream protocol is used for unidirectional data transmission from the master system to the slave system, cancels address mapping, allows unlimited data packet length, and is suitable for high-speed data stream transmission inside the FPGA. Aurora 64b / 66b is used for one or more GTX transceivers to transmit data between devices, connected in full-duplex (bidirectional data) or simplex (data in either direction) mode.

[0024] (3) UDP frame data exchange: Construct an internal data exchange system for the electronic chassis. All terminals interact with the UDP frame data exchange module through GTX, configure the exchange path routing table, and transmit UDP frames to the destination port of the data exchange system.

[0025] Photoelectric image UDP frame reception, decoding and image recovery: Receive image UDP frame data stream, buffer the image data in DDR3 SDRAM, then decode and recover the image line and field signals according to the image decoding protocol, and apply the recovered image data to various image processing algorithms.

[0026] In one embodiment of the present invention, the photoelectric signal acquisition module is selected with a resolution of 4K (3840). The sensor is a CMOS high-speed image sensor with a 2160 (YUV) format and a frame rate of 30fps. The sensor output interface is MIPI-CSI2. The built-in automatic exposure (AE) and automatic white balance (AWB) modules ensure the brightness and color stability of the original image data.

[0027] like Figure 2As shown, in one embodiment of the present invention, the input interface of the photoelectric image encoding and transmission module is the image line and field signals (Fval, Lval, Data). A three-line image buffering mechanism is adopted, with input image data being cyclically written into three FIFO spaces. When the image buffer controller buffers a complete line of image data in the FIFO, the data encoding controller requests to read the image data from the FIFO. Based on the image input format type, different encoding methods are selected to convert the image data into 32-bit UDP protocol AXI4-stream data. The user configures the source port number, destination port number of the UDP frame, and parameters such as the image resolution and image type of the image encoded message. The AXI4-stream data stream undergoes secondary encoding through an Aurora 64b / 66b encoder and is finally transmitted to the data exchange module via a GTX high-speed transceiver to complete the image transmission operation. The image data encoding controller processes each line of image data as a unit, packages the image data in a message format according to the image encoding protocol, and adds a message header and message trailer. The message information includes a message start identifier character, image resolution, image type, current line number, current frame number, etc., and the message trailer is a message end identifier character. The second step involves packetizing the image messages according to the UDP frame format, generating N AXI4-stream data packets using the UDP frame protocol for each image line. The principle of the image data encoder is as follows: Figure 3 As shown. The output interface of the optoelectronic image encoding and transmission module adopts the AXI4-stream (tdata, tvalid, tready, tlast) protocol. The AXI4-stream interface supports low-resource, high-bandwidth unidirectional data transmission. The transmission protocol allows for a trade-off between high frequency and clock delay, supports ZYNQ series chips, and is a general-purpose transmission protocol suitable for data interaction between different IP cores. To meet the data exchange function requirements, the output AXI4-stream data packets adopt the UDP frame format, adding UDP frame header information (source port number, destination port number, length, checksum). The UDP protocol AXI4-stream data packet format is as follows. Figure 4 As shown.

[0028] In one embodiment of the present invention, in the application scenario of simultaneous transmission of multiple images, the total transmission bandwidth does not exceed the maximum transmission bandwidth of GTX, and the impact of instantaneous bandwidth on the transmission link must be considered. When transmitting multiple high-bandwidth image data using time-division multiplexing transmission mode, if the instantaneous bandwidth is too high, a certain image encoding and transmission module may experience FIFO overflow due to excessive waiting time, resulting in the loss of some image UDP frames. To avoid the risks caused by excessive instantaneous bandwidth, the present invention proposes a UDP frame smoothing method, such as... Figure 5As shown, by controlling the UDP frame output interval, all UDP frames are output evenly, alleviating the pressure of FIFO buffer data backlog and ensuring the stability of the multi-channel image synchronous transmission mode.

[0029] In one embodiment of the present invention, the UDP frame data exchange module is based on the OSI layered model, dividing the optical signal data transmission network into a physical layer, a data link layer, and a transport layer. The data link layer and the transport layer are implemented using the Aurora protocol and the UDP protocol, respectively. Sixteen switching nodes communicate with the data exchange module through a GTX transceiver to complete the reception, buffering, and forwarding of UDP frames, thus constructing a complete local area switching network. The UDP frame data exchange system is as follows: Figure 6 As shown, the data transceiver channel handles the reception and transmission of UDP frames between ports A and B, performing 64b / 66b protocol encoding / decoding and serial-to-parallel conversion, and high-speed transmission via a GTX transceiver. The system is designed based on a Crossbar architecture, which enables the establishment of multiple transmission routes and non-blocking transmission of multiple data packets, meeting the application requirements of various high-speed transmission scenarios. A switching routing table is set up to realize data exchange routing between ports B and B, with each port B having both receiving and sending capabilities. The exchanged cells use UDP frame format, with the cell header including source port number, destination port number, effective length, and checksum. The destination port number can be configured as a point-to-point or multicast address. The switching system maps cell address information to data transmission paths by looking up the routing table. Point-to-point data uses a point-to-point transmission mode, allowing multiple cells to be sent simultaneously to the same port, achieving a multi-point transmission mode. Multicast data uses a point-to-multicast transmission mode. The switching architecture is as follows. Figure 6 As shown.

[0030] In one embodiment of the present invention, the photoelectric image receiving and recovery module consists of a Programmable Logic (PL) and a DDR3 SDRAM. The DDR3 is composed of two MT41K256M16 chips, each with a storage capacity of 512MB and a 16-bit data interface width. One frame of a YUV format 4K image requires 16.6MB of memory, and 1GB of memory is sufficient to store multiple frames of 4K image data. AXI4 is the fourth-generation AMBA interface specification introduced by ARM. AXI4 is used for memory-mapped interfaces, allowing high-throughput burst read / write operations of up to 256 data transfer cycles in a single addressing cycle. The ZYNQ7 Processing System IP core controls the data read / write operations of the DDR3. The IP core provides a 533.33MHz operating clock to the DDR3 through internal multiplication and division. The DDR3 is dual-edge triggered, meaning that data reception and transmission can occur on both the rising and falling edges of the reference clock signal, thus supporting a bandwidth of up to 33.33Gbit / s. The principle of the photoelectric image receiving and recovery module is as follows: Figure 7 As shown, the Aurora64b / 66b decoder receives image UDP frames transmitted by the UDP data exchange system. The timing conversion controller converts the AXI4-stream data stream into an AXI4 data stream. The PL (Programmer) autonomously controls the AXI4 bus to write image data into DDR3. DDR3 is configured with a 4-frame image buffer address space. The status controller controls the read and write operations of the entire IP core. When an image UDP frame enters this module, the IP core performs a DDR3 write operation. When the image buffer address space for that frame is full, the system automatically jumps to the next frame address space. The image recovery controller uses one line of image as the smallest processing unit. When one line of image UDP frame is written to DDR3, the PL reads the image data from DDR3 through the AXI4 bus, decodes it using the pixel clock according to the image encoding protocol, and recovers the image line and field signals. To solve the problem of high-frequency clock decoding of image data caused by the FIFO buffer image data mode, this embodiment uses DDR3 SDRAM to replace the FIFO buffer image UDP frame data, effectively reducing the decoding clock frequency and facilitating its integration with image processing algorithms. DDR3 has a sufficiently large storage space and can serve as a "reservoir" for image data. Figure 8 As shown, the photoelectric image UDP frame receiving and recovery module receives image UDP frames at high speed, writes them sequentially into DDR3 according to the address mapping relationship, and splices them into a line to complete the image data. Then, a low-frequency pixel clock is used to read each line of image data from DDR3, forming a "fast in, slow out" working mode. This mode makes full use of hardware memory resources, reduces the FIFO resource occupancy rate, and finally outputs uniform image line and field signals.

[0031] In addition to providing a photoelectric image transmission system, the present invention further provides a method for implementing photoelectric image transmission using the above system, the method comprising the following steps: The photoelectric signal acquisition module acquires the horizontal and vertical signals of the image. The image line and field signals are encapsulated into data frames conforming to the connectionless transmission protocol format to obtain a data stream in the streaming transmission protocol format. The photoelectric image encoding and transmission module transmits the data stream to the frame data exchange module via a high-speed serial transceiver after high-speed serial encoding. The UDP frame data exchange module routes and forwards the data frames according to the pre-configured routing table, transmitting the data frames to the destination port; The photoelectric image UDP frame receiving and recovery module receives serial data from the destination port and writes the decoded image data into a large-capacity memory at a first clock frequency; the photoelectric image UDP frame receiving and recovery module reads the image data from the large-capacity memory at a pixel clock frequency lower than the first clock frequency and recovers the image line and field signals.

[0032] The above are preferred embodiments of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A photoelectric image transmission system, characterized in that: The system includes: The photoelectric signal acquisition module receives photoelectric image data collected from the outside world and transmits it to the photoelectric image encoding and transmission module; The photoelectric image encoding and transmission module converts the received image data into 32-bit UDP protocol AXI4-stream data, then performs secondary encoding through an Aurora 64b / 66b encoder, and transmits it to the UDP frame data exchange module through a GTX high-speed transceiver. The UDP frame data exchange module routes and forwards the received image UDP frames according to the pre-configured routing table, transmitting the data frames to the destination port; The photoelectric image UDP frame receiving and recovery module receives serial data from the UDP frame data exchange module, writes the decoded image data into a large-capacity memory at a first clock frequency, and then reads the image data from the large-capacity memory at a pixel clock frequency lower than the first clock frequency to recover the image line and field signals.

2. The photoelectric image transmission system as described in claim 1, characterized in that: The photoelectric signal acquisition module uses a CMOS high-speed image sensor with a resolution of 4K, YUV format, and a frame rate of 30fps. The sensor output interface is MIPI-CSI2.

3. The photoelectric image transmission system as described in claim 2, characterized in that: The input interface of the photoelectric image encoding and transmission module is the image line and field signals. It adopts a three-line image buffering mechanism, and the input image data is cyclically written into three FIFO spaces. The output interface of the photoelectric image encoding and transmission module adopts the AXI4-stream protocol.

4. The photoelectric image transmission system as described in claim 3, characterized in that: The photoelectric image encoding and transmission module includes: Image buffer controller, which buffers complete image data in FIFO; When the image buffer controller buffers a complete line of image data in the FIFO, the data encoding controller requests to read the image data in the FIFO. Based on the image input format type, it selects different encoding methods to convert the image data into 32-bit UDP protocol AXI4-stream data.

5. The photoelectric image transmission system as described in claim 4, characterized in that: The image buffer controller uses a line of image as a processing unit, packages image data in message format according to the image encoding protocol, and adds message headers and message trailers.

6. The photoelectric image transmission system as described in claim 5, characterized in that: The photoelectric image encoding and transmission module adopts a UDP frame uniformity method, which achieves uniform output of all UDP frames by controlling the UDP frame output interval.

7. The photoelectric image transmission system as described in claim 6, characterized in that: The UDP frame data exchange module is based on the OSI layered model, which divides the optical signal data transmission network into the physical layer, data link layer and transport layer. The data link layer and transport layer are implemented through the Aurora protocol and the UDP protocol, respectively. The 16 exchange nodes communicate with the data exchange module through the GTX transceiver to complete the reception, buffering and forwarding of UDP frames, and build a complete local area exchange network.

8. The photoelectric image transmission system as described in claim 7, characterized in that: The UDP frame data exchange module's data transceiver channel completes the reception and transmission of UDP frame data between ports A and B, performs 64b / 66b protocol encoding / decoding and serial-to-parallel conversion, and enables high-speed transmission via a GTX transceiver. The UDP frame data exchange module is designed based on a Crossbar structure, implementing data exchange routing between ports B and C by setting a switching routing table. Each port B has both receiving and sending capabilities. Exchanged cells use UDP frame format, with cell header data including source port number, destination port number, effective length, and checksum. The destination port number is configured as either a pay-as-you-go or multicast address. The UDP frame data exchange module maps cell address information to data transmission paths by looking up the routing table. Pay-as-you-go data uses a point-to-point transmission mode, allowing multiple cells to be sent simultaneously to the same port, achieving a multi-point transmission mode. Multicast data uses a point-to-multicast transmission mode.

9. The photoelectric image transmission system as described in claim 8, characterized in that: The photoelectric image UDP frame reception and recovery module includes: PL writes image data to DDR3 by autonomously controlling the AXI4 bus; The DDR3 SDRAM consists of two MT41K256M16 chips, with a storage capacity of 512MB and a data interface width of 16 bits. The Aurora 64b / 66b decoder receives image UDP frames transmitted by the UDP frame data exchange module. The timing conversion controller converts the AXI4-stream data stream into an AXI4 data stream. The PL writes the image data into DDR3 by autonomously controlling the AXI4 bus. DDR3 is configured with a 4-frame image buffer address space. The status controller controls the read and write operations of the IP core. When an image UDP frame enters the photoelectric image UDP frame receiving and recovery module, the IP core performs a DDR3 write operation. When the address space of the image buffer for that frame is full, the system automatically jumps to the address space of the next frame. The image controller recovers the image data by processing one line of image data as the smallest unit. When a line of image data UDP frame is written to DDR3, PL reads the image data in DDR3 through the AXI4 bus, and decodes and recovers the image line and field signals using the pixel clock according to the image encoding protocol.

10. A photoelectric image transmission method, characterized in that: The system according to any one of claims 1-9 is used to realize photoelectric image transmission, and the method includes the following steps: The photoelectric signal acquisition module acquires the horizontal and vertical signals of the image. The image line and field signals are encapsulated into data frames conforming to the connectionless transmission protocol format to obtain a data stream in the streaming transmission protocol format. The photoelectric image encoding and transmission module transmits the data stream to the frame data exchange module via a high-speed serial transceiver after high-speed serial encoding. The UDP frame data exchange module routes and forwards the data frames according to the pre-configured routing table, transmitting the data frames to the destination port; The photoelectric image UDP frame receiving and recovery module receives serial data from the destination port and writes the decoded image data into a large-capacity memory at a first clock frequency; the photoelectric image UDP frame receiving and recovery module reads the image data from the large-capacity memory at a pixel clock frequency lower than the first clock frequency and recovers the image line and field signals.

Images