Isomeric dual time source seamless switching time calibration method and device, electronic equipment and medium

Abstract

The application provides a heterogeneous dual-time source seamless switching time correction method and device, electronic equipment and medium, comprising: obtaining link state parameters of a first communication link and a second communication link; performing weighted calculation on the link state parameters to obtain link quality scores of the first communication link and the second communication link; discriminating the link quality scores according to a three-level judgment strategy to generate valid / invalid marks corresponding to each link; entering a hysteresis window to perform seamless switching preparation, buffering a last valid timestamp and starting stability confirmation timing of the second communication link, and the duration of the hysteresis window is a preset hysteresis window length; using a frequency traction algorithm to perform smooth updating on a local clock, dividing a time deviation into multiple micro-step values to gradually correct to a target time; and when the first communication link is restored, using an asymmetric hysteresis condition to determine whether to perform back switching. In this way, seamless switching under a weak network is realized, the clock does not jump, and the system does not oscillate.

Description

Technical Field

[0001] This invention relates to the field of time synchronization technology, and in particular to a method, apparatus, electronic device and medium for seamless time synchronization of heterogeneous dual time sources. Background Technology

[0002] With the widespread application of intelligent converged terminals in industrial control, vehicle communication, and the Internet of Things, the requirements for the continuity and stability of time synchronization in these terminals are increasing. Currently, most intelligent converged terminals use single Ethernet NTP time synchronization or simply configure a wireless link as a backup time source. The switching strategy is typically "switching to the backup source upon primary source failure," with the judgment based solely on physical connectivity or a single timeout. This approach has the following drawbacks: First, wired link interruptions and wireless signal fluctuations have completely different failure modes; the former is a sudden hard failure, while the latter is a gradual soft failure. Existing homogeneous judgment methods cannot accurately distinguish between them, making it highly susceptible to erroneous switching due to momentary interference. Second, the switching process lacks a clock smoothing mechanism, directly overriding the RTC and causing second-level jumps, leading to event timing disorder. Third, there is no hysteresis protection or stability confirmation, causing ping-pong oscillations when the link recovers instantaneously. These problems are particularly prominent in scenarios with weak networks and strong electromagnetic interference, and to date, no dual-source switching time synchronization scheme has been found that addresses the heterogeneous characteristics of wired and wireless links. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a method, device, electronic device and medium for seamless switching and time synchronization of heterogeneous dual time sources, which implements differentiated layer judgment for heterogeneous link characteristics, and combines frequency-driven smoothing time synchronization and asymmetric hysteresis anti-ping-pong to achieve seamless switching under weak network conditions, with no clock jumps and zero system oscillation.

[0004] In a first aspect, embodiments of the present invention provide a heterogeneous dual-time-source seamless switching time synchronization method, applied to an intelligent fusion terminal configured with a first communication link and a second communication link. The method includes: acquiring link status parameters of the first communication link and the second communication link in parallel according to a preset sampling period; performing weighted calculation on the link status parameters based on preset multiple coordination parameters to obtain the link quality scores of the first communication link and the second communication link respectively; and determining the validity of the link quality scores according to a three-level judgment strategy to generate valid / failed labels for each link. The three-level judgment strategy includes physical layer hard failure judgment, continuous timeout soft failure judgment, and average index degradation within a window period. The system distinguishes between the first and second communication links and assigns different judgment weights based on their heterogeneous characteristics. When the first communication link is marked as failed, it enters a hysteresis window to prepare for seamless switching, caches the previous valid timestamp, and starts the stability confirmation timer for the second communication link. The duration of the hysteresis window is a preset hysteresis window duration. After the second communication link has been continuously and stably maintained for the preset stability confirmation duration, the local clock is smoothly updated using a frequency-pull algorithm. The time deviation is divided into multiple micro-step values ​​and gradually corrected to the target time, while constraining the timestamp sequence to be strictly monotonically increasing. When the first communication link recovers, an asymmetric hysteresis condition is used to determine whether to perform a backswitching.

[0005] In a preferred embodiment of the present invention, the above-mentioned three-level determination strategy specifically includes: detecting the physical layer connectivity indicator; if the physical layer is disconnected, the current link is directly marked as failed; detecting whether the number of consecutive request timeouts has reached a preset number of consecutive detections; if so, the link is marked as entering a degraded state; detecting whether the average round-trip latency within a preset stable confirmation time window is greater than the latency limit or the average packet loss rate is greater than the packet loss rate limit; if so, a handover process is triggered; wherein, the first communication link is an Ethernet wired link, configured as the primary link, and its first-level determination weight is higher than the third-level determination weight; the second communication link is a GPRS wireless link, configured as a backup link, and its third-level determination weight is higher than the first-level determination weight, in order to adapt to the heterogeneous characteristics of hard failure of wired links and soft failure of wireless links.

[0006] In a preferred embodiment of the present invention, the above-mentioned preparation for seamless handover upon entering the hysteresis window specifically includes: maintaining independent timekeeping of the local RTC within a preset hysteresis window duration, without interrupting the currently executing time synchronization task; maintaining external timing output using the cached previous valid timestamp to ensure uninterrupted timing during the handover process; performing high-frequency sampling on the second communication link, and confirming the second communication link as a valid target link only when the link quality score of the second communication link continuously meets the preset quality threshold within a preset stable confirmation duration.

[0007] In a preferred embodiment of the present invention, the frequency traction algorithm specifically includes: calculating the time deviation between the current time of the local RTC and the standard time of the target time source corresponding to the second communication link; dividing the time deviation into multiple micro-step adjustment amounts, the number of micro-step adjustment amounts being equal to the preset stable confirmation duration in seconds multiplied by a preset coefficient; preset a maximum adjustment step size, and gradually tractioning the local clock frequency to approach the target time within multiple time synchronization cycles; if the time deviation is negative, i.e., the local clock is ahead of the target time, then traction adjustment is paused and the current timekeeping state is maintained, ensuring that the timestamp sequence output to the service task is strictly monotonically increasing and without step abrupt changes.

[0008] In a preferred embodiment of the present invention, the above-mentioned asymmetric hysteresis condition specifically includes: setting a switching trigger delay threshold as a first threshold; setting a back-cut trigger delay threshold as a second threshold, and the second threshold being less than the first threshold; when the first communication link is restored, the back-cut is performed simultaneously if the following two conditions are met: the first communication link operates continuously and stably within a preset stable confirmation period, and the real-time round-trip delay of the first communication link is continuously lower than the second threshold.

[0009] In a preferred embodiment of the present invention, the method further includes a parameter adaptive configuration step: after the intelligent fusion terminal is powered on for the first time or a reset operation is performed, it automatically enters a learning period of a preset duration; during the learning period, the average round-trip time, delay standard deviation, and packet loss rate distribution characteristics of the first communication link and the second communication link are statistically analyzed respectively; the value of the delay upper limit is dynamically adjusted according to the statistical results, and the delay upper limit is updated to the sum of the average round-trip time and the delay standard deviation of a preset multiple, so as to achieve parameter adaptive matching under different weak network environments.

[0010] In a preferred embodiment of the present invention, the parallel acquisition of link status parameters specifically includes: at each preset sampling period, concurrently performing the following read operations: reading the link status register of the Ethernet PHY chip to obtain the physical layer connectivity identifier; reading the round-trip timestamp of the NTP protocol interaction message to calculate the round-trip delay; reading the physical layer transmit / receive packet statistics counter to calculate the number of consecutive packet losses and the packet loss rate; reading the signal strength indicator value of the GPRS module; and storing the link status parameters in a circular buffer in chronological order, wherein the write and read operations of the circular buffer do not block the main time synchronization task.

[0011] Secondly, embodiments of the present invention also provide a heterogeneous dual-time-source seamless switching and synchronization device, applied to an intelligent fusion terminal configured with a first communication link and a second communication link. The device includes: a parameter acquisition module, used to acquire link status parameters of the first communication link and the second communication link in parallel according to a preset sampling period; a weighted calculation module, used to perform weighted calculation on the link status parameters based on preset multiple collaborative parameters to obtain the link quality scores of the first communication link and the second communication link respectively; and an validity discrimination module, used to discriminate the validity of the link quality scores according to a three-level judgment strategy and generate valid / failed labels for each link; the three-level judgment strategy includes physical layer hard failure discrimination, continuous timeout soft failure discrimination, and average index degradation within a window period. The system employs several mechanisms: a discrimination mechanism, assigning different judgment weights to the heterogeneous characteristics of the first and second communication links; a seamless handover preparation module, used to perform seamless handover preparation within a hysteresis window when the first communication link is marked as failed, caching the previous valid timestamp and starting the stability confirmation timer for the second communication link, with the duration of the hysteresis window being a preset hysteresis window duration; a smooth update module, used to smoothly update the local clock using a frequency-pull algorithm after the second communication link has continuously and stably reached a preset stability confirmation time, dividing the time deviation into multiple micro-step values ​​to gradually correct to the target time, and constraining the timestamp sequence to be strictly monotonically increasing; and an execution judgment module, used to determine whether to perform a back-switching after the first communication link recovers using an asymmetric hysteresis condition.

[0012] Thirdly, embodiments of the present invention also provide an electronic device, including a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the heterogeneous dual-time source seamless switching time synchronization method of the first aspect described above.

[0013] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are invoked and executed by a processor, the computer-executable instructions cause the processor to implement the heterogeneous dual-time source seamless switching time synchronization method described in the first aspect.

[0014] The embodiments of the present invention bring the following beneficial effects: This invention provides a heterogeneous dual-time-source seamless switching and synchronization method, apparatus, electronic device, and medium. The method involves acquiring link status parameters of a first and second communication link in parallel according to a preset sampling period; weighting the link status parameters based on multiple preset coordination parameters to obtain link quality scores for each of the first and second communication links; and determining the validity of the link quality scores according to a three-level judgment strategy to generate valid / failed labels for each link. The three-level judgment strategy includes physical layer hard failure judgment, continuous timeout soft failure judgment, and average index degradation judgment within a window period, and is specifically designed for the first communication link. Different judgment weights are assigned to the heterogeneous characteristics of the first communication link and the second communication link. When the first communication link is marked as failed, a hysteresis window is entered to prepare for seamless handover, the previous valid timestamp is cached, and the stability confirmation timer for the second communication link is started. The duration of the hysteresis window is a preset hysteresis window duration. After the second communication link has been continuously stable for a preset stability confirmation duration, a frequency-pull algorithm is used to smoothly update the local clock, dividing the time deviation into multiple micro-step values ​​to gradually correct it to the target time, and constraining the timestamp sequence to be strictly monotonically increasing. When the first communication link recovers, an asymmetric hysteresis condition is used to determine whether to perform a back-switching. In this method, differentiated hierarchical judgment is implemented for the characteristics of heterogeneous links, combined with frequency-pull smooth time synchronization and asymmetric hysteresis to prevent ping-pong, to achieve seamless handover under weak network conditions, with no clock jumps and zero system oscillations.

[0015] Other features and advantages of this disclosure will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0016] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 A flowchart of a heterogeneous dual-time-source seamless switching time synchronization method provided in an embodiment of the present invention; Figure 2 A flowchart of another heterogeneous dual-time-source seamless switching time synchronization method provided in an embodiment of the present invention; Figure 3This is a schematic diagram of a heterogeneous dual-time-source seamless switching time synchronization device provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Based on this, the present invention provides a heterogeneous dual-time-source seamless switching and synchronization method, apparatus, electronic device, and medium, which can acquire link status parameters of a first communication link and a second communication link in parallel according to a preset sampling period; perform weighted calculation on the link status parameters based on preset multiple coordination parameters to obtain the link quality scores of the first and second communication links respectively; and perform validity judgment on the link quality scores according to a three-level judgment strategy to generate valid / failed labels for each link. The three-level judgment strategy includes physical layer hard failure judgment, continuous timeout soft failure judgment, and average index degradation judgment within the window period, and is specifically for the first communication link. Different judgment weights are assigned to the heterogeneous characteristics of the first and second communication links. When the first communication link is marked as failed, a hysteresis window is entered to prepare for seamless handover, the previous valid timestamp is cached, and the stability confirmation timer for the second communication link is started. The duration of the hysteresis window is a preset hysteresis window duration. After the second communication link has been continuously stable for the preset stability confirmation duration, a frequency-pull algorithm is used to smoothly update the local clock, dividing the time deviation into multiple micro-step values ​​to gradually correct it to the target time, and constraining the timestamp sequence to be strictly monotonically increasing. When the first communication link recovers, an asymmetric hysteresis condition is used to determine whether to perform a back-switching. In this method, differentiated hierarchical judgment is implemented for the characteristics of heterogeneous links, combined with frequency-pull smooth time synchronization and asymmetric hysteresis to prevent ping-pong, to achieve seamless handover under weak network conditions, with no clock jumps and zero system oscillations.

[0021] To facilitate understanding of this embodiment, a heterogeneous dual-time-source seamless switching time synchronization method disclosed in this embodiment of the invention will first be described in detail.

[0022] Example 1 This invention provides a heterogeneous dual-time-source seamless switching and time synchronization method, applied to an intelligent converged terminal configured with a first communication link and a second communication link. Figure 1 This is a flowchart illustrating a heterogeneous dual-time-source seamless switching and time synchronization method provided in an embodiment of the present invention. Figure 1 As shown, the heterogeneous dual-time-source seamless switching time synchronization method may include the following steps: Step S101: Obtain the link status parameters of the first communication link and the second communication link in parallel according to the preset sampling period.

[0023] The preset sampling period is a fixed time interval at which the system samples the status of the two links. This period is pre-configured by the system and can be set according to the actual scenario requirements. The selection of the sampling period needs to balance two factors: too short a period will consume too many processor resources, while too long a period will not be able to detect changes in the link status in a timely manner. Preferably, the sampling period is set to 1 second.

[0024] Parallel acquisition refers to performing status reading operations on the first and second communication links simultaneously within the same moment or a very short time window, rather than reading them serially. Parallel acquisition ensures that the status data of the two links are comparable in time, providing a data basis at the same moment for subsequent weighted calculations.

[0025] The first communication link connects to the NTP time server via a wired Ethernet interface. Its failure mode is primarily sudden hard failure, such as unplugging the network cable or powering off the switch; the physical layer status can be quickly detected. Preferably, the first communication link is a wired Ethernet link.

[0026] The second communication link connects to a remote time server via a GPRS wireless communication module. Its failure mode is primarily a gradual soft failure, such as gradual signal weakening, gradual increase in latency, and gradual increase in packet loss rate, without a corresponding physical layer connection / disconnection. Preferably, the second communication link is a GPRS wireless link.

[0027] Link status parameters refer to a set of quantitative indicators that reflect the current operating status of the link, including but not limited to: link connectivity flag: a flag indicating whether the link is reachable at the physical or network layer; round-trip time: the total time taken from sending a time synchronization request to receiving a response; consecutive packet loss: the number of consecutive requests that failed to receive a response; signal strength: the received signal strength indication value of the wireless link.

[0028] The intelligent fusion terminal's processor is equipped with a hardware timer, with a timing period set to a preset sampling period. Each time the timing period arrives, a timer interrupt is triggered, initiating the link status acquisition process within the interrupt service routine. The link status bit in the basic mode status register of the Ethernet PHY chip is read via the MDIO bus. A bit of 1 indicates a physical layer link is connected, and 0 indicates a link is disconnected. An NTP request message is sent to the NTP time server, recording the sending time; the server records the receiving time upon receiving the request; the server records the sending time when sending a response message; and the terminal records the receiving time when receiving the response. Round-trip timeout = (time the terminal receives the response - time the terminal sends the request) - (time the server sends the response - time the server receives the request). A counter is maintained, incrementing by 1 each time a request times out and resetting to zero upon successful response reception. The signal strength indicator value of the GPRS module is read via AT commands; this value is typically represented as a numerical range corresponding to different signal reception quality levels. Similar to the Ethernet link, a request is sent to the time server via the time synchronization protocol carried by GPRS, and a timestamp is recorded to calculate the round-trip timeout. A continuous timeout counter is also maintained. All collected state parameters are stored in a circular buffer in chronological order.

[0029] The circular buffer is a fixed-size circular queue data structure that maintains read and write pointers. When the write pointer reaches the end of the buffer, it automatically wraps back to the beginning. The write operation adopts a lock-free design. Since only one task performs the write operation and the amount of data written is fixed, the write operation does not involve blocking or waiting, ensuring that it does not interfere with the execution of the main time synchronization task.

[0030] In terms of effectiveness, by collecting complete status parameters of two heterogeneous links in parallel at a preset sampling period, the system can monitor the operational status of the two time source links in real time and synchronously, providing an accurate data foundation for subsequent link quality assessment and switching decisions. The use of a circular buffer ensures that data acquisition does not block the main time synchronization task, meeting the requirements of embedded real-time systems.

[0031] Specifically, the link status parameters are acquired in parallel, including: at each preset sampling period, the following read operations are performed concurrently: read the link status register of the Ethernet PHY chip to obtain the physical layer connectivity identifier; read the round-trip timestamp of the NTP protocol interaction message to calculate the round-trip delay; read the physical layer transmit and receive packet statistics counter to calculate the number of consecutive packet losses and the packet loss rate; read the signal strength indicator value of the GPRS module; and store the link status parameters in a circular buffer in chronological order. The write and read operations of the circular buffer do not block the main time synchronization task.

[0032] When the timer interrupt is triggered, all operations that do not require waiting (PHY register, statistical counter) are read first, and then operations that require waiting (NTP request) are initiated. However, the system does not block the wait for a response, and the response is handled through an interrupt or callback.

[0033] Specifically, a read command is sent to the PHY chip via the MDIO bus to read the link status bits of the basic mode status register.

[0034] The system records four timestamps: the time when the terminal sends the NTP request, the time when the NTP server receives the request (as returned by the server in the response), the time when the NTP server sends the response (as returned by the server in the response), and the time when the terminal receives the response.

[0035] Round-trip time = (time when the terminal receives the response - time when the terminal sends the request) - (time when the server sends the response - time when the server receives the request).

[0036] Step S102: The link status parameters are weighted and calculated based on a number of preset collaborative parameters to obtain the link quality scores of the first communication link and the second communication link respectively.

[0037] Among them, multiple collaborative parameters refer to a set of pre-defined configuration parameters that work together to assess link quality. A single parameter cannot independently complete the link quality assessment; multiple parameters must be used in combination to accurately reflect the true state of the link.

[0038] Weighted calculation refers to assigning different weight coefficients to different indicators (latency, packet loss rate, etc.) in the link state parameters, and obtaining a comprehensive score through weighted summation or other weighted operations. The purpose of weighted calculation is to enable indicators with different dimensions and different importance to be compared within the same scoring system.

[0039] The link quality score is a dimensionless numerical value used to quantitatively characterize the suitability of the current link as a time source. The higher the score, the better the link quality and the more suitable it is as a time source for time synchronization.

[0040] The link status parameters acquired during the current sampling period include: the current round-trip delay, the current packet loss rate, and the signal strength indication (GPRS link only).

[0041] The scoring method uses a piecewise linear weighted method. Taking a full score of 100 points as an example, if the round-trip delay is less than or equal to the first preset delay value, the delay score is 100. If the round-trip delay is between the first preset delay value and the second preset delay value, the delay score is 100 × (second preset delay value - round-trip delay) / (second preset delay value - first preset delay value). If the round-trip delay is greater than the second preset delay value, the delay score is 0.

[0042] For example, the packet loss rate score is out of 100: If the packet loss rate is 0, the packet loss rate score is 100. If the packet loss rate is between 0 and the preset packet loss rate limit, the packet loss rate score is 100 × (preset packet loss rate limit - packet loss rate) / preset packet loss rate limit. If the packet loss rate is greater than the preset packet loss rate limit, the packet loss rate score is 0.

[0043] The overall score is calculated as follows: latency weight coefficient × latency score + packet loss rate weight coefficient × packet loss rate score.

[0044] Specifically, heterogeneous links require differentiated processing: For Ethernet links, the physical layer connectivity status is used as a prerequisite for rejection; if the physical layer is disconnected, the link is directly deemed unusable (score of 0), and latency and packet loss rate calculations are no longer performed. For GPRS links, signal strength is used as an auxiliary reference indicator; when the signal strength is below a certain preset threshold, an attenuation coefficient is multiplied from the comprehensive score to reflect the impact of weak signals on time synchronization accuracy.

[0045] After each link state sampling is completed, a link quality score is calculated immediately. The calculation result is stored in a circular buffer corresponding to the link state parameters for use in the subsequent three-level judgment steps.

[0046] In terms of effectiveness, weighted calculations quantify multi-dimensional link status parameters into a unified link quality score, enabling the system to quantitatively compare the merits of two heterogeneous links and provide an objective basis for handover decisions. Differential processing for the heterogeneous characteristics of Ethernet and GPRS ensures that the scoring model accurately reflects the characteristics and problems of each type of link.

[0047] Step S103: Determine the validity of the link quality score according to the three-level judgment strategy, and generate valid / failed tags for each link.

[0048] The three-level judgment strategy includes physical layer hard failure judgment, continuous timeout soft failure judgment, and average index degradation judgment within the window period, and different judgment weights are assigned to the heterogeneous characteristics of the first communication link and the second communication link.

[0049] The three-level judgment strategy is a hierarchical and progressive link validity determination mechanism. It executes judgments at three levels sequentially, from fastest to most accurate and from hard to soft methods. If any level of judgment triggers a failure condition, the link is marked as failed. The three levels are logically related by an "OR" relationship.

[0050] Among them, physical layer hard failure detection is the fastest failure detection based on hardware status, which directly reads the status register of the physical layer chip to determine whether the link is physically disconnected.

[0051] Among them, continuous timeout soft failure judgment: failure detection based on protocol interaction timeout, when multiple consecutive requests have no response, it is determined that the link is degraded.

[0052] Among them, the average index degradation judgment within the window period is based on statistical analysis of failure detection. The average latency and average packet loss rate are calculated within a specified time window. When the average value exceeds the threshold, the link quality is determined to be degraded.

[0053] Different judgment weights are assigned to heterogeneous characteristics: for different failure modes of Ethernet (mainly wired hard failure) and GPRS (mainly wireless soft failure), different priorities are assigned in the three-level judgment.

[0054] Specifically, the three-level judgment strategy includes: detecting the physical layer connectivity indicator; if the physical layer is disconnected, the current link is directly marked as failed; detecting whether the number of consecutive request timeouts has reached the preset number of consecutive detections; if so, the link is marked as entering a degraded state; and detecting whether the average round-trip latency within the preset stable confirmation time window is greater than the latency limit or the average packet loss rate is greater than the packet loss rate limit; if so, a handover process is triggered. Among these, the first communication link is an Ethernet wired link, configured as the primary link, and its first-level judgment weight is higher than the third-level judgment weight; the second communication link is a GPRS wireless link, configured as a backup link, and its third-level judgment weight is higher than the first-level judgment weight, in order to adapt to the heterogeneous characteristics of hard failure of wired links and soft failure of wireless links.

[0055] The first-level judgment can detect the physical layer connectivity status. If the physical layer is disconnected, the current link will be marked as faulty.

[0056] The physical layer connectivity flag is a link status bit in the basic mode status register of the Ethernet PHY chip. This bit is automatically maintained by the PHY chip's hardware; it is set to 1 when a valid Ethernet physical signal is detected, and cleared to zero otherwise.

[0057] Among them, direct marking is the highest priority of the first-level judgment, and it takes effect immediately once triggered, without waiting for the results of the second- or third-level judgment.

[0058] Specifically, the link status bit of the PHY chip's basic mode status register is read via the MDIO bus. If the read value is 0, the current link is immediately marked as failed, and a hysteresis window procedure is triggered.

[0059] For example, physical layer faults such as the network cable being unplugged, the power being cut off to the switch at the other end, or the network cable breaking.

[0060] In the differentiated processing for GPRS, there is no corresponding concept of physical layer connectivity for GPRS links. The GPRS module is always attached to the network, but the signal strength may be extremely weak, causing communication failure. For GPRS links, the weight of the first-level judgment is set to zero, and instead, the average index degradation judgment in the third-level judgment is relied upon.

[0061] The secondary judgment can detect whether the number of consecutive request timeouts has reached the preset number of consecutive detections. If so, the link is marked as entering a degraded state.

[0062] The consecutive request timeout count is the number of times a time synchronization request is sent consecutively without receiving a response within the preset timeout period.

[0063] Among them, the degraded state is an intermediate state between normal and failure, indicating that although the link has not been completely interrupted, the communication quality has been severely degraded.

[0064] Each link maintains a continuous timeout counter, initially set to 0. A timeout timer is started after each time synchronization request is sent. If a response is received before the timer expires, the counter is reset to zero. If no response is received before the timer expires, the counter is incremented by 1. If the number of consecutive timeouts reaches the preset number of consecutive checks, the link is marked as entering a degraded state, triggering a handover preparation process. If a successful response is received even once, the counter is immediately reset to zero and begins counting again.

[0065] For example, NTP servers may be busy and unresponsive, network congestion may cause packet loss, and GPRS signals may be briefly interrupted.

[0066] The three-level judgment can detect whether the average round-trip latency within the preset stable confirmation time window is greater than the latency limit or whether the average packet loss rate is greater than the packet loss rate limit. If so, the switching process is triggered.

[0067] The sliding window is a data window of fixed length that slides forward over time. In this embodiment, the window length is the number of sampling points obtained by dividing a preset stable confirmation time by a preset sampling period.

[0068] The average round-trip time is the arithmetic mean of the round-trip times of all valid sampling points within the window.

[0069] The average packet loss rate is the percentage of the total number of lost packets within a window relative to the total number of requests.

[0070] The circular buffer maintains link status data within the most recent preset stable acknowledgment duration. A handover process is triggered each time new data arrives, provided any of the following conditions are met: new data is written to the buffer; the average latency and average packet loss rate of all sampling points within the window are calculated; or, if the average latency exceeds the latency limit or the average packet loss rate exceeds the packet loss rate limit, the handover process is triggered.

[0071] For example, a continuously weakening GPRS signal can lead to a gradual increase in latency, and intermittent packet loss can occur in Ethernet links due to electromagnetic interference.

[0072] Among them, Ethernet link failures are mainly sudden hard failures, with physical layer disconnection being the primary failure mode. Therefore, the first-level judgment (physical layer detection) is the most critical and fastest.

[0073] Among them, GPRS link failures are mainly gradual soft failures, with the main failure modes being gradually weakening signal, gradually increasing latency, and gradually increasing packet loss rate. Therefore, the three-level judgment (average index statistics) is the most accurate and effective.

[0074] In practice, the higher weight is reflected in the following ways: for Ethernet, the first-level judgment is triggered and then fails, without waiting for the result of the third-level judgment; for GPRS, the first-level judgment is not applicable (the weight is zero), and it relies entirely on the third-level judgment.

[0075] In terms of effectiveness, the three-level judgment strategy achieves layered coverage from rapid response to accurate judgment: Level 1 judgment responds to physical disconnections in milliseconds, Level 2 judgment responds to protocol timeouts in seconds, and Level 3 judgment responds to quality degradation in several seconds. Differential weight allocation for heterogeneous links ensures that both sudden Ethernet disconnections and gradual GPRS degradation can be accurately identified, avoiding misjudgments and missed judgments.

[0076] Step S104: When the first communication link is marked as failed, enter the hysteresis window to perform seamless handover preparation, cache the previous valid timestamp and start the stability confirmation timer for the second communication link.

[0077] The duration of the hysteresis window is the preset hysteresis window duration.

[0078] The hysteresis window is the waiting time between when the first communication link is marked as faulty and when the actual handover is performed. The purpose of the hysteresis window is to prevent instantaneous fluctuations in the link from triggering unnecessary handovers and to provide a buffer time for possible brief recovery of the link.

[0079] Seamless handover preparation involves a series of preparatory operations performed during the hysteresis window, including maintaining local timekeeping, caching timestamps, and monitoring the second communication link, to ensure uninterrupted service when handover occurs.

[0080] The cached previous valid timestamp is the standard timestamp obtained from the last successful time synchronization before the failure of the first communication link, which is stored in memory. During the handover, the system relies on this cached timestamp in conjunction with the local RTC to maintain timing output.

[0081] Among them, the stability confirmation timing is a timing process for continuously monitoring the second communication link. It requires the second communication link to continuously meet the quality requirements within the preset stability confirmation time before it is confirmed as a valid target link, thus preventing secondary switching caused by the instability of the second communication link itself.

[0082] When any of the three conditions in the decision-making process is triggered and the first communication link is marked as failed, a handover is not immediately executed. Instead, a hysteresis timer is started for a preset hysteresis window duration. During the hysteresis window, the system does not disconnect from the first communication link and continues to attempt to receive time synchronization responses from it. If the first communication link becomes active again within the hysteresis window, the handover process is canceled, and the first communication link is used again. The hysteresis window is essentially a jitter reduction mechanism to prevent frequent handovers caused by instantaneous link fluctuations.

[0083] During the hysteresis window and subsequent handover process, the local RTC chip operates independently without relying on any external time source. The system output timestamp = the cached last valid timestamp + the RTC's cumulative elapsed time increment, ensuring that the time series output to the outside world is continuous and uninterrupted during the handover process.

[0084] Specifically, when the first communication link is marked as invalid, the correspondence between the current RTC time and the standard time obtained from the last successful time synchronization is immediately read and saved. Specifically, two values ​​are saved: the standard time of the last successful time synchronization and the corresponding RTC time. During subsequent timekeeping operations, the actual output time = the standard time of the last successful time synchronization + (the current RTC time - the corresponding RTC time).

[0085] Upon entering the hysteresis window, high-frequency sampling of the second communication link begins, and a quality score is immediately performed after each sampling.

[0086] Among them, the stability confirmation timer starts counting, requiring that the link quality score of each sampled link in the second communication link meets the preset quality threshold within a continuous time of the preset stability confirmation duration.

[0087] The meaning of "continuous and stable" is that all samples within the preset stability confirmation time must meet the standard. If any sample fails to meet the standard, the stability confirmation timer will be interrupted and the timer will be restarted.

[0088] In terms of effectiveness, the hysteresis window mechanism effectively avoids frequent erroneous handovers caused by instantaneous link fluctuations. During the hysteresis window, the system maintains the continuity of timing output through RTC timekeeping and buffered timestamps, ensuring uninterrupted service during the handover preparation process. The stability confirmation timing of the second communication link ensures that only truly stable backup links are activated, avoiding switching from one unstable link to another.

[0089] Specifically, the seamless handover preparation process within the hysteresis window includes: maintaining independent timekeeping of the local RTC within the preset hysteresis window duration, without interrupting the currently executing time synchronization task; maintaining external timing output using the cached previous valid timestamp to ensure uninterrupted timing during the handover process; and performing high-frequency sampling on the second communication link, confirming the second communication link as a valid target link only after the link quality score of the second communication link continuously meets the preset quality threshold within the preset stable confirmation duration.

[0090] The time synchronization task is the most critical task in the system, responsible for periodically synchronizing with the time source and correcting the local clock. This task has the highest priority, and its execution must not be interrupted or blocked by any switching operation.

[0091] When the first communication link is marked as invalid, the system does not stop the currently running time synchronization task; the time synchronization task continues to run in the background. The RTC chip operates independently of the processor, and the RTC continues to keep time even when the processor executes the switching logic. The switching logic and the time synchronization task run at different task priorities or interrupt levels to ensure that the switching operation does not block the time synchronization task.

[0092] The cached content includes the standard time of the last successful time synchronization and the corresponding RTC time.

[0093] The output time calculation is as follows: actual output time = standard time of the last successful time synchronization + (current RTC time - corresponding RTC time).

[0094] This calculation is performed every time a timestamp needs to be output, ensuring that the output timestamps are continuous, without jumps or interruptions during the switching process.

[0095] Among them, high-frequency sampling: still samples according to the preset sampling period, but performs quality scoring and threshold comparison immediately after each sampling, no longer waiting for the complete judgment period.

[0096] Among them, the preset quality threshold is a more stringent condition that the second communication link must meet.

[0097] Among them, the following must be continuously met: all samples within the preset stable confirmation time must meet the standard, and the timer must be restarted if any sample fails to meet the standard.

[0098] Among them, confirmation of validity: only after continuous and stable compliance with the standard can the second communication link be confirmed as a valid target link and allowed to enter frequency traction time calibration.

[0099] Step S105: After the second communication link has been continuously and stably reached the preset stable confirmation time, the local clock is updated smoothly using the frequency traction algorithm. The time deviation is divided into multiple micro-step values ​​and gradually corrected to the target time. The timestamp sequence is constrained to be strictly monotonically increasing.

[0100] The frequency pulling algorithm is a smooth time synchronization method that approximates the target time by gradually adjusting the local clock frequency, rather than setting the local clock to the target value all at once. The term "pulling" borrows from the frequency pulling concept in phase-locked loops, referring to gradually aligning the local clock with the standard time through small step adjustments.

[0101] The microstep value divides the total time deviation into several extremely small adjustment amounts, each of which is limited to a very small range, so that no single adjustment will produce a perceptible clock jump.

[0102] Among these requirements, the timestamp sequence must be strictly monotonically increasing: all timestamps output to business tasks must strictly increase in chronological order, and time rollback is not allowed. This is a strict requirement for time-sensitive business applications, as time rollback can lead to serious problems such as duplicate data records and reversed event order.

[0103] Among them, gradual correction to the target time refers to making the local clock gradually approach and eventually align with the target time through multiple small adjustments, rather than jumping to the target time all at once.

[0104] Once the second communication link is confirmed to be stable, a time synchronization request is immediately initiated through the second communication link to obtain the current standard time. Simultaneously, the current time on the local RTC is read. The deviation value is calculated as: Standard Time - Local RTC Current Time. A positive deviation value indicates that the local clock is too slow and needs to be caught up; a negative deviation value indicates that the local clock is too fast.

[0105] The number of micro-step adjustments is equal to the preset stabilization confirmation time in seconds multiplied by a preset coefficient. Each micro-step adjustment = time deviation / number of micro-step adjustments. The maximum adjustment step size in a single operation is rigidly limited to the preset maximum adjustment step size. If the absolute value of a single micro-step adjustment exceeds the preset maximum adjustment step size, the preset maximum adjustment step size is forcibly used, and the remaining deviation is distributed in subsequent adjustment cycles. Adjustment cycle: Micro-step adjustment is performed once per time calibration cycle.

[0106] In each time synchronization cycle, the local clock is sped up or slowed down relative to the standard clock by a micro-step by adjusting the frequency compensation register of the RTC. Specifically, this is achieved by adjusting the clock pulse count per second by setting the compensation register inside the RTC chip.

[0107] If the time deviation is negative (i.e., the local clock is ahead of the target time), all traction adjustments are paused, the current timekeeping state is maintained, and the clock is not allowed to be turned back. When the time deviation is negative, the system does not perform any adjustment operations, keeps the current clock frequency unchanged, and waits for natural drift or the next time synchronization cycle to recalculate the time deviation. If the time deviation is negative for several consecutive cycles, it indicates that the local clock is continuously ahead. This can be slowly corrected at the RTC hardware level by reducing the crystal oscillator frequency compensation value, but a one-time jump back is never allowed. Before each output timestamp, the system compares the current timestamp to be output with the previous timestamp. If the former is less than or equal to the latter, the output is rejected and an anomaly is reported.

[0108] In terms of effectiveness, the frequency-pull algorithm breaks down what would otherwise be a one-time clock correction that could result in second- or even minute-level jumps into dozens of tiny step adjustments. Since any single adjustment does not exceed the preset maximum adjustment step size, the business system remains unaware of it. The strict monotonically increasing timestamp constraint completely eliminates the risk of time rollback, meeting the stringent timing consistency requirements of time-sensitive businesses.

[0109] Specifically, the frequency traction algorithm includes: calculating the time deviation between the current time of the local RTC and the standard time of the target time source corresponding to the second communication link; dividing the time deviation into multiple micro-step adjustment amounts, the number of which is equal to the preset stable confirmation duration in seconds multiplied by a preset coefficient; preset the maximum adjustment step size, and gradually traction the local clock frequency to approach the target time within multiple time synchronization cycles; if the time deviation is negative, that is, the local clock is ahead of the target time, then the traction adjustment is paused and the current timekeeping state is maintained to ensure that the timestamp sequence output to the service task is strictly monotonically increasing and without step changes.

[0110] The process involves initiating a time synchronization request via the second communication link to obtain the standard time. The current time on the local RTC is then read. The time deviation is calculated as: Standard Time - Current Local RTC Time. For example, if the standard time is 12:00:00.000 and the current RTC time is 11:59:58.500, the time deviation is +1.5 seconds (the local time is 1.5 seconds slower).

[0111] The number of micro-step adjustments is equal to the preset stability confirmation time multiplied by the preset coefficient.

[0112] Wherein, each microstep adjustment amount = time deviation / number of microstep adjustments.

[0113] For example, if the preset stability confirmation time is 5 seconds and the preset coefficient is 10, then the number of micro-step adjustments is 50, and each micro-step adjustment is the time deviation divided by 50. If the time deviation is 1500ms, then each micro-step adjustment is 30ms. However, due to the preset maximum adjustment step size limit, the actual step size is the preset maximum adjustment step size, and the remaining deviation is distributed in subsequent adjustment cycles.

[0114] The calibration period is usually consistent with the preset sampling period, that is, the adjustment is performed once in each sampling period.

[0115] This is achieved by writing to the frequency compensation register of the RTC chip. Taking the TIMSP430RTC_B module as an example, the crystal oscillator frequency is adjusted by setting the RTCCALx bit, with each step corresponding to a frequency change of approximately +4ppm or -2ppm.

[0116] After multiple time synchronization cycles, the local clock is aligned with the target time.

[0117] If the time deviation is less than 0 (e.g., standard time 12:00:00.000, RTC is 12:00:01.500, time deviation is -1.5 seconds): the system does not perform any adjustment operation; keeps the current RTC frequency unchanged; and waits for the next time synchronization cycle to recalculate the time deviation.

[0118] If the time deviation is negative for several consecutive rounds, it can be slowly corrected at the RTC hardware level by reducing the crystal oscillator frequency compensation value, but it is absolutely forbidden to turn the clock back all at once.

[0119] Step S106: After the first communication link is restored, an asymmetric hysteresis condition is used to determine whether to perform a back-switch.

[0120] In this context, "switchback" refers to the operation of switching back from the second communication link to the first communication link. In a typical scenario of this invention, the initial state is Ethernet as the primary and GPRS as the backup. After switching to GPRS due to an Ethernet failure, it is necessary to determine whether to switch back to Ethernet when Ethernet recovers.

[0121] Among them, the asymmetric hysteresis condition is that the switching condition and the back-off condition use different threshold standards, with the back-off condition being more stringent than the switching condition. The "asymmetry" is reflected in the different threshold values, with the back-off threshold being stricter than the switching threshold.

[0122] Hysteresis is a delay effect in cybernetics, which avoids the system from frequently acting near the critical point by setting different action thresholds.

[0123] Among them, the switching trigger threshold is the time delay threshold from the first communication link to the second communication link.

[0124] Among them, the back-switch trigger threshold is the time delay threshold for switching back from the second communication link to the first communication link.

[0125] Among them, the back-cut trigger threshold is less than the switching trigger threshold, meaning that the back-cut condition is more stringent than the switching condition.

[0126] When the first communication link is detected as recovered, a switchback is not immediately executed; instead, a switchback confirmation timer is started. A switchback will only be executed if both of the following conditions are met simultaneously: the first communication link operates continuously and stably within a preset stable confirmation period without any failure triggers; and the real-time round-trip latency of the first communication link remains below the switchback trigger threshold.

[0127] Among them, the anti-ping-pong principle of asymmetric hysteresis: Hypothetical scenario: Ethernet link latency fluctuates around the handover threshold.

[0128] If a symmetrical threshold is used: when the current delay drops below the switching threshold, it immediately switches back; when it rises above the switching threshold again, it immediately switches out, forming a ping-pong oscillation.

[0129] An asymmetric threshold is used: even if the latency drops below the handover threshold but does not reach the back-off threshold, the back-off condition is not met, and the second communication link continues to be used; back-off only occurs when the link quality truly and stably improves to below the back-off threshold. After back-off, even if the latency rises again but is below the handover threshold, it will not hand off again.

[0130] This mechanism is known in control theory as the Schmitt trigger characteristic. The action threshold varies depending on the current state, thus creating a hysteresis interval between the switching point and the cut-back point. Within this interval, the system maintains its current state, effectively suppressing ping-pong oscillations.

[0131] In terms of effectiveness, the asymmetric hysteresis condition makes the back-off threshold stricter than the handover threshold, preventing frequent back-offs due to brief quality fluctuations after the first communication link is restored, thus avoiding ping-pong oscillations. The hysteresis interval provides a stable hold region for the system, ensuring the stability and reliability of handover decisions.

[0132] Specifically, the asymmetric hysteresis condition includes: setting the switching trigger delay threshold as a first threshold; setting the back-cut trigger delay threshold as a second threshold, and the second threshold being less than the first threshold; when the first communication link is restored, the back-cut is performed simultaneously if the following two conditions are met: the first communication link operates continuously and stably within a preset stable confirmation period, and the real-time round-trip delay of the first communication link is continuously lower than the second threshold.

[0133] Specifically, when the average round-trip time of the first communication link exceeds a first threshold, a switch from the first communication link to the second communication link is triggered.

[0134] The average value refers to the average value within the sliding window in the three-level judgment, rather than the value of a single sample, to avoid instantaneous fluctuations triggering switching.

[0135] Among them, after the first communication link is restored, the real-time round-trip latency must remain below the second threshold before a switchback is allowed.

[0136] Here, "real-time" refers to the instantaneous value of the current sample, rather than the average value, to ensure that the link quality is indeed excellent during the back-switch.

[0137] The heterogeneous dual-time-source seamless switching and synchronization method provided in this invention can acquire link status parameters of a first communication link and a second communication link in parallel according to a preset sampling period; calculate the link status parameters by weighting them based on multiple preset coordination parameters to obtain the link quality scores of the first and second communication links respectively; and determine the validity of the link quality scores according to a three-level judgment strategy to generate valid / failed labels for each link. The three-level judgment strategy includes physical layer hard failure judgment, continuous timeout soft failure judgment, and average index degradation judgment within the window period, and is applied to both the first and second communication links. Different judgment weights are assigned to the heterogeneous characteristics of the links. When the first communication link is marked as failed, a hysteresis window is entered to prepare for seamless handover, the previous valid timestamp is cached, and the stability confirmation timer for the second communication link is started. The duration of the hysteresis window is a preset hysteresis window duration. After the second communication link has been continuously stable for the preset stability confirmation duration, a frequency-pull algorithm is used to smoothly update the local clock, dividing the time deviation into multiple micro-step values ​​to gradually correct it to the target time, and constraining the timestamp sequence to be strictly monotonically increasing. When the first communication link recovers, an asymmetric hysteresis condition is used to determine whether to perform a back-switching. In this method, differentiated hierarchical judgment is implemented for the characteristics of heterogeneous links, combined with frequency-pull smooth time synchronization and asymmetric hysteresis to prevent ping-pong, to achieve seamless handover under weak network conditions, with no clock jumps and zero system oscillations.

[0138] Example 2 This invention also provides another method for seamless switching and time synchronization between heterogeneous dual time sources; this method is implemented based on the method described in the above embodiments.

[0139] Figure 2 A flowchart of another heterogeneous dual-time-source seamless switching time synchronization method provided in an embodiment of the present invention is shown below. Figure 2 As shown, the method may include a parameter adaptive configuration step: Step S201: After the intelligent fusion terminal is powered on for the first time or a reset operation is performed, it automatically enters a learning period of a preset duration.

[0140] The learning period is a time window specifically used to collect link status statistics. During this period, the system does not make switching decisions, but only collects and records the operating data of the two links.

[0141] The preset duration is preferably 24 hours, covering different network load periods and different wireless signal conditions throughout the day.

[0142] When the intelligent fusion terminal is powered on or reset for the first time, it automatically enters the learning mode. During the learning period, the system still uses the first communication link as the primary link (if available) to perform normal time synchronization. At the same time, it collects the status parameters of the two links at a preset sampling period, and all collected data is stored in non-volatile memory (such as Flash or EEPROM).

[0143] Step S202: During the learning period, the average round-trip time, delay standard deviation, and packet loss rate distribution characteristics of the first and second communication links are statistically analyzed.

[0144] Wherein, average round-trip time = sum of all valid sampling delays / number of valid samplings.

[0145] Wherein, the standard deviation of delay is the square root of the sum of the squares of the differences between each delay and the average delay, divided by (number of samples minus 1).

[0146] Wherein, packet loss rate distribution = the proportion of sampling points within different packet loss rate intervals.

[0147] The statistical period can be calculated by the hour to obtain multiple sets of statistical data, reflecting the changes in link quality at different times of the day.

[0148] Step S203: Dynamically adjust the value of the delay limit based on the statistical results, and update the delay limit to the sum of the average round-trip delay and the delay standard deviation of a preset multiple, so as to achieve adaptive matching of parameters under different weak network environments.

[0149] Among them, the upper limit of latency adaptive value = average round-trip latency + preset multiple × latency standard deviation.

[0150] In this scenario, it is assumed that the time delay follows a normal distribution, and the mean plus several times the standard deviation can cover the vast majority of time delay samples, meaning that only extreme outliers will be judged as failures.

[0151] For example, if the average Ethernet latency during the learning period is 120ms, the standard deviation is 40ms, and the preset multiplier is 3, then the adaptive upper limit of latency is 120 + 3 × 40 = 240ms, which is more sensitive than the fixed upper limit of latency and is more suitable for strong network environments.

[0152] If the link quality is extremely poor during the learning period (e.g., average latency of 400ms and standard deviation of 150ms), the upper limit of latency is adaptively set to 400 + 3 × 150 = 850ms, which is more forgiving than the fixed upper limit of latency and avoids frequent false handovers in weak network environments.

[0153] Example 3 Corresponding to the above method embodiments, this invention provides a heterogeneous dual-time-source seamless switching and synchronization device, applied to an intelligent fusion terminal configured with a first communication link and a second communication link. Figure 3 This is a schematic diagram of a heterogeneous dual-time-source seamless switching time synchronization device provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the heterogeneous dual-time-source seamless switching time synchronization device may include: The parameter acquisition module 301 is used to acquire the link status parameters of the first communication link and the second communication link in parallel according to a preset sampling period.

[0154] The weighted calculation module 302 is used to perform weighted calculations on the link status parameters based on a number of preset collaborative parameters to obtain the link quality scores of the first communication link and the second communication link respectively.

[0155] The validity discrimination module 303 is used to make validity discrimination of the link quality score according to the three-level judgment strategy and generate valid / failed labels for each link. The three-level judgment strategy includes physical layer hard failure discrimination, continuous timeout soft failure discrimination and average index degradation discrimination within the window period, and different judgment weights are assigned for the heterogeneous characteristics of the first communication link and the second communication link.

[0156] The seamless handover preparation module 304 is used to perform seamless handover preparation in the hysteresis window when the first communication link is marked as failed. It caches the previous valid timestamp and starts the stability confirmation timer for the second communication link. The duration of the hysteresis window is a preset hysteresis window duration.

[0157] The smooth update module 305 is used to smoothly update the local clock using a frequency traction algorithm after the second communication link has been continuously and stably reached the preset stable confirmation time. The time deviation is divided into multiple micro-step values ​​to be gradually corrected to the target time, and the timestamp sequence is constrained to be strictly monotonically increasing. The execution determination module 306 is used to determine whether to perform a back-switching after the first communication link is restored, using an asymmetric hysteresis condition.

[0158] The heterogeneous dual-time-source seamless switching and synchronization device provided in this invention can acquire link status parameters of a first communication link and a second communication link in parallel according to a preset sampling period; calculate the link status parameters by weighting them based on multiple preset coordination parameters to obtain the link quality scores of the first and second communication links respectively; and determine the validity of the link quality scores according to a three-level judgment strategy to generate valid / failed labels for each link. The three-level judgment strategy includes physical layer hard failure judgment, continuous timeout soft failure judgment, and average index degradation judgment within the window period, and is applied to both the first and second communication links. Different judgment weights are assigned to the heterogeneous characteristics of the links. When the first communication link is marked as failed, a hysteresis window is entered to prepare for seamless handover, the previous valid timestamp is cached, and the stability confirmation timer for the second communication link is started. The duration of the hysteresis window is a preset hysteresis window duration. After the second communication link has been continuously stable for the preset stability confirmation duration, a frequency-pull algorithm is used to smoothly update the local clock, dividing the time deviation into multiple micro-step values ​​to gradually correct it to the target time, and constraining the timestamp sequence to be strictly monotonically increasing. When the first communication link recovers, an asymmetric hysteresis condition is used to determine whether to perform a back-switching. In this method, differentiated hierarchical judgment is implemented for the characteristics of heterogeneous links, combined with frequency-pull smooth time synchronization and asymmetric hysteresis to prevent ping-pong, to achieve seamless handover under weak network conditions, with no clock jumps and zero system oscillations.

[0159] In some embodiments, the validity determination module is further configured to detect physical layer connectivity indicators; if the physical layer is disconnected, the current link is directly marked as failed; detect whether the number of consecutive request timeouts has reached a preset number of consecutive detections; if so, the link is marked as entering a degraded state; detect whether the average round-trip latency within a preset stable confirmation time window is greater than the latency limit or the average packet loss rate is greater than the packet loss rate limit; if so, a switching process is triggered; wherein, the first communication link is an Ethernet wired link, configured as the primary link, and its first-level determination weight is higher than the third-level determination weight; the second communication link is a GPRS wireless link, configured as a backup link, and its third-level determination weight is higher than the first-level determination weight, in order to adapt to the heterogeneous characteristics of wired link hard failure and wireless link soft failure.

[0160] In some embodiments, the seamless switching preparation module is further configured to maintain independent timekeeping of the local RTC within a preset hysteresis window duration, without interrupting the currently executing time synchronization task; maintain external timing output using the cached previous valid timestamp to ensure that timing is not interrupted during the switching process; perform high-frequency sampling on the second communication link, and only confirm the second communication link as a valid target link if the link quality score of the second communication link continuously meets the preset quality threshold within a preset stable confirmation duration.

[0161] In some embodiments, the smooth update module is further configured to calculate the time deviation between the current time of the local RTC and the standard time of the target time source corresponding to the second communication link; divide the time deviation into multiple micro-step adjustment amounts, the number of micro-step adjustment amounts being equal to the preset stable confirmation duration in seconds multiplied by a preset coefficient; preset a maximum adjustment step size, and gradually pull the local clock frequency closer to the target time within multiple time synchronization cycles; if the time deviation is negative, i.e. the local clock is ahead of the target time, then the pulling adjustment is paused and the current timekeeping state is maintained, ensuring that the timestamp sequence output to the service task is strictly monotonically increasing and without step abrupt changes.

[0162] In some embodiments, the execution determination module is further configured to set the switching trigger delay threshold to a first threshold; set the back-switching trigger delay threshold to a second threshold, and the second threshold is less than the first threshold; when the first communication link is restored, the back-switching is executed if the following two conditions are met simultaneously: the first communication link operates continuously and stably within a preset stable confirmation time, and the real-time round-trip delay of the first communication link is continuously lower than the second threshold.

[0163] In some embodiments, the parameter acquisition module is further configured to automatically enter a learning period of a preset duration after the intelligent fusion terminal is powered on for the first time or after a reset operation is performed; during the learning period, the average round-trip time, delay standard deviation, and packet loss rate distribution characteristics of the first communication link and the second communication link are statistically analyzed respectively; the value of the delay upper limit is dynamically adjusted according to the statistical results, and the delay upper limit is updated to the sum of the average round-trip time and the delay standard deviation of a preset multiple, so as to achieve parameter adaptive matching under different weak network environments.

[0164] In some embodiments, the parameter acquisition module is further configured to concurrently perform the following read operations at preset sampling intervals: read the link status register of the Ethernet PHY chip to obtain the physical layer connectivity identifier; read the round-trip timestamp of the NTP protocol interaction message to calculate the round-trip delay; read the physical layer transmit / receive packet statistics counter to calculate the number of consecutive packet losses and the packet loss rate; read the signal strength indicator value of the GPRS module; and store the link status parameters into a circular buffer in chronological order, wherein the write and read operations of the circular buffer do not block the main time synchronization task.

[0165] The device provided in this embodiment of the invention has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0166] Example 4 This invention also provides an electronic device for running the above-described heterogeneous dual-time-source seamless switching time synchronization method; see also Figure 4The diagram shows the structure of an electronic device, which includes a memory 500 and a processor 501. The memory 500 is used to store one or more computer instructions, which are executed by the processor 501 to realize the above-mentioned heterogeneous dual time source seamless switching and time synchronization method.

[0167] Furthermore, Figure 4 The electronic device shown also includes a bus 502 and a communication interface 503. The processor 501, the communication interface 503, and the memory 500 are connected via the bus 502.

[0168] The memory 500 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 503 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 502 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 4 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0169] Processor 501 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 501 or by instructions in software form. Processor 501 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a readily available storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 500, and processor 501 reads information from memory 500 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0170] This invention also provides a computer-readable storage medium storing computer-executable instructions. When these computer-executable instructions are called and executed by a processor, they cause the processor to implement the above-described heterogeneous dual-time source seamless switching time synchronization method. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0171] The computer program product for the seamless switching and time synchronization method for heterogeneous dual time sources provided in this embodiment of the invention includes a computer-readable storage medium storing non-volatile program code executable by a processor. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0172] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0173] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0174] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0175] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0176] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0177] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for seamless switching and time synchronization between heterogeneous dual time sources, characterized in that, The method, applied to an intelligent converged terminal configured with a first communication link and a second communication link, includes: The link status parameters of the first communication link and the second communication link are acquired in parallel according to a preset sampling period; The link status parameters are weighted and calculated based on multiple preset coordination parameters to obtain the link quality scores of the first communication link and the second communication link respectively. The link quality score is evaluated for validity based on a three-level judgment strategy, generating valid / failed labels for each link. The three-level judgment strategy includes physical layer hard failure judgment, continuous timeout soft failure judgment, and average index degradation judgment within the window period. Different judgment weights are assigned to the heterogeneous characteristics of the first communication link and the second communication link. When the first communication link is marked as failed, a hysteresis window is entered to perform seamless handover preparation, the previous valid timestamp is cached and the stability confirmation timer of the second communication link is started. The duration of the hysteresis window is a preset hysteresis window duration. Once the second communication link has been continuously and stably maintained for a preset stable confirmation period, the local clock is updated smoothly using a frequency traction algorithm. The time deviation is divided into multiple micro-step values ​​and gradually corrected to the target time. The timestamp sequence is also constrained to be strictly monotonically increasing. Once the first communication link is restored, an asymmetric hysteresis condition is used to determine whether to perform a back-switch.

2. The method according to claim 1, characterized in that, The three-level judgment strategy specifically includes: Detect the physical layer connectivity indicator; if the physical layer is disconnected, mark the current link as failed. Check if the number of consecutive request timeouts has reached the preset number of consecutive checks; if so, mark the link as entering a degraded state. The system detects whether the average round-trip latency within the preset stable confirmation time window is greater than the latency limit or whether the average packet loss rate is greater than the packet loss rate limit. If so, the switching process is triggered. The first communication link is an Ethernet wired link, which is configured as the primary link and has a higher first-level judgment weight than the third-level judgment weight. The second communication link is a GPRS wireless link, which is configured as a backup link and has a higher third-level judgment weight than the first-level judgment weight, in order to adapt to the heterogeneous characteristics of hard failure of wired link and soft failure of wireless link.

3. The method according to claim 1, characterized in that, Enter the hysteresis window to perform seamless handover preparation, which includes: Within the preset hysteresis window duration, the local RTC maintains independent timekeeping without interrupting the currently executing time synchronization task; The previous valid timestamp in the cache is used to maintain the external timing output, ensuring that the timing is not interrupted during the switching process; The second communication link is sampled at high frequency, and the second communication link is confirmed as a valid target link only if the link quality score of the second communication link continuously meets the preset quality threshold within the preset stable confirmation time.

4. The method according to claim 1, characterized in that, The frequency traction algorithm specifically includes: Calculate the time deviation between the current time of the local RTC and the standard time of the target time source corresponding to the second communication link; The time deviation is divided into multiple micro-step adjustment amounts, and the number of micro-step adjustment amounts is equal to the preset stable confirmation time in seconds multiplied by a preset coefficient. The maximum adjustment step size is preset, and the local clock frequency is gradually pulled closer to the target time within multiple time synchronization cycles; If the time deviation is negative, meaning the local clock is ahead of the target time, then the traction adjustment is paused and the current timekeeping state is maintained to ensure that the timestamp sequence output to the business task is strictly monotonically increasing and without step changes.

5. The method according to claim 1, characterized in that, The specific conditions for asymmetric hysteresis include: Set the switching trigger delay threshold to the first threshold; Set the back-cut trigger delay threshold to a second threshold, and the second threshold is less than the first threshold; When the first communication link is restored, a switchback is performed if the following two conditions are met simultaneously: the first communication link operates stably and continuously within the preset stable confirmation period, and the real-time round-trip latency of the first communication link is consistently lower than the second threshold.

6. The method according to claim 1, characterized in that, The method also includes a parameter adaptive configuration step: After the intelligent fusion terminal is powered on for the first time or a reset operation is performed, it automatically enters a learning period of a preset duration. During the learning period, the average round-trip time, delay standard deviation, and packet loss rate distribution characteristics of the first communication link and the second communication link are statistically analyzed respectively. The upper limit of latency is dynamically adjusted based on statistical results. The upper limit of latency is updated to the sum of the average round-trip latency and the latency standard deviation of a preset multiple, so as to achieve adaptive matching of parameters under different weak network environments.

7. The method according to claim 2, characterized in that, Parallel acquisition of link status parameters, specifically including: At each of the preset sampling periods, the following read operations are performed concurrently: Read the link status register of the Ethernet PHY chip to obtain the physical layer connectivity identifier; Read the round-trip timestamps of NTP protocol exchange messages and calculate the round-trip delay; Read the physical layer packet transmission and reception statistics counter to calculate the number of consecutive packet losses and the packet loss rate; Read the signal strength indicator value of the GPRS module; The link status parameters are stored in a circular buffer in chronological order. The write and read operations of the circular buffer do not block the main time synchronization task.

8. A heterogeneous dual-time-source seamless switching time synchronization device, characterized in that, An apparatus for use in an intelligent converged terminal configured with a first communication link and a second communication link, the apparatus comprising: The parameter acquisition module is used to acquire the link status parameters of the first communication link and the second communication link in parallel according to a preset sampling period; The weighted calculation module is used to perform weighted calculations on the link status parameters based on multiple preset collaborative parameters to obtain the link quality scores of the first communication link and the second communication link respectively. The validity determination module is used to determine the validity of the link quality score according to the three-level determination strategy and generate valid / failed labels for each link. The three-level determination strategy includes physical layer hard failure determination, continuous timeout soft failure determination and average index degradation determination within the window period, and different determination weights are assigned according to the heterogeneous characteristics of the first communication link and the second communication link. The seamless handover preparation module is used to perform seamless handover preparation in a hysteresis window when the first communication link is marked as failed, cache the previous valid timestamp and start the stability confirmation timer of the second communication link. The duration of the hysteresis window is a preset hysteresis window duration. The smooth update module is used to smoothly update the local clock using a frequency traction algorithm after the second communication link has been continuously and stably reached the preset stable confirmation time. The time deviation is divided into multiple micro-step values ​​and gradually corrected to the target time, and the timestamp sequence is constrained to be strictly monotonically increasing. The execution determination module is used to determine whether to perform a back-switching after the first communication link is restored, using an asymmetric hysteresis condition.

9. An electronic device, characterized in that, The method includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, the processor executing the computer-executable instructions to implement the heterogeneous dual-time-source seamless switching time synchronization method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the heterogeneous dual-time-source seamless switching time synchronization method as described in any one of claims 1 to 7.

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