Highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit

Abstract

The application relates to a high-reliability and low-cost single-wire communication electric vehicle flasher chip circuit, which comprises a left-right turning detection module, a single-wire communication module, a SWIM communication protocol module, a flash control module, a control logic module, an overcurrent protection driving module one and an overcurrent protection driving module two. The left-right turning detection module is used for generating a left-right turning detection signal and sending the signal to the single-wire communication module. The single-wire communication module comprises the SWIM communication protocol module and the flash control module. The SWIM communication protocol module performs data read-write operation with an external MCU through a SWIM port and converts 8-bit serial data into parallel output. The control logic module is connected with the single-wire communication module. The overcurrent protection driving module one and the overcurrent protection driving module two are used for generating an overcurrent signal and sending the signal to the single-wire communication module and simultaneously generating a gate driving signal. The gate of a double-channel PMOS driving tube is used for receiving the gate driving signal to control conduction and turn-off of the double-channel PMOS driving tube. The application highly integrates communication, control, driving and detection protection functions in a single chip, and the number of peripheral components is very small.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit. Background Technology

[0002] In the safety system of electric vehicles, the flashing light system is undoubtedly a crucial component. Flashing lights, including turn signals and hazard lights, can send corresponding warning messages to other vehicles, making it essential to ensure that the vehicle's flashers can be activated at any time. Traditional electric vehicle flashers often use discrete components or simple control structures. These flasher chips or discrete components mostly only have basic flashing drive functions, which can meet basic usage requirements to a certain extent.

[0003] For example, the fully integrated electric vehicle flasher driver chip with patent publication number CN110740555A in the prior art integrates the oscillator, logic control, drive transistor and some protection circuits into a single chip. Compared with the traditional discrete component solution, it has made significant progress in integration and reliability, but it still has the following obvious shortcomings: (1) Functional limitations: Existing electric vehicle flasher chips only have basic flasher driving functions, and the flashing frequency and flashing time cannot be adjusted; the chip's detection functions are not rich enough, relying on peripheral discrete devices, and the chip's detection status cannot be transmitted to the outside world, thus failing to realize data communication transmission functions and having a low level of intelligence.

[0004] (2) Insufficient stability and limited application scenarios: The input terminals of existing flasher chips support low voltage. When the input voltage is over-exposed or the output is short-circuited, the driver chip is easily burned out due to insufficient voltage resistance and heat dissipation. Discrete devices occupy a large area, which limits the application scenarios.

[0005] (3) Limited peripheral components: Traditional flash chip requires additional external charging capacitors and has certain requirements on capacitance and voltage rating, which increases the cost of use.

[0006] Therefore, there is an urgent need to propose a highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit to solve the above-mentioned technical defects. Summary of the Invention

[0007] The purpose of this invention is to provide a highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit. By integrating dual-channel P-channel driver transistors, the chip can achieve left-turn, right-turn, and emergency hazard flashing functions via a physical switch. It also supports hazard flashing control at different frequencies and cycle counts under a single-wire communication protocol, enabling hazard flashing effects such as vehicle location warning, fault alarm lights, and welcome mode. The chip integrates left / right turn detection as well as overvoltage, overcurrent, and light loss detection functions, which can be fed back to the MCU for display on the dashboard via a communication interface. The chip has a DC withstand voltage of up to 120V. Compared to traditional flasher chips, it is less prone to damage under input overshoot and output short circuit conditions, resulting in higher reliability. Furthermore, it saves two external capacitors compared to traditional solutions, reducing operating costs.

[0008] To achieve the above objectives, the present invention provides a highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit, comprising: The left and right turn detection module is used to connect to the left and right turn detection ports LD~RD and generate left and right turn detection signals LDI~RDI, which are then sent to the single-wire communication module. The single-wire communication module includes a SWIM communication protocol module and a blink control module. The SWIM communication protocol module performs data read and write operations with an external MCU through the SWIM port, and converts the written 8-bit serial data into parallel output to obtain channel enable signals A0~A1, blink frequency control signals B0~B2, and blink count control signals C0~C2. The blink control module is used to input blink frequency control signals B0~B2, blink count control signals C0~C2, and low load signal LL2, and outputs channel two clock CLK_OUT2. The control logic module, connected to the single-wire communication module, is used to input the reset signal POR, system clock CLK, overvoltage signal OVP, undervoltage signal UVP, overtemperature signal OTP, low load signal LL1, overcurrent signals OCP1~OCP2 and channel two clock CLK_OUT2. After internal logic processing, it outputs drive signals DR1~DR2 and drive inversion signals DR1_N~DR2_N to overcurrent protection drive module one and overcurrent protection drive module two. Overcurrent protection drive module one and overcurrent protection drive module two are used to generate overcurrent signals OCP1~OCP2 and send them to the single-wire communication module, and at the same time generate gate drive signals P_GATE1~P_GATE2. The dual-channel PMOS driver transistor has its gate used to receive gate drive signals P_GATE1~P_GATE2, its source connected to the power supply VIN, and its drain connected to the dual-channel output ports OUT1~OUT2 to control the conduction and turn-off of the dual-channel PMOS driver transistor.

[0009] Preferably, the left and right turn detection module includes: resistors R0~R2, NMOS transistors NM1~NM3, a Schmitt trigger (SMIT), and a D flip-flop (DFF); one end of resistors R0~R1 is connected to the left and right turn detection ports LD~RD, the other end of resistor R0 is grounded, the other end of resistor R1 is connected to the grounded resistor R2, the input terminal of the Schmitt trigger (SMIT), and the drain and gate of NMOS transistor NM1, the source of NMOS transistor NM1 is connected to the gate and drain of NMOS transistor NM2, the source of NMOS transistor NM2 is connected to the gate and drain of NMOS transistor NM3, and the source of NMOS transistor NM3 is grounded; the power supply terminal of the Schmitt trigger (SMIT) is connected to the power supply VDD, the ground terminal is grounded, and the output terminal is connected to the input terminal of the D flip-flop (DFF); the clock terminal of the D flip-flop (DFF) receives the sampling clock CLK_SAM, the reset terminal receives the reset signal POR, and the output terminal outputs the left and right turn detection signals LDI~RDI.

[0010] Preferably, the communication data of the single-line communication module adopts the form of proportional code, including: defining 1 / 3 of the low level in one cycle as the data byte "1", 2 / 3 of the low level in one cycle as the data byte "0", and the period of one data byte is 50μs, that is, the communication rate is 20KHz; One complete data byte is 11 bits, including: The 1-bit start bit is fixed at 0. 8 bits of valid bytes, to be written as needed; A 1-bit parity bit, the parity bit is equal to the sum of the 8 bits of the valid byte's data bits; The 1-bit ACK is sent by the receiver. If ACK=1, the byte was successfully received; if ACK=0, the byte was not received.

[0011] Preferably, the control logic module includes: a frequency divider module, NAND gates NAND1~NAND6, NOT gates NOT1~NOT6, and NOR gate NOR1; the frequency divider module is used to divide the input system clock CLK and output channel one clock CLK_OUT1, and the channel one clock CLK_OUT1 is controlled by the channel one low load signal LL1; the two inputs of NAND gate NAND1 are respectively input to channel one clock CLK_OUT1 and reset signal POR, and the output is connected to the input of NOT gate NOT1; the output of NOT gate NOT1 and the channel enable signal A0 are respectively connected to the two inputs of NAND gate NAND2; the output of NAND gate NAND2 is connected to the input of NOT gate NOT2; the outputs of NOT gate NOT2 and NOR gate NOR1 are respectively connected to the input of NOT gate NAND3; and the output of NOT gate NAND3 outputs a drive inverting signal DR1_N. The NOT gate is connected to the input of NOT3, and the output of NOT3 outputs the drive signal DR1. The two inputs of NAND4 are respectively input to the channel clock CLK_OUT2 and the reset signal POR, and the output is connected to the input of NOT4. The output of NOT4 and the channel enable signal A1 are respectively connected to the two inputs of NAND5. The output of NAND5 is connected to the input of NOT5. The outputs of NOT5 and NOR1 are respectively connected to the input of NAND6. The output of NAND6 outputs the drive invert signal DR2_N and is connected to the input of NOT6. The output of NOT6 outputs the drive signal DR2. The three inputs of NOR1 are respectively input to the over-temperature signal OTP, the over-voltage signal OVP or the under-voltage signal UVP, and the over-current signals OCP1~OCP2.

[0012] Preferably, the overcurrent protection drive module one and the overcurrent protection drive module two have the same circuit structure, both including: The overcurrent protection module includes: PMOS transistors PM12~PM16; NMOS transistors NM11~NM17; resistors R10~R13; Zener diodes D11~D12; inverter INV1; and a reference current source IREF. The source of PMOS transistor PM13, and one end of resistors R10 and R12 are connected to the power supply VIN. The gate of PMOS transistor PM13 is connected to the overvoltage signal OVP. The drain is connected to the other end of resistor R10 and one end of resistor R11. The other end of resistor R11 is connected to... The source of PMOS transistor PM14; the gate and drain of PMOS transistor PM14 are connected to the gate of PMOS transistor PM15 and the drain of NMOS transistor NM14, the gate of NMOS transistor NM14 is connected to power supply VDD, and the source is connected to the drain of NMOS transistor NM12, the gate of NMOS transistor NM12 is connected to the gate and drain of NMOS transistor NM11, the reference current source IREF connected to power supply VDD, and the gates of NMOS transistors NM13 and NMOS transistor NM16; NMOS transistors NM11~N The source of NMOS transistor M13 is grounded. The drain of NMOS transistor NM13 is connected to the source of NMOS transistor NM15. The gate of NMOS transistor NM15 is connected to power supply VDD, and its drain is connected to the drain of PMOS transistor PM15, the gate of PMOS transistor PM16, and the Zener diode D11 connected to power supply VIN. The source of PMOS transistor PM15 is connected to the other end of resistor R12 and the source of PMOS transistor PM12. The gate of PMOS transistor PM12 is connected to gate drive signals P_GATE1~P_GAT. E2, the drain is connected to the dual-channel output ports OUT1~OUT2; the source of the PMOS transistor PM16 is connected to the power supply VIN, and the drain is connected to the drain of the NMOS transistor NM16, the grounded Zener diode D12, and the gate of the NMOS transistor NM17; the drain of the NMOS transistor NM17 is connected to the input terminal of the inverter INV1 and the resistor R13 connected to the power supply VIN; the sources of the NMOS transistors NM16~NM17 are grounded; the output terminal of the inverter INV1 outputs overcurrent signals OCP1~OCP2; The driving module includes: PMOS transistors PM21~PM22, NMOS transistors NM20~NM24, resistor R21, reference current source IREF, and Zener diode D21; the sources of PMOS transistors PM21~PM22 are connected to the power supply VIN, and the gate and drain of PMOS transistor PM22 are connected to the gate of PMOS transistor PM21 and the drain of NMOS transistor NM21; the gate of NMOS transistor NM21 is connected to drive signals DR1~DR2, and its source is connected to the drain of NMOS transistor NM23; the gate of NMOS transistor NM23 is connected to N... The gate and drain of MOSFET NM22 are connected to the reference current source IREF connected to the power supply VDD and the gate of NMOS transistor NM24; the sources of NMOS transistors NM22~NM24 are grounded, and the drain of NMOS transistor NM24 is connected to the source of NMOS transistor NM20; the gate of NMOS transistor NM20 is connected to the drive inverting signals DR1_N~DR2_N, the drain is connected to the drain of PMOS transistor PM21, and the resistor R21 and Zener diode D21 connected to the power supply VIN are connected, and the gate drive signals P_GATE1~P_GATE2 are output.

[0013] Preferred options also include: The bandgap reference module is used to provide the reference voltage VREF for the power-on reset module and the reference current source IREF, bias voltage VBIAS1~VBIAS2 and reference voltage VREF1~VREF2 for the oscillation module. The power-on reset module provides a reset signal POR for the oscillation module and the single-wire communication module. The oscillation module is used to provide the system clock CLK for the single-wire communication module; The overvoltage and undervoltage protection module, as well as the overtemperature protection module, are used to generate an overvoltage signal OVP, an undervoltage signal UVP, and an overtemperature signal OTP, and send them to the single-wire communication module. Low load detection module one and low load detection module two are used to generate low load signals LL1~LL2 and send them to the single-wire communication module.

[0014] Preferably, the oscillation module includes: PMOS transistors PM31~PM41, NMOS transistors NM31~NM37, capacitor C1, comparators CMP1~CMP2, NAND gates X1~X2, and buffer X3; the sources of the PMOS transistors PM31~PM35 are sequentially connected to current sources I1~I5 connected to the power supply VDD, and their drains are connected to the reference current source IREF connected to the power supply VDD, the drain of NMOS transistor NM31, and the gates of NMOS transistors NM32~NM33 and NMOS transistor NM37, with the gates sequentially connected to fuse control signals F1~F5; the gate of the NMOS transistor NM31 is connected to a bias voltage VBIAS. 1. The gates of NMOS transistors NM34 and NM36; the source of NMOS transistor NM31 is connected to the drain of NMOS transistor NM32; the source of NMOS transistor NM34 is connected to the drain of NMOS transistor NM33; the source of NMOS transistor NM36 is connected to the drain of NMOS transistor NM37; the sources of NMOS transistors NM37 and NMOS transistors NM32-NM33, and one end of capacitor C1 are grounded; the other end of capacitor C1 is connected to the drains of NMOS transistors NM35 and PMOS transistors PM40-PM41, the inverting input of comparator CMP1, and the non-inverting input of comparator CMP2. The terminals are connected to form node VS; the source of NMOS transistor NM35 is connected to the drain of NMOS transistor NM36, and its gate is connected to the gate of PMOS transistor PM40 and node M; the source of PMOS transistor PM40 is connected to the drain of PMOS transistor PM39, and the gate of PMOS transistor PM39 is connected to the gate of PMOS transistor PM37 and bias voltage VBIAS2; the drain of PMOS transistor PM37 is connected to the gates of PMOS transistors PM36 and PM38, as well as the drain of NMOS transistor NM34; the sources of PMOS transistors PM36, PM38, and PM41 are connected to power supply VD. D; The drain of PMOS transistor PM38 is connected to the source of PMOS transistor PM39, and the gate of PMOS transistor PM41 is connected to the reset signal POR; The non-inverting input of comparator CMP1 and the inverting input of comparator CMP2 are connected to reference voltages VREF1~VREF2 in sequence; The outputs of comparators CMP1~CMP2 are connected to the first input of NAND gates X1~X2 in sequence, the second input of NAND gate X1 is connected to the output of NAND gate X2, the second input of NAND gate X2 is connected to the output of NAND gate X1, node M and the input of buffer X3, and the output of buffer X3 outputs the system clock CLK; The current sources I1 to I5 are binary weighted current sources, and their ratio is I1:I2:I3:I4:I5=1:2:4:8:16.

[0015] Preferably, the low-load detection module one and the low-load detection module two have the same circuit structure, both including: A low-load reference voltage generation module includes: a voltage divider resistor unit, a comparator unit, and a voltage adjustment unit; the voltage divider resistor unit is connected in series between the power supply VIN and ground, and is used to output voltage divider signals VD1~VD8; the comparator unit is used to compare the input voltage divider signals VD1~VD8 with the reference voltage VREF, and output control signals Y1~Y8; the voltage adjustment unit is used to input control signals Y1~Y8 to adjust the equivalent resistance value of the resistor string, and inject an adjustable current source into the resistor string to output a low-load reference voltage VREF_LOWLOAD with controllable voltage. The low load detection signal generation module includes a current sampling unit and a comparator CMP3. The current sampling unit is connected in series between the power supply VIN and the dual-channel output ports OUT1~OUT2, and is used to convert the load current into a proportional sampling voltage VSENSE, and output it to the inverting input terminal of the comparator CMP3. The non-inverting input terminal of the comparator CMP3 receives the low load reference voltage VREF_LOWLOAD, and outputs low load signals LL1~LL2 after internal comparison processing.

[0016] Preferably, the voltage adjustment unit includes: The resistor adjustment array includes: a resistor string and NMOS transistors NM51~NM58; the resistor string is composed of eight resistors connected in series, the drain and source of the NMOS transistors NM51~NM58 are connected end to end in sequence, the gates are connected to control signals Y1~Y8 in sequence, the two ends of each resistor are connected to the source and drain of the NMOS transistors NM51~NM58 in sequence, one end of the resistor string is grounded, and the other end is connected to the output terminal of the current source adjustment array to generate a low load reference voltage VREF_LOWLOAD; A current source adjustment array includes: a reference current source IREF, current sources Id1~Id4, and PMOS transistors PM51~PM54; one end of the reference current source IREF and one end of the current sources Id1~Id4 are connected to the power supply VDD, and the other end of the current sources Id1~Id4 are sequentially connected to the source of the PMOS transistors PM51~PM54. The gates of the PMOS transistors PM51~PM54 are sequentially connected to fuse adjustment signals Fa~Fd. The drain of the PMOS transistors PM51~PM54 is connected to the other end of the reference current source IREF as the output terminal of the current source adjustment array; and the current sources Id1~Id4 are binary weighted current sources with a ratio of Id1:Id2:Id3:Id4=1:2:4:8.

[0017] This invention also provides an application of a single-wire communication electric vehicle flasher chip. The flasher chip includes peripheral circuitry and an internally integrated high-reliability, low-cost single-wire communication electric vehicle flasher chip circuit as described above. The flasher chip performs data read / write operations with an external MCU via a SWIM port. The peripheral circuitry includes a grounded load LED, which includes a left LED and a right LED. The left and right LEDs are respectively connected to the left / right turn detection ports LD~RD and simultaneously connected to the dual-channel output port OUT2. The left and right LEDs are connected to the dual-channel output port OUT1 via a switch. Alternatively, diodes D0~D1 are connected in series between the dual-channel output ports OUT1~OUT2 and the load LEDs.

[0018] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention incorporates dual-channel high-voltage P-channel driver transistors, enabling independent control of the flasher's left and right rotation and dual flashing. It employs a single-wire communication interface, requiring only one communication line to complete all data interaction between the external MCU and the flasher chip. Compared to traditional I2C or SPI multi-wire interfaces, this significantly reduces MCU pin occupancy and PCB wiring area, lowering the overall system cost. Furthermore, this invention highly integrates communication, control, drive, and detection / protection functions into a single chip, minimizing the need for external components.

[0019] 2. This invention receives control parameters written by an external MCU through a single-wire communication interface, enabling adjustable flashing frequency and flash count, and supporting independent enable control for left and right channels; it supports higher voltage input, eliminates the need for additional discrete components, improves chip reliability in the event of input overshoot and output short circuit, and saves two external high-voltage charging capacitors, reducing usage costs.

[0020] 3. This invention improves the chip integration and intelligence, realizes the data communication function of the electric vehicle flasher chip, and can use the chip to realize effects such as electric vehicle location warning, fault alarm light, and welcome mode. It also realizes the detection function of multiple protection mechanisms such as left and right turns of electric vehicles, overvoltage protection (OVP), undervoltage protection (UVP), overtemperature protection (OTP), and overcurrent protection (OCP). The status can be displayed on the instrument panel through MCU, which improves the overall intelligence of the flasher and ensures the safety of power tubes and loads.

[0021] 4. This invention employs an adjustable low-load reference voltage generation circuit and a current sampling circuit, enabling accurate detection of the load current status. When the turn signal bulb is damaged or has poor contact, causing a decrease in load current, the chip can promptly output a low-load indicator signal, which can be used to drive the fault indicator light or report to the MCU via the communication interface, reminding the user to check the turn signals.

[0022] 5. This invention employs a relaxation oscillator structure combined with a binary weighted current source adjustment network. The oscillation frequency is calibrated using fuse adjustment technology, effectively compensating for frequency deviations caused by process angle, temperature, and power supply voltage variations, ensuring the accuracy and consistency of the flicker frequency. Simultaneously, the dual-channel clocks are independently generated by the system clock divider and the communication control module, respectively, and the two channels can be independently configured with different flicker modes.

[0023] 6. In the left and right turn detection module, the present invention uses a Schmitt trigger to shape the input signal, effectively eliminating mechanical switch jitter and electromagnetic interference; in the communication protocol, a proportional code encoding method is used, and the receiving end decodes by identifying the low-level duty cycle, without relying on external clock synchronization, and has good anti-noise performance. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 The present invention provides a schematic diagram of a highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit.

[0026] Figure 2 The circuit diagram of the left and right turn detection module provided by the present invention.

[0027] Figure 3 This is a schematic diagram of the single-line communication module provided by the present invention.

[0028] Figure 4 A schematic diagram of the communication data format provided by this invention.

[0029] Figure 5 The circuit diagram of the control logic module provided by the present invention.

[0030] Figure 6 The circuit diagram of the oscillation module provided by the present invention.

[0031] Figure 7 The circuit diagram of the overcurrent protection module provided by the present invention.

[0032] Figure 8 The circuit diagram of the driving module provided by the present invention.

[0033] Figure 9 The circuit diagrams for the low load detection module one and the low load detection module two provided by the present invention are shown.

[0034] Figure 10 The circuit diagram of the voltage adjustment unit provided by the present invention.

[0035] Figure 11 The circuit diagram shows a typical peripheral application of the single-wire communication electric vehicle flasher chip circuit provided by this invention.

[0036] Figure 12 The peripheral application circuit diagram for preventing current backflow in the single-wire communication electric vehicle flasher chip circuit provided by the present invention is shown. Detailed Implementation

[0037] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] Combination Figure 1 and Figure 3 As shown in the figure, this embodiment of the invention specifically discloses a highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit, including: The left and right turn detection module is used to connect to the left and right turn detection ports LD~RD and generate left and right turn detection signals LDI~RDI, which are then sent to the single-wire communication module. The single-wire communication module includes a SWIM communication protocol module and a blink control module. The SWIM communication protocol module performs data read and write operations with an external MCU through the SWIM port, and converts the written 8-bit serial data into parallel output to obtain channel enable signals A0~A1, blink frequency control signals B0~B2, and blink count control signals C0~C2. The blink control module is used to input blink frequency control signals B0~B2, blink count control signals C0~C2, and low load signal LL2, and outputs channel two clock CLK_OUT2. The control logic module, connected to the single-wire communication module, is used to input the reset signal POR, system clock CLK, overvoltage signal OVP, undervoltage signal UVP, overtemperature signal OTP, low load signal LL1, overcurrent signals OCP1~OCP2 and channel two clock CLK_OUT2. After internal logic processing, it outputs drive signals DR1~DR2 and drive inversion signals DR1_N~DR2_N to overcurrent protection drive module one and overcurrent protection drive module two. Overcurrent protection drive module one and overcurrent protection drive module two are used to generate overcurrent signals OCP1~OCP2 and send them to the single-wire communication module, and at the same time generate gate drive signals P_GATE1~P_GATE2. The dual-channel PMOS driver transistor has its gate used to receive gate drive signals P_GATE1~P_GATE2, its source connected to the power supply VIN, and its drain connected to the dual-channel output ports OUT1~OUT2 to control the conduction and turn-off of the dual-channel PMOS driver transistor.

[0039] like Figure 2 As shown, the left and right turn detection module includes: resistors R0~R2, NMOS transistors NM1~NM3, a Schmitt trigger (SMIT), and a D flip-flop (DFF); one end of resistors R0~R1 is connected to the left and right turn detection ports LD~RD, the other end of resistor R0 is grounded, the other end of resistor R1 is connected to the grounded resistor R2, the input terminal of the Schmitt trigger (SMIT), and the drain and gate of NMOS transistor NM1, the source of NMOS transistor NM1 is connected to the gate and drain of NMOS transistor NM2, the source of NMOS transistor NM2 is connected to the gate and drain of NMOS transistor NM3, and the source of NMOS transistor NM3 is grounded; the power supply terminal of the Schmitt trigger (SMIT) is connected to the power supply VDD, the ground terminal is grounded, and the output terminal is connected to the input terminal of the D flip-flop (DFF); the clock terminal of the D flip-flop (DFF) receives the sampling clock CLK_SAM, the reset terminal receives the reset signal POR, and the output terminal outputs the left and right turn detection signals LDI~RDI.

[0040] Referring to Figure 2, the left / right turn detection module detects left or right turns by detecting the high or low level of the output switch node (i.e., the LD / RD port). When the left or right flashing switch is activated while the electric vehicle is in motion, the LD / RD port generates a rectangular wave of a fixed frequency during left or right turns. The left or right turn status of the electric vehicle can be determined by detecting whether there is an output from the LD / RD port. When the switch is closed, the rectangular wave on the load lamp is divided and then transmitted to the subsequent sampling unit, i.e., the D flip-flop (DFF), through a Schmitt trigger (SMIT). The Schmitt trigger (SMIT) is used to shape the waveform of the input signal after resistor voltage division and clamping, eliminating signal glitches caused by mechanical switch jitter or electromagnetic interference, and outputting a shaped signal with steep edges. Among them, transistors NM1~NM3 are voltage limiting circuits to ensure that the voltage of the voltage divider node is maintained at a low voltage, preventing the breakdown of the subsequent constant voltage circuit. The CLK_SAM signal is the sampling clock, whose clock frequency is consistent with the output rectangular wave, and the rising edge of the clock is located at the center of the high level of the output rectangular wave pulse. That is, it is sampled once per cycle. If a change in direction is detected, a high level is output to the communication module, and vice versa. The POR signal is the system power-on reset signal, used to initialize the output state of the DFF flip-flop.

[0041] like Figure 4As shown, the communication data of the single-wire communication module is encoded and transmitted using a proportional code. The proportional code encoding rule is as follows: a data byte "1" is defined as having a low-level duration of 1 / 3T within one cycle T, and a data byte "0" is defined as having a low-level duration of 2 / 3T within one cycle T. The cycle T of one data byte is 50μs, i.e., the communication rate is 20kHz. Using proportional code encoding, the receiving end can determine whether the data bit is "1" or "0" by measuring the proportion of the low-level duration to the cycle T, without relying on an external synchronization clock, thus exhibiting strong anti-interference capability. One complete data byte is 11 bits, including: A 1-bit start bit, fixed at logic 0, is used to mark the start of a data frame. The receiving end starts receiving subsequent valid data after detecting the start bit. An 8-bit valid byte can be written with control parameters such as channel enable control bit, flashing frequency control bit, and flash count control bit as needed. The external MCU can flexibly configure the flasher's working mode by writing different valid byte values. A 1-bit parity bit is used, which is equal to the sum of the 8 bits of the valid byte. The sending end calculates the number of "1"s in the valid byte; if the number is odd, the parity bit is set to 1; if the number is even, the parity bit is set to 0 (or vice versa, depending on the specific convention). The receiving end recalculates the parity of the valid byte after receiving the data and compares it with the received parity bit. If they match, the data transmission is correct; otherwise, the transmission is incorrect. The 1-bit ACK is sent by the receiver (i.e., the flash chip). If the receiver receives the data correctly and the verification passes, it sends an ACK=1 to indicate that the byte was successfully received. If the receiver detects a verification error or other abnormality, it sends an ACK=0 to indicate that the byte was not received and the sender (external MCU) should resend the data byte.

[0042] like Figure 5As shown, the control logic module includes: a frequency divider module, NAND gates NAND1~NAND6, NOT gates NOT1~NOT6, and NOR gate NOR1. The frequency divider module is used to divide the input system clock CLK and output the channel-one clock CLK_OUT1. The channel-one clock CLK_OUT1 is controlled by the channel-one low-load signal LL1. The two inputs of NAND gate NAND1 are respectively connected to the channel-one clock CLK_OUT1 and the reset signal POR. The output is connected to the input of NOT gate NOT1. The output of NOT gate NOT1 and the channel enable signal A0 are respectively connected to the two inputs of NAND gate NAND2. The output of NAND gate NAND2 is connected to the input of NOT gate NOT2. The outputs of NOT gate NOT2 and NOR gate NOR1 are respectively connected to the input of NOT gate NAND3. The output of NOT gate NAND3 outputs the drive invert signal DR1_N. The NOT gate is connected to the input of NOT3, and the output of NOT3 outputs the drive signal DR1. The two inputs of NAND4 are respectively input to the channel clock CLK_OUT2 and the reset signal POR, and the output is connected to the input of NOT4. The output of NOT4 and the channel enable signal A1 are respectively connected to the two inputs of NAND5. The output of NAND5 is connected to the input of NOT5. The outputs of NOT5 and NOR1 are respectively connected to the input of NAND6. The output of NAND6 outputs the drive invert signal DR2_N and is connected to the input of NOT6. The output of NOT6 outputs the drive signal DR2. The three inputs of NOR1 are respectively input to the over-temperature signal OTP, the over-voltage signal OVP or the under-voltage signal UVP, and the over-current signals OCP1~OCP2.

[0043] The SWIM communication protocol module converts the serial 8-bit data input from SWIM into parallel 8-bit data. A0 and A1 are channel enable signals, directly connected to the control logic module; B0, B1, and B2 are flashing frequency control signals; and C0, C1, and C2 are flash count control signals. The 6-bit data control generates the CLK_OUT2 signal, which is sent to the subsequent control logic module to provide clock pulses for dual flashing. CLK_OUT2 is controlled by the low-load signal LL2; when an external lamp in channel two is missing, CLK_OUT2 is multiplied for frequency output. The communication module can also read the system's overvoltage, overcurrent, and undervoltage detection status through the SWIM communication port.

[0044] CLK_OUT1 is the rated frequency clock for channel one, generated by frequency division by the oscillation module and controlled by the low load signal LL1 for channel one. CLK_OUT2 is the output clock of the communication module. Both are transmitted to the subsequent driver circuits through the control logic module. POR is the system power-on reset signal, which is high after power supply VDD is powered on, otherwise it is low. OTP, OVP, and UVP are the system over-temperature, over-voltage, and under-voltage signals, respectively, and are high under abnormal conditions. The channel enable signal A0 controls the switch of channel one OUT1 (left and right turning and flashing), and the channel enable signal A1 controls the switch of channel two OUT2 (double flashing). When it is logic 1, either CLK_OUT1 or CLK_OUT2 can be transmitted to the subsequent driver. The values ​​of the channel enable signals A0 and A1 are determined by the communication module. After power-on, A0 defaults to logic 1, and A1 defaults to logic 0, that is, channel one OUT1 is enabled by default.

[0045] The operating principle of the above control logic module is as follows: When the reset signal POR is valid (low level), all drive signals are forced low, and the chip is in a reset state. When POR is high, the output of the drive signal is determined by the channel enable signal, the corresponding channel clock signal, and the protection signal. Only when the channel enable is valid (A0 or A1 is high), the corresponding clock signal is valid, and all protection signals are invalid (OTP=0, OVP=0 and UVP=0, OCP1=0 and OCP2=0), the drive signal follows the clock signal, controlling the power transistor to periodically turn on and off, thereby achieving the flashing control of the turn signals. If any protection signal is valid, the drive signal is forced low, the power transistor is turned off, and fault protection is achieved.

[0046] like Figure 7 and Figure 8 As shown, the circuit structures of the overcurrent protection drive module one and the overcurrent protection drive module two are the same, both including: The overcurrent protection module includes: PMOS transistors PM12~PM16; NMOS transistors NM11~NM17; resistors R10~R13; Zener diodes D11~D12; inverter INV1; and a reference current source IREF. The source of PMOS transistor PM13, and one end of resistors R10 and R12 are connected to the power supply VIN. The gate of PMOS transistor PM13 is connected to the overvoltage signal OVP. The drain is connected to the other end of resistor R10 and one end of resistor R11. The other end of resistor R11 is connected to... The source of PMOS transistor PM14; the gate and drain of PMOS transistor PM14 are connected to the gate of PMOS transistor PM15 and the drain of NMOS transistor NM14, the gate of NMOS transistor NM14 is connected to power supply VDD, and the source is connected to the drain of NMOS transistor NM12, the gate of NMOS transistor NM12 is connected to the gate and drain of NMOS transistor NM11, the reference current source IREF connected to power supply VDD, and the gates of NMOS transistors NM13 and NMOS transistor NM16; NMOS transistors NM11~N The source of NMOS transistor M13 is grounded. The drain of NMOS transistor NM13 is connected to the source of NMOS transistor NM15. The gate of NMOS transistor NM15 is connected to power supply VDD, and its drain is connected to the drain of PMOS transistor PM15, the gate of PMOS transistor PM16, and the Zener diode D11 connected to power supply VIN. The source of PMOS transistor PM15 is connected to the other end of resistor R12 and the source of PMOS transistor PM12. The gate of PMOS transistor PM12 is connected to gate drive signals P_GATE1~P_GAT. E2, the drain is connected to the dual-channel output ports OUT1~OUT2; the source of the PMOS transistor PM16 is connected to the power supply VIN, and the drain is connected to the drain of the NMOS transistor NM16, the grounded Zener diode D12, and the gate of the NMOS transistor NM17; the drain of the NMOS transistor NM17 is connected to the input terminal of the inverter INV1 and the resistor R13 connected to the power supply VIN; the sources of the NMOS transistors NM16~NM17 are grounded; the output terminal of the inverter INV1 outputs overcurrent signals OCP1~OCP2; The driving module includes: PMOS transistors PM21~PM22, NMOS transistors NM20~NM24, resistor R21, reference current source IREF, and Zener diode D21; the sources of PMOS transistors PM21~PM22 are connected to the power supply VIN, and the gate and drain of PMOS transistor PM22 are connected to the gate of PMOS transistor PM21 and the drain of NMOS transistor NM21; the gate of NMOS transistor NM21 is connected to drive signals DR1~DR2, and its source is connected to the drain of NMOS transistor NM23; the gate of NMOS transistor NM23 is connected to N... The gate and drain of MOSFET NM22 are connected to the reference current source IREF connected to the power supply VDD and the gate of NMOS transistor NM24; the sources of NMOS transistors NM22~NM24 are grounded, and the drain of NMOS transistor NM24 is connected to the source of NMOS transistor NM20; the gate of NMOS transistor NM20 is connected to the drive inverting signals DR1_N~DR2_N, the drain is connected to the drain of PMOS transistor PM21, and the resistor R21 and Zener diode D21 connected to the power supply VIN are connected, and the gate drive signals P_GATE1~P_GATE2 are output.

[0047] The aforementioned overcurrent protection module primarily shuts off the P-drive transistor by outputting overcurrent signals OCP1 and OCP2 when the output current is large. The overcurrent protection modules for channel one and channel two have the same structure, with output signals OCP1 and OCP2 respectively. The reference current source IREF is mirrored through NM11 to the NM12 branch and provides bias for the NM13 and NM16 branches. The current in the NM12 branch flows through resistors R10 and R11, generating a fixed voltage drop. The PM15 and PM14 transistors, along with the bias circuit, form a simple common-gate input comparator. The PM12 transistor is the current sampling transistor. Under normal conditions, the voltage drop across resistor R12 is less than the voltage drop across resistors R10 and R11, pulling the drain of the PM15 transistor high and the gate of the NM17 transistor low, resulting in low-level outputs for the overcurrent signals OCP1 and OCP2. When the load current is too high, the voltage drop across resistor R12 is greater than the voltage drop across resistors R10 and R11. This causes transistor PM15 to pull the gate of transistor PM16 low, which in turn pulls the gate of transistor NM17 high. Overcurrent signals OCP1 and OCP2 output a high level, turning off the P-driver transistor. NM14 and NM15 are high-voltage transistors, acting as isolation potentials. D11 and D12 are Zener diodes, ensuring that the gate-source voltage of transistors PM16 and NM14 does not exceed the device's tolerance. OVP is the overvoltage signal; it is logic 0 when overvoltage occurs. During overvoltage, it controls transistor PM13 to conduct, thereby reducing the source voltage drop of transistor PM14 and further reducing the current limit, ensuring the chip operates without overpower.

[0048] When the aforementioned driver module is operating, the DR1 and DR2 signals are outputs from the control logic module, and the DR1_N and DR2_N signals are the inverted signals of DR1 and DR2, respectively. This driver module circuit uses a constant current source to turn the P-driver transistor on or off. When the DR1 / DR2 signals are high, the NM24 branch is on, the NM23 branch is off, and the gate drive signal P_GATE1 of the P-driver transistor is pulled low by the NM24 transistor, turning the P-driver transistor on. Conversely, when the signals are low, the NM23 branch is on, and the PM21 transistor pulls up the gate drive signal P_GATE1 of the P-driver transistor, turning the P-driver transistor off. The speed at which the P-driver transistor turns on and off can be controlled by controlling the initial current source. The NM21 and NM20 transistors use high-voltage isolation potentials. Resistor R21 provides a pull-up when there is no signal input, ensuring that the P-driver transistor does not turn on accidentally. Zener diode D21 is used to limit the VGS voltage of the P-driver transistor.

[0049] Continue reading Figure 1 As shown, it also includes: The bandgap reference module is used to provide the reference voltage VREF for the power-on reset module and the reference current source IREF, bias voltage VBIAS1~VBIAS2 and reference voltage VREF1~VREF2 for the oscillation module. The power-on reset module provides a reset signal POR for the oscillation module and the single-wire communication module. The oscillation module is used to provide the system clock CLK for the single-wire communication module; The overvoltage and undervoltage protection module, as well as the overtemperature protection module, are used to generate an overvoltage signal OVP, an undervoltage signal UVP, and an overtemperature signal OTP, and send them to the single-wire communication module. Low load detection module one and low load detection module two are used to generate low load signals LL1~LL2 and send them to the single-wire communication module.

[0050] like Figure 6As shown, the oscillation module adopts a relaxation oscillator structure, including: PMOS transistors PM31~PM41, NMOS transistors NM31~NM37, capacitor C1, comparators CMP1~CMP2, NAND gates X1~X2, and buffer X3; the sources of PMOS transistors PM31~PM35 are sequentially connected to current sources I1~I5 connected to power supply VDD, and their drains are connected to the reference current source IREF connected to power supply VDD, the drain of NMOS transistor NM31, and the gates of NMOS transistors NM32~NM33 and NMOS transistor NM37, with the gates sequentially connected to fuse control signals F1~F5; the gate of NMOS transistor NM31 is connected to a bias current source IREF connected to power supply VDD. The voltage VBIAS1 is applied to the gates of NMOS transistors NM34 and NM36; the source of NMOS transistor NM31 is connected to the drain of NMOS transistor NM32; the source of NMOS transistor NM34 is connected to the drain of NMOS transistor NM33; and the source of NMOS transistor NM36 is connected to the drain of NMOS transistor NM37. The sources of NMOS transistors NM37 and NMOS transistors NM32-NM33, and one end of capacitor C1 are grounded; the other end of capacitor C1 is connected to the drains of NMOS transistors NM35 and PMOS transistors PM40-PM41, the inverting input of comparator CMP1, and comparator CMP2. The non-inverting input terminals of the NMOS transistors are connected to form node VS; the source of the NMOS transistor NM35 is connected to the drain of the NMOS transistor NM36, and its gate is connected to the gate of the PMOS transistor PM40 and node M; the source of the PMOS transistor PM40 is connected to the drain of the PMOS transistor PM39, and the gate of the PMOS transistor PM39 is connected to the gate of the PMOS transistor PM37 and the bias voltage VBIAS2; the drain of the PMOS transistor PM37 is connected to the gates of the PMOS transistors PM36 and PM38, and the drain of the NMOS transistor NM34; the sources of the PMOS transistors PM36, PM38, and PM41 are connected to the power supply. VDD; the drain of PMOS transistor PM38 is connected to the source of PMOS transistor PM39, and the gate of PMOS transistor PM41 is connected to the reset signal POR; the non-inverting input of comparator CMP1 and the inverting input of comparator CMP2 are connected to reference voltages VREF1~VREF2 in sequence; the outputs of comparators CMP1~CMP2 are connected to the first input of NAND gates X1~X2 in sequence, the second input of NAND gate X1 is connected to the output of NAND gate X2, the second input of NAND gate X2 is connected to the output of NAND gate X1, node M and the input of buffer X3, and the output of buffer X3 outputs the system clock CLK.

[0051] The working principle of the above oscillation module is as follows: the reference current source IREF is mirrored to the PM38 and NM37 branches via a common-source cascode current mirror, and PM40 and NM35 are the charge / discharge control switches. After power-on, the POR reset signal changes from 0 to 1, at which point node M is high, controlling node VS to discharge. When the voltage of node VS is less than the reference voltage VREF2, node M changes from 1 to 0, controlling node VS to charge. After charging, when the voltage of node VS is greater than the reference voltage VREF1, node M changes from 0 to 1 again. The oscillation frequency is determined by the difference between the reference voltages VREF1 and VREF2, as well as the size of the reference current source IREF and capacitor C1. The design employs a common-source, common-gate current mirror to reduce the impact of the power supply voltage VDD on the output frequency. The current source IREF, generated by the bandgap reference module with near-zero temperature coefficient current, minimizes the temperature effect on the output frequency. The current source IREF is adjusted using a 5-bit fuse design, with fuses F1-F5 controlled by individual fuses. By selecting different combinations of current sources connected to the circuit, the drain current of the NM31 transistor is altered, thereby changing the charging and discharging current of capacitor C1, thus achieving adjustment of the oscillation frequency (OSC). This allows for adjustment of the oscillation frequency even when process corner deviations occur, ultimately achieving ±2% accuracy across the entire PVT range after adjustment. Since the OSC frequency determines the communication frequency of the external SWIM communication port, the high-precision OSC frequency output effectively enhances the chip's communication anti-interference capability, ensuring normal communication even with certain deviations in the external clock.

[0052] The current sources I1 to I5 are binary weighted current sources, with a ratio of I1:I2:I3:I4:I5=1:2:4:8:16. Through a 5-bit fuse control signal, precise adjustment of 32 frequency levels can be achieved, effectively compensating for the impact of process deviations on the oscillation frequency.

[0053] like Figure 9 As shown, the low-load detection module one and the low-load detection module two have the same circuit structure, both including: A low-load reference voltage generation module includes: a voltage divider resistor unit, a comparator unit, and a voltage adjustment unit; the voltage divider resistor unit is connected in series between the power supply VIN and ground, and is used to output voltage divider signals VD1~VD8; the comparator unit is used to compare the input voltage divider signals VD1~VD8 with the reference voltage VREF, and output control signals Y1~Y8; the voltage adjustment unit is used to input control signals Y1~Y8 to adjust the equivalent resistance value of the resistor string, and inject an adjustable current source into the resistor string to output a low-load reference voltage VREF_LOWLOAD with controllable voltage. The low load detection signal generation module includes a current sampling unit and a comparator CMP3. The current sampling unit is connected in series between the power supply VIN and the dual-channel output ports OUT1~OUT2, and is used to convert the load current into a proportional sampling voltage VSENSE, and output it to the inverting input terminal of the comparator CMP3. The non-inverting input terminal of the comparator CMP3 receives the low load reference voltage VREF_LOWLOAD, and outputs low load signals LL1~LL2 after internal comparison processing.

[0054] like Figure 10 As shown, the voltage adjustment unit includes: The resistor adjustment array includes: a resistor string and NMOS transistors NM51~NM58; the resistor string is composed of eight resistors connected in series, the drain and source of the NMOS transistors NM51~NM58 are connected end to end in sequence, the gates are connected to control signals Y1~Y8 in sequence, the two ends of each resistor are connected to the source and drain of the NMOS transistors NM51~NM58 in sequence, one end of the resistor string is grounded, and the other end is connected to the output terminal of the current source adjustment array to generate a low load reference voltage VREF_LOWLOAD; A current source adjustment array includes: a reference current source IREF, current sources Id1~Id4, and PMOS transistors PM51~PM54; one end of the reference current source IREF and one end of the current sources Id1~Id4 are connected to the power supply VDD, and the other end of the current sources Id1~Id4 are sequentially connected to the source of the PMOS transistors PM51~PM54. The gates of the PMOS transistors PM51~PM54 are sequentially connected to fuse adjustment signals Fa~Fd. The drain of the PMOS transistors PM51~PM54 is connected to the other end of the reference current source IREF as the output terminal of the current source adjustment array; and the current sources Id1~Id4 are binary weighted current sources with a ratio of Id1:Id2:Id3:Id4=1:2:4:8.

[0055] The working principle of the above-mentioned low load detection module one or low load detection module two includes: the output current of the load LED is different under different input voltages, and the low load detection realizes that when the output load is lower than a certain threshold under different voltages, a low load signal will be issued to control the frequency multiplication output of the subsequent circuit.

[0056] The VIN power supply outputs eight voltage divider signals (VD1~VD8) through a resistor divider unit, representing eight voltage levels. These divided signals are then compared by a comparator unit to output control signals Y1~Y8, controlling whether transistors NM1~NM8 are turned on. This controls the resistance value of the resistor string corresponding to the low-load reference voltage VREF_LOWLOAD, allowing for changes in the equivalent resistance value of the resistor string and thus coarse adjustment of the VREF_LOWLOAD voltage. The VREF_LOWLOAD voltage is compared with the VSENSE voltage by comparator CMP3, outputting either channel one low-load signal LL1 or channel two low-load signal LL2. VSENSE is the sampling voltage of the load current flowing out through the current sampling unit. Therefore, different VREF_LOWLOAD voltages correspond to different load current detection points, thereby achieving low-load detection under different input voltages VIN.

[0057] Simultaneously, the chip performs fuse trimming on the current flowing into the resistor string: the gates of transistors PM1 to PM4 are controlled by fuse control signals Fa, Fb, Fc, and Fd respectively. When the fuse control signal is logic 0, the branch current can flow into the lower resistor string; when it is logic 1, the current branch is turned off, thereby controlling the magnitude of the trimming current injected into the resistor string, thus achieving fine trimming of the VREF_LOWLOAD voltage. Through the combined trimming of the resistor trimming array (coarse trimming) and the current source trimming array (fine trimming), a high-precision low-load current detection effect can be achieved, avoiding misjudgments caused by process deviations.

[0058] like Figure 11 The diagram shows a typical peripheral application circuit for the flasher chip in an ESOP8L package. VDD is the 5V power supply pin, VIN is the high-voltage input pin, LD / RD are the output left / right turn detection pins, OUT1 and OUT2 are the left / right turn flashing and dual-flash channel outputs respectively, and SWIM is the single-wire communication port. The chip requires no other additional peripheral components, achieving a very simple peripheral application solution. Figure 12 When the peripheral application circuit diagram is shown, diodes D0 and D1 can effectively prevent current backflow and further improve the reliability of the flasher.

[0059] As a further description of the embodiments of the present invention, when the low-voltage power supply VDD and the high-voltage power supply VIN are input, the internal bandgap reference module of the chip is activated, the power-on reset module controls the oscillation module and other state detection circuit modules to work normally, and the system clock CLK is divided by the frequency divider module to drive the left and right turn signals (i.e., channel OUT1) to flash and the double flash (i.e., channel OUT2) to output. The output voltage is approximately equal to the VIN voltage, driving the external bulb to flash. The overvoltage, overcurrent, and overtemperature protection modules shut down the P-driver transistor to achieve protection when the input voltage is too high, the output current is too high, and the chip temperature is too high, respectively. When the low load detection module detects that the external load current is less than the set threshold, it considers that the system is missing a lamp and controls the output frequency to be twice the rated frequency to achieve the effect of missing lamp flashing.

[0060] The single-wire communication module transmits data through the single-wire communication port SWIM. The single-wire communication port can perform data read and write operations in the form of commands and data. When there is no signal input at the SWIM port, the chip defaults to enabling the OUT1 channel and disabling the OUT2 output. The clock frequency of the OUT1 output is a fixed-frequency divider of the system clock frequency, and the chip implements the physical left and right blinking function. When the SWIM port performs a write operation, the output of OUT1 or OUT2 can be turned on depending on the data written. When OUT2 is turned on, the logic outputs clocks of different frequencies and times are controlled according to the different data written. The clock drives the P drive transistor to achieve double flashing output with different flashing frequencies and times. This method can be used to realize double flashing effects such as vehicle search warning, fault alarm light, and welcome mode for electric vehicles. The output signals of each status detection module are connected to the single-wire communication module. When SWIM performs a read operation, it can read the status information of the flasher, such as left turn, right turn, over-temperature, over-voltage, over-current, and missing light, within a specific time period and display it on the instrument panel through the MCU. No other discrete components are required to achieve intelligent display.

[0061] The chip uses a high-voltage P-type transistor as its driver, with an input port DC withstand voltage up to 120V. Using a P-type driver eliminates the need for external charging capacitors in traditional flasher chips. The P-type driver also increases the heat dissipation area, improving the overcurrent capability during short circuits. The invention ultimately achieves a flasher function with left turn, right turn, and emergency dual flashes via a physical switch. It also supports dual flash control at different frequencies and cycles under a single-wire communication protocol, integrates various abnormal state monitoring and feedback functions, improves chip reliability, and reduces operating costs.

[0062] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit, characterized in that, include: The left and right turn detection module is used to connect to the left and right turn detection ports LD~RD and generate left and right turn detection signals LDI~RDI, which are then sent to the single-wire communication module. The single-wire communication module includes a SWIM communication protocol module and a blink control module. The SWIM communication protocol module performs data read and write operations with an external MCU through the SWIM port, and converts the written 8-bit serial data into parallel output to obtain channel enable signals A0~A1, blink frequency control signals B0~B2, and blink count control signals C0~C2. The blink control module is used to input blink frequency control signals B0~B2, blink count control signals C0~C2, and low load signal LL2, and outputs channel two clock CLK_OUT2. The control logic module, connected to the single-wire communication module, is used to input the reset signal POR, system clock CLK, overvoltage signal OVP, undervoltage signal UVP, overtemperature signal OTP, low load signal LL1, overcurrent signals OCP1~OCP2 and channel two clock CLK_OUT2. After internal logic processing, it outputs drive signals DR1~DR2 and drive inversion signals DR1_N~DR2_N to overcurrent protection drive module one and overcurrent protection drive module two. Overcurrent protection drive module one and overcurrent protection drive module two are used to generate overcurrent signals OCP1~OCP2 and send them to the single-wire communication module, and at the same time generate gate drive signals P_GATE1~P_GATE2. The dual-channel PMOS driver transistor has its gate used to receive gate drive signals P_GATE1~P_GATE2, its source connected to the power supply VIN, and its drain connected to the dual-channel output ports OUT1~OUT2 to control the conduction and turn-off of the dual-channel PMOS driver transistor.

2. The highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit as described in claim 1, characterized in that, The left and right turn detection module includes: resistors R0~R2, NMOS transistors NM1~NM3, a Schmitt trigger (SMIT), and a D flip-flop (DFF); one end of resistors R0~R1 is connected to the left and right turn detection ports LD~RD, the other end of resistor R0 is grounded, the other end of resistor R1 is connected to the grounded resistor R2, the input terminal of the Schmitt trigger (SMIT), and the drain and gate of NMOS transistor NM1, the source of NMOS transistor NM1 is connected to the gate and drain of NMOS transistor NM2, the source of NMOS transistor NM2 is connected to the gate and drain of NMOS transistor NM3, and the source of NMOS transistor NM3 is grounded; the power supply terminal of the Schmitt trigger (SMIT) is connected to the power supply VDD, the ground terminal is grounded, and the output terminal is connected to the input terminal of the D flip-flop (DFF); the clock terminal of the D flip-flop (DFF) receives the sampling clock CLK_SAM, the reset terminal receives the reset signal POR, and the output terminal outputs the left and right turn detection signals LDI~RDI.

3. The highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit as described in claim 1, characterized in that, The communication data of the single-line communication module adopts the form of proportional code, including: defining 1 / 3 of the low level in one cycle as the data byte "1", 2 / 3 of the low level in one cycle as the data byte "0", and the period of one data byte is 50μs, that is, the communication rate is 20KHz; One complete data byte is 11 bits, including: The 1-bit start bit is fixed at 0. 8 bits of valid bytes, to be written as needed; A 1-bit parity bit, the parity bit is equal to the sum of the 8 bits of the valid byte's data bits; The 1-bit ACK is sent by the receiver. If ACK=1, the byte was successfully received; if ACK=0, the byte was not received.

4. The highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit as described in claim 1, characterized in that, The control logic module includes: a frequency divider module, NAND gates NAND1~NAND6, NOT gates NOT1~NOT6, and NOR gate NOR1. The frequency divider module is used to divide the input system clock CLK and output the channel-one clock CLK_OUT1. The channel-one clock CLK_OUT1 is controlled by the channel-one low-load signal LL1. The two inputs of NAND gate NAND1 are respectively connected to the channel-one clock CLK_OUT1 and the reset signal POR. The output is connected to the input of NOT gate NOT1. The output of NOT gate NOT1 and the channel enable signal A0 are respectively connected to the two inputs of NAND gate NAND2. The output of NAND gate NAND2 is connected to the input of NOT gate NOT2. The outputs of NOT gate NOT2 and NOR gate NOR1 are respectively connected to the input of NOT gate NAND3. The output of NOT gate NAND3 outputs a drive inverted signal DR1_N and connects to... The NOT gate's input terminal is connected to the NOT gate's input terminal, and the NOT gate's output terminal outputs the drive signal DR1. The NAND gate's two input terminals are respectively connected to the channel clock CLK_OUT2 and the reset signal POR, and its output terminal is connected to the NOT gate's input terminal. The NOT gate's output terminal and the channel enable signal A1 are respectively connected to the two input terminals of the NAND gate's NAND gate. The NAND gate's output terminal is connected to the NOT gate's input terminal. The NOT gate's output terminal and the NOR gate's output terminal are respectively connected to the NOT gate's input terminal. The NAND gate's output terminal outputs the drive invert signal DR2_N and is connected to the NOT gate's input terminal. The NOT gate's output terminal outputs the drive signal DR2. The NOR gate's three input terminals are respectively connected to the over-temperature signal OTP, the over-voltage signal OVP or the under-voltage signal UVP, and the over-current signals OCP1~OCP2.

5. The highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit as described in claim 1, characterized in that, The overcurrent protection drive module one and the overcurrent protection drive module two have the same circuit structure, both including: The overcurrent protection module includes: PMOS transistors PM12~PM16; NMOS transistors NM11~NM17; resistors R10~R13; Zener diodes D11~D12; inverter INV1; and a reference current source IREF. The source of PMOS transistor PM13, and one end of resistors R10 and R12 are connected to the power supply VIN. The gate of PMOS transistor PM13 is connected to the overvoltage signal OVP. The drain is connected to the other end of resistor R10 and one end of resistor R11. The other end of resistor R11 is connected to... The source of PMOS transistor PM14; the gate and drain of PMOS transistor PM14 are connected to the gate of PMOS transistor PM15 and the drain of NMOS transistor NM14, the gate of NMOS transistor NM14 is connected to power supply VDD, and the source is connected to the drain of NMOS transistor NM12, the gate of NMOS transistor NM12 is connected to the gate and drain of NMOS transistor NM11, the reference current source IREF connected to power supply VDD, and the gates of NMOS transistors NM13 and NMOS transistor NM16; NMOS transistors NM11~N The source of NMOS transistor M13 is grounded. The drain of NMOS transistor NM13 is connected to the source of NMOS transistor NM15. The gate of NMOS transistor NM15 is connected to power supply VDD, and its drain is connected to the drain of PMOS transistor PM15, the gate of PMOS transistor PM16, and the Zener diode D11 connected to power supply VIN. The source of PMOS transistor PM15 is connected to the other end of resistor R12 and the source of PMOS transistor PM12. The gate of PMOS transistor PM12 is connected to gate drive signals P_GATE1~P_GAT. E2, the drain is connected to the dual-channel output ports OUT1~OUT2; the source of the PMOS transistor PM16 is connected to the power supply VIN, and the drain is connected to the drain of the NMOS transistor NM16, the grounded Zener diode D12, and the gate of the NMOS transistor NM17; the drain of the NMOS transistor NM17 is connected to the input terminal of the inverter INV1 and the resistor R13 connected to the power supply VIN; the sources of the NMOS transistors NM16~NM17 are grounded; the output terminal of the inverter INV1 outputs overcurrent signals OCP1~OCP2; The driving module includes: PMOS transistors PM21~PM22, NMOS transistors NM20~NM24, resistor R21, reference current source IREF, and Zener diode D21; the sources of PMOS transistors PM21~PM22 are connected to the power supply VIN, and the gate and drain of PMOS transistor PM22 are connected to the gate of PMOS transistor PM21 and the drain of NMOS transistor NM21; the gate of NMOS transistor NM21 is connected to drive signals DR1~DR2, and its source is connected to the drain of NMOS transistor NM23; the gate of NMOS transistor NM23 is connected to N... The gate and drain of MOSFET NM22 are connected to the reference current source IREF connected to the power supply VDD and the gate of NMOS transistor NM24; the sources of NMOS transistors NM22~NM24 are grounded, and the drain of NMOS transistor NM24 is connected to the source of NMOS transistor NM20; the gate of NMOS transistor NM20 is connected to the drive inverting signals DR1_N~DR2_N, the drain is connected to the drain of PMOS transistor PM21, and the resistor R21 and Zener diode D21 connected to the power supply VIN are connected, and the gate drive signals P_GATE1~P_GATE2 are output.

6. The highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit as described in claim 1, characterized in that, Also includes: The bandgap reference module is used to provide the reference voltage VREF for the power-on reset module and the reference current source IREF, bias voltage VBIAS1~VBIAS2 and reference voltage VREF1~VREF2 for the oscillation module. The power-on reset module provides a reset signal POR for the oscillation module and the single-wire communication module. The oscillation module is used to provide the system clock CLK for the single-wire communication module; The overvoltage and undervoltage protection module, as well as the overtemperature protection module, are used to generate an overvoltage signal OVP, an undervoltage signal UVP, and an overtemperature signal OTP, and send them to the single-wire communication module. Low load detection module one and low load detection module two are used to generate low load signals LL1~LL2 and send them to the single-wire communication module.

7. The highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit as described in claim 6, characterized in that, The oscillation module includes: PMOS transistors PM31~PM41, NMOS transistors NM31~NM37, capacitor C1, comparators CMP1~CMP2, NAND gates X1~X2, and buffer X3; the sources of PMOS transistors PM31~PM35 are sequentially connected to current sources I1~I5 connected to power supply VDD, and their drains are connected to the reference current source IREF connected to power supply VDD, the drain of NMOS transistor NM31, and the gates of NMOS transistors NM32~NM33 and NMOS transistor NM37, with the gates sequentially connected to fuse control signals F1~F5; the gate of NMOS transistor NM31 is connected to bias voltage VBIAS1, N... The gates of NMOS transistors NM34 and NM36 are connected; the source of NMOS transistor NM31 is connected to the drain of NMOS transistor NM32; the source of NMOS transistor NM34 is connected to the drain of NMOS transistor NM33; the source of NMOS transistor NM36 is connected to the drain of NMOS transistor NM37; the sources of NMOS transistors NM37 and NMOS transistors NM32-NM33, and one end of capacitor C1 are grounded; the other end of capacitor C1 is connected to the drains of NMOS transistors NM35 and PMOS transistors PM40-PM41, the inverting input of comparator CMP1, and the non-inverting input of comparator CMP2. Node VS is formed; the source of NMOS transistor NM35 is connected to the drain of NMOS transistor NM36, and its gate is connected to the gate of PMOS transistor PM40 and node M; the source of PMOS transistor PM40 is connected to the drain of PMOS transistor PM39, and the gate of PMOS transistor PM39 is connected to the gate of PMOS transistor PM37 and bias voltage VBIAS2; the drain of PMOS transistor PM37 is connected to the gates of PMOS transistors PM36 and PM38, as well as the drain of NMOS transistor NM34; the sources of PMOS transistors PM36, PM38, and PM41 are connected to power supply VDD. The drain of PMOS transistor PM38 is connected to the source of PMOS transistor PM39, and the gate of PMOS transistor PM41 is connected to the reset signal POR. The non-inverting input of comparator CMP1 and the inverting input of comparator CMP2 are connected to reference voltages VREF1~VREF2 in sequence. The outputs of comparators CMP1~CMP2 are connected to the first input of NAND gates X1~X2 in sequence. The second input of NAND gate X1 is connected to the output of NAND gate X2. The second input of NAND gate X2 is connected to the output of NAND gate X1, node M, and the input of buffer X3. The output of buffer X3 outputs the system clock CLK. The current sources I1 to I5 are binary weighted current sources, and their ratio is I1:I2:I3:I4:I5=1:2:4:8:

16.

8. The highly reliable and low-cost single-wire communication electric vehicle flasher chip circuit as described in claim 6, characterized in that, The low-load detection module one and the low-load detection module two have the same circuit structure, both including: A low-load reference voltage generation module includes: a voltage divider resistor unit, a comparator unit, and a voltage adjustment unit; the voltage divider resistor unit is connected in series between the power supply VIN and ground, and is used to output voltage divider signals VD1~VD8; the comparator unit is used to compare the input voltage divider signals VD1~VD8 with the reference voltage VREF, and output control signals Y1~Y8; the voltage adjustment unit is used to input control signals Y1~Y8 to adjust the equivalent resistance value of the resistor string, and inject an adjustable current source into the resistor string to output a low-load reference voltage VREF_LOWLOAD with controllable voltage. The low load detection signal generation module includes a current sampling unit and a comparator CMP3. The current sampling unit is connected in series between the power supply VIN and the dual-channel output ports OUT1~OUT2, and is used to convert the load current into a proportional sampling voltage VSENSE, and output it to the inverting input terminal of the comparator CMP3. The non-inverting input terminal of the comparator CMP3 receives the low load reference voltage VREF_LOWLOAD, and outputs low load signals LL1~LL2 after internal comparison processing.

9. The high-reliability, low-cost single-wire communication electric vehicle flasher chip circuit as described in claim 8, characterized in that, The voltage adjustment unit includes: The resistor adjustment array includes: a resistor string and NMOS transistors NM51~NM58; the resistor string is composed of eight resistors connected in series, the drain and source of the NMOS transistors NM51~NM58 are connected end to end in sequence, the gates are connected to control signals Y1~Y8 in sequence, the two ends of each resistor are connected to the source and drain of the NMOS transistors NM51~NM58 in sequence, one end of the resistor string is grounded, and the other end is connected to the output terminal of the current source adjustment array to generate a low load reference voltage VREF_LOWLOAD; A current source adjustment array includes: a reference current source IREF, current sources Id1~Id4, and PMOS transistors PM51~PM54; one end of the reference current source IREF and one end of the current sources Id1~Id4 are connected to the power supply VDD, and the other end of the current sources Id1~Id4 are sequentially connected to the source of the PMOS transistors PM51~PM54. The gates of the PMOS transistors PM51~PM54 are sequentially connected to fuse adjustment signals Fa~Fd. The drain of the PMOS transistors PM51~PM54 is connected to the other end of the reference current source IREF as the output terminal of the current source adjustment array; and the current sources Id1~Id4 are binary weighted current sources with a ratio of Id1:Id2:Id3:Id4=1:2:4:

8.

10. An application of a single-wire communication electric vehicle flasher chip, characterized in that, The flasher chip includes peripheral circuitry and an internally integrated high-reliability, low-cost single-wire communication electric vehicle flasher chip circuit as described in any one of claims 1 to 9. The flasher chip performs data read / write operations with an external MCU via a SWIM port. The peripheral circuitry includes a grounded load LED, which includes a left LED and a right LED. The left and right LEDs are respectively connected to the left and right turn detection ports LD~RD and simultaneously connected to the dual-channel output port OUT2. The left and right LEDs are connected to the dual-channel output port OUT1 via a switch. Alternatively, diodes D0~D1 are connected in series between the dual-channel output ports OUT1~OUT2 and the load LEDs.

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