A parameter optimization method for electroplating copper-filled via in high-power PCB bolt pressure-bearing area

Abstract

The application discloses a parameter optimization method for copper-filled via hole electroplating in a high-power PCB bolt pressure-bearing area, and relates to the technical field of high-power power electronic printed circuit board design and optimization. The method comprises the following steps: collecting the voltage drop amplitude of a plurality of sampling positions of a power tube under the condition that the power tube is pressed against a PCB pressure-bearing pad through a locking bolt, calculating the voltage drop gradient between adjacent sampling positions, dividing the PCB pressure-bearing pad into regions according to the spatial distribution of the voltage drop gradient, and determining each current injection region. The application determines the target current-carrying capacity of each position solid copper column through the voltage drop and current distribution under the locking state of the power tube, optimizes the hole diameter, center distance and number of the copper-filled via hole electroplating according to the target current-carrying capacity, realizes the differentiated matching of the via hole parameters and the local current-carrying demand, improves the current sharing state of the via hole array, reduces the conduction loss and temperature rise risk caused by local current concentration, and improves the current-carrying utilization efficiency and continuous working reliability of the PCB pressure-bearing area.

Description

Technical Field

[0001] This invention relates to the field of high-power power electronic printed circuit board design and optimization technology, specifically to a parameter optimization method for copper-filled vias in the bolt bearing area of ​​a high-power PCB. Background Technology

[0002] Parameter optimization of copper-plated vias in the bolt bearing area of ​​high-power PCBs refers to the rational selection and combination of structural parameters such as hole diameter, hole spacing, number of vias, array size, and arrangement of copper-plated vias located within the bolt bearing pads or corresponding pressure areas in high-power power electronic devices such as SST solid-state transformers, which are formed when power transistors are connected to PCB power pads by bolt clamping. This optimization addresses the localized high mechanical load, high current, and high heat flux density areas created by the bolt clamping method to connect power transistors to PCB power pads. The goal is to create dense, solid copper pillars without cavities within these vias through full-hole copper plating. These vias then serve as low-resistance conductive and heat-conducting pathways connecting the PCB surface power pads, multiple conductive copper layers in the middle, and the bottom heat-dissipating conductive copper layer. Furthermore, they form multiple distributed rigid support points along the PCB thickness, thereby improving the bolt bearing capacity. The bolt clamping area has the ability to resist locking torque, local compression deformation, and long-term high-frequency vibration. Specifically, the diameter of the solid copper pillar via is preferably 0.2mm-0.4mm. The purpose is to ensure the yield of electroplating copper filling process without occupying too much PCB wiring space. The center distance between adjacent vias is preferably not less than 0.5mm. The array can adopt a 4×4 or 5×5 matrix, but is not limited to the above matrix specifications. The number of vias and the geometric arrangement can be adjusted according to the size of the pressure-bearing pad, bolt specifications, and power module assembly structure. For example, a specific structure can adopt a 5×5 matrix, a single via diameter of 0.3mm, and a center distance between adjacent vias of 0.6mm. Each via is completely filled with metallic copper to form a solid copper pillar that vertically penetrates the PCB surface layer, the middle power copper layer, and the bottom heat dissipation copper layer.

[0003] Therefore, parameter optimization is not simply about pursuing larger and more numerous vias, but rather about achieving a comprehensive balance between the feasibility of copper plating, PCB space occupation, conductivity and current carrying capacity, longitudinal heat dissipation capacity, and mechanical stiffness of the bolt bearing area. By optimizing the hole diameter, spacing, and array size, multiple solid copper pillars can form an array structure in the bolt bearing area that serves as a conductive channel, a heat-conducting channel, and a mechanical support pillar. This addresses the problems of traditional hollow through-holes that rely solely on a thin layer of copper on the hole wall for conductivity and heat conduction, as well as the issues that easily arise at the bolt clamping position, such as copper skin crushing, peeling, slippage, and board delamination and cracking. It achieves a synergistic improvement in electrical performance, thermal performance, and mechanical bearing reliability of the bolt connection area of ​​high-power PCBs.

[0004] Existing technologies have the following shortcomings: During the process of pressing the power transistor onto the PCB power pads with locking bolts, the parameters such as the aperture, spacing, and array number of the electroplated copper-filled vias are usually optimized based on the conductivity characteristics of the PCB when it is not under pressure, and the corresponding parameters are determined according to the expected current shunting capacity of each solid copper pillar. However, when the locking bolts apply pressure to the power transistor's electrode face, the bolt clamping load changes the actual contact state of the power transistor's electrode face on the pressure-bearing pad, causing changes in the position and distribution range of the current entering the pressure-bearing pad, which in turn leads to a redistribution of the current in the matrix-type electroplated copper-filled vias. At this time, some solid copper pillars that originally only carried a small shunt current may become the main current-carrying channels, causing a significant increase in the current density of local copper pillars, resulting in large current carrying differences between different copper pillars, and in severe cases, causing increased local conduction losses and abnormal temperature rise. Therefore, the optimal aperture, spacing, and array number determined based on the PCB when it is not under pressure cannot accurately reflect the conductivity requirements of the power transistor under the actual bolt-tightened state, which can easily lead to deviations in the optimization results of the electroplated copper-filled via parameters.

[0005] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a parameter optimization method for the electroplating copper-filled vias in the pressure-bearing area of ​​high-power PCB bolts, so as to solve the problems in the background art mentioned above.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a method for optimizing the parameters of copper-plated vias in the bearing area of ​​high-power PCB bolts, comprising the following steps: The voltage drop amplitude at multiple sampling locations is collected when the power transistor is pressed into the PCB pressure pad by the locking bolt. The voltage drop gradient between adjacent sampling locations is calculated. The PCB pressure pad is divided into regions according to the spatial distribution of the voltage drop gradient to determine each current injection region. The local current density is calculated using the voltage drop gradient corresponding to each current injection region, and the current concentration region is determined according to the distribution of local current density on the PCB pressure pad, and the current density distribution corresponding to the current concentration region is obtained. The target current carrying capacity of the solid copper pillars in the electroplated copper-filled vias at each location is determined according to the current density distribution corresponding to the current concentration area. The corresponding aperture difference is determined according to the target current carrying capacity of the solid copper pillars at different locations, so as to obtain the aperture parameters of the solid copper pillars that match the local current carrying capacity requirements. The center-to-center spacing between adjacent solid copper pillars is adjusted by referring to the difference in the aperture of the solid copper pillars at each position, and the local density of the electroplated copper-filled via array is configured according to the target current carrying capacity of the solid copper pillars at each position to determine the center-to-center spacing parameters corresponding to different positions. Based on the local density of the copper-filled via array and the center-to-center spacing parameters at different locations, the number of copper-filled vias at each location is determined. The via diameter, center-to-center spacing, and number of vias are output to match the current distribution under the locked state of the power transistor, thus completing the parameter optimization of the copper-filled vias in the bolt bearing area of ​​the high-power PCB.

[0008] Preferably, multiple sampling positions are continuously arranged along intersecting first and second spatial directions. Two sampling positions with continuous positional relationships are determined as spatially adjacent sampling positions. The current output position corresponding to the PCB pressure pad is selected as a unified potential reference position. The voltage drop amplitude between each sampling position and the unified potential reference position is collected respectively. The voltage drop gradient is determined according to the change in the voltage drop amplitude corresponding to the spatially adjacent sampling positions and the actual distance between them. The spatial direction of the voltage drop gradient is determined according to the potential drop direction between two sampling positions, thus obtaining the spatial distribution of the voltage drop gradient.

[0009] Preferably, the spatial distribution of the voltage drop gradient is divided into multiple continuous and non-overlapping voltage drop gradient intervals according to the value range corresponding to all voltage drop gradients. Each voltage drop gradient interval corresponds to a gradient level. Sampling positions that are spatially continuous, have the same gradient level, and have a continuous transmission relationship in the voltage drop gradient direction are grouped into the same current injection region. When spatially adjacent sampling positions correspond to different gradient levels, the region boundary is determined by the position between the two. When the gradient levels are the same but the voltage drop gradient directions point to different current transmission ranges, the region boundary is determined by the direction conversion position, thereby obtaining the spatial boundary corresponding to each current injection region.

[0010] Preferably, the voltage drop gradient corresponding to each current injection region is used to determine the local potential change rate, and the local current density at each sampling position is determined in combination with the conductivity corresponding to the PCB pressure pad. The sampling positions with the first spatial voltage drop gradient and the second spatial voltage drop gradient respectively obtain the local current density components in the first spatial direction and the local current density components in the second spatial direction. The local current density and current transmission direction of the corresponding sampling position are determined by the local current density components in the two directions. The local current densities corresponding to each sampling position are arranged according to the spatial position to obtain the spatial distribution of the local current density of the PCB pressure pad.

[0011] Preferably, the current density boundary value in the spatial distribution of local current density is jointly determined by the allowable current carrying capacity of the solid copper column corresponding to the initial aperture parameter and the current carrying capacity distribution range of a single solid copper column corresponding to the initial center-to-center spacing parameter. The range corresponding to the sampling position where the local current density reaches the current density boundary value and is spatially continuous is determined as the current concentration region, and the continuous ranges that are separated from each other are determined as different current concentration regions. Each current concentration region retains the local current density, local current density direction, spatial adjacency relationship, and current density change relationship corresponding to the two spatial directions corresponding to the sampling position, thus obtaining the corresponding current density distribution.

[0012] Preferably, the current density distribution corresponding to the current concentration area is divided into multiple current distribution ranges according to the candidate center position of the solid copper pillar. The midpoint between adjacent candidate center positions is used as the boundary position of the current distribution range. Based on the local current density, effective transmission range and current transmission direction corresponding to the boundary of each current distribution range, the inflow current entering the current distribution range and the in-plane outflow current leaving the current distribution range along the plane direction of the PCB pressure pad are determined respectively. The current demand obtained by subtracting the in-plane outflow current from the inflow current is used as the vertical shunt demand, and the vertical shunt demand is allocated to the corresponding solid copper pillar to determine the target current carrying capacity.

[0013] Preferably, the target current carrying capacity of the solid copper column and the preset allowable current density jointly determine the minimum effective conductive cross-sectional area required to bear the target current carrying capacity. According to the correspondence between the effective conductive cross-sectional area of ​​the solid copper column and the aperture, the smallest aperture level whose allowable current carrying capacity can cover the target current carrying capacity is selected from the first aperture level, the second aperture level, the third aperture level and subsequent aperture levels arranged in sequence as the aperture parameter of the solid copper column at the corresponding position. When the target current carrying capacity exceeds the allowable current carrying capacity corresponding to the largest aperture level, the corresponding vertical current shunting requirement is configured to two or more solid copper columns, and the current requirement exceeding the allowable current carrying capacity of a single solid copper column is borne by the number of vias.

[0014] Preferably, the numerical difference between the corresponding aperture parameters of solid copper pillars at different positions is determined as the aperture difference value. The minimum allowable center spacing is determined based on the actual aperture parameters of two adjacent solid copper pillars and the preset minimum interval. Multiple center spacing levels are arranged in ascending order of center spacing. First, center spacing levels smaller than the minimum center spacing are excluded. Then, the actual center spacing parameters are selected from the remaining center spacing levels according to the target current carrying capacity corresponding to adjacent positions. When two adjacent solid copper pillars correspond to different target current carrying capacities, the center spacing level corresponding to the target current carrying capacity with the larger current carrying capacity is used as the initial selection, and the center spacing level is adjusted according to the minimum center spacing.

[0015] Preferably, the local density of the electroplated copper-filled via array is determined by the number of electroplated copper-filled vias per unit configuration range and the center-to-center distance between adjacent solid copper pillars. For continuous locations with high target current carrying capacity, a center-to-center distance level with a small value that meets the minimum center-to-center distance condition is selected, while for continuous locations with low target current carrying capacity, a center-to-center distance level with a large value is selected. A continuous spatial range with the same aperture level and the same center-to-center distance level in the same current concentration region is defined as a via configuration range. The location where the aperture level or center-to-center distance level changes is used as the boundary between adjacent via configuration ranges. The local density configuration area is determined by the spatial boundary corresponding to each via configuration range.

[0016] Preferably, the candidate center positions of the electroplated copper-filled vias are arranged along the first and second spatial directions according to the corresponding center-to-center spacing parameters. The candidate center positions that meet the minimum center-to-center spacing condition are determined as effective via positions, and the initial number of electroplated copper-filled vias is determined according to the number of effective via positions. The allowable current carrying capacity of the solid copper pillars generated by the corresponding aperture parameters is summarized. When the total allowable current carrying capacity is less than the target current carrying capacity requirement, the current carrying capacity of the corresponding positions is changed by increasing the number of effective via positions, adjusting the center-to-center spacing level, and adjusting the aperture level. Finally, the aperture parameters, center-to-center spacing parameters, and number of vias corresponding to each position are output.

[0017] The technical effects and advantages provided by the present invention in the above technical solution are as follows: This invention collects voltage drop values ​​at multiple sampling locations of the power transistor under bolt-tightening conditions. It incorporates the actual current transmission state after bolt tightening into the parameter optimization process of the copper-filled via. By gradually determining the current injection region and local current density through the voltage drop gradient, it further identifies current concentration areas and their density distribution. This transforms the local current changes caused by the tightening action into current-carrying requirements that can be used for via parameter configuration. This reduces deviations caused by configuring parameters according to a preset uniform current distribution, lowers conduction losses and temperature rise risks caused by excessive current carried by local solid copper pillars, and improves the adaptability between the copper-filled via configuration and the actual tightening state of the power transistor.

[0018] This invention further converts the current density distribution corresponding to the current concentration area into the target current carrying capacity of solid copper pillars at different locations. The target current carrying capacity is used to determine the aperture difference, and the center-to-center spacing of adjacent solid copper pillars is adjusted within the spatial constraints corresponding to the aperture size. This results in a via array density distribution corresponding to local current carrying capacity requirements, and the number of electroplated copper-filled vias at each location is determined accordingly. This parameter transfer method can collaboratively incorporate the current carrying capacity of a single solid copper pillar with the number of vias within the area into the optimization process. It configures the corresponding current carrying capacity at locations with concentrated current demand and reduces unnecessary via configurations at other locations, thereby improving the current distribution within the via array, reducing the degree of local current concentration, and enhancing the current utilization efficiency and continuous operational reliability of the PCB pressure-bearing area. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0020] Figure 1 This is a flowchart of a method for optimizing the parameters of a copper-filled via for electroplating in the pressure-bearing area of ​​a high-power PCB bolt according to the present invention. Detailed Implementation

[0021] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art.

[0022] This invention provides, for example Figure 1 The method for optimizing the parameters of copper-plated vias in the bearing area of ​​high-power PCB bolts, as shown, includes the following steps: The voltage drop amplitude at multiple sampling locations is collected when the power transistor is pressed into the PCB pressure pad by the locking bolt. The voltage drop gradient between adjacent sampling locations is calculated. The PCB pressure pad is divided into regions according to the spatial distribution of the voltage drop gradient to determine each current injection region. The local current density is calculated using the voltage drop gradient corresponding to each current injection region, and the current concentration region is determined according to the distribution of local current density on the PCB pressure pad, and the current density distribution corresponding to the current concentration region is obtained. The target current carrying capacity of the solid copper pillars in the electroplated copper-filled vias at each location is determined according to the current density distribution corresponding to the current concentration area. The corresponding aperture difference is determined according to the target current carrying capacity of the solid copper pillars at different locations, so as to obtain the aperture parameters of the solid copper pillars that match the local current carrying capacity requirements. The center-to-center spacing between adjacent solid copper pillars is adjusted by referring to the difference in the aperture of the solid copper pillars at each position, and the local density of the electroplated copper-filled via array is configured according to the target current carrying capacity of the solid copper pillars at each position to determine the center-to-center spacing parameters corresponding to different positions. Based on the local density of the copper-filled via array and the center-to-center spacing parameters at different locations, the number of copper-filled vias at each location is determined. The via diameter, center-to-center spacing, and number of vias are output to match the current distribution under the locked state of the power transistor, thus completing the parameter optimization of the copper-filled vias in the bolt bearing area of ​​the high-power PCB.

[0023] This embodiment provides a parameter optimization method for electroplated copper-filled vias in the bolt bearing area of ​​a high-power PCB. After a power transistor is pressed onto the PCB bearing pad by locking bolts, the method differentiates the hole diameter, center-to-center spacing, and number of electroplated copper-filled vias within the bearing area based on the current transmission requirements of different positions on the PCB bearing pad under the actual locking state of the power transistor. The parameter optimization process uses the actual electrical state of the PCB bearing pad when the power transistor is in a predetermined locking state as the basis for parameter determination. This ensures that the final obtained electroplated copper-filled via parameters correspond to the current distribution generated after the power transistor is locked, reducing parameter configuration deviations caused by determining the electroplated copper-filled via parameters solely based on a preset current shunt state when the PCB is in an unpressurized state.

[0024] In the specific implementation process, the power transistor is positioned on the corresponding location of the PCB pressure pad according to its actual assembly location. The power transistor is then pressed onto the PCB pressure pad using locking bolts, and locked according to the predetermined assembly conditions of the power transistor. After locking, the locked state is maintained, and a predetermined test current is applied to the power transistor. The predetermined test current is determined according to the power transistor's design operating current or the operating current under the corresponding target operating condition, so that the subsequently collected voltage drop value can reflect the current transmission state of the PCB pressure pad under the actual locking condition of the power transistor.

[0025] Before collecting voltage drop values ​​at multiple sampling locations when the power transistor is pressed against the PCB pressure pad with locking bolts, the effective sampling range of the power transistor's terminal face corresponding to the PCB pressure pad must first be determined. The effective sampling range covers the area where current transfer occurs between the power transistor's terminal face and the PCB pressure pad, and extends to the corresponding current transfer range outside this area. This ensures that the changes in current entry and current diffusion locations after the locking bolts apply pressure are included within the effective sampling range.

[0026] Multiple sampling positions are set within the effective sampling range according to a preset sampling interval. These sampling positions are arranged continuously along a first spatial direction and a second spatial direction, intersecting each other. This divides the effective sampling range into multiple continuously distributed sampling units, each corresponding to at least one sampling position. The sampling interval is determined based on the center-to-center spacing range of the copper-filled vias to be optimized. The sampling interval is smaller than the allowable center-to-center spacing of the copper-filled vias to be optimized, ensuring that the local current-carrying range corresponding to a single copper-filled via has at least one sampling position. When a local current-carrying range contains multiple sampling positions, the electrical state corresponding to that local current-carrying range is determined using these multiple sampling positions.

[0027] Spatial adjacency is determined based on the positional relationship between each sampling unit. Two sampling positions with a continuous positional relationship along a first spatial direction are defined as adjacent sampling positions in the first direction, and two sampling positions with a continuous positional relationship along a second spatial direction are defined as adjacent sampling positions in the second direction. This establishes the spatial adjacency relationship between all sampling positions, ensuring that each subsequently determined pressure drop gradient corresponds to two sampling positions with a defined spatial distance and a defined spatial direction.

[0028] The voltage drop amplitude is acquired using a unified potential reference position. During implementation, the current output position corresponding to the PCB pressure pad is determined as the potential reference position. With the power transistor held in a locked state and the predetermined test current maintained, the potential difference between each sampling position and the potential reference position is acquired. The amplitude of the corresponding potential difference is used as the voltage drop amplitude at each sampling position. All sampling positions use the same potential reference position, ensuring that the voltage drop amplitudes at each sampling position are under a unified potential reference and allowing for continuous comparison based on spatial location.

[0029] After collecting the voltage drop amplitude at each sampling location, the voltage drop gradient between adjacent sampling locations is determined according to the established spatial adjacency relationship. For any two spatially adjacent sampling locations, the change in voltage drop amplitude between the two locations and the actual distance between them are obtained. The change in voltage drop amplitude per unit distance is determined as the voltage drop gradient between the two spatially adjacent sampling locations. Simultaneously, the spatial direction of the voltage drop gradient is determined according to the direction of potential decrease between the two sampling locations. Therefore, the voltage drop gradient simultaneously includes both the degree and direction of voltage drop change.

[0030] All adjacent sampling positions along the first spatial direction are processed sequentially, and all adjacent sampling positions along the second spatial direction are processed sequentially to obtain the voltage drop gradients corresponding to different positions within the effective sampling range. Each voltage drop gradient is associated with its corresponding spatial position and spatial direction. All voltage drop gradients are arranged according to their positional relationships on the PCB pressure pads to form the spatial distribution of the voltage drop gradients.

[0031] When dividing the PCB pressure pads into regions based on the spatial distribution of the voltage drop gradient, multiple continuous and non-overlapping voltage drop gradient intervals are established according to the total range of voltage drop gradient values. These intervals are arranged in ascending order of voltage drop gradient, with each interval corresponding to a gradient level. Each sampling location is assigned to the appropriate gradient level based on its corresponding voltage drop gradient. A unified gradient classification rule is used between the voltage drop gradient intervals, ensuring that all sampling locations in the same parameter optimization process are divided according to the same standard.

[0032] During the region partitioning process, sampling locations that are spatially continuous, have consistent gradient levels, and exhibit a continuous transmission relationship in the voltage drop gradient direction are grouped into the same current injection region. When two spatially adjacent sampling locations correspond to different gradient levels, the position between the two spatially adjacent sampling locations is taken as the boundary position between adjacent current injection regions; when two spatially adjacent sampling locations are at the same gradient level but their voltage drop gradient directions point to different current transmission ranges, the position where the corresponding directions are reversed is taken as the boundary position between adjacent current injection regions. All sampling locations within the effective sampling range are processed according to the above partitioning method to determine each current injection region.

[0033] The current injection region represents a spatial area with corresponding local current transmission characteristics, defined based on the voltage drop across the PCB pads when the power transistor is in the locked state. The current injection region does not directly equate a single sampling location with an independent contact position on the power transistor's terminal face; rather, it serves as a spatial unit distinguishing different local current transmission states of the PCB pads, enabling subsequent local current density, current concentration areas, target current carrying capacity, and copper-filled via parameters to establish a unified spatial relationship.

[0034] After determining each current injection region, the local current density is calculated using the voltage drop gradient corresponding to each region. Specifically, the rate of change of local potential at the corresponding location is determined based on the change in voltage drop amplitude between adjacent sampling locations and the corresponding sampling distance. Then, according to the conductivity of the PCB pressure pads under the current test conditions, the rate of change of local potential is converted into the local current density at the corresponding location. The direction of the local current density is determined according to the potential decrease direction corresponding to the voltage drop gradient, thus obtaining a local current density with spatial location, numerical value, and directional correspondence.

[0035] For a sampling location that simultaneously possesses a voltage drop gradient in both spatial directions, the local current density components corresponding to the first and second spatial directions are determined, respectively. The local current density and current transmission direction corresponding to this sampling location are then determined based on these two spatial current density components. After processing all sampling locations, the local current densities corresponding to each sampling location are arranged according to their spatial positions to obtain the spatial distribution of the local current density corresponding to the PCB pressure pads.

[0036] The local current density obtained here is first used to reflect the in-plane current transmission state within the PCB pressure pads, and is not directly used as the target current carrying capacity of the solid copper pillars within the plated copper-filled vias. Subsequently, the vertical current shunting requirement that needs to be transmitted through the solid copper pillars is determined by the current inflow and outflow corresponding to the current distribution range boundary, thereby completing the conversion from the in-plane current transmission state of the PCB pressure pads to the target current carrying capacity of the solid copper pillars.

[0037] When determining the current concentration area based on the distribution of local current density on the PCB pressure pads, first determine the current density boundary value. The current density boundary value is set according to the local current requirement allowed under the initial electroplated copper-filled via configuration. Specifically, the allowable current carrying capacity of the solid copper pillar corresponding to the initial via diameter parameters and the current carrying capacity distribution range of a single solid copper pillar corresponding to the initial center-to-center spacing parameters can be used to determine the current density allowed to be carried by the current carrying capacity distribution range, and this current density is used as the current density boundary value.

[0038] When the local current density at multiple consecutive sampling locations reaches the current density threshold, the area corresponding to these spatially consecutive sampling locations is defined as a current concentration region. When multiple spatial ranges reaching the current density threshold are separate from each other, they are each defined as a different current concentration region. Using this method, a correspondence is established between the current concentration region and the current-carrying capacity of the initial copper-filled via configuration, which is used to identify the local spatial range where the copper-filled via parameter configuration needs to be changed under power transistor locking conditions.

[0039] Once the current concentration region is determined, the corresponding current density distribution is obtained according to the spatial coordinates of each sampling location within the current concentration region. The current density distribution includes the local current density at each sampling location within the current concentration region, the direction of the local current density, the spatial adjacency relationship between sampling locations, and the variation relationship of the local current density along the first and second spatial directions. If multiple local current convergence points exist within a current concentration region, the current density distribution corresponding to each local current convergence point is retained, allowing for differentiated determination of the target current carrying capacity based on the actual spatial location.

[0040] After obtaining the current density distribution corresponding to the current concentration area, the target current carrying capacity of the solid copper pillars in the copper-filled vias at each location is determined according to the current density distribution corresponding to the current concentration area. To achieve the conversion between local current density and target current carrying capacity, multiple candidate center positions of solid copper pillars are determined within the range where copper-filled vias need to be configured on the PCB pressure pads, and a corresponding current carrying capacity distribution range is determined for each candidate center position of solid copper pillars.

[0041] The current-carrying distribution range is divided according to the spatial relationship between the candidate center positions of adjacent solid copper pillars. For two adjacent candidate center positions of solid copper pillars, the midpoint between the two candidate center positions is used as the boundary position between the corresponding current-carrying distribution ranges. The boundary positions between the current candidate center position of solid copper pillar and the adjacent candidate center positions are determined along the first spatial direction and the second spatial direction, respectively. The current-carrying distribution range corresponding to the current candidate center position of solid copper pillar is defined by multiple boundary positions. Using the above method, the area where electroplated copper-filled vias need to be configured is divided into multiple non-overlapping and continuously covering current-carrying distribution ranges.

[0042] For a solid copper pillar candidate center located at the edge of the PCB pressure pad, on the side where there is no adjacent solid copper pillar candidate center, the boundary of the effective configuration range corresponding to the PCB pressure pad is used as the current distribution range boundary, thereby ensuring that the current distribution range located at the edge also has a definite spatial boundary.

[0043] For any current-carrying distribution range, the current transmission state at the boundary is determined based on the local current density and current transmission direction corresponding to the sampling position near the boundary of the current-carrying distribution range. When the local current density direction points into the current-carrying distribution range, the corresponding current is determined as the current entering the current-carrying distribution range; when the local current density direction points out of the current-carrying distribution range, the corresponding current is determined as the current leaving the current-carrying distribution range along the plane of the PCB pressure pad.

[0044] Based on the local current density and effective transmission range of each boundary of the current distribution range, the current quantity corresponding to each boundary is determined. The current quantity entering the current distribution range through each boundary is summarized to determine the inflow current quantity of the current distribution range. The current quantity leaving the current distribution range through each boundary along the plane of the PCB pressure pad is summarized to determine the in-plane outflow current quantity of the current distribution range. The current requirement after deducting the in-plane outflow current quantity from the inflow current quantity is determined as the vertical shunt current requirement that needs to be transmitted into the PCB through the plated copper-filled vias in this current distribution range.

[0045] When a current-carrying allocation range corresponds to a candidate center position of a solid copper pillar, the corresponding vertical current-carrying demand is used as the target current-carrying capacity of that solid copper pillar. When multiple solid copper pillars need to be configured within a current-carrying allocation range, the vertical current-carrying demand corresponding to the current-carrying allocation range is allocated according to the current-carrying capacity of the multiple solid copper pillars, so that the sum of the target current-carrying capacities corresponding to the multiple solid copper pillars covers the vertical current-carrying demand corresponding to the current-carrying allocation range.

[0046] When the initial aperture is not yet determined, the vertical flow demand can be allocated according to the condition that each solid copper column adopts the same initial aperture level; after the aperture parameters of each solid copper column are determined, the target flow rate of each solid copper column is adjusted according to the allowable current carrying capacity corresponding to different aperture levels, so that the target flow rate is consistent with the current carrying correspondence between the actual aperture parameters of the corresponding solid copper column.

[0047] Therefore, the current density distribution corresponding to the current concentration area is first converted into the inflow current and outflow current in each current distribution range. Then, the vertical current shunting demand is determined by the current difference between the two. Finally, the vertical current shunting demand is allocated to the solid copper pillars at the corresponding positions, thereby determining the target current carrying capacity of each solid copper pillar and avoiding the direct use of the local current density in the PCB pressure pad as the vertical current carrying capacity of the solid copper pillar.

[0048] After determining the target current carrying capacity of each solid copper column, the corresponding aperture difference is determined according to the target current carrying capacity of the solid copper column at different locations. The aperture parameter is determined based on the current density that the solid copper column can withstand as the current carrying capacity constraint. For any solid copper column, the minimum effective conductive cross-sectional area required to withstand the target current carrying capacity is determined according to the target current carrying capacity and the preset allowable current density. Then, the aperture parameter that meets the minimum effective conductive cross-sectional area requirement is determined according to the correspondence between the effective conductive cross-sectional area of ​​the solid copper column and the aperture.

[0049] To facilitate the conversion of continuously varying target current carrying capacity into practically configurable via diameter parameters for electroplated copper-filled vias, multiple via diameter levels are pre-defined within the permissible via diameter range. These multiple via diameter levels include at least a first via diameter level, a second via diameter level, and a third via diameter level. These three via diameter levels are arranged in ascending order of via diameter and correspond to different effective conductive cross-sectional areas and permissible current carrying capacities, respectively.

[0050] The specific aperture parameters for the first, second, and third aperture orders are determined based on PCB manufacturing conditions, the allowable range of the electroplating copper filling process, and the current carrying capacity that the corresponding solid copper pillar needs to handle. Once each aperture order is determined, the corresponding relationship remains unchanged during the same parameter optimization process, ensuring that solid copper pillars in different positions can be configured according to a unified aperture order standard.

[0051] For any solid copper column, starting from the first aperture level, determine whether the corresponding allowable current carrying capacity can cover the target current carrying capacity of the solid copper column. If the allowable current carrying capacity corresponding to the first aperture level can cover the target current carrying capacity, the first aperture level is determined as the aperture parameter of the corresponding solid copper column; if the allowable current carrying capacity corresponding to the first aperture level cannot cover the target current carrying capacity, continue to select the second aperture level; if the allowable current carrying capacity corresponding to the second aperture level still cannot cover the target current carrying capacity, continue to select the third aperture level or subsequent aperture levels, until the allowable current carrying capacity corresponding to the selected aperture level can cover the target current carrying capacity.

[0052] Using the above method, the smallest aperture level that allows the current carrying capacity to cover the target current carrying capacity is selected from multiple aperture levels, so that a single solid copper column has an effective conductive cross-sectional area that meets the corresponding target current carrying capacity requirement, while avoiding the direct use of a large aperture level when the target current carrying capacity can be borne by a small aperture level.

[0053] When the target current carrying capacity at a certain location exceeds the allowable current carrying capacity corresponding to the maximum allowable aperture class, the aperture of a single solid copper pillar is not further increased. Instead, the vertical current shunting demand at that location is distributed to two or more solid copper pillars, and the portion exceeding the allowable current carrying capacity of a single solid copper pillar is handled by increasing the number of electroplated copper-filled vias at the corresponding location. Thus, the aperture parameters always remain within the allowable aperture class range.

[0054] Once the aperture parameters for two solid copper pillars at different locations are determined, the numerical difference between the two aperture parameters is used as the aperture difference between the corresponding solid copper pillars. The aperture difference is used to represent the difference in aperture configuration of solid copper pillars at different locations due to different target current carrying capacities, and serves as the basis for subsequent adjustments to the center-to-center distance between adjacent solid copper pillars.

[0055] When adjusting the center-to-center distance between adjacent solid copper columns by referring to the difference in aperture of the solid copper columns at various locations, the minimum allowable center-to-center distance between the two columns is first determined according to their actual aperture parameters. In practice, the minimum center-to-center distance is determined based on the space occupied by the corresponding apertures of the two solid copper columns and the preset minimum interval. When the aperture parameters of adjacent solid copper columns change, the minimum center-to-center distance changes synchronously with the actual apertures of the two solid copper columns; therefore, the aperture difference can reflect the change in the constraint conditions of the center-to-center distance between adjacent solid copper columns.

[0056] Based on meeting the minimum center-to-center spacing, the actual center-to-center spacing parameters are determined according to the target current carrying capacity of adjacent positions. To this end, multiple center-to-center spacing levels are pre-set within the permissible range, arranged in ascending order of center-to-center spacing. Each center-to-center spacing level corresponds to a density of electroplated copper-filled vias that can be arranged within a unit configuration range.

[0057] The specific center-pitch parameters corresponding to multiple center-pitch levels are jointly determined based on PCB manufacturing conditions, the allowable placement range of electroplated copper-filled vias, the minimum spacing required between adjacent solid copper pillars, and the effective configuration range of PCB pressure-bearing pads. Once each center-pitch level is determined, it is selected according to a unified standard during the same parameter optimization process.

[0058] For locations with high target current carrying capacity, select a smaller center spacing level from multiple center spacing levels that are not less than the corresponding minimum center spacing to increase the number of plated copper-filled vias that can be configured within a unit configuration range; for locations with low target current carrying capacity, select a larger center spacing level from the center spacing levels that meet the minimum center spacing requirements to reduce the number of plated copper-filled vias within a unit configuration range.

[0059] When two adjacent solid copper pillars correspond to different target current carrying capacities, the center-to-center spacing level corresponding to the target current carrying capacity that is larger is used as the initial center-to-center spacing parameter. Then, it is determined whether this initial center-to-center spacing parameter meets the minimum center-to-center spacing requirement corresponding to the actual aperture diameters of the two solid copper pillars. If the initial center-to-center spacing parameter is less than the minimum center-to-center spacing, the spacing is adjusted to the next center-to-center spacing level in ascending order until the selected center-to-center spacing parameter is not less than the minimum center-to-center spacing.

[0060] The aperture difference is used in this process to limit the spatial configuration constraints of adjacent solid copper pillars due to their different apertures, and the target current carrying capacity is used to determine the direction of the center-to-center spacing after satisfying the spatial configuration constraints. Therefore, the center-to-center spacing is not determined solely by the aperture difference or solely by the target current carrying capacity, but rather by selecting the actual center-to-center spacing parameter according to the local current carrying capacity requirements within the spatial constraint range corresponding to the aperture difference.

[0061] Subsequently, the local density of the copper-filled via array is configured according to the target current carrying capacity of the solid copper pillars at each location. In this embodiment, the local density is defined as the spatial configuration state corresponding to the number of copper-filled vias per unit configuration area and the center-to-center distance between adjacent solid copper pillars. When the number of copper-filled vias per unit configuration area increases and the center-to-center distance decreases, it corresponds to a dense configuration; when the number of copper-filled vias per unit configuration area decreases and the center-to-center distance increases, it corresponds to a sparse configuration.

[0062] For continuous locations with high target current carrying capacity within a concentrated current area, a smaller center-to-center spacing level is selected while still meeting the corresponding minimum center-to-center spacing requirement, allowing for more plated copper-filled vias to be arranged within a unit configuration area. Conversely, for continuous locations with low target current carrying capacity, a larger center-to-center spacing level is selected, reducing the number of plated copper-filled vias arranged within a unit configuration area. Through this method, the local density of the plated copper-filled via array is spatially varied according to the actual current carrying capacity requirements of different locations on the PCB pressure pads.

[0063] When the target current carrying capacity within the same current concentration region changes continuously along the first or second spatial direction, adjacent solid copper pillars are sequentially configured according to the center-to-center spacing level corresponding to the target current carrying capacity at each location. This ensures that the electroplated copper-filled via array has corresponding local density at different locations. When different center-to-center spacing levels are used at adjacent locations, the location where the target current carrying capacity range changes is used as the center-to-center spacing parameter switching location. At the same time, it is ensured that the actual center-to-center distance between the two closest solid copper pillars on both sides of the parameter switching location is not less than their corresponding minimum center-to-center spacing.

[0064] When determining the number of electroplated copper-filled vias at each location based on the local density of the copper-filled via array and the center-to-center spacing parameters at different positions, multiple via configuration ranges are first determined according to the spatial distribution of the current concentration area and the target current carrying capacity. A continuous spatial range with the same aperture class and the same center-to-center spacing class within a current concentration area is determined as a via configuration range; when the aperture class or center-to-center spacing class changes, the location of the corresponding parameter change is used as the boundary between adjacent via configuration ranges.

[0065] Each via configuration range corresponds to a defined spatial boundary, target current carrying capacity, via diameter parameters, center-to-center spacing parameters, and local density. Candidate center positions for electroplated copper-filled vias are sequentially set along the first spatial direction according to the center-to-center spacing parameters corresponding to the current via configuration range. Then, candidate center positions are arranged along the second spatial direction according to the corresponding center-to-center spacing parameters. Candidate center positions located within the via configuration range boundary and meeting the minimum center-to-center spacing requirement for adjacent solid copper pillars are determined as valid via positions.

[0066] The number of all valid via locations within a given via configuration range is counted, and this number is taken as the initial number of copper-filled vias for that configuration range. Then, the effective conductive cross-sectional area of ​​a single solid copper pillar is determined based on the via diameter level corresponding to that configuration range, and the allowable current carrying capacity of a single solid copper pillar is determined based on the effective conductive cross-sectional area and a preset allowable current density. The allowable current carrying capacity corresponding to all solid copper pillars within the via configuration range is summed to obtain the total allowable current carrying capacity that can be handled according to the initial number of copper-filled vias.

[0067] When the sum of the allowable current carrying capacity of all solid copper pillars configured according to the initial number of plated copper-filled vias is less than the target current carrying capacity corresponding to the via configuration range, new effective via locations that meet the minimum center-to-center spacing requirements are determined within the via configuration range, with priority given to adding plated copper-filled vias at locations with high local current density values. For each additional plated copper-filled via, the allowable current carrying capacity corresponding to the newly added solid copper pillar is added to the total allowable current carrying capacity, until the sum of the allowable current carrying capacity of all solid copper pillars can cover the target current carrying capacity corresponding to the via configuration range.

[0068] If there are no new valid via locations within the current via configuration range that meet the existing center-to-center spacing requirements, and the sum of the allowable current carrying capacity of all solid copper pillars still cannot cover the target current carrying capacity, the center-to-center spacing parameters are adjusted to the next permissible center-to-center spacing level, and the valid via locations and the initial number of plated copper-filled vias are re-determined. After adjusting the center-to-center spacing parameters, it is re-evaluated whether the sum of the allowable current carrying capacity of all solid copper pillars can cover the corresponding target current carrying capacity.

[0069] If the current center spacing has already adopted the minimum center spacing level that meets the minimum center spacing requirement, and it is still not possible to cover the target current carrying capacity by increasing the number of electroplated copper-filled vias, then the aperture parameters of the corresponding solid copper pillars will be adjusted to the next aperture level. Based on the adjusted aperture level, the effective conductive cross-sectional area and allowable current carrying capacity of a single solid copper pillar will be re-determined, and then the number of electroplated copper-filled vias required for this via configuration range will be re-determined.

[0070] After the aperture level is adjusted, the minimum center-to-center distance between adjacent solid copper pillars changes synchronously. Therefore, the minimum center-to-center distance is determined again based on the adjusted actual aperture parameters, and the actual center-to-center distance is reselected from multiple center-to-center distance levels that meet this minimum center-to-center distance. This establishes a linkage configuration relationship between aperture parameters, center-to-center distance parameters, and the number of vias.

[0071] When the sum of the allowable current carrying capacity of all solid copper pillars configured according to the initial number of electroplated copper-filled vias can cover the target current carrying capacity of the corresponding via configuration range, the electroplated copper-filled vias within the current via configuration range are sorted by position according to local current density, and it is determined from the position with the smaller local current density value whether the corresponding electroplated copper-filled vias can be reduced.

[0072] After each copper-filled via is removed, the sum of the allowable current carrying capacity of all remaining solid copper pillars is recalculated. If the sum of the allowable current carrying capacity of all remaining solid copper pillars still covers the target current carrying capacity for that via configuration range, the process continues to the next position. If removing any copper-filled via would cause the sum of the allowable current carrying capacity of all remaining solid copper pillars to fall short of the target current carrying capacity, the removal process stops, and the current number of retained copper-filled vias is determined as the final number of vias corresponding to that via configuration range.

[0073] Through the above processing, each via configuration range ensures that the sum of the allowable current carrying capacity of all solid copper pillars can cover the corresponding target current carrying capacity, while guaranteeing that the actual center distance between any two adjacent solid copper pillars is not less than the minimum center spacing determined by the corresponding via diameter parameters. This ensures that the via diameter parameters, center spacing parameters, and number of vias collectively correspond to the actual current carrying capacity requirements at different locations on the PCB pressure pads.

[0074] When two adjacent via configuration ranges have different local density levels, electroplated copper-filled vias are set on both sides of the common boundary of the two via configuration ranges according to their respective aperture levels and center-to-center spacing levels. The actual center-to-center distance between the two closest solid copper pillars on both sides of the common boundary is determined. When this actual center-to-center distance is less than the minimum center-to-center spacing corresponding to the two solid copper pillars, the position of the electroplated copper-filled via corresponding to the side with the lower local current density is adjusted first, so that the solid copper pillars on both sides of the common boundary meet the corresponding spatial configuration requirements.

[0075] After determining the parameters for the entire via configuration range, record the center position of each plated copper-filled via according to the unified position reference of the PCB pressure pad, and establish a one-to-one correspondence between each center position and the corresponding solid copper pillar hole diameter parameter. For each plated copper-filled via, record the center-to-center distance parameters between it and adjacent plated copper-filled vias in the first and second spatial directions, and count the number of plated copper-filled vias included in each via configuration range.

[0076] The final output includes the diameter parameters, center-to-center spacing parameters, and number of vias for each location. It also retains the correspondence between the diameter parameters, center-to-center spacing parameters, and number of vias and the spatial position of the PCB pressure pads. This outputs the diameter parameters, center-to-center spacing parameters, and number of vias that are adapted to the current distribution under the power transistor locking state, thus completing the parameter optimization of the copper-plated vias in the bolt pressure area of ​​the high-power PCB.

[0077] In a further embodiment, within the permissible range of via diameters for copper plating, a first, second, and third aperture order are established, wherein the first aperture order is smaller than the second aperture order, and the second aperture order is smaller than the third aperture order. Each aperture order corresponds to a different effective conductive cross-sectional area and permissible current carrying capacity. The specific values ​​of the first, second, and third aperture orders are determined according to the permissible range of the actual copper plating process and the target current carrying capacity requirements.

[0078] For any solid copper column, firstly, determine whether the allowable current carrying capacity corresponding to the first aperture class can cover the target current carrying capacity of the solid copper column. If it can, the first aperture class is used; if not, further determine the allowable current carrying capacity corresponding to the second aperture class. If the second aperture class can cover the target current carrying capacity, the second aperture class is used; if the second aperture class still cannot cover the target current carrying capacity, the third aperture class is used. Through this step-by-step selection method, the allowable current carrying capacity corresponding to the finally used aperture class can cover the target current carrying capacity.

[0079] When the third aperture level still cannot handle the full vertical current shunting demand at the corresponding location, the vertical current shunting demand is distributed to multiple solid copper pillars, and the corresponding current is handled by increasing the number of electroplated copper-filled vias, without further increasing the aperture of a single solid copper pillar. This allows for current-carrying configurations at different locations within the permissible aperture range.

[0080] For the corresponding center-to-center spacing parameters, within the allowable center-to-center spacing range, a first center-to-center spacing level, a second center-to-center spacing level, a third center-to-center spacing level, and subsequent center-to-center spacing levels are set, arranged in ascending order of center-to-center spacing. The specific center-to-center spacing parameters are determined jointly based on PCB manufacturing conditions, the actual hole diameter of adjacent solid copper pillars, the preset minimum interval, and the target current carrying capacity at the corresponding location.

[0081] For any two adjacent solid copper pillars, the minimum center-to-center distance is first determined based on their actual aperture parameters, and then center-to-center distance levels smaller than this minimum are excluded. For the remaining center-to-center distance levels, the actual center-to-center distance is determined based on the target current carrying capacity of the adjacent positions. Positions with higher target current carrying capacity are preferentially assigned to center-to-center distance levels with smaller values, while positions with lower target current carrying capacity are assigned to center-to-center distance levels with larger values, thereby adjusting the density of the solid copper pillar array according to the local current carrying capacity.

[0082] In this implementation, the first, second, and third aperture levels are used to convert different target current carrying capacities into different solid copper pillar aperture parameters. Multiple center-spacing levels are used to further modify the spatial distribution density of the electroplated copper-filled vias while satisfying the spatial constraints corresponding to the apertures. Finally, the number of electroplated copper-filled vias is determined according to the spatial boundaries, center-spacing parameters, aperture parameters, and target current carrying requirements of each via configuration range, thereby obtaining a differentiated electroplated copper-filled via configuration result corresponding to the local current distribution under the power transistor's locked state.

[0083] Using the above specific implementation method, a continuous technical parameter transfer relationship is established throughout the parameter optimization process. The voltage drop amplitude at multiple sampling positions under the power transistor lock-in state is used to determine the voltage drop gradient between adjacent sampling positions. The spatial distribution of the voltage drop gradient is used to divide each current injection region. The voltage drop gradient corresponding to each current injection region is used to calculate the local current density. The distribution of the local current density on the PCB pressure pads is used to determine the current concentration region and obtain the current density distribution corresponding to the current concentration region.

[0084] The current density distribution corresponding to the current concentration area determines the vertical current shunting requirement by the inflow current at the boundary of the current distribution range and the in-plane outflow current. The vertical current shunting requirement is further used to determine the target current carrying capacity of the solid copper pillars in the electroplated copper-filled vias at each location. The target current carrying capacity is mapped to the aperture level by the allowable current density and effective conductive cross-sectional area. The aperture parameters corresponding to the aperture levels at different locations further determine the aperture difference between the solid copper pillars.

[0085] The actual aperture variation corresponding to the aperture difference is used to define the minimum permissible center-to-center spacing between adjacent solid copper pillars. The target current carrying capacity is further used to determine the actual center-to-center spacing parameters from multiple center-to-center spacing levels that meet the minimum center-to-center spacing requirement. The center-to-center spacing parameters corresponding to each location further change the number of plated copper-filled vias within a unit configuration range, thereby changing the density of the solid copper pillar array according to the local current carrying capacity.

[0086] Based on the local density of the copper-filled via array and the center-to-center spacing parameters at different locations, the number of copper-filled vias at each location is determined by combining the target current-carrying requirements corresponding to each via configuration range. The retention status of the via number is then determined by whether the sum of the allowable current-carrying capacity of all solid copper pillars can cover the corresponding target current-carrying requirements. This outputs copper-filled via diameter parameters, center-to-center spacing parameters, and the number of vias that are compatible with the current distribution under the power transistor's locked state.

[0087] Through the above parameter optimization method, after the power transistor is pressed onto the PCB pressure pad by the locking bolt, the changes in the current entry location and current transmission range caused by the clamping action can be reflected by the voltage drop amplitude and voltage drop gradient at multiple sampling locations. This is further converted into local current density, current concentration area, vertical shunt demand, and target current carrying capacity of the solid copper pillar at different locations. The target current carrying capacity at different locations is then assigned to the solid copper pillar aperture parameters, the center-to-center distance parameters of adjacent solid copper pillars, and the number of electroplated copper-filled vias at the corresponding locations, so that the current carrying capacity of the electroplated copper-filled vias at different locations corresponds to the local current carrying capacity generated under the power transistor's clamping state.

[0088] Compared to the method of configuring parameters based on a pre-set current distribution in the unpressurized state of the PCB using uniform aperture, uniform center spacing, and uniform array quantity, this embodiment incorporates the actual current transmission state of the power transistor after being pressed by locking bolts into the process of determining the parameters of the electroplated copper-filled vias. By continuously transferring parameters such as voltage drop amplitude, voltage drop gradient, current injection area, local current density, current concentration area, target current carrying capacity, aperture difference, center spacing parameter, local density, and number of electroplated copper-filled vias, differentiated parameter configurations are implemented for different positions of the PCB pressure pads. This reduces the deviation between the actual current carried by the solid copper pillar and the preset current carrying capacity, reduces the possibility of local conduction loss and abnormal temperature rise, and improves the compatibility between the electroplated copper-filled via parameters in the bolt pressure area of ​​high-power PCBs and the actual locking working state of the power transistor.

[0089] This invention collects voltage drop values ​​at multiple sampling locations of the power transistor under bolt-tightening conditions. It incorporates the actual current transmission state after bolt tightening into the parameter optimization process of the copper-filled via. By gradually determining the current injection region and local current density through the voltage drop gradient, it further identifies current concentration areas and their density distribution. This transforms the local current changes caused by the tightening action into current-carrying requirements that can be used for via parameter configuration. This reduces deviations caused by configuring parameters according to a preset uniform current distribution, lowers conduction losses and temperature rise risks caused by excessive current carried by local solid copper pillars, and improves the adaptability between the copper-filled via configuration and the actual tightening state of the power transistor.

[0090] This invention further converts the current density distribution corresponding to the current concentration area into the target current carrying capacity of solid copper pillars at different locations. The target current carrying capacity is used to determine the aperture difference, and the center-to-center spacing of adjacent solid copper pillars is adjusted within the spatial constraints corresponding to the aperture size. This results in a via array density distribution corresponding to local current carrying capacity requirements, and the number of electroplated copper-filled vias at each location is determined accordingly. This parameter transfer method can collaboratively incorporate the current carrying capacity of a single solid copper pillar with the number of vias within the area into the optimization process. It configures the corresponding current carrying capacity at locations with concentrated current demand and reduces unnecessary via configurations at other locations, thereby improving the current distribution within the via array, reducing the degree of local current concentration, and enhancing the current utilization efficiency and continuous operational reliability of the PCB pressure-bearing area.

[0091] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for optimizing parameters of copper-plated vias in the bearing area of ​​high-power PCB bolts, characterized in that, Includes the following steps: The voltage drop amplitude at multiple sampling locations is collected when the power transistor is pressed into the PCB pressure pad by the locking bolt. The voltage drop gradient between adjacent sampling locations is calculated. The PCB pressure pad is divided into regions according to the spatial distribution of the voltage drop gradient to determine each current injection region. The local current density is calculated using the voltage drop gradient corresponding to each current injection region, and the current concentration region is determined according to the distribution of local current density on the PCB pressure pad, and the current density distribution corresponding to the current concentration region is obtained. The target current carrying capacity of the solid copper pillars in the electroplated copper-filled vias at each location is determined according to the current density distribution corresponding to the current concentration area. The corresponding aperture difference is determined according to the target current carrying capacity of the solid copper pillars at different locations, so as to obtain the aperture parameters of the solid copper pillars that match the local current carrying capacity requirements. The center-to-center spacing between adjacent solid copper pillars is adjusted by referring to the difference in the aperture of the solid copper pillars at each position, and the local density of the electroplated copper-filled via array is configured according to the target current carrying capacity of the solid copper pillars at each position to determine the center-to-center spacing parameters corresponding to different positions. The number of electroplated copper-filled vias at each position is determined based on the local density of the electroplated copper-filled via array and the center-to-center spacing parameters corresponding to different positions. The output is adapted to the current distribution of the electroplated copper-filled vias under the locked state, including via diameter parameters, center-to-center spacing parameters, and number of vias.

2. The parameter optimization method for copper-plated vias in the bearing area of ​​high-power PCB bolts according to claim 1, characterized in that, Multiple sampling positions are continuously arranged along intersecting first and second spatial directions. Two sampling positions with continuous positional relationships are defined as spatially adjacent sampling positions. The current output position corresponding to the PCB pressure pad is selected as a unified potential reference position. The voltage drop amplitude between each sampling position and the unified potential reference position is collected. The voltage drop gradient is determined based on the change in the voltage drop amplitude corresponding to the spatially adjacent sampling positions and the actual distance between them. The spatial direction of the voltage drop gradient is determined according to the potential drop direction between two sampling positions, thus obtaining the spatial distribution of the voltage drop gradient.

3. The parameter optimization method for copper-plated vias in the bearing area of ​​high-power PCB bolts according to claim 2, characterized in that, The spatial distribution of the voltage drop gradient is divided into multiple continuous and non-overlapping voltage drop gradient intervals according to the value range corresponding to all voltage drop gradients. Each voltage drop gradient interval corresponds to a gradient level. Sampling positions that are spatially continuous, have the same gradient level, and have a continuous transmission relationship in the voltage drop gradient direction are grouped into the same current injection region. When spatially adjacent sampling positions correspond to different gradient levels, the region boundary is determined by the position between the two. When the gradient levels are the same but the voltage drop gradient directions point to different current transmission ranges, the region boundary is determined by the direction reversal position, thereby obtaining the spatial boundary corresponding to each current injection region.

4. The parameter optimization method for copper-plated vias in the bearing area of ​​high-power PCB bolts according to claim 3, characterized in that, The voltage drop gradient corresponding to each current injection region is used to determine the local potential change rate, and combined with the conductivity corresponding to the PCB pressure pad, the local current density at each sampling position is determined. The sampling positions with the first spatial voltage drop gradient and the second spatial voltage drop gradient respectively obtain the local current density components in the first spatial direction and the local current density components in the second spatial direction. The local current density and current transmission direction of the corresponding sampling position are determined by the local current density components in the two directions. The local current densities corresponding to each sampling position are arranged according to the spatial position to obtain the spatial distribution of the local current density of the PCB pressure pad.

5. The parameter optimization method for copper-plated vias in the bearing area of ​​high-power PCB bolts according to claim 4, characterized in that, The current density boundary value in the spatial distribution of local current density is jointly determined by the allowable current carrying capacity of the solid copper column corresponding to the initial aperture parameter and the current carrying capacity distribution range of a single solid copper column corresponding to the initial center spacing parameter. The range corresponding to the sampling position where the local current density reaches the current density boundary value and is spatially continuous is determined as the current concentration region. The continuous ranges that are separated from each other are determined as different current concentration regions. Each current concentration region retains the local current density, local current density direction, spatial adjacency relationship, and current density change relationship corresponding to the two spatial directions corresponding to the sampling position, thus obtaining the corresponding current density distribution.

6. The parameter optimization method for copper-plated vias in the bearing area of ​​high-power PCB bolts according to claim 5, characterized in that, The current density distribution corresponding to the current concentration area is divided into multiple current distribution ranges according to the candidate center position of the solid copper pillar. The midpoint between adjacent candidate center positions is used as the boundary position of the current distribution range. Based on the local current density, effective transmission range and current transmission direction corresponding to the boundary of each current distribution range, the inflow current entering the current distribution range and the in-plane outflow current leaving the current distribution range along the plane direction of the PCB pressure pad are determined respectively. The current demand obtained by subtracting the in-plane outflow current from the inflow current is used as the vertical shunt demand, and the vertical shunt demand is allocated to the corresponding solid copper pillar to determine the target current carrying capacity.

7. The parameter optimization method for copper-plated vias in the bearing area of ​​high-power PCB bolts according to claim 6, characterized in that, The target current carrying capacity of the solid copper column and the preset allowable current density jointly determine the minimum effective conductive cross-sectional area required to bear the target current carrying capacity. According to the correspondence between the effective conductive cross-sectional area of ​​the solid copper column and the aperture, the smallest aperture level whose allowable current carrying capacity can cover the target current carrying capacity is selected from the first aperture level, the second aperture level, the third aperture level and subsequent aperture levels arranged in sequence as the aperture parameter of the solid copper column at the corresponding position. When the target current carrying capacity exceeds the allowable current carrying capacity corresponding to the largest aperture level, the corresponding vertical current shunting demand is configured to two or more solid copper columns, and the current demand exceeding the allowable current carrying capacity of a single solid copper column is borne by the number of vias.

8. The parameter optimization method for copper-plated vias in the bearing area of ​​high-power PCB bolts according to claim 7, characterized in that, The numerical difference between the corresponding aperture parameters of solid copper pillars at different positions is determined as the aperture difference. The minimum allowable center spacing is determined based on the actual aperture parameters of two adjacent solid copper pillars and the preset minimum interval. Multiple center spacing levels are arranged in ascending order of center spacing. First, center spacing levels smaller than the minimum center spacing are excluded. Then, the actual center spacing parameters are selected from the remaining center spacing levels according to the target current carrying capacity corresponding to the adjacent positions. When two adjacent solid copper pillars correspond to different target current carrying capacities, the center spacing level corresponding to the target current carrying capacity with the larger current carrying capacity is used as the initial selection, and the center spacing level is adjusted according to the minimum center spacing.

9. The parameter optimization method for copper-plated vias in the bearing area of ​​high-power PCB bolts according to claim 1, characterized in that, The local density of the electroplated copper-filled via array is determined by the number of electroplated copper-filled vias per unit configuration range and the center-to-center distance between adjacent solid copper pillars. For continuous locations with high target current carrying capacity, a center-to-center distance level with a small value that meets the minimum center-to-center distance condition is selected, while for continuous locations with low target current carrying capacity, a center-to-center distance level with a large value is selected. A continuous spatial range with the same aperture level and the same center-to-center distance level in the same current concentration region is defined as a via configuration range. The location where the aperture level or center-to-center distance level changes is used as the boundary between adjacent via configuration ranges. The local density configuration area is determined by the spatial boundary corresponding to each via configuration range.

10. The parameter optimization method for copper-plated vias in the bearing area of ​​high-power PCB bolts according to claim 9, characterized in that, Each via configuration range arranges the candidate center positions of the electroplated copper-filled vias along the first and second spatial directions according to the corresponding center-to-center spacing parameters. The candidate center positions that meet the minimum center-to-center spacing condition are determined as effective via positions, and the initial number of electroplated copper-filled vias is determined based on the number of effective via positions. The allowable current carrying capacity of the solid copper pillars generated by the corresponding aperture parameters is summarized. When the total allowable current carrying capacity is less than the target current carrying capacity requirement, the current carrying capacity of the corresponding positions is changed by increasing the number of effective via positions, adjusting the center-to-center spacing level, and adjusting the aperture level. Finally, the aperture parameters, center-to-center spacing parameters, and number of vias corresponding to each position are output.

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