Printed circuit board and method of manufacturing the same

Abstract

The application relates to the technical field of printed wiring boards, and discloses a printed wiring board and a manufacturing method thereof. The manufacturing method of the printed wiring board comprises the following steps: providing a laminated board, the laminated board comprising a buried embedding layer, a dielectric layer and a target layer, the dielectric layer being located between the buried embedding layer and the target layer, the buried embedding layer comprising a sub-board and a ceramic piece, the ceramic piece being provided with a first circuit layer on a side away from the dielectric layer, and the target layer being provided with a target circuit layer on a side facing the dielectric layer; using a laser to process a connecting hole on the laminated board from a side of the first circuit layer away from the dielectric layer, the connecting hole penetrating through the first circuit layer, the ceramic piece and the dielectric layer; and arranging a conductive layer on an inner hole wall of the connecting hole, the first circuit layer and the target circuit layer being connected with the conductive layer and electrically connected. The printed wiring board and the manufacturing method thereof are used to solve the problem that the existing manufacturing method of the printed wiring board has a high requirement on the alignment degree of mechanical drilling.

Description

Technical Field

[0001] This application relates to the field of printed circuit board technology, and more particularly to a printed circuit board and a method for manufacturing the same. Background Technology

[0002] In the current field of high-density, high-reliability electronic packaging, especially for advanced packaging platforms such as CoWop (Chip-on-Wafer-on-Package), one of the core challenges lies in dealing with the thermomechanical stress caused by the mismatch of thermal expansion coefficients between different materials. This stress can lead to package structure warping, microbumps, or interconnect fatigue failure, severely affecting the long-term reliability of high-performance chips. Against this backdrop, the core value of embedded ceramic regions becomes apparent: ceramic materials (silicon nitride) have a low CTE (Coefficient of Thermal Expansion) similar to that of silicon chips. By embedding them as functional blocks or local reinforcements in organic substrates or redistribution layers, the overall CTE of the package can be effectively adjusted and reduced.

[0003] Currently, in embedded ceramic solutions, if conductivity is to be achieved in the area where the embedded ceramic component is located, it can only be achieved by pre-drilling holes in the ceramic component and pressing the ceramic component into the sub-plate. Subsequent mechanical drilling needs to be performed in the pre-drilled area. This solution has high requirements for the alignment of the mechanical drilling and the alignment between the ceramic component and the sub-plate. If the alignment is off, the drill bit will break during mechanical drilling. Therefore, this solution needs improvement. Summary of the Invention

[0004] This application provides a printed circuit board and a method for manufacturing the same, which solves the problem of high alignment accuracy of mechanical drilling in existing printed circuit board manufacturing methods.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a printed circuit board, comprising: A laminating plate is provided, the laminating plate including an embedded layer, a dielectric layer and a target layer stacked together, the dielectric layer being located between the embedded layer and the target layer, the embedded layer including a sub-board and a ceramic component disposed within the sub-board, a first circuit layer being disposed on the side of the ceramic component facing away from the dielectric layer, and a target circuit layer being disposed on the side of the target layer facing the dielectric layer; A connection hole is machined on the lamination plate from the side of the first circuit layer away from the dielectric layer using a laser. The connection hole penetrates the first circuit layer, the ceramic component, and the dielectric layer. The target circuit layer defines a portion of the inner wall of the connection hole. A conductive layer is provided on the inner wall of the connection hole, and both the first circuit layer and the target circuit layer are connected to the conductive layer and are electrically conductive.

[0006] In some embodiments, the step of using a laser to process a connection hole on the lamination plate from the side of the first circuit layer opposite to the dielectric layer specifically includes: A first hole is machined on the lamination plate from the side of the first circuit layer away from the dielectric layer using an ultraviolet laser. The first hole penetrates the first circuit layer and the ceramic component, and the dielectric layer defines the bottom wall of the first hole. A second hole is machined from the bottom of the first hole onto the lamination plate using a carbon dioxide laser. The second hole penetrates the dielectric layer, and the target circuit layer defines the bottom wall of the second hole. The first hole and the second hole form the connection hole.

[0007] In some embodiments, a second circuit layer is provided on the side of the ceramic component facing the dielectric layer, the second circuit layer including a protective pad; the first hole penetrates the protective pad, the absorption rate of the ceramic component to the ultraviolet laser is less than or equal to the absorption rate of the protective pad to the ultraviolet laser, and the absorption rate of the protective pad to the ultraviolet laser is less than the absorption rate of the dielectric layer to the ultraviolet laser.

[0008] In some embodiments, a protective layer is provided on the side of the protective pad facing away from the ceramic part, the protective layer having a lower absorption rate of the ultraviolet laser than the protective pad has, and the first hole penetrates the protective layer.

[0009] In some embodiments, the protective pads are made of copper, and the protective layer is made of at least one of gold, palladium, and tin.

[0010] In some embodiments, the diameter of the first hole at the protective pad is equal to the diameter of the protective pad; the second circuit layer includes connecting lines that are spaced apart from the protective pad.

[0011] In some embodiments, the second circuit layer includes a connection bit located between the connection line and the protective pad, and both the connection line and the protective pad are connected to and electrically conductive to the connection bit; the connection bit is connected to and electrically conductive to the conductive layer.

[0012] In some embodiments, the method of fabricating the printed circuit board prior to providing the laminating plate includes: The target layer, adhesive layer, and sub-board are stacked together. The target layer is provided with a first positioning hole and a second positioning hole. A first positioning element is inserted into the first positioning hole, and a second positioning element is inserted into the second positioning hole. The sub-board is provided with a first mating hole, and the first positioning element passes through the first mating hole. The sub-board is provided with an embedding groove, and the ceramic part is provided inside the embedding groove. The ceramic part is provided with a second mating hole, and the second positioning element passes through the second mating hole. The target layer, the adhesive layer, and the sub-plate are pressed together, with a portion of the adhesive layer filling the gap between the inner wall of the embedded groove and the ceramic part, and a portion of the adhesive layer forming the dielectric layer.

[0013] Secondly, embodiments of this application provide a printed circuit board, the printed circuit board including a laminating plate, the laminating plate including a buried layer, a dielectric layer and a target layer stacked together, the dielectric layer being located between the buried layer and the target layer, the buried layer including a sub-board and a ceramic component disposed within the sub-board, a first circuit layer being disposed on the side of the ceramic component facing away from the dielectric layer, and a target circuit layer being disposed on the side of the target layer facing the dielectric layer; a connecting hole is provided on the laminating plate, the connecting hole penetrating the first circuit layer, the ceramic component and the dielectric layer, the target circuit layer defining a portion of the inner wall of the connecting hole, a conductive layer being disposed on the inner wall of the connecting hole, and both the first circuit layer and the target circuit layer being connected to and electrically conductive to the conductive layer.

[0014] Thirdly, embodiments of this application provide a printed circuit board, which is manufactured by the printed circuit board manufacturing method described in the first aspect.

[0015] The printed circuit board manufacturing method provided in this application has the following advantages: Since the lamination board includes a stacked embedded layer, a dielectric layer and a target layer, with the dielectric layer located between the embedded layer and the target layer, the embedded layer includes a sub-board and a ceramic component disposed within the sub-board. A first circuit layer is disposed on the side of the ceramic component away from the dielectric layer, and a target circuit layer is disposed on the side of the target layer facing the dielectric layer. A connecting hole is machined on the lamination board using a laser from the side of the first circuit layer away from the dielectric layer. The connecting hole penetrates the first circuit layer, the ceramic component and the dielectric layer, and the target circuit layer defines part of the inner wall of the connecting hole. Therefore, it is not necessary to set a pre-drilled area on the ceramic component, so there is no need to consider the alignment of the mechanical drilling. Furthermore, after a conductive layer is disposed on the inner wall of the connecting hole, both the first circuit layer and the target circuit layer can be connected to the conductive layer and electrically conductive.

[0016] The advantages of the printed circuit board provided in this application compared to the prior art can be seen in the description of the advantages of the manufacturing method of the printed circuit board provided in this application compared to the prior art, which will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a method for manufacturing a printed circuit board in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of the pressing plate in one embodiment of this application; Figure 3 yes Figure 2 A partial structural schematic diagram of the press plate is shown; Figure 4 yes Figure 3 Top view of the second circuit layer on the laminate shown; Figure 5 It uses ultraviolet lasers. Figure 3 The diagram shows a first hole being machined on the side of the first circuit layer away from the dielectric layer on a laminating plate. Figure 6 It uses a carbon dioxide laser. Figure 5 The diagram shows the bottom of the first hole being machined into the second hole on the pressing plate; Figure 7 Is Figure 6 A schematic diagram of the structure of the pressure plate after the inner wall of the connecting hole is provided with a conductive layer. Figure 8 yes Figure 2 The diagram shows the structure of the embedded layer in the laminated plate. Figure 9 yes Figure 2 The diagram shows the structural schematic of the target layer in the lamination plate. Figure 10 yes Figure 9 The diagram shows a partial structural representation of the target layer. Figure 11 yes Figure 2 A schematic diagram of the first clearance hole of the medium layer in the press plate and the first mating hole of the sub-plate; Figure 12 This is a top view of the second circuit layer in another embodiment of this application; Figure 13This is a partial structural schematic diagram of the pressing plate in another embodiment of this application; Figure 14 yes Figure 13 A top view of the second circuit layer on the laminated plate shown.

[0019] The markings in the diagram mean: 100. Pressed plate; 10. Embedded layer; 11. Sub-board; 111. Embedded groove; 112. First mating hole; 12. Ceramic component; 121. First circuit layer; 122. Second circuit layer; 1221. Protective pad; 1222. Connecting line; 1223. Connecting position; 13. Protective layer; 20. Dielectric layer; 21. First clearance hole; 30. Target layer; 31. Target circuit layer; 32. First positioning hole; 33. Second positioning hole; 40. First hole; 50. Second hole; 60. Conductive layer; 70. First positioning component; 80. Second positioning component. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0023] In this specification, references to "one embodiment," "some embodiments," or "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0024] To illustrate the technical solution of this application, the following description is provided in conjunction with specific accompanying drawings and embodiments.

[0025] Please refer to Figures 1 to 7 In a first aspect, embodiments of this application provide a method for manufacturing a printed circuit board, comprising: S100: A laminating plate 100 is provided. The laminating plate 100 includes an embedded layer 10, a dielectric layer 20 and a target layer 30 stacked together. The dielectric layer 20 is located between the embedded layer 10 and the target layer 30. The embedded layer 10 includes a sub-plate 11 and a ceramic component 12 disposed in the sub-plate 11. A first circuit layer 121 is disposed on the side of the ceramic component 12 facing away from the dielectric layer 20. A target circuit layer 31 is disposed on the side of the target layer 30 facing the dielectric layer 20.

[0026] The press plate 100 is formed by pressing and can be a multi-layer plate. The embedded layer 10 and the target layer 30 are connected together through the medium layer 20. The embedded layer 10 and the target layer 30 will not move relative to each other. The embedded layer 10 and the medium layer 20 can be set on opposite sides of the target layer 30.

[0027] The dielectric layer 20 may include resin and glass fiber, for example, the dielectric layer 20 may be formed by melting and curing a prepreg. The target layer 30 may be a single-layer board or a multi-layer board, and the target circuit layer 31 may be made of copper, silver or aluminum, etc. The sub-board 11 may be a single-layer board or a multi-layer board, and the first circuit layer 121 may be made of copper, silver or aluminum, for example, the sub-board 11 may be a copper-clad laminate, and the first circuit layer 121 may be made of copper.

[0028] S200: A connection hole is machined on the lamination plate 100 from the side of the first circuit layer 121 away from the dielectric layer 20 using a laser. The connection hole penetrates the first circuit layer 121, the ceramic part 12 and the dielectric layer 20. The target circuit layer 31 defines part of the inner wall of the connection hole.

[0029] The laser may include ultraviolet (UV) lasers, carbon dioxide (CO2) lasers, or other lasers.

[0030] Understandably, since the connecting hole penetrating the first circuit layer 121, ceramic component 12, and dielectric layer 20 is directly machined using laser, there is no need to pre-drill holes on the ceramic component 12. Therefore, there is no need to consider the alignment of mechanical drilling or the alignment between the ceramic component 12 and the sub-board 11. This can improve the problem of drill bit breakage during mechanical drilling caused by alignment deviations in conventional solutions. Part of the inner wall of the connecting hole can be the bottom wall and / or side wall of the connecting hole.

[0031] S300: A conductive layer 60 is provided on the inner wall of the connecting hole. The first circuit layer 121 and the target circuit layer 31 are both connected to the conductive layer 60 and are electrically conductive.

[0032] A conductive layer 60 can be formed on the inner wall of the connecting hole using chemical electroplating. The conductive layer 60 can be made of materials such as copper, silver, or aluminum. The first circuit layer 121 and the target circuit layer 31 are electrically connected through the conductive layer 60.

[0033] As can be seen from the above, the method for manufacturing a printed circuit board provided in this application embodiment includes a laminated board 100 comprising a buried layer 10, a dielectric layer 20, and a target layer 30 stacked together. The dielectric layer 20 is located between the buried layer 10 and the target layer 30. The buried layer 10 includes a sub-board 11 and a ceramic component 12 disposed within the sub-board 11. A first circuit layer 121 is disposed on the side of the ceramic component 12 facing away from the dielectric layer 20. A target circuit layer 31 is disposed on the side of the target layer 30 facing the dielectric layer 20. The first circuit layer 121 is then fabricated using a laser. A connection hole is machined on the side of the circuit layer 121 away from the dielectric layer 20 on the laminating plate 100. The connection hole penetrates the first circuit layer 121, the ceramic part 12 and the dielectric layer 20. The target circuit layer 31 defines part of the inner wall of the connection hole. Therefore, there is no need to set a pre-drilled area on the ceramic part 12. Thus, there is no need to consider the alignment of the mechanical drilling. After the conductive layer 60 is set on the inner wall of the connection hole, both the first circuit layer 121 and the target circuit layer 31 can be connected to the conductive layer 60 and electrically conductive.

[0034] Please refer to Figures 1 to 7 In some embodiments, the step of using a laser to process connection holes on the lamination plate 100 from the side of the first circuit layer 121 opposite to the dielectric layer 20 specifically includes: First, an ultraviolet laser is used to process a first hole 40 on the lamination plate 100 from the side of the first circuit layer 121 away from the dielectric layer 20. The first hole 40 penetrates the first circuit layer 121 and the ceramic part 12, and the dielectric layer 20 defines the bottom wall of the first hole 40.

[0035] Among them, the ultraviolet laser can remove part of the dielectric layer 20, and the first hole 40 is a blind hole.

[0036] Next, a carbon dioxide laser is used to process a second hole 50 on the laminating plate 100 from the bottom of the first hole 40. The second hole 50 penetrates the dielectric layer 20, and the target circuit layer 31 defines the bottom wall of the second hole 50. The first hole 40 and the second hole 50 form a connection hole.

[0037] Among them, carbon dioxide laser can remove the remaining dielectric layer 20.

[0038] By adopting the above solution, it is possible to avoid the ultraviolet laser directly penetrating the target circuit layer 31, or even penetrating other circuit layers below the target circuit layer 31, which would cause the subsequent conductive layer 60 to conduct electricity to other circuit layers below the target circuit layer 31, resulting in electrical performance failure.

[0039] It is understandable that the conductive layer 60 connects the first circuit layer 121 and the target circuit layer 31 across the first hole 40 and the second hole 50.

[0040] It should be noted that when the first hole 40 is processed using an ultraviolet laser, the corresponding light source is usually a UV nanosecond light source. The tolerance of different materials to this light source is: ceramic > copper foil > dielectric layer 20. Due to the special properties of ceramic materials, different light sources are required. Generally, an ultraviolet laser is used. Moreover, the bottom of the target circuit layer 31 is mostly FR4 (Flame Retardant 4, flame-retardant grade 4 epoxy fiberglass cloth substrate). Therefore, when making the connection hole, due to the direct ablation and brittle fracture under high energy density, the bottom of the connection hole is prone to forming a sharp corner. The sharp corner will penetrate the target circuit layer 31 and even penetrate other circuit layers below the target circuit layer 31, causing the subsequent conductive layer 60 to conduct to other circuit layers below the target circuit layer 31, resulting in electrical performance failure.

[0041] Optionally, a second circuit layer 122 is provided on the side of the ceramic component 12 facing the dielectric layer 20. The second circuit layer 122 includes a protective pad 1221. A first hole 40 penetrates the protective pad 1221. The absorption rate of the ceramic component 12 to ultraviolet laser is less than or equal to the absorption rate of the protective pad 1221 to ultraviolet laser, and the absorption rate of the protective pad 1221 to ultraviolet laser is less than the absorption rate of the dielectric layer 20 to ultraviolet laser.

[0042] With this setup, the protective pad 1221 can absorb some of the energy of the ultraviolet laser, preventing the ultraviolet laser from easily removing the entire dielectric layer 20 or even breaking through the target circuit layer 31, thus improving the problem of the first hole 40 being sharp-angled after being processed by ultraviolet laser.

[0043] It should be noted that the material of the protective pad 1221 can be the same as the material of the target circuit layer 31.

[0044] Please refer to Figure 12In other embodiments, the second circuit layer 122 includes a connection point 1223, which is located between the connection line 1222 and the protective pad 1221. Both the connection line 1222 and the protective pad 1221 are connected to the connection point 1223 and are electrically connected. The connection point 1223 is connected to the conductive layer 60 and is electrically connected.

[0045] This configuration not only allows the conductive layer 60 to be electrically connected to the connecting line 1222 through the connection point 1223 when it is necessary to connect the conductive layer 60 to the connecting line 1222, but also unifies the parameters of the ultraviolet laser compared to the case where it is not necessary to connect the conductive layer 60 to the connecting line 1222. This ensures that there is no difference in the absorption of ultraviolet laser at the location of the protective pad 1221, eliminating the need to adjust the ultraviolet laser equipment.

[0046] It should be noted that the width of the connection position 1223 can be 0.1mm to ensure the conductivity of the connection line 1222 at this position.

[0047] Please refer to Figure 13 and Figure 14 To prevent the first hole 40 from penetrating the ceramic component 12 and the protective pad 1221 after penetrating the ceramic component 12 and the protective pad 1221, and further damaging the target circuit layer 31, in other embodiments, a protective layer 13 is provided on the side of the protective pad 1221 away from the ceramic component 12. The absorption rate of the protective layer 13 to ultraviolet laser is less than that of the protective pad 1221 to ultraviolet laser, and the first hole 40 penetrates the protective layer 13.

[0048] By adopting the above solution, the damage to the target circuit layer 31 caused by ultraviolet laser after it penetrates the ceramic component 12 and the protective pad 1221 can be reduced by the protective layer 13, thus avoiding penetration of the target circuit layer 31.

[0049] The protective pad 1221 is made of copper, and the protective layer 13 is made of at least one of gold, palladium, and tin.

[0050] This design avoids the possibility that the first hole 40 might penetrate the protective pad 1221 after penetrating the ceramic component 12 and the protective pad 1221, which could further damage the target circuit layer 31.

[0051] It should be noted that the material of the protective layer 13 can be selected according to the degree of absorption of different metals by different ultraviolet lasers. For example, when the ultraviolet laser has a wavelength of 355nm, the absorption rate of different metals to ultraviolet lasers is: nickel > copper > gold > palladium > tin. Therefore, surface treatments such as immersion gold, immersion nickel palladium gold, and immersion tin can be added to the protective pad 1221 to obtain the protective layer 13.

[0052] For example, the protective pad 1221 is made of copper. The protective pad 1221 has a high absorption rate of ultraviolet laser. For example, the protective pad 1221 has an absorption rate of about 60% for ultraviolet laser with a wavelength of 355nm. After the ultraviolet laser penetrates the ceramic component 12, it may still penetrate the protective pad 1221, which may further lead to the risk of damage to the target circuit layer 31. Therefore, a protective layer 13 can be obtained by fabricating a nickel-palladium-gold process. The protective layer 13 includes a nickel layer, a palladium layer, and a gold layer. The thickness of the nickel layer is 3um-6um, the thickness of the palladium layer is 0.1um-0.3um, and the thickness of the gold layer is 0.05um-0.1um. After the ultraviolet laser penetrates the ceramic component 12, the palladium layer and the gold layer have a low absorption rate of ultraviolet laser. Therefore, after the ultraviolet laser penetrates the ceramic component 12, the damage to the dielectric layer 20 is small. The second hole 50 formed in the area where the dielectric layer 20 is located is then fabricated by carbon dioxide laser desmearing, so that a connection hole with a qualified hole shape and no penetration of the target circuit layer 31 can be obtained.

[0053] Optionally, the diameter of the first hole 40 at the protective pad 1221 is equal to the diameter of the protective pad 1221; the second circuit layer 122 includes connecting lines 1222, which are spaced apart from the protective pad 1221.

[0054] This configuration avoids the subsequent conductive layer 60 from becoming connected to the connecting line 1222 due to the misalignment of the first hole 40 when it is not necessary to connect the conductive layer 60 to the connecting line 1222.

[0055] It should be noted that the spacing between the connecting line 1222 and the protective pad 1221 can be 0.1mm-0.15mm. If it is 0.1mm, and the spacing cannot be met, part of the connecting line 1222 can be removed.

[0056] Please refer to Figure 1 as well as Figures 9 to 11 In some embodiments, the method of fabricating the printed circuit board before providing the laminating plate 100 includes: First, the target layer 30, the adhesive layer, and the sub-plate 11 are stacked. The target layer 30 is provided with a first positioning hole 32 and a second positioning hole 33. A first positioning element 70 is inserted into the first positioning hole 32, and a second positioning element 80 is inserted into the second positioning hole 33. The sub-plate 11 is provided with a first mating hole 112, and the first positioning element 70 passes through the first mating hole 112. The sub-plate 11 is provided with an embedded groove 111, and a ceramic part 12 is provided inside the embedded groove 111. The ceramic part 12 is provided with a second mating hole, and the second positioning element 80 passes through the second mating hole.

[0057] The adhesive layer may include a prepreg, etc. Multiple first positioning holes 32, first positioning elements 70 and first mating holes 112 may be provided, and the first positioning holes 32, first positioning elements 70 and first mating holes 112 are provided in a one-to-one correspondence. Multiple second positioning holes 33, second positioning elements 80 and second mating holes may be provided, and the second positioning holes 33, second positioning elements 80 and second mating holes are provided in a one-to-one correspondence.

[0058] Next, the target layer 30, the adhesive layer and the sub-plate 11 are pressed together. Part of the adhesive layer fills the gap between the inner wall of the embedded groove 111 and the ceramic part 12, and part of the adhesive layer forms the dielectric layer 20.

[0059] The target layer 30, the adhesive layer and the sub-plate 11 can be pressed together by a press machine. After the adhesive layer melts, it solidifies to form the medium layer 20.

[0060] By adopting the above solution, the alignment problem can be solved when pressing the target layer 30, the adhesive layer and the sub-plate 11, and the misalignment of the target layer 30, the adhesive layer, the sub-plate 11 and the ceramic part 12 can be avoided.

[0061] It is understandable that before pressing the target layer 30, the adhesive layer, and the sub-plate 11, the thickness of the adhesive layer will be greater than the thickness of the dielectric layer 20 formed after pressing. Therefore, in order to ensure that the first positioning member 70 and the second positioning member 80 can fix each layer before pressing, the length of the first positioning member 70 and the length of the second positioning member 80 are required to be greater than the thickness of the target layer 30 before pressing. It can be selected as the thickness of the target layer 30 before pressing plus 1 / 3 to 1 / 2 of the thickness of the ceramic part, to ensure that the first positioning member 70 and the second positioning member 80 can correctly fix the ceramic part 12 and the sub-plate 11. However, the adhesive layer will be filled with glue, and the plate thickness needs to be reduced after pressing. Therefore, it is necessary to ensure that the first positioning member 70 and the second positioning member 80 are less than the thickness of the pressed plate 100 formed after pressing, to avoid the first positioning member 70 and the second positioning member 80 exceeding the plate thickness after pressing, resulting in insufficient pressing or abnormal layer misalignment.

[0062] It should be noted that both the first positioning element 70 and the second positioning element 80 can be copper nails or other positioning pins. A CCD (Charge Coupled Device) can be added to the SET (unit) edge of the target layer 30 to align the target, ensuring that the positions of the first positioning hole 32 and the second positioning hole 33 drilled by the mechanical drill match the inner layer position of the target layer 30 after the target is grasped. After mechanical drilling, the first positioning element 70 and the second positioning element 80 are used to bond the target layer 30, the core board of the sub-board 11, and the ceramic.

[0063] It should also be noted that, since the CTE of the ceramic part 12 is significantly different from that of the sub-plate 11 and the dielectric layer 20, if the gap between the ceramic part 12 and the embedding groove 111 is small, the compression between the ceramic part 12 and the groove wall of the embedding groove 111 during pressing can easily lead to local warping. Since the embodiment of this application relies on the second positioning member 80 to position the ceramic part 12, the size of the embedding groove 111 can be increased to reduce the warping problem without affecting the embedding accuracy.

[0064] Optionally, the adhesive layer is provided with a first clearance hole 21, the first positioning member 70 passes through the first clearance hole 21, and the diameter of the first clearance hole 21 is at least 0.1 mm larger on one side than that of the first mating hole 112.

[0065] This configuration avoids significant misalignment of the dielectric layer 20 and also reduces warping issues caused by a large difference between the CTE of the factor plate 11 and the CTE of the adhesive layer.

[0066] And / or, the adhesive layer is provided with a second clearance hole, the second positioning member 80 is inserted into the second clearance hole, and the diameter of the second clearance hole is at least 0.1 mm larger on one side than that of the second mating hole.

[0067] This configuration avoids significant misalignment of the dielectric layer 20 and also reduces warping issues caused by a large difference between the CTE of the ceramic component 12 and the CTE of the adhesive layer.

[0068] For example, the target layer 30 is produced through processes such as pre-processing, image film exposure, mechanical drilling, and browning.

[0069] The preceding processes include material feeding, image film application and exposure, image etching, AOI (Automated Optical Inspection) & VRS (Virtual Rescan), browning, lamination, target drilling, mechanical drilling, electroplating, resin plugging, resin plugging baking plate, resin grinding, and POFV (Plating Over Filled Via).

[0070] Image film exposure: An LDI (Laser Direct Imaging) exposure machine is used to expose the required circuitry and target positions onto the board surface. When fabricating the circuitry of each layer of the inner substrate, except for the target positions, all other areas are protected and the circuitry is fabricated normally in these areas. The circuitry is completed after all the layers are laminated together to form the inner substrate.

[0071] Image etching: Using an etching solution, the copper conductors without dry film protection are etched away, while the copper conductors with dry film protection are left behind.

[0072] AOI: Optical inspection of the completed inner layer circuit board to confirm its quality.

[0073] Drill positioning holes: Machin the first positioning hole 32 and the second positioning hole 33.

[0074] Browning: Through a chemical reaction, a uniform organometallic complex film with a specific roughness is generated on a clean copper surface to obtain the target layer 30.

[0075] For example, ceramic parts 12 are manufactured through processes such as material feeding, copper sputtering, image coating exposure, image etching, titanium removal, AOI & VRS, image coating exposure, nickel-palladium-gold, film removal, and browning.

[0076] Material preparation: Cut the large ceramic slab into the required working boards according to the design requirements.

[0077] Sputtered copper: A layer of titanium is first deposited on the work plate by vacuum sputtering, and then thickened to the target copper thickness.

[0078] Image film exposure: Using an LDI exposure machine, the required lines and target positions are exposed onto the board surface.

[0079] Image etching: The copper conductors without dry film protection are etched away using an etching solution, while the copper conductors with dry film protection are left behind, forming the first circuit layer 121 and the second circuit layer 122.

[0080] AOI: Perform optical inspection on the completed first circuit layer 121 and second circuit layer 122 to confirm quality.

[0081] Titanium removal: The palladium layer in the etched circuit gaps is removed using a special solution (usually sodium hydroxide) to prevent short circuits.

[0082] Image film exposure: The second circuit layer 122 is completely covered with anti-electroplating gold dry film. Using an LDI exposure machine, the required circuit and target positions are exposed to the board surface. This process creates dry film windows for the protective pads 1221 that are to be made into nickel-palladium-gold.

[0083] Nickel-palladium-gold: A protective layer 13 is formed by combining a nickel layer, a palladium layer and a gold layer on the protective pad 1221.

[0084] Film removal: The anti-electroplated gold dry film is removed using a film removal solution.

[0085] Browning: A chemical reaction is used to generate a uniform organometallic complex film with a specific roughness on a clean board surface.

[0086] For example, sub-board 11 is manufactured through processes such as material feeding, image film exposure, image etching, AOI, drilling mating holes, milling grooves, and browning.

[0087] Image film exposure: Apply dry film and use an LDI exposure machine to expose the required lines and target positions onto the board surface.

[0088] Image etching: Using an etching solution, the copper conductors without dry film protection are etched away, while the copper conductors with dry film protection are left behind.

[0089] AOI: To perform optical inspection on the completed circuit to confirm its quality.

[0090] Drill mating holes: Drill a first mating hole 112 that matches the first positioning hole 32 and a second mating hole that matches the second positioning hole 33. To avoid misalignment, the first mating hole 112 is 0.1 mm larger on one side than the first positioning hole 32, and the second mating hole is 0.1 mm larger on one side than the second positioning hole 33.

[0091] Gong groove: A recessed groove 111 is formed by gonging to accommodate ceramic parts 12.

[0092] Browning: A chemical reaction is used to generate a uniform, organometallic complex film with a specific roughness on a clean copper surface.

[0093] Insert copper nails: Insert copper nails into the first positioning hole 32 as the first positioning element 70, and insert copper nails into the second positioning hole 33 as the second positioning element 80.

[0094] Pre-stack: The adhesive layer and the target layer 30 are pre-stacked on the board surface where the embedded layer 10 has been placed.

[0095] Pressing: The ceramic part 12, the sub-plate 11 and the target layer 30 are bonded together as a whole in a press under high temperature conditions through an adhesive layer.

[0096] Laser drilling: First, an ultraviolet laser is used to process a first hole 40 on the laminating plate 100 from the side of the first circuit layer 121 away from the dielectric layer 20. The first hole 40 penetrates the first circuit layer 121 and the ceramic part 12. The dielectric layer 20 defines the bottom wall of the first hole 40. Then, a carbon dioxide laser is used to process a second hole 50 on the laminating plate 100 from the bottom of the first hole 40. The second hole 50 penetrates the dielectric layer 20. The target circuit layer 31 defines the bottom wall of the second hole 50. The first hole 40 and the second hole 50 form a connecting hole.

[0097] The subsequent processes can be completed sequentially, namely blind hole electroplating, resin plugging, POFV, image film exposure, image etching, and further lamination and layering.

[0098] Secondly, embodiments of this application provide a printed circuit board, which includes a lamination board 100. The lamination board 100 includes a buried layer 10, a dielectric layer 20, and a target layer 30 stacked together. The dielectric layer 20 is located between the buried layer 10 and the target layer 30. The buried layer 10 includes a sub-board 11 and a ceramic component 12 disposed within the sub-board 11. A first circuit layer 121 is disposed on the side of the ceramic component 12 facing away from the dielectric layer 20, and a target circuit layer 31 is disposed on the side of the target layer 30 facing the dielectric layer 20. A connection hole is provided on the lamination board 100, which penetrates the first circuit layer 121, the ceramic component 12, and the dielectric layer 20. The target circuit layer 31 defines part of the inner wall of the connection hole. A conductive layer 60 is disposed on the inner wall of the connection hole. Both the first circuit layer 121 and the target circuit layer 31 are connected to the conductive layer 60 and are electrically conductive.

[0099] The printed circuit board provided in this application embodiment includes a laminated board 100 comprising a stacked embedded layer 10, a dielectric layer 20, and a target layer 30. The dielectric layer 20 is located between the embedded layer 10 and the target layer 30. The embedded layer 10 includes a sub-board 11 and a ceramic component 12 disposed within the sub-board 11. A first circuit layer 121 is disposed on the side of the ceramic component 12 away from the dielectric layer 20, and a target circuit layer 31 is disposed on the side of the target layer 30 facing the dielectric layer 20. A connection hole is provided on the laminated board 100, which penetrates the first circuit layer 121, the ceramic component 12, and the dielectric layer 20. The target circuit layer 31 defines part of the inner wall of the connection hole. Therefore, it is not necessary to provide a pre-drilled area on the ceramic component 12, and thus there is no need to consider the alignment of the mechanical drilling. At the same time, a conductive layer 60 is provided on the inner wall of the connection hole, which allows both the first circuit layer 121 and the target circuit layer 31 to be connected to the conductive layer 60 and electrically conductive.

[0100] Thirdly, embodiments of this application provide a printed circuit board, which is manufactured by the printed circuit board manufacturing method of the first aspect.

[0101] The printed circuit board provided in this application embodiment includes a laminated board 100 comprising a stacked embedded layer 10, a dielectric layer 20, and a target layer 30. The dielectric layer 20 is located between the embedded layer 10 and the target layer 30. The embedded layer 10 includes a sub-board 11 and a ceramic component 12 disposed within the sub-board 11. A first circuit layer 121 is disposed on the side of the ceramic component 12 away from the dielectric layer 20, and a target circuit layer 31 is disposed on the side of the target layer 30 facing the dielectric layer 20. A connection hole is machined on the laminated board 100 using a laser from the side of the first circuit layer 121 away from the dielectric layer 20. The connection hole penetrates the first circuit layer 121, the ceramic component 12, and the dielectric layer 20. The target circuit layer 31 defines part of the inner wall of the connection hole. Therefore, it is not necessary to provide a pre-drilled area on the ceramic component 12, and there is no need to consider the alignment of the mechanical drilling. Furthermore, after providing a conductive layer 60 on the inner wall of the connection hole, both the first circuit layer 121 and the target circuit layer 31 can be connected to the conductive layer 60 and electrically conductive.

[0102] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for manufacturing a printed circuit board, characterized in that, include: A laminating plate is provided, the laminating plate including an embedded layer, a dielectric layer and a target layer stacked together, the dielectric layer being located between the embedded layer and the target layer, the embedded layer including a sub-board and a ceramic component disposed within the sub-board, a first circuit layer being disposed on the side of the ceramic component facing away from the dielectric layer, and a target circuit layer being disposed on the side of the target layer facing the dielectric layer; A connection hole is machined on the lamination plate from the side of the first circuit layer away from the dielectric layer using a laser. The connection hole penetrates the first circuit layer, the ceramic component, and the dielectric layer. The target circuit layer defines a portion of the inner wall of the connection hole. A conductive layer is provided on the inner wall of the connection hole, and both the first circuit layer and the target circuit layer are connected to the conductive layer and are electrically conductive.

2. The method for manufacturing a printed circuit board according to claim 1, characterized in that, The step of using a laser to process a connection hole on the lamination plate from the side of the first circuit layer away from the dielectric layer specifically includes: A first hole is machined on the lamination plate from the side of the first circuit layer away from the dielectric layer using an ultraviolet laser. The first hole penetrates the first circuit layer and the ceramic component, and the dielectric layer defines the bottom wall of the first hole. A second hole is machined from the bottom of the first hole onto the lamination plate using a carbon dioxide laser. The second hole penetrates the dielectric layer, and the target circuit layer defines the bottom wall of the second hole. The first hole and the second hole form the connection hole.

3. The method for manufacturing a printed circuit board according to claim 2, characterized in that, A second circuit layer is provided on the side of the ceramic component facing the dielectric layer, and the second circuit layer includes a protective pad; the first hole penetrates the protective pad, the absorption rate of the ceramic component to the ultraviolet laser is less than or equal to the absorption rate of the protective pad to the ultraviolet laser, and the absorption rate of the protective pad to the ultraviolet laser is less than the absorption rate of the dielectric layer to the ultraviolet laser.

4. The method for manufacturing a printed circuit board according to claim 3, characterized in that, A protective layer is provided on the side of the protective pad away from the ceramic part. The absorption rate of the protective layer to the ultraviolet laser is less than that of the protective pad to the ultraviolet laser. The first hole penetrates the protective layer.

5. The method for manufacturing a printed circuit board according to claim 4, characterized in that, The protective pads are made of copper, and the protective layer is made of at least one of gold, palladium, and tin.

6. The method for manufacturing a printed circuit board according to claim 3, characterized in that, The diameter of the first hole at the protective pad is equal to the diameter of the protective pad; the second circuit layer includes connecting lines, which are spaced apart from the protective pad.

7. The method for manufacturing a printed circuit board according to claim 6, characterized in that, The second circuit layer includes a connection point located between the connection line and the protective pad, and both the connection line and the protective pad are connected to the connection point and electrically conductive; the connection point is connected to the conductive layer and electrically conductive.

8. The method for manufacturing a printed circuit board according to any one of claims 1 to 7, characterized in that, Before providing the laminating plate, the method for manufacturing the printed circuit board includes: The target layer, adhesive layer, and sub-board are stacked together. The target layer is provided with a first positioning hole and a second positioning hole. A first positioning element is inserted into the first positioning hole, and a second positioning element is inserted into the second positioning hole. The sub-board is provided with a first mating hole, and the first positioning element passes through the first mating hole. The sub-board is provided with an embedding groove, and the ceramic part is provided inside the embedding groove. The ceramic part is provided with a second mating hole, and the second positioning element passes through the second mating hole. The target layer, the adhesive layer, and the sub-plate are pressed together, with a portion of the adhesive layer filling the gap between the inner wall of the embedded groove and the ceramic part, and a portion of the adhesive layer forming the dielectric layer.

9. A printed circuit board, characterized in that, The printed circuit board includes a lamination board, which includes a stacked embedded layer, a dielectric layer, and a target layer. The dielectric layer is located between the embedded layer and the target layer. The embedded layer includes a sub-board and a ceramic component disposed within the sub-board. A first circuit layer is disposed on the side of the ceramic component facing away from the dielectric layer, and a target circuit layer is disposed on the side of the target layer facing the dielectric layer. A connection hole is provided on the lamination board, which penetrates the first circuit layer, the ceramic component, and the dielectric layer. The target circuit layer defines a portion of the inner wall of the connection hole, and a conductive layer is disposed on the inner wall of the connection hole. Both the first circuit layer and the target circuit layer are connected to the conductive layer and are electrically conductive.

10. A printed circuit board, characterized in that, The printed circuit board is manufactured by the method for manufacturing a printed circuit board as described in any one of claims 1 to 8.

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