Electrical detection method for dry film hole sealing performance of PCB

Abstract

The application discloses a kind of electrical detection methods of PCB dry film hole sealing performance, including providing insulating substrate, and on insulating substrate drill several through holes;Form conductive layer on the surface of substrate and the hole wall of through hole;The top surface and bottom surface of insulating substrate are respectively attached dry film, and exposure is carried out, and the dry film solidification of aperture is solidified, and the dry film solidification area of top surface and the dry film solidification area of bottom surface are electrically connected by conductive layer;Dry film is developed and handled, and the dry film of un-solidified area is removed;Using dry film as resist layer, insulating substrate is etched and handled, and the conductive layer not covered by dry film is removed, so that the remaining conductive layer forms series connection line between multiple through holes;Remove dry film, and electrical test is carried out to conductive line, and the hole sealing integrity of each through hole is judged according to electrical test result.The application connects all holes by line series connection, and after etching, specific broken hole position can be directly confirmed by open circuit test, and there is no loss without relying on visual inspection.

Description

Technical Field

[0001] This invention relates to the field of PCB manufacturing processes, and in particular to an electrical testing method for the sealing performance of PCB dry film. Background Technology

[0002] In the manufacturing process of flexible printed circuit boards (PCBs), dry film is widely used as a photoresist in processes such as pattern transfer and via protection. When dry film covers the surface of vias, it must remain intact during subsequent wet processes such as development and etching to prevent accidental etching or contamination of the copper layer inside the via, thereby ensuring the reliability of the via. To verify the coverage integrity of dry film for different via diameters (e.g., 0.15mm, 0.20mm, 0.30mm, etc.), the industry typically designs dedicated test boards to evaluate the sealing effect by simulating actual production processes.

[0003] Currently, the conventional manufacturing process for dry film sealing capability test boards includes the following steps: material preparation, mechanical drilling, pretreatment (acid washing and micro-etching), laminating the dry film, exposure of the aligned hole areas (the mask completely blocks the hole areas, allowing the dry film to solidify and cover the hole openings), development with sodium carbonate solution, and finally, visual inspection of each through-hole opening by testing personnel using a magnifying glass or microscope to confirm whether the dry film has defects such as cracks, wrinkles, or punching. These test boards typically have hundreds to thousands of test holes of different diameters arranged on a single board to cover various process conditions.

[0004] However, this traditional method has significant limitations. First, due to the large number of test holes, inspectors need to observe each hole individually, which is extremely time-consuming and severely reduces inspection efficiency, especially in mass production or process verification stages, where this manual operation becomes a bottleneck. Secondly, visual inspection is highly dependent on the inspector's experience, focus, and eyesight; tiny cracks or localized damage at the hole edges are easily missed, leading to misjudgments or missed detections. The judgments of different personnel may also differ, making it difficult to guarantee the reliability of the test results. Furthermore, the developing process itself is extremely sensitive to process parameters (such as solution concentration, temperature, spray pressure, and time). Even slight deviations in control can lead to overdevelopment, where the dry film at the hole opening may be washed away or thinned. This defect will directly cause the copper layer inside the hole to be eroded during subsequent etching. However, traditional methods can only detect dry film appearance problems before etching and cannot predict the actual copper layer protection effect after etching. Moreover, after the test board has undergone developing, the dry film coverage is basically fixed, but if secondary damage occurs during transportation or post-processing, it is difficult to trace visually. More importantly, existing methods only indicate whether a hole is qualified or unqualified, and cannot accurately pinpoint which hole has experienced sealing failure.

[0005] In summary, traditional manual visual inspection methods are no longer sufficient to meet the demands of modern PCB manufacturing for high precision, high efficiency, and traceability. There is an urgent need for a testing method that can quickly and accurately identify sealing defects and locate failure points. Summary of the Invention

[0006] The technical solution of this invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the main objective of this invention is to provide an electrical testing method for the performance of PCB dry film sealing vias. This method connects all vias in series, and after etching, the specific location of any defects can be directly confirmed through open-circuit testing, without relying on visual inspection and ensuring no omissions.

[0007] To achieve the above objectives, the present invention provides an electrical testing method for the sealing performance of PCB dry film, comprising the following steps: S1, providing an insulating substrate and drilling a plurality of through holes on the insulating substrate; S2, forming a conductive layer on the surface of the insulating substrate and the hole walls of the through holes; S3, attaching dry film to the top and bottom surfaces of the insulating substrate respectively, and exposing the dry film to cure the dry film at the opening of the through holes, wherein the cured area of ​​the dry film on the top surface and the cured area of ​​the dry film on the bottom surface are electrically connected through the conductive layer; S4, developing the exposed dry film to remove the uncured areas of the dry film; S5, using the dry film as a resist layer, etching the insulating substrate to remove the conductive layer not covered by the dry film, so that the remaining conductive layer forms a series conductive line between the plurality of through holes; S6, removing the dry film and performing an electrical test on the conductive line, and determining the sealing integrity of each through hole based on the electrical test results.

[0008] As a further embodiment of the present invention, the conductive layer in step S2 is formed by chemical copper plating and electroplating flash plating.

[0009] The thickness of the conductive layer is 3-8 μm.

[0010] As a further embodiment of the present invention, in step S3, a mask is used to completely block the through-hole area during exposure, while the mask retains a circuit pattern between adjacent through holes, so that the dry film around the opening of each through hole after development is connected to each other through the dry film in the circuit pattern area.

[0011] As a further embodiment of the present invention, in step S3, the circuit pattern on the top surface and the circuit pattern on the bottom surface are arranged in an alternating manner, so that the series-connected conductive lines form a serpentine pattern.

[0012] As a further embodiment of the present invention, the electrical test in step S6 is an open circuit test. If the measured resistance value of the conductive line is less than a preset threshold, it is determined that the sealing of each through hole is complete.

[0013] If the measured resistance value tends to infinity, it is determined that there is a through hole with a failed seal in the conductive line, and the failed through hole is located according to the location of the open circuit.

[0014] As a further embodiment of the present invention, the through holes in step S1 include at least two different apertures, and the through holes of different apertures are arranged into independent test units, and the through holes in each test unit are connected in series through the conductive line.

[0015] As a further embodiment of the present invention, a material cutting step is included before step S1, in which an FR-4 substrate is selected and cut to a preset size;

[0016] In step S1, mechanical drilling is used, and the drilling accuracy is controlled within ±0.05mm.

[0017] As a further embodiment of the present invention, a pretreatment step is included before step S3, in which the insulating substrate after drilling is subjected to acid washing and micro-etching treatment, and the micro-etching amount is controlled to be 1.0-1.5μm.

[0018] As a further embodiment of the present invention, in step S3, the dry film is applied using a laminating machine, with a laminating temperature of 110±5℃, a pressure of 0.5-0.8MPa, and a laminating time of 30-60s.

[0019] The exposure energy is 80-120 mJ / cm².

[0020] As a further embodiment of the present invention, in step S4, the developing solution uses a concentration of 0.8%-1.2% by mass. The solution was developed in 30-60 seconds, and the spray pressure was 0.15-0.25 MPa.

[0021] The beneficial effects of this invention are as follows:

[0022] This invention proposes an electrical testing method for the sealing performance of PCB dry film vias. By forming a conductive layer on an insulating substrate and connecting all vias in series via conductive lines to form a circuit, the method transforms manual visual inspection into electrical testing. Only one open-circuit test is needed to evaluate all vias, significantly improving testing efficiency. The electrical test results are accurate and quantifiable, eliminating missed detections and misjudgments caused by human factors, ensuring the reliability of the test results. For example, when a via fails to seal, the conductive layer at that point is damaged during the etching step, causing a circuit break. Inspectors can accurately locate the failed via and its diameter based on the break location. Furthermore, independent test units for different via diameters can be set up to test the sealing capability of multiple via diameters. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0024] Figure 1 This is a partial planar schematic diagram of a test board in the prior art.

[0025] Figure 2 This is a schematic diagram of a partial cross-section of a test board in the prior art.

[0026] Figure 3 This is a partial planar schematic diagram of the process of the present invention after the holes are connected in series by a circuit.

[0027] Figure 4 Appendix to this invention Figure 3 A partial cross-sectional schematic diagram.

[0028] Figures 5-6 This is a schematic diagram of the existing technology process steps.

[0029] Figures 7-8 This is a schematic diagram of the process steps of the present invention.

[0030] Figure 9 This is a photograph of the actual object before the dry film sealing etching process of this invention.

[0031] Figure 10 This is a photograph of the actual product after etching and film removal in the process of this invention.

[0032] Figure 11 This is a schematic block diagram illustrating the main implementation process of the present invention. Detailed Implementation

[0033] In the description of this invention, it should be noted that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0035] as follows:

[0036] Please see the appendix Figure 1-11 ,

[0037] Among them, the appendix Figure 7-8 Only existing technologies will be shown (with appendix) Figure 5-6 Different steps, namely, material cutting and drilling, are not shown, and are attached. Figure 7-8 Electroplating, film application, and exposure in the text correspond to existing technologies (see appendix). Figure 5-6 The processes involved in film application, exposure, and development.

[0038] The proposed testing method involves fabricating a test circuit consisting of conductive layers connected in series on an insulating substrate, and then using electrical testing techniques to evaluate the sealing integrity of the dry film on vias. The specific process is as follows:

[0039] First, proceed with the material cutting steps (see attached document for reference). Figure 5 ),

[0040] A standard FR-4 copper-clad insulating substrate is selected and cut according to the preset test board dimensions. FR-4 substrate has good mechanical strength and electrical insulation properties, and is one of the most commonly used substrate materials in the PCB manufacturing industry. During cutting, it is necessary to ensure that the substrate dimensions are accurate, the edges are flat, and there are no burrs or delamination defects to guarantee the processing accuracy of subsequent processes.

[0041] After the material cutting is completed, proceed to the drilling step (see attached document for reference). Figure 5 ),

[0042] Several through holes are drilled on the insulating substrate using CNC mechanical drilling equipment. During drilling, the hole position accuracy must be controlled within ±0.05mm to ensure the accurate alignment of subsequent conductive lines. The diameter of the through holes can be designed according to actual testing requirements. Generally, multiple test units with different hole diameters can be set up. For example, hole groups with diameters of 0.15mm, 0.20mm, and 0.30mm can be arranged on the same test board, with each group containing several through holes.

[0043] After drilling, a conductive layer is formed on the surface of the insulating substrate and the walls of the through holes (see attached diagram). Figure 7 ),

[0044] Specifically, the process begins with chemical copper plating, where a thin layer of copper is deposited on the substrate surface and hole walls through a chemical reduction reaction, making the originally insulating hole walls conductive. Then, electroplating flash plating is performed, where an additional layer of copper is deposited on the copper plating layer through electrolytic deposition, so that the copper layer on the hole walls reaches the required thickness.

[0045] In this embodiment, the thickness of the conductive layer is controlled at 5 μm. The temperature, composition concentration and current density of the plating solution are controlled during the copper plating and electroplating process to ensure that the copper layer on the hole wall is uniform, dense and free of pinholes and voids, thereby ensuring good electrical connectivity between subsequent vias.

[0046] After the conductive layer is formed, a pretreatment step is performed to clean the copper surface and improve the adhesion of the dry film.

[0047] The pretreatment process includes two steps: pickling and micro-etching. Pickling involves immersing the substrate in a dilute sulfuric acid solution to remove oxides and minor contaminants from the copper surface. Micro-etching uses a micro-etching solution to slightly corrode the copper surface, creating a micro-rough structure.

[0048] In this embodiment, the micro-etching amount is controlled between 1.0 μm and 1.5 μm (because if the micro-etching amount is too small, the copper surface roughness will be insufficient, resulting in poor adhesion of the dry film. If the micro-etching amount is too large, it may corrode the copper layer and affect the circuit). After the pretreatment is completed, the substrate is cleaned with deionized water and dried.

[0049] Then, the film is applied, that is, a photosensitive dry film is applied to the top and bottom surfaces of the insulating substrate (see attached image). Figure 7 ),

[0050] The film is applied using a laminating machine, which rolls and adheres the dry film to the substrate under heat and pressure. The laminating temperature is controlled at 110℃±5℃, the pressure is controlled at 0.5MPa to 0.8MPa, and the laminating time is 30 to 60 seconds. After lamination, the film needs to be left to stand for a period of time to allow the dry film to bond with the substrate.

[0051] Then, a photomask is used to expose the substrate (see attached image). Figure 7 During the curing process, the photomask completely blocks the through-hole area during exposure, meaning the dry film completely covers the through-hole opening. Simultaneously, the photomask retains a circuit pattern between adjacent through-holes, allowing the dry film around each through-hole opening to connect through the circuit pattern area after development.

[0052] In addition, the circuit patterns on the top and bottom surfaces are arranged in an alternating pattern, so that the series-connected conductive lines form a serpentine path (mainly to make full use of the board space).

[0053] The exposure energy can be set from 80mJ / cm² to 120mJ / cm² depending on the dry film type. Too low an energy will result in poor curing of the dry film, which may be washed away during development. Too high an exposure energy may cause over-curing of the dry film, affecting accuracy.

[0054] After exposure, develop the film to remove the uncured areas (see attached image). Figure 8 ),

[0055] The developing agent used has a mass concentration of 0.8% to 1.2%. The solution is used as a developing solution to develop the substrate by spraying.

[0056] In this embodiment, the development time is 30 to 60 seconds, and the spray pressure is 0.15 MPa to 0.25 MPa. During the development process, the dry film areas that are not exposed to ultraviolet light (i.e., uncured areas) dissolve in the developing solution, while the cured areas that have been fully exposed remain on the substrate surface, forming a resist pattern.

[0057] Etching steps (see attached) Figure 8 and physical display of the object before etching. Figure 9 Using the dry film remaining on the substrate surface as a resist layer, the substrate is subjected to acid etching to remove the conductive layer not covered by the dry film.

[0058] In this embodiment, an acidic copper chloride etching solution is used for etching. The copper ions and hydrochloric acid in the etching solution react with the exposed copper layer, dissolving the copper into the etching solution, while the copper layer in the dry film-covered area is protected from etching.

[0059] During the etching process, it is ensured that the copper layer not covered by the dry film is completely removed, avoiding over-etching that could erode the copper layer at the edges of the dry film-covered area. After etching, the conductive layer forms a series circuit between multiple vias. Since the circuit patterns on the top and bottom surfaces are electrically connected through the conductive layer on the via walls, all vias are connected in series to form a loop.

[0060] Then proceed with the film removal step (see attached document). Figure 8 And physical display after film removal Figure 10 Remove the remaining dry film from the substrate surface.

[0061] Specifically, the film removal process involves immersing the substrate in an alkaline solution (such as NaOH solution) at an appropriate temperature to dissolve the dry film and expose the underlying copper circuitry. Once completed, a test board with series conductive lines is obtained. All vias on the test board are connected in series through the conductive layer and copper circuitry to form a complete circuit. If the dry film of any via fails to seal during development or etching, the conductive layer will be eroded by the etching solution, resulting in an open circuit.

[0062] Finally, an electrical test is performed on the conductive lines, and the integrity of the sealing of each through hole is determined based on the test results.

[0063] In this embodiment, a multimeter or a dedicated resistance tester can be used to measure the circuit. If the measured resistance value is less than a preset threshold (e.g., less than 1Ω, etc.), it indicates that the entire series circuit is conducting well, meaning that the dry film sealing of all vias is intact. If the measured resistance value tends to infinity, i.e., an open circuit, it indicates that there is a break point, meaning that at least one via sealing has failed. At this time, the testing personnel can further locate the failed via based on the break point location. By measuring the resistance of the sections before and after the break point, they can determine which via specifically failed to seal.

[0064] Overall, compared with the traditional method that requires visual inspection of each hole, this solution only requires one electrical test to complete the sealing inspection of all through holes, which greatly improves efficiency and eliminates the risk of human error in missing inspection.

[0065] In another embodiment, after the conductive layer is formed by chemical copper plating and electroplating flash plating, the thickness of the conductive layer is controlled to be 3μm to 8μm.

[0066] When the test board is used to test thinner dry films or smaller aperture sealing, the conductive layer thickness can be appropriately reduced to about 3μm to minimize the impact of the copper layer on the aperture wall on the dry film coverage. When used to test thicker dry films or larger aperture sealing, the conductive layer thickness can be increased to about 8μm to ensure that the conductive lines have sufficient strength and conductivity.

[0067] In another embodiment, the vias include three different apertures, namely 0.15mm, 0.20mm and 0.30mm, and the vias of each aperture are arranged into independent test units, and the vias in each test unit are connected in series independently through conductive lines.

[0068] More specifically, three independent test areas are divided on the insulating substrate. The first area is arranged with a matrix of through holes with a diameter of 0.15 mm and connected in series to form the first conductive line. The second area is arranged with a matrix of through holes with a diameter of 0.20 mm and connected in series to form the second conductive line. The third area is arranged with a matrix of through holes with a diameter of 0.30 mm and connected in series to form the third conductive line.

[0069] The three conductive lines are independent and not connected. During testing, electrical tests are performed on the three lines separately, which can simultaneously obtain data on the sealing ability of the dry film for different pore sizes, facilitating analysis and optimization.

[0070] In another embodiment, in addition to performing conventional open-circuit tests, the electrical tests further measure the precise resistance value of the series conductive lines, and determine whether there are any minor sealing defects based on the deviation between the measured resistance value and the theoretical resistance value.

[0071] Specifically, the theoretical resistance value of the series circuit is first calculated based on the resistivity of the conductive layer, the line length, and the cross-sectional area. Then, the measured resistance value is compared with the theoretical value. If the measured value is within the allowable error range of the theoretical value (e.g., ±5%), it is determined that all vias are intact. If the measured value is significantly higher than the theoretical value but there is no open circuit, it indicates that there may be a situation where the copper layer on the wall of some vias is partially corroded but not completely broken. In this case, further confirmation can be made, such as by using a microscope.

[0072] In another embodiment, the temperature of the developer is controlled at 30℃±2℃, and the development time is 40 to 70 seconds. For dry films with greater thickness or weaker photosensitivity, the development time can be slightly extended or the spray pressure increased to ensure that the uncured dry film in the uncured areas is completely removed. For dry films with less thickness or stronger photosensitivity, the development time and spray pressure are shortened to prevent over-development from causing the cured dry film at the apertures to be washed away. After development, the substrate can be thoroughly cleaned with deionized water to remove residual developer and dissolved dry film debris, and then dried before proceeding to the next process.

[0073] The following points need to be explained:

[0074] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0075] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0076] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An electrical testing method for the sealing performance of PCB dry film, characterized in that, Includes the following steps: S1. Provide an insulating substrate and drill a plurality of through holes in the insulating substrate; S2. A conductive layer is formed on the surface of the insulating substrate and on the wall of the through hole; S3. Dry films are attached to the top and bottom surfaces of the insulating substrate, and the dry films are exposed to cure the dry films at the openings of the through holes. An electrical connection is formed between the cured dry film area on the top surface and the cured dry film area on the bottom surface through the conductive layer. S4. The exposed dry film is developed to remove the uncured areas of the dry film. S5. Using the dry film as a resist layer, the insulating substrate is etched to remove the conductive layer not covered by the dry film, so that the remaining conductive layer forms a series conductive line between the multiple vias. S6. Remove the dry film and perform an electrical test on the conductive circuit. Determine the sealing integrity of each through hole based on the electrical test results.

2. The electrical testing method for the sealing performance of PCB dry film according to claim 1, characterized in that, The conductive layer described in step S2 is formed by chemical copper plating and electroplating flash plating. The thickness of the conductive layer is 3-8 μm.

3. The electrical testing method for the sealing performance of PCB dry film according to claim 1, characterized in that, In step S3, a mask is used to completely block the through-hole area during exposure. At the same time, the mask retains a circuit pattern between adjacent through holes, so that the dry film around the opening of each through hole can be connected to each other through the dry film in the circuit pattern area after development.

4. The electrical testing method for the sealing performance of PCB dry film according to claim 1, characterized in that, In step S3, the circuit pattern on the top surface and the circuit pattern on the bottom surface are arranged in an alternating manner, so that the series-connected conductive lines form a serpentine pattern.

5. The electrical testing method for the sealing performance of PCB dry film according to claim 1, characterized in that, The electrical test in step S6 is an open circuit test. If the measured resistance value of the conductive line is less than a preset threshold, it is determined that the sealing of each through hole is complete. If the measured resistance value tends to infinity, it is determined that there is a through hole with a failed seal in the conductive line, and the failed through hole is located according to the location of the open circuit.

6. The electrical testing method for the sealing performance of PCB dry film according to claim 1, characterized in that, The through holes in step S1 include at least two different apertures. The through holes of different apertures are arranged into independent test units, and the through holes in each test unit are connected in series through the conductive line.

7. The electrical testing method for the sealing performance of PCB dry film according to claim 1, characterized in that, Before step S1, there is also a material cutting step, in which FR-4 substrate is selected and cut according to the preset size; in step S1, mechanical drilling is used, and the drilling accuracy is controlled within ±0.05mm.

8. The electrical testing method for the sealing performance of PCB dry film according to claim 1, characterized in that, Before step S3, a pretreatment step is also included, in which the insulating substrate after drilling is subjected to acid washing and micro-etching treatment, and the micro-etching amount is controlled to be 1.0-1.5μm.

9. The electrical testing method for the sealing performance of PCB dry film according to claim 1, characterized in that, In step S3, the dry film is applied using a laminating machine. The laminating temperature is 110±5℃, the pressure is 0.5-0.8MPa, and the laminating time is 30-60s. The exposure energy is 80-120 mJ / cm².

10. The electrical testing method for the sealing performance of PCB dry film according to claim 1, characterized in that, In step S4, the developer used has a mass concentration of 0.8%-1.2%. The solution was developed in 30-60 seconds, and the spray pressure was 0.15-0.25 MPa.

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