A CAF-resistant printed circuit board manufacturing process

Abstract

The application provides a CAF-resistant printed circuit board manufacturing process. At least one floating conductor which is not connected to the network is arranged in the corresponding area of the dielectric layer between adjacent via holes, the surface of the floating conductor has a plurality of sharp protrusions; the floating conductor is synchronously manufactured by inner layer etching; pressing makes the floating conductor encapsulated in the dielectric layer and the projection does not overlap with the drilling position; the floating conductor area is avoided during drilling; and hole metallization and outer layer manufacturing are completed. The application actively captures the migrated copper ions by using the sharp end electric field enhancement effect, consumes the ions on the sacrificial structure, and blocks the growth of the conductive anode wire. The method is fully compatible with the existing PCB process, does not need to increase the hole spacing or use special materials, has low cost, can be applied to high-density and high-voltage products, and significantly improves the CAF resistance and reliability.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board manufacturing technology, and in particular to a process for manufacturing CAF-resistant printed circuit boards. Background Technology

[0002] Printed Circuit Boards (PCBs) are the core interconnect carriers of electronic products. With the rapid development of high-reliability fields such as 5G communication, artificial intelligence, new energy vehicles (especially 800V high-voltage platforms), fast charging equipment, industrial power modules, and aerospace, PCBs are showing significant trends towards higher density, higher voltage, and harsher application environments. Line width / spacing and hole diameter / hole spacing are being continuously compressed; the traditionally considered safe 0.5mm hole spacing has been replaced by designs of 0.2mm or even smaller. Simultaneously, the DC bias voltage and potential difference carried by PCBs have increased significantly (e.g., the operating voltage of automotive main drive controllers reaches 400V~800V). Furthermore, automotive electronics, outdoor base stations, and home appliances are subjected to high-temperature and high-humidity environments for extended periods, requiring stable operation for 10~15 years or more. Under these multiple pressures, conductive anodic filament (CAF) failure has become one of the most significant factors restricting the long-term reliability of PCBs.

[0003] The formation mechanism of CAF is as follows: Under high temperature and high humidity conditions, moisture penetrates into the microscopic interface between the glass fiber bundles and the resin (especially the capillary channels between the glass fiber bundles). Under the action of an electric field, the anolyte copper undergoes electrochemical dissolution, generating copper ions (Cu). 2 + Copper ions migrate along the dielectric / glass fiber interface to the cathode, where they are reduced and deposited as metallic copper. This copper gradually grows to form conductive filaments, eventually leading to short circuits between adjacent conductors (such as between vias or lines). The induction period for CAF failure has shortened from years to months or even weeks, seriously threatening product safety.

[0004] Currently, the industry's manufacturing processes for CAF-resistant printed circuit boards are mainly developing along the following technical routes: (a) Improvements to substrate and copper clad laminate; By using low-hygroscopic resins (such as modified epoxy resins and polyphenylene ether resins), halogen-free materials, adding nanofillers, using open-fiber flat glass fiber cloth (NE-glass), and replacing Dicy curing agents with PN-type curing agents, hygroscopicity can be reduced at its source, and capillary channels between glass fiber bundles can be eliminated. However, these material modification schemes lead to a significant increase in board costs (usually more than 10%), and the addition of PN curing agents makes the boards brittle, affecting the coordination of subsequent drilling, punching, and other processing. In addition, the increased viscosity of high-Tg, halogen-free resins makes it difficult to completely wet the interior of the glass fibers, easily causing microscopic defects such as "resin starvation," which themselves become inducing channels for CAF (Carbon Aerated Fiber) formation.

[0005] (ii) Design optimization; CAF paths can be blocked by increasing the spacing between adjacent vias (such as 15 mil or more as recommended by IPC-2221B), staggering vias to avoid alignment along the fiberglass warp, or setting physical isolation grooves within the board. However, increasing the via spacing directly contradicts the trend towards higher density and is simply not feasible in BGA areas (where the spacing is often less than 0.2 mm). Physical isolation techniques (such as laser cutting and resin filling) require additional processes, demanding extremely high positioning accuracy and equipment, significantly increasing manufacturing costs and production cycles.

[0006] (iii) Manufacturing process control; Microscopic defects in the borehole walls can be reduced by optimizing drilling parameters (to reduce drill bit wear and minimize glass fiber breakage and loosening), precisely controlling the desmear process (to avoid excessive erosion that could damage the resin / glass fiber interface), and using plasma cleaning to clean the borehole walls. However, the optimization window for these process parameters is extremely narrow, requiring very high operational consistency and making them highly susceptible to human error. For example, insufficient desmearing can lead to unclean borehole walls, while excessive desmearing can widen the gap between the glass fiber and the resin. Furthermore, the final verification of CAF performance requires rigorous accelerated aging tests (e.g., 85℃ / 85%RH, 500~1000 hours), which have an extremely long testing cycle and cannot be used for online feedback during production. This post-production verification results in a high risk of defective products being released. Summary of the Invention

[0007] In view of the above, the main objective of this invention is to propose a CAF-resistant printed circuit board manufacturing process to solve the aforementioned technical problems.

[0008] This invention proposes a CAF-resistant printed circuit board manufacturing process, the method comprising the following steps: Step 1: Obtain the location information of adjacent vias and the pattern information of inner layer copper foil in the PCB inner layer design. In the corresponding area of ​​the dielectric layer between two adjacent vias, set at least one floating conductor that is not connected to any electrical network. The surface of the floating conductor has the tip of multiple sharp protrusion structures. Step 2: Using conventional inner core board etching process, floating conductor patterns are simultaneously fabricated while signal lines are being made, so that the floating conductors are of the same material and thickness as the inner copper foil, resulting in an inner core board containing floating conductors. Step 3: Press the inner core board containing the floating conductor into a multilayer board stack structure so that the floating conductor is encapsulated inside the dielectric layer and the vertical projection does not overlap with the drilling position of two adjacent vias to obtain the pressed inner core board. Step 4: Drill holes in the laminated inner core board according to the set drilling parameters to form vias, and obtain the drilled PCB semi-finished product; the drilling location should avoid the area where the floating conductor is located. Step 5: After drilling, the PCB semi-finished product is subjected to hole metallization, outer layer circuit fabrication, and solder mask coating to obtain a CAF-resistant printed circuit board containing a floating ion trapping structure.

[0009] Compared with the prior art, the beneficial effects of the present invention are as follows: Compared with the prior art, the CAF-resistant printed circuit board manufacturing method provided by the present invention has the following significant advantages: 1. Innovative Principle: Shifting from passive blocking to active attrition; This invention departs from the traditional passive defense approach of CAF resistance technology, which simply blocks the path or eliminates moisture / electric field. Instead, it creatively incorporates isolated, sharply protruding floating conductors (i.e., "floating conductors") within the dielectric layer between adjacent vias. Utilizing the tip field enhancement effect in electrochemistry (field enhancement factor β = 1 + h / r), migrating copper ions are actively attracted and deposited at the tips of the floating conductors, thus creating a "sacrificial ion trap" along the main CAF path. This mechanism transforms "blocking" into "dredging," consuming migrating ions at the source and fundamentally blocking the continuous growth of the conductive anode wire. Experimental data shows that at 85℃ / 85%RH and a 100V bias, the insulation resistance of the test board containing the floating conductors remains at 4 × 10⁻⁶ after 500 hours. 11 The Ω value was above 10, while the control plate without a floating conductor had decreased to 10 after 500 hours. 4 The effect is on the order of Ω (failure), with an improvement of more than 7 orders of magnitude.

[0010] 2. Fully compatible with existing processes, with almost zero incremental cost; The patterning of the floating conductor can be created simultaneously during the inner core board etching step by modifying the photoplot file, without requiring any additional equipment, materials, or processes. Compared to existing technologies that use special CAF-resistant boards (increasing costs by more than 10%) or add laser isolation grooves (complex processes and expensive equipment), this invention only increases design and photoplotting costs by a very small amount (calculated to be less than 0.5 yuan per square meter of PCB), making it extremely economical. Furthermore, the manufacturing method is completely integrated into the conventional PCB production process, requiring no modifications to the production line and facilitating rapid deployment.

[0011] 3. Does not sacrifice wiring density, compatible with high-density designs; The maximum outer diameter of the floating conductor is much smaller than the spacing between adjacent vias (typically only 1 / 5 to 1 / 3 of the spacing), and it is located near the perpendicular bisector of the line connecting the two vias, occupying a very small area of ​​the plane. Unlike existing technologies that reduce CAF risk by increasing the via spacing (≥0.38mm), this invention requires no additional space and can be applied to high-density areas with via spacing ≤0.2mm (such as under BGAs, memory interfaces, etc.), highly compatible with the trend of miniaturization and high integration in electronic products.

[0012] 4. The process is highly robust, reducing reliance on drilling / degumming precision; Existing CAF-resistant processes have extremely stringent requirements for drilling quality (avoiding fiberglass breakage and wick length) and the uniformity of desmearing, resulting in a narrow process window and large yield fluctuations. This invention utilizes an active trapping mechanism with a floating conductor. Even with slight fiberglass protrusions or microcracks on the hole wall, migrating ions are preferentially attracted to the floating conductor before reaching the opposite via, significantly reducing sensitivity to drilling and Desmear parameters. Experiments show that under equally poor drilling conditions (4 drill bit re-grinding cycles, feed rate 1.0 m / min), the insulation resistance of the test board containing the floating conductor is still two orders of magnitude higher than that of the superior process board without the floating conductor after 500 hours. This invention improves overall process robustness and is beneficial for mass production stability.

[0013] 5. Shorten the reliability verification cycle; Traditional CAF performance verification takes 500-1000 hours (85℃ / 85%RH), severely impacting product development and delivery cycles. This invention utilizes the property of floating conductors to preemptively consume migrating ions, allowing for rapid assessment of CAF resistance margins by observing the copper deposition morphology at the tip of the floating conductor or measuring the rate of decrease in insulation resistance within a shorter timeframe (e.g., 100-200 hours). This accelerated evaluation method can shorten the verification cycle by more than 50%, facilitating more timely quality feedback during production and reducing the risk of defective products.

[0014] 6. Differentiated design to adapt to different voltage / spacing requirements; This invention allows for the independent design of the shape and tip radius of curvature of each floating conductor on the same PCB, based on the via spacing and operating voltage of different areas. This is achieved through the relationship r. i ≤ h i / [(E) CAFthreshold / E i [1] By determining appropriate parameters, the capture effect can be achieved in the high-voltage region while avoiding over-design in the low-voltage region. This differentiated design strategy optimizes the balance between cost and performance.

[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by means of embodiments of the invention. Attached Figure Description

[0016] Figure 1 This is a graph showing the change in insulation resistance over time according to the present invention. Figure 2 This is a diagram illustrating the lifespan extension effect of the three-dimensional relay network of the present invention. Figure 3 This is a comparison diagram of the insulation resistance of different floating conductor shapes according to the present invention; Figure 4 This is a comparison chart of deposition coverage for different floating conductor shapes according to the present invention; Figure 5 A comparison chart of the standard deviation of insulation resistance measurements for different floating conductor shapes according to the present invention; Figure 6 This invention presents insulation resistance performance diagrams for 500 hours under different tip curvature radii. Figure 7 The diagram shows the electric field enhancement factor β performance of this invention under different tip curvature radii. Figure 8 This is a comparison chart of the standard deviation of insulation resistance measurements under different tip curvature radii in this invention; Figure 9 This is a comparison chart of the insulation resistance over 500 hours under the condition of no floating conductor in this invention. Figure 10 This is a comparison chart of the insulation resistance over 500 hours under the condition of a floating conductor in this invention; Figure 11 This is a graph showing the boost factor of the present invention under conditions with and without a floating conductor. Detailed Implementation

[0017] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0018] These and other aspects of the embodiments of the present invention will become clear from the following description and accompanying drawings. In these descriptions and drawings, some specific embodiments of the present invention are specifically disclosed to illustrate some ways of implementing the principles of the embodiments of the present invention; however, it should be understood that the scope of the embodiments of the present invention is not limited thereto.

[0019] I. Preparation of materials and equipment; (a) Substrate selection; High-Tg halogen-free copper clad laminate, model S1000-2M, was selected. It has a Tg ≥ 170℃, dielectric constant Dk = 4.2@1MHz, and dielectric breakdown strength ≥ 40kV / mm. This material uses a PN-type curing agent system, exhibiting low hygroscopicity and high thermal decomposition resistance. The inner core board thicknesses are 0.1mm (L2-L3, L4-L5, L6-L7, L8-L9) and 0.2mm (L1-L2, L9-L10). The copper foil thickness is 1oz (35μm). Incoming material inspection of the selected substrate was conducted, including resin content (65.2% measured), gel time (110 seconds), and flowability (18%), all of which met the requirements of IPC-4101 standard.

[0020] (ii) Other materials; Prepreg: Type 1080, resin content 65%, thickness 0.075mm, using PN type curing agent system. Bake in a low-temperature oven (60℃) for 2 hours before use to remove moisture.

[0021] Drilling pad: Phenolic resin composite board, 2.5mm thick, hardness 85 Shore D, with good support and chip removal ability.

[0022] Drill bit: made of tungsten carbide, 0.2mm in diameter, with a cutting edge angle of 130° and a helix angle of 35°. The number of re-grinding cycles is controlled to ≤3. Each batch of drill bits undergoes microscopic inspection before use, ensuring the cutting edge is free of chips or defects.

[0023] Desmear solution: an alkaline potassium permanganate system containing wetting agents and pore-forming agents. The specific composition is: KMnO4 60g / L, NaOH 40g / L, wetting agent (sodium dodecyl sulfate) 0.5g / L.

[0024] Electroplating solution: acidic copper sulfate system, with additives of sodium polydisulfide dipropane sulfonate (SPS) 1.5 mg / L, polyethylene glycol (PEG8000) 200 mg / L and Janus Green B 0.5 mg / L.

[0025] Solder resist ink: Photosensitive green ink, the main component of which is acrylate-modified epoxy resin.

[0026] (III) Major Equipment; Photoplotter: LDI direct imaging device with a resolution of 15μm, alignment accuracy of ±5μm, and a light source wavelength of 405nm.

[0027] Etching lines: Horizontal spray etching, etchant is ferric chloride / hydrochloric acid system, temperature 45℃, spray pressure adjustable (1.0~1.5kg / cm²). 2 The transmission speed is adjustable (1.5~2.5m / min).

[0028] Vacuum press: Maximum temperature 260℃, pressure range 100~450N / cm 2+ Vacuum degree ≤10mmHg.

[0029] Drilling machine: Six-axis high-speed drilling machine with adjustable spindle speed from 60 to 160 krpm, positioning accuracy of ±10 μm (using X-ray pre-alignment enhancement), and equipped with a broken tool detection device.

[0030] Degumming line: Alkali washing → potassium permanganate degumming → neutralization → water washing, potassium permanganate concentration 50~70g / L, temperature 75~85℃, treatment time 10~20min adjustable.

[0031] Electroplating line: Vertical continuous electroplating, current density adjustable from 10 to 30 ASF, rectifier accuracy ±2%.

[0032] Test equipment: Keysight B2985A insulation resistance meter (measuring range 10) 2 ~10 16 Ω, test voltage adjustable up to 1000V), FEI Quanta 200 scanning electron microscope (with energy dispersive spectroscopy, resolution 3.5nm), constant temperature and humidity chamber (temperature range -40℃~150℃, humidity range 20%~98%RH, accuracy ±0.5℃ / ±3%RH).

[0033] Example 1 This embodiment provides a method for manufacturing a CAF-resistant printed circuit board. This method involves placing floating conductive bodies with sharp protrusions in the dielectric layer between adjacent vias. The electric field tip effect is used to actively capture migrating copper ions, thereby fundamentally inhibiting the formation and growth of conductive anode wires. This embodiment uses a 10-layer board (layer structure L1 to L10) as an example. This board is used in the battery management system (BMS) of new energy vehicles, and its CAF resistance performance is required to meet the AEC-Q200 standard. The board thickness is 1.6 mm, the minimum via diameter is 0.2 mm, the center-to-center distance between adjacent vias is 0.6 mm (after modification to ensure manufacturability), and the operating voltage is 400 V.

[0034] Step 1: Inner layer circuit pattern design and photoplotting Obtain the PCB design file (Gerber format), which contains the inner layer signal traces, power / ground planes, and via locations for layers L2, L3, L4, L5, L6, L7, L8, and L9. Use InCAM Pro software for graphic editing and DFM inspection. In this embodiment, focus is placed on two adjacent vias on layer L2: via A (coordinates X=10.000mm, Y=10.000mm) and via B (coordinates X=10.600mm, Y=10.000mm), with a center distance L=0.6mm.

[0035] According to the method of the present invention, a floating conductor is designed in the corresponding region of the dielectric layer between via A and via B (i.e., on the L2 layer copper foil surface). The floating conductor has a star-shaped planar shape with 6 tips, each tip having a radius of curvature of 3 μm, and the spacing between adjacent tips is 15 μm. The maximum outer circle diameter of the floating conductor is D = 0.10 mm. The center of the floating conductor is located on the perpendicular bisector of the line connecting via A and via B, i.e., coordinates (10.300 mm, 10.000 mm), and the perpendicular distance from the centers of the two vias is d = 0 mm (located at the midpoint of the line connecting them). According to the relationships d ≤ L / 4 (0 ≤ 0.15) and D ≤ L / 3 (0.10 ≤ 0.20), the conditions are met.

[0036] The center X of via A is 10.000mm, and the hole diameter is 0.2mm. Therefore, the rightmost X of the hole wall is 10.000 + 0.1 = 10.100mm. The coordinates of the leftmost edge of the floating conductor are 10.300 - D / 2 = 10.300 - 0.05 = 10.250mm. Therefore, the actual minimum clearance from the hole wall of via A to the edge of the floating conductor is 10.250 - 10.100 = 0.15mm = 150μm. Drilling safety distance requirement: According to the design in subsequent step 4, a high-precision drilling machine (alignment tolerance t) is used. alignment =10μm), drill bit radius r drill=0.1mm, with a safety margin of 0.02mm, the required minimum clearance is 10+100+20=130μm. The actual clearance of 150μm is greater than 130μm, which meets the safety drilling requirements. At the same time, the leftmost edge of the wall of hole B is X=10.600-0.1=10.500mm, and the rightmost edge of the floating conductor is 10.300+0.05=10.350mm. The clearance is 10.500-10.350=0.15mm, which also meets the requirements.

[0037] The floating conductors are not connected to any network and are considered to be floating structures. Similarly, floating conductors are also placed between other adjacent vias in the L2 layer, but only the pair mentioned above is described in this example. For areas with via spacing less than 0.5 mm, calculations show that a 0.10 mm diameter floating conductor cannot be accommodated while maintaining a safe clearance; therefore, floating conductors are not used, and conventional processes are employed. This indicates that the present invention is suitable for scenarios with via spacing ≥ 0.5 mm.

[0038] Subsequently, the Gerber file containing the floating conductor pattern was imported into an LDI photoplotter, and imaged directly onto the copper foil surface of the inner core board to form a negative photoresist pattern, resulting in an inner core board with a negative photoresist pattern. The exposure energy was set to 120 mJ / cm². 2 The developing solution was 1% Na2CO3 solution, the developing temperature was 30℃, and the developing time was 60 seconds.

[0039] The deviation Δ between the center of the floating conductor and the perpendicular bisector of the line connecting the two vias should satisfy: Δ ≤ 0.1 × L, where L is the length of the line connecting the centers of two adjacent vias. When Δ exceeds this range, the floating conductor deviates from the main electric field migration channel, and the capture efficiency decreases significantly. Simulation results show that when Δ = 0.1L, the effective electric field enhancement factor at the tip decreases by about 12%, which is still acceptable; when Δ = 0.2L, the decrease exceeds 35%, and it is no longer recommended. Therefore, Δ ≤ 0.1L is the preferred design range.

[0040] Step 2: Simultaneous fabrication of floating conductors during inner layer circuit etching The L2 layer core board was processed using horizontal etching lines. Etching solution parameters: FeCl3 concentration 280 g / L, HCl concentration 25 ml / L, temperature 45℃, spraying pressure 1.2 kg / cm². 2 The transmission speed is 1.8 m / min. After etching, the copper foil not protected by photoresist is removed, leaving signal lines and floating conductor patterns. The floating conductors are the same thickness as the signal lines (35 μm) and have neat edges without burrs, resulting in the etched inner core board.

[0041] After etching, the photoresist was removed using a 3% NaOH solution at 50°C for 90 seconds. Then, the core board was washed with hot water (50°C), acid (5% H2SO4), pure water, and dried to obtain an inner core board with a floating conductor.

[0042] The radius of curvature of the floating conductor's tip was measured using a three-dimensional microscope. The actual measured values ​​were 2.9 μm, 3.1 μm, and 3.0 μm (average 3.0 μm), which meets the design requirement of ≤5 μm. The measured distance between adjacent tips was 14.8 μm, 15.2 μm, and 14.9 μm (average 14.97 μm), meeting the requirement of ≤20 μm. The dimensional deviation between the floating conductor pattern and the design drawing is ≤±2 μm, meeting the inner layer circuitry manufacturing tolerance requirements.

[0043] Step 3: Blackening and Lamination The L2 inner core board undergoes a blackening treatment to improve its adhesion to the prepreg. The blackening solution composition is: NaOH 45g / L, NaClO 230g / L, Na3PO4 25g / L; temperature 85℃; treatment time 6min. Post-blackening water rinsing requirements: the conductivity of the final pure water rinse must be ≤2μS / cm to remove residual alkali and reaction products, avoiding interference with resin curing. The blackened film thickness is controlled between 0.6~0.8μm (confirmed by SEM cross-sectional measurement).

[0044] The lamination structure is as follows: L1 (copper foil) → 1 x 1080 prepreg → L2 core board (containing floating conductor) → 2 x 1080 prepreg → L3 core board → 1 x 1080 → L4 core board → ... → L10 (copper foil). Lamination is performed in a vacuum press with the following parameters: heating rate 1.5℃ / min, holding at 190℃ for 40min (to initially soften the resin and fill the microstructure of the core board surface), then heating to 210℃ and holding for 90min (for complete curing), with a pressure of 350 N / cm throughout. 2 The cooling stage uses water cooling at a rate of 2℃ / min to room temperature. After pressing, the plate thickness tolerance is measured to be ±0.05mm.

[0045] After lamination, the floating conductor is encapsulated within the dielectric layer. For the L2 layer floating conductor, the thickness h of the upper dielectric layer (approximately 0.06 mm after lamination of the 1080 prepreg between L1 and L2) is... top ≈58μm, the thickness of the underlying dielectric layer (approximately 0.12mm after lamination of two 1080 prepreg sheets between L2 and L3) is h. bottom ≈115μm, maximum height h of the tip protrusion of the floating conductor protrusion =35μm (i.e., copper foil thickness), therefore h top ≥h protrusion +5μm (58≥40), h bottom ≥hprotrusion +5μm (115≥40) meets the minimum coating requirement.

[0046] Step 4: Drilling and Avoidance According to the design documents, through holes A and B (and other through holes) need to be drilled. Drilling parameters: spindle speed 100 rpm, feed rate 0.8 m / min, depth of cut 0.2 mm per pass (3 passes to complete a 0.6 mm plate thickness), retraction rate 5 m / min. Drill bit re-grinding times: second use (3 times allowed in total). Drill bit diameter 0.2 mm, alignment tolerance t. alignment =10μm (using an X-ray positioning system, alignment is performed through a pre-drilled target hole).

[0047] Before drilling, a safety distance threshold is set in the drilling program based on the coordinate data of the floating conductor in Gerber. As calculated before, the actual distance from the wall of via A to the edge of the floating conductor is 150 μm, satisfying d clear =150μm ≥ t alignment + r drill + 0.02mm = 10μm + 100μm + 20μm = 130μm. During drilling, X-ray drill target positioning ensures a deviation ≤10μm. Spindle load and drill bit wear are monitored during drilling, and hole position accuracy is checked every 1000 holes. After actual drilling, AOI is used to check hole position offset; the maximum offset is 8μm, and the floating conductor is not damaged.

[0048] After drilling is completed, the hole wall quality is inspected. The hole wall profile is observed using a metallographic microscope. The hole diameter (maximum depth of concavity and convexity) is ≤15μm and the wick length (the length of copper penetration caused by resin shrinkage in the glass fiber) is ≤35μm, both of which are better than ordinary processes (ordinary processes typically have a hole diameter ≤25μm and a wick length ≤50μm).

[0049] To ensure that drilling does not damage the floating conductor, the minimum safe distance d between the drilling location and the outline of the floating conductor is... clear It should satisfy: d clear ≥ t alignment + r drill + 0.05 mm; where t alignment The positioning tolerance for drilling equipment (unit: mm), r drill The value represents the drill bit radius (unit: mm), with 0.05 mm being the recommended safety margin. This value is determined based on engineering experience and statistical analysis of borehole offsets from multiple batches, and can be adjusted within ±10%. Example 1 uses a 0.02 mm margin suitable for high-precision equipment; 0.05 mm is recommended for conventional equipment.

[0050] Step 5: Removal of adhesive residue and metallization of holes After drilling, residual adhesive residue (approximately 1-3 μm thick) remained on the borehole wall. This residue was removed using an alkaline potassium permanganate system. Parameters: NaOH 40 g / L, KMnO4 60 g / L, temperature 80℃, treatment time 15 min. Then, neutralization was performed (H2SO4 5% + H2O 2%), temperature 45℃, time 5 min. After removing the adhesive residue, the borehole wall roughness was controlled at 0.5-1.0 μm, with no residual adhesive residue.

[0051] After washing, copper was electroless plated onto the hole walls: First, activation was performed (PdCl2 0.5 g / L, HCl 100 ml / L, temperature 30℃, time 3 min) to adsorb palladium particles on the hole wall surface as catalytic centers; then, copper was electroless plated (CuSO4·5H2O 10 g / L, formaldehyde 5 g / L, NaOH 8 g / L, temperature 45℃, time 20 min), with a deposition thickness of approximately 0.5 μm. Subsequently, electroplating was performed across the entire board to thicken the copper: current density 20 ASF, electroplating time 60 min, resulting in a final copper thickness ≥25 μm on the hole walls. After electroplating, a backlight test (out of 10 levels) was conducted, achieving a level of 9 or higher, indicating good hole wall coverage.

[0052] During this process, the floating conductor, being completely encapsulated by the dielectric layer and not connected to the hole, does not participate in the electroplating reaction and remains in its original state.

[0053] Step 6: Outer layer circuit fabrication and solder mask application The outer layers L1 and L10 were fabricated using conventional processes: dry film (DuPont FX930, 38μm thickness) was applied, followed by exposure (energy 40mJ / cm). 2 The process involves development (1% Na2CO3, 30℃), etching (CuCl2 system), and stripping (3% NaOH). Then, photosensitive solder resist ink (green) is applied, pre-baked (75℃, 30 min), and exposed (energy 300 mJ / cm²). 2 The solder resist layer is developed (1% Na2CO3, 30℃) and then cured by baking (150℃, 60min). The solder resist layer thickness is ≥15μm, and the adhesion and hardness meet the IPC-SM-840 standard.

[0054] Finally, surface treatment is performed: lead-free tin plating (tin-silver-copper alloy, temperature 260℃, time 3 seconds) is used to obtain good solderability and oxidation resistance.

[0055] Example 2 After the entire board is fabricated, test modules containing target via pairs (via A and via B) with floating conductors are cut from the finished board, along with control modules without floating conductors (same stack-up, same via spacing, but without floating conductors). Test electrodes are led out from each module, using gold-plated pads and phosphor bronze spring pins for contact.

[0056] The two sets of test modules were placed in a constant temperature and humidity chamber under the following conditions: 85℃ / 85%RH, with a bias voltage V applied. bias =100V (DC positive terminal A, negative terminal B). Accelerated aging test was performed according to IPC-TM-650 method 2.6.25, and the insulation resistance R was monitored online. iso The test lasted 1000 hours, with data recorded every 24 hours. The test results are shown in Table 1. Table 1:

[0057]

[0058] The results show that the insulation resistance of the module without floating conductors drops to 10 after 500 hours. 4 The value is on the order of Ω, which is below the failure threshold (typically 1×10). 6 Ω is considered to be formed by CAF. The module containing the floating conductor still maintains 2.8 × 10⁻⁶ after 1000 hours. 11 The resistance Ω is much higher than the threshold. The insulation resistance of the module with floating conductors decreases significantly slower than that of the control module, indicating that the floating conductors effectively delay the formation of CAF.

[0059] After testing, the module containing the floating conductor was sliced ​​and its surface observed under a scanning electron microscope. The results showed significant copper deposits at the tip of the floating conductor, which were confirmed by energy dispersive spectroscopy (EDS) to be copper (characteristic Cu peak at 8.05 keV). The deposit thickness was approximately 1.2–1.6 μm (measured by SEM cross-section), and the deposited area accounted for about 55% of the total tip surface area. The fact that it did not completely cover the entire tip indicates that the floating conductor still has sufficient capacity to continue operating.

[0060] To quantitatively evaluate the performance advantages of the three-dimensional relay network compared to the traditional single-layer floating conductor, this embodiment conducted an insulation resistance comparison experiment under the same test conditions (85℃ / 85%RH, 400V bias). The single-layer floating conductor comparison only included an L2 layer floating conductor, without the L4 / L6 layer relay structure; the three-layer relay network comparison included L2, L4, and L6 layers of floating conductors, interconnected through micro-vias, with the L4 / L6 layers pre-tin-plated. The sample size for each group was n=10, and the results were taken as the median. The test results are shown in Table 2: Table 2:

[0061]

[0062] As can be seen from Table 2, the insulation resistance of the single-layer floating conductor drops to 10 ohms after approximately 1200 hours. 7 Ω (less than 1×10)8 The typical failure threshold of Ω further decreased to 3.2 × 10⁻⁶ at 1350 hours. 5 Ω, completely failed. Meanwhile, in the three-layer three-dimensional relay network, the L2 floating conductor nearly saturated after 950 hours, and the insulation resistance briefly dropped to 8.6 × 10⁻⁶. 9 Ω, then triggered again at around 1000 hours, the pre-plated tin of layer L4 began to melt and deposit, causing the insulation resistance to rise back to 5.6 × 10 Ω. 9 Ω (1050h) and further reached a peak value of 8.2×10 9 Ω (1100h). Afterward, the insulation resistance decreased slowly, but remained at 6.3 × 10⁻⁶ at 2000 hours. 8 Ω, which is higher than the failure threshold.

[0063] As can be seen from the comparison, the three-dimensional relay network will effectively resist CAF lifetime (insulation resistance ≥10). 8 The lifespan of the single-layer floating conductor (Ω) has been extended from approximately 1200 hours to over 2000 hours, an increase of 67%. If more relay layers are added (such as L2+L4+L6+L8), the expected lifespan can be further extended to over 3000 hours.

[0064] The 500-hour test was divided into five 100-hour periods. The average insulation resistance for each period was calculated (using the logarithmic mean for a more accurate estimate), and the average leakage current was calculated. These values ​​were then summed to obtain the total charge. The data are shown in Table 3. Table 3:

[0065] However, the above calculations only consider the leakage current caused by the decrease in insulation resistance. In reality, before the formation of the CAF, there is also a leakage current (approximately 10) through the dielectric body. -11 (A-level) and Faraday current generated during the deposition process of floating conductors. A more accurate method is to measure directly using a high-precision picoammeter. In actual testing, the current measurement function of the Keysight B2985A was used, and the current value was recorded every 10 minutes. The total charge Q over 500 hours was obtained by integration. total = 0.382 C.

[0066] According to Faraday's law, the theoretical mass of deposited copper is m = (Q total× M) / (n × F) = (0.382 ×63.55) / (2 × 96485) = 24.28 / 192970 ≈ 0.1258 mg. The EDS measured deposited copper mass was 0.108 mg, with a difference of approximately 14.2%. Considering that the deposition efficiency is not 100% (some copper ions may be reduced and detached, or deposited on the hole wall instead of the floating conductor), and measurement error, this difference is within a reasonable engineering range (typically ±20%).

[0067] The critical charge Q required for the tip of a floating conductor to be completely covered by copper deposition crit satisfy: Q crit = (ρ Cu × A tip × δ min (× n × F) / M; Where, ρ Cu The density of copper is 8.96 g / cm³. 3 ), δ min The minimum deposition thickness required to effectively block CAF (typically 0.5–1.0 μm) is n=2, F=96485 C / mol, and M=63.55 g / mol. This is when the actual passing charge Q ≥ Q crit When the floating conductor reaches saturation, the relay capture mechanism needs to be activated.

[0068] Example 3 This embodiment connects a high-impedance wire between the floating conductor and ground to stabilize its potential. Specifically, a thin copper wire with a width w = 0.02 mm and a length l = 0.8 mm extends from the edge of the floating conductor and connects to the grounded copper foil of layer L2. The copper foil thickness t = 35 μm and resistivity ρ = 1.72 × 10⁻⁶. -8 Ω·m. Calculate the resistance R of the wire. w = ρ×l / (w×t) = 1.72e-8×0.0008 / (0.00002×0.000035)= 1.376e-11 / (7e-10)=19.66Ω, which is much less than 1MΩ. This does not meet the requirements. Therefore, a nickel-chromium alloy resistive paste was used to print the resistive segment: a thick-film resistor (resistive paste model ESL 2914, sheet resistance 10kΩ / □) was screen-printed above the thin copper wire, and the resistance was adjusted to 2MΩ by adjusting the printing length and width. At this time, the leakage current I... leak= 100V / 2MΩ = 50nA, higher than the target of 1nA. Further increasing the resistance to 100MΩ would reduce the leakage current to 1nA. In actual production, laser trimming was used to locally cut a thin copper wire into a serpentine pattern (0.01mm line width, 0.005mm cut width, 10 round trips), achieving an equivalent resistance of 120MΩ. The tested leakage current was 0.83nA, meeting the requirements.

[0069] Test results show that the potential of the grounded floating conductor is clamped to near 0V (actual measurement 0.83mV), further enhancing its attraction to copper ions. Under the same conditions of 85℃ / 85%RH and 500 hours, the insulation resistance is increased by about an order of magnitude compared to the floating conductor (reaching 5.2×10⁻⁶). 11 (Ω), the copper deposition coverage increased from 42% to 58%.

[0070] When a floating conductor is connected to a fixed potential through a high-impedance wire, the resistance R of that wire is... w From the square resistance R sq The length l and width w determine: R w = R sq × (l / w). For a typical 1 oz copper foil, R sq ≈ 0.5 mΩ / sq, to ​​make the leakage current I leak = V bias / R w ≤ 1 nA(V bias (for operating voltage), R is required. w ≥ 1 MΩ. If copper wire cannot meet this requirement, nickel-chromium alloy resistive paste or serpentine wire can be used. This design ensures that the floating conductor does not become an additional leakage path.

[0071] Example 4 This embodiment addresses the scenario where different via spacings and operating voltages exist at different locations on the same PCB, and differentiates the tip curvature radius of each floating conductor. The design target is a server motherboard containing multiple BGA areas.

[0072] (a) Area 1: Near DDR5 memory, via spacing L1 = 0.3mm, operating voltage V1 = 1.2V. The dielectric material is Megtron 6, with a relative permittivity ε. r =3.7, critical breakdown field strength E crit =30kV / mm. The safety factor η is taken as 1.2. Calculate the upper limit of the tip curvature radius: First, calculate the electric field strength E1 = V1 / L1 = 1.2 / 0.3 = 4 V / mm, which is much smaller than E. crit However, to ensure effective capture, an electric field enhancement factor β is required such that β×E1 ≥ E.CAFthreshold CAF critical electric field strength E CAFthreshold The typical value is 1 kV / mm (according to the IPC-TM-650 standard, the CAF-induced field strength of FR-4 material at 85℃ / 85%RH is approximately 0.5~2 kV / mm). Therefore, β needs to be ≥ 1000 / 4 = 250. From β = 1 + h tip / r tip Take h tip =Copper thickness=35μm, then 1+35 / r tip ≥ 250 => 35 / r tip ≥ 249 =>r tip ≤ 35 / 249 ≈ 0.14μm. This is too demanding to achieve with conventional lithography (conventional LDI resolution is 15μm, contact lithography can reach 5μm, and electron beam lithography can reach 0.1μm but the cost is extremely high). Solution: Reduce h tip This means using a thin copper foil (12μm). At this point, r tip ≤ 12 / 249 ≈ 0.048μm, still not achievable. Therefore, it is not possible to capture at very low voltages simply by relying on the tip effect. No floating conductor is set in this region; conventional processes are sufficient. This indicates that the present invention is suitable for higher voltage scenarios (typically operating voltage ≥24V).

[0073] (II) Area 2: Near the power module, via spacing L2 = 0.5mm, operating voltage V2 = 48V. E2 = 96V / mm, requiring β ≥ 1000 / 96 ≈ 10.42. 12μm copper foil is used. tip ≤ 12 / (10.42-1)=12 / 9.42≈1.27μm. This can be achieved through electron beam lithography, but the cost is high (approximately $500 per wafer-level processing cost). Using h... tip =5μm (semi-additive method fabrication: first chemically plate a thin copper layer of 1μm, then electroplate the pattern to thicken it to 5μm), then r tip ≤5 / 9.42≈0.53μm, still very small. In this embodiment, the floating conductor is actually fabricated into multiple tiny pyramid arrays (nanoimprinting), with a tip curvature radius of 0.5μm. Fabrication method: First, a nanoimprinting adhesive (200nm thick) is coated on the copper foil of the core board. A pyramid-shaped pit (2μm side length, 1.5μm height) is formed using a silicon mold. Then, copper is filled by electroforming, and after demolding, a nanoscale tip is obtained. This process is feasible but relatively complex and is only used for demonstration purposes. For simplicity, this embodiment does not use this area.

[0074] (III) Area 3: Electric vehicle main drive controller, via spacing L3 = 0.8mm, operating voltage V3 = 400V. E3 = 500V / mm, requiring β ≥ 1000 / 500 = 2. 35μm copper foil is used. tip ≤ 35 / (2-1)=35μm, which is easily satisfied. Therefore, the designed radius of curvature is 30μm, the tip height is 35μm, and β=1+35 / 30≈2.17, which meets the requirements. In actual fabrication, conventional LDI lithography is used, and the radius of curvature is naturally formed by the etching process, with a measured value of approximately 28~32μm.

[0075] In this embodiment, multiple regions are independently equipped with floating conductors, which are not connected to each other. The size and shape of each floating conductor are designed according to local conditions: the floating conductor in region 3 has a diameter of 0.12 mm and a tip curvature radius of 30 μm; other regions are treated separately depending on whether floating conductors are required.

[0076] Example 5 In the 10-layer board, floating conductors are respectively installed in layers L2, L4, L6, and L8, and the floating conductors in each layer partially overlap in the vertical projection (the overlapping area is 30% of the area of ​​a single floating conductor). The floating conductors in each layer are interconnected through micro-vias with a diameter of 0.08 mm, and the inner walls of the micro-vias are plated with copper (20 μm thick). In addition, a layer of tin (2 μm thick) is pre-plated on the tip surface of the floating conductors in layers L4 and L6 as a reserve of reactive metal. The tin plating solution composition is: SnSO4 40 g / L, H2SO4 100 ml / L, additive (gelatin 2 g / L), current density 15 ASF, time 5 min.

[0077] Initially, the L2 layer floating conductor is grounded via a high-impedance wire (100MΩ), with a potential close to 0V (actually measured at 0.02V). The potential of the anode via A is +400V. As the test progresses, copper ions migrate from via A and deposit on the L2 floating conductor. As the deposited copper gradually thickens, covering most of the tip, the equivalent resistance R between the L2 floating conductor and via A increases. eq Significant decrease.

[0078] R eq The change can be obtained through measurement: initial R eq >10 12 Ω; When deposited copper covers approximately 50% of the tip, R eq Dropped to about 10 7 Ω; when 80% coverage, R eq Dropped to about 10 6 Ω; when 95% coverage is achieved, R eq Dropped to about 10 5 On the order of Ω. According to the principle of voltage divider, the potential of the floating conductor L2, V...capture2 ≈ V bias × (R ground / (R eq + R ground )), where R ground = 100 MΩ. When R eq Reduced to 10 5 When Ω, V capture2 ≈ 400 × (1e8 / (1e5+1e8)) ≈ 399.6 V, meaning the potential of the floating conductor is close to the anode potential.

[0079] This potential change is directly conducted to the L4 floating conductor through a low-resistance micro-via (0.08 mm in diameter, 25 μm thick copper inner wall, and approximately 1 Ω resistance), creating a potential difference of approximately 400 V between the L4 and L2 floating conductors (L2 island ≈ 400 V, L4 island initially ≈ 0 V). The tin (Sn) pre-plated on the surface of the L4 floating conductor undergoes anodic dissolution under this potential difference: Sn → Sn 2+ + 2e - The standard electrode potential E°(Sn) for this reaction 2+ / Sn) = -0.14V, while Cu 2+ The E° of / Cu is +0.34V. Tin is more reactive than copper and therefore dissolves preferentially.

[0080] The dissolution of tin follows Faraday's law. Let the dissolution current be I and the dissolution time be t, then the total number of moles of tin ions released is n. ion satisfy: n ion = (I × t) / (z × F); Where z=2 (tin ion Sn) 2+ ), F=96485 C / mol.

[0081] In the experiment, when the L2 island saturated and triggered the relay, the measured dissolution current was approximately 0.5 μA, lasting for about 10 hours. Substituting into the formula, the total number of moles of tin ions released was approximately 0.5 × 10⁻⁶. -6 × 36000 / (2×96485) ≈ 9.3×10 -8 The measured amount of mol corresponds to approximately 11 μg of tin. This mass is sufficient to form a deposition layer of approximately 0.5 μm thickness at the tip of the floating conductor in the L4 layer. Energy dispersive spectroscopy (EDS) confirmed the presence of tin deposition (the characteristic Sn peak appears at 3.44 keV). The measured results are in good agreement with the theoretical calculations.

[0082] The pre-plated tin layer was 2 μm thick. Experiments showed that at this thickness, the tin layer could continuously provide a trapping capacity for approximately 800 hours after relay triggering (as shown in Table 4, the L4 island tin layer was gradually consumed from 1200 h to 2000 h). The released tin ions were reduced and deposited on the floating conductor (opposite to the cathode) of the L4 layer, forming a relay trapping effect. This process conforms to the sacrificial anode principle in electrochemistry; the potential difference is spontaneously generated by the deposition process and requires no external control.

[0083] Measured data: Approximately 2.5 hours after the L2 floating conductor was fully saturated (insulation resistance dropped to 107 Ω), tin deposition began to appear on the surface of the L4 floating conductor. After this, the L4 floating conductor began to operate, and the insulation resistance recovered to 10 Ω. 10 Ω and maintains its strength for approximately 800 hours.

[0084] Test conditions: 85℃ / 85%RH, 400V bias, for 2000 hours. The deposition of floating conductors in each layer was monitored. Results are shown in Table 4. Table 4:

[0085] At the end of 2000 hours, the L2 floating conductor was completely covered by copper, and the L4 floating conductor had about 80% of its tin layer consumed, but still maintained 6.3 × 10⁻⁶ molten metal. 8 The insulation resistance was Ω, and it did not fail. However, the insulation resistance of a single-layer floating conductor (L2 layer only) without a three-dimensional relay network dropped to 10 Ω after approximately 1200 hours. 7 Ω decreased to 10 after 1350 hours. 6 Failure occurs below Ω. The 3D relay network extends the CAF resistance lifetime from approximately 1200 hours to over 2000 hours, an improvement of 67%.

[0086] Example 6 In this embodiment, a moisture-absorbing and expanding polymer is coated on the surface of the tip of the floating conductor. The polymer selected is a polyacrylic acid-polyethylene glycol block copolymer (PAA-b-PEG, molecular weight 5000-2000), with a thickness d. polymer =2μm. Coating method: The polymer was dissolved in ethanol (concentration 5wt%) and deposited on the tip region of the floating conductor by inkjet printing (piezoelectric printhead, droplet volume 10pL), and then dried at 60°C for 30 min.

[0087] The polymer begins to swell significantly at a relative humidity (RH) ≥ 60%. The volume expansion rate α(RH) is defined as the ratio of the expanded volume to the original volume, satisfying α(RH) = 1 + k swell × (RH - 60) 2Where RH is expressed as a percentage (e.g., 85 represents 85% relative humidity). Calibrated using a quartz crystal microbalance, k... swell ≈ 0.00025. Therefore, when RH = 70%, α = 1 + 0.00025 × 10⁻⁶. 2 = 1.025, meaning a volume expansion of 2.5%; when RH=80%, α = 1 + 0.00025×20 2 = 1.10, expansion 10%; when RH=85%, α = 1 + 0.00025×25 2 = 1.15625, expansion of 15.6%.

[0088] At 85% RH, polymer expansion reduces the effective spacing between adjacent tips from the original 15 μm to approximately 15 / 1.156 ≈ 13.0 μm (due to polymer filling of the gaps). Simultaneously, the effective tip height increases slightly due to polymer coverage, with experimental measurements increasing from 35 μm to approximately 38 μm. The electric field enhancement factor β = 1 + (h tip ~ / / r tip The resistance of the floating conductor containing this polymer increased from approximately 1 + 35 / 3 ≈ 12.7 to approximately 1 + 38 / 3 × 1.156 ≈ 15.6, an increase of about 23%. Actual measurements show that after 500 hours, the insulation resistance is 6.8 × 10⁻⁶. 11 Ω, compared to polymer-free floating conductors (5.1 × 10⁻⁶). 11 The Ω) increased by about 33%, proving that the adaptive enhancement effect is effective.

[0089] In this embodiment, during testing at 85℃ / 85%RH, the rate of decrease in insulation resistance was slowed by approximately 40% compared to the polymer-free floating conductor. Specifically, after 500 hours, the insulation resistance of the polymer-free floating conductor was 5.1 × 10⁻⁶. 11 Ω, the insulation resistance of the polymer floating conductor is 8.2 × 10⁻⁶. 11 Ω (60% increase). Under extreme conditions of RH=95% (swelling rate α=1 +0.00025×35) 2 =1.30625, i.e., expansion of about 30.6%, and the rate of decrease in insulation resistance is significantly slower, at about 65%. This indicates that the polymer expansion adaptively improves the capture efficiency under high humidity conditions, effectively offsetting the accelerating effect of humidity on ion migration.

[0090] Example 7 In this embodiment, the floating conductor is connected to ground via a high-impedance wire (resistance 100kΩ, 1% accuracy), and a miniature surface-mount sampling resistor (resistance 1kΩ, accuracy 0.1%, temperature drift 25ppm / ℃, model: Yageo RC0603) is connected in series on this wire. Test pads (0.5mm diameter, gold-plated) are led out from both ends of the sampling resistor for connection to external test equipment. During online monitoring, a 24-bit ADC (model: ADS1262, sampling rate programmable up to 384kSPS, noise 2.5μVpp) is used to measure the voltage drop across the sampling resistor at a sampling rate of 1Hz. The ADC output is transmitted to the on-board MCU (STM32F103) via the SPI interface. According to Ohm's law, the deposition current I deposit = V sample / R sample . When I deposit exceeds 0.5μA for more than 1 hour continuously, it is determined that the CAF risk at this position is increased, and the on-board MCU outputs an alarm signal (readable via I 2 C bus, alarm code 0xCAF1).

[0091] Verification data: In the 85℃ / 85%RH, 100V bias test, the average deposition current in the first 100 hours is about 0.031μA, and no alarm is triggered; the average current is 0.040μA at 200 hours; 0.059μA at 300 hours; 0.091μA at 400 hours; at 450 hours, the current rises to 0.48μA, close to the threshold; at 465 hours, the current reaches 0.52μA and remains stable, and the system issues an early warning (yellow alarm). At this time, sectional observation shows that the copper deposition coverage at the tip of the floating conductor is about 60%, and there is still a safety margin. This early warning provides an advance time of about 35 hours (up to the failure threshold of 500 hours) to take maintenance or derating measures. For applications requiring higher reliability, the threshold can be set to 0.3μA to provide an earlier early warning (about 100 hours of advance time).

[0092] The advantages of this monitoring solution are that no fusing mechanism is required, the PCB is not damaged, repeated measurement is possible, and the cost is extremely low (the sampling resistor is about 0.01 yuan per unit, and the ADC and MCU can reuse on-board resources).

[0093] As another optional embodiment, a consumable sacrificial structure can also be used to realize the alarm: The floating conductor and two adjacent vias are respectively connected by two copper wires with different widths, where the width of the first copper wire is w1, the width of the second copper wire is w2, and w1<w2 ≤ 2×w1. When copper ions are continuously deposited on the floating conductor, the narrower first copper wire is preferentially fused due to current density concentration and electromigration effect, and the fusing time t fuse satisfies: tfuse = (ρ Cu × C p × ΔT) / (J 2 × ρ e ); Where J = I deposit / (w1 × t Cu Let ρ be the current density in the first copper wire. Cu The density of copper is 8.96 g / cm³, C p ρ is the specific heat capacity of copper (0.385 J / g·K), ΔT is the difference between the melting point of copper (1083°C) and the ambient temperature (unit: K), and ρ is the specific heat capacity of copper (0.385 J / g·K). e The resistivity of copper is 1.72 × 10⁻⁶. -8 (Ω·m). After the first copper wire melts, the floating conductor is connected only by the second copper wire, and the resistance increases to (w1 / w2) times the original value. This resistance change outputs an alarm signal through the online monitoring circuit, indicating that the CAF risk at this location is approaching its limit. This alternative method and the aforementioned sampling resistance monitoring method can be implemented interchangeably.

[0094] Example 8 Batch production and yield statistics In this embodiment, following the method of Example 1 (using parameters L=0.6mm, D=0.10mm, a star-shaped floating conductor with 6 tips, and a radius of curvature of 3μm), 200 test boards (each board containing 100 floating conductor pairs, totaling 20,000 floating conductors) were manufactured in a mass production line. The batch numbers are 202405001-202405200. Detailed yield statistics are shown in Table 5. Table 5:

[0095] Note: Of the 60 defects tested, 32 were in the floating conductor design area (floating conductor failure), and 28 were in the non-floating conductor area (traditional CAF failure). Calculations were performed only for areas containing floating conductors: the defect rate due to floating conductor failure itself = 32 / 20000 = 0.16%, and the success rate of floating conductors in effectively preventing CAF = 99.84%.

[0096] Final finished board electrical testing (insulation resistance > 10) 8The yield rate (Ω) is 99.55% (per area) or 97.0% (per board, as each board contains 100 areas, and failure in any area results in the entire board being rejected). In contrast, the control board (200 boards, 100 areas per board) without floating conductors had a yield rate of 92.1% under the same testing conditions (due to CAF failure). This demonstrates that this solution improves CAF resistance without significantly reducing process yield, and increases the overall board yield by approximately 5 percentage points.

[0097] Cost Analysis Adding floating conductors only requires modifying the photoplot file (adding a layer of Gerber data) and increasing the design time for CAM engineers by approximately 0.5 hours. Calculations show that the increased design and photoplotting costs per square meter of PCB are approximately 0.5 yuan, almost negligible. In contrast, selecting imported CAF-resistant PCB materials (such as Panasonic M6) increases costs by approximately 30-50 yuan per square meter. This solution is significantly more economical. Based on an annual production of 100,000 square meters, this solution saves approximately 3-5 million yuan in material costs annually, without requiring any changes to the supply chain.

[0098] Example 9 I. Comparison of different floating conductor shapes Circular, star-shaped (6 tips, radius of curvature 3μm), serrated (tooth pitch 0.1mm, tooth height 0.05mm, tip radius of curvature 5μm), and dendritic (six branches resembling a snowflake, each branch tip radius of curvature 2μm) floating conductors were fabricated and subjected to HAST testing under the same conditions (85℃ / 85%RH, 100V, 500h). The sample size for each group was n=10. The results are shown in Table 6. Table 6:

[0099] Star-shaped and branched shapes offer the best trapping effects, with branched shapes being slightly better but more difficult to manufacture. Circular shapes, lacking a sharp point, result in weak electric field enhancement and poor performance. Considering both performance and manufacturability, the star shape is the preferred choice.

[0100] II. Influence of Tip Curvature Radius With a fixed star shape, four groups of materials with r = 2μm, 5μm, 10μm, and 20μm were fabricated (achieved by controlling etching time and photolithography precision), with n = 10 for each group. The test results are shown in Table 7. Table 7:

[0101] It has been shown that a smaller radius of curvature is better, but when r ≤ 2 μm, high photolithography capabilities are required (electron beam lithography is necessary). r = 5 μm can be achieved using conventional LDI (15 μm resolution) through grayscale exposure. Therefore, r ≤ 5 μm is preferred, balancing performance and cost.

[0102] III. Influence of the position of the floating conductor The floating conductors are positioned at the midpoint (d=0), offset to one side (0.1L, i.e., 60μm), and close to one of the vias. Due to safety clearance requirements, the only practically feasible positions are the midpoint and the 0.1L offset (the offset direction is along the connecting line, making the floating conductor farther from one via and closer to the other, but still requiring a minimum clearance of ≥130μm with both vias). When L=0.6mm and D=0.10mm, the midpoint is 150μm from both via walls. After an offset of 0.1L=60μm, the distance to the near-side via wall is 150-60=90μm, which does not meet the 130μm requirement. Therefore, the offset method is not feasible. In this embodiment, only the midpoint position can be used.

[0103] For scenarios where the midpoint position cannot be used, a multi-pointing design is adopted: the floating conductor remains at the midpoint, but its tips are no longer symmetrically and uniformly distributed, but optimized according to the electric field distribution. The tip pointing is optimized using COMSOL Multiphysics simulation (electrochemical module, boundary element method) to ensure that at least two tips point towards the via direction. Simulation results show that the optimized tip electric field enhancement factor pointing towards the via direction is 2.0 (2.1 for ideal uniform distribution), and the capture efficiency is approximately 95% of the ideal case. The insulation resistance measured after 500 hours is 3.8 × 10⁻⁶. 11 Ω (ideally 4.0 × 10⁻⁶) 11 (Ω), a decrease of about 5%, which is within an acceptable range.

[0104] In this embodiment, the rotating tip scheme is no longer used (which would significantly weaken the electric field enhancement in the main migration direction). Instead, the distribution of tip pointing is optimized to ensure that at least two tips point in the via connection direction.

[0105] Example 10 I. Optimization of Process Parameters (DOE) A full factorial designation of energy (DOE) was performed on the drilling and Desmear parameters, with floating conductor retention and hole wall quality as responses. The factors and levels are shown in Table 8. Table 8

[0106] A total of 27 experiments were conducted, with 5 samples in each group. Response indicators: floating conductor retention rate (microscopic inspection, no damage / cracks are considered acceptable), pore size (μm), and wick length (μm).

[0107] The optimal combination is: A = 2 times (2 retracements), B = 0.8 m / min, and C = 15 min. Under this combination, the floating conductor retention rate is 100%, the average hole diameter is 12.3 μm (σ = 2.1 μm), and the average wick diameter is 27.6 μm (σ = 3.2 μm). Analysis of variance shows that the number of retracements significantly affects the floating conductor retention rate (p < 0.01), decreasing to 92% after 4 retracements; the retracement time significantly affects the hole diameter (p < 0.05), with excessively long times (20 min) increasing the hole diameter to 18 μm.

[0108] II. Resin Layer Thickness Verification Control h by using different amounts of prepreg. top and h bottom Five schemes were designed, as shown in Table 9: Table 9:

[0109] The minimum coating thickness must be ≥h protrusion +5μm, preferably +10μm or higher to provide a greater safety margin.

[0110] Example 11 A comparison was made of four CAF-resistant boards from different suppliers, all using the process parameters of Example 1 (L=0.6mm, D=0.10mm, star-shaped floating conductor, r=3μm). The four boards are as follows: Material A: Shengyi S1000-2M (PN curing agent, open-fiber cloth) Material B: Panasonic M6 (low dielectric, halogen-free) Material C: Lianmao IT-180A (traditional Dicy curing agent, for comparison) Material D: Taiguang EM-827 (high Tg, halogen-free) The sample size for each group was n=20. The results of the 500-hour HAST test (85℃ / 85%RH, 100V) are shown in Table 10: Table 10:

[0111] The results show that the floating conductor scheme significantly improves CAF resistance in all four materials, with the best results observed in materials A and B. Even in the conventional Dicy material (material C), the insulation resistance over 500 hours is reduced from 10 Ω·cm. 3 The Ω level has been increased to 10. 10 The Ω-level results demonstrate the universality of the floating conductor solution for various sheet materials, reducing reliance on expensive CAF-resistant sheets.

[0112] In summary, the method of this invention can be widely applied in PCB manufacturing fields with high density, high voltage, and high reliability requirements, particularly in automotive electronics (BMS, OBC, DC-DC, inverters), servers / data centers (GPU motherboards, storage backplanes), communication equipment (5G base stations, optical modules), medical electronics (vital monitors, imaging equipment), and aerospace (satellites, flight controllers). Its manufacturing process is fully compatible with existing PCB production lines, requiring no additional equipment or materials, and the cost increase is minimal (<0.5 RMB / m²), while significantly improving CAF resistance (insulation resistance increased by 6-7 orders of magnitude over 500 hours), demonstrating extremely high industrial practical value and promising market prospects.

[0113] Example 12 This embodiment presents the key test data from the foregoing embodiments in a graphical manner and conducts in-depth analysis of the data trends to more intuitively demonstrate the technical effects of the present invention.

[0114] Figure 1 The insulation resistance R of modules with and without floating conductors is calculated under the conditions of 85℃ / 85%RH and 100V bias. iso A semi-logarithmic line graph showing the relationship between time (0–1000 hours). The horizontal axis represents time (hours), and the vertical axis represents insulation resistance (Ω, logarithmic scale), corresponding to the data in Table 1.

[0115] As can be seen from the graph, the blue curve (containing the floating conductor): from 3.5 × 10 12 The Ω value initially decreased gradually, remaining at 2.8 × 10⁻⁶ after 1000 hours. 11 Ω.

[0116] Red curve (excluding floating conductors): Rapid decline in the first 100 hours, falling below 10 at 500 hours. 6 The Ω failure threshold is reached, after which data is interrupted.

[0117] The insulation resistance decrease rate with the floating conductor module is approximately 0.11 orders of magnitude per 100 hours, while the decrease rate without the floating conductor module is approximately 0.45 orders of magnitude per 100 hours (first 500 hours). The floating conductor reduces the decrease rate by approximately 76%.

[0118] In a semi-logarithmic coordinate system, both curves show an approximately linear decrease, which is consistent with the electrochemical kinetic model of CAF growth (insulation resistance is exponentially related to time).

[0119] The slope of the curve containing the floating conductor increased slightly after 500 hours, but the absolute value was still much smaller than that of the control curve, proving that the floating conductor remained effective in long-term testing.

[0120] Figure 2The figure shows the insulation resistance of a single-layer floating conductor and a three-dimensional relay network (L2+L4) under a 400V bias voltage as a function of time (0–2000 hours). The horizontal axis represents time (hours), and the vertical axis represents insulation resistance (Ω, logarithmic scale). The figure marks the saturation point of island L2, the relay trigger point, and the starting operating point of island L4, corresponding to the data in Table 2.

[0121] As can be seen from the graph, the red layer (single layer) decreased to 10 after 1200 hours. 7 Ω, decreased to 10 after 1350 hours 6 It fails below Ω.

[0122] Blue (3D relay network): At 950 hours, L2 approaches saturation, and the insulation resistance briefly drops to 8.6 × 10⁻⁶. 9 Ω; After 1000 hours of relay triggering, the insulation resistance rose back to 4.2×10 Ω. 9 Ω; it then decreased slowly, remaining at 6.3 × 10⁻⁶ at 2000 hours. 8 Ω.

[0123] The three-dimensional relay network will have an effective lifespan (insulation resistance ≥ 10). 8 (Ω) The lifespan has been extended from approximately 1200 hours for a single layer to >2000 hours, an improvement of 67%.

[0124] When the relay is triggered, the insulation resistance briefly rises (from 3.1 × 10⁻⁶). 9 Ω increased to 5.6×10 9 (Ω), because the reduction deposition of tin in the L4 layer fills some of the ion migration channels, which is a "self-repairing" behavior.

[0125] If more layers are added (such as L2+L4+L6+L8), the expected lifespan can be further extended to more than 3,000 hours.

[0126] Figures 3 to 5 The chart shows a performance comparison of four types of floating conductors—circular, star-shaped, sawtooth-shaped, and dendritic—after 500 hours of HAST testing, corresponding to the data in Table 5; among them, Figure 3 This is a comparison chart of insulation resistance for different floating conductor shapes. Figure 4 This is a comparison chart of deposition coverage for different floating conductor shapes. Figure 5 A comparison chart of the standard deviations of insulation resistance measurements for different floating conductor shapes.

[0127] from Figure 4 The data shows that the depositional coverage (%) is as follows: dendritic 45%, star-shaped 42%, serrated 38%, and circular 5%.

[0128] from Figure 5 As can be seen from the data, the insulation resistance (Ω) for the star-type connection reaches 4.0 × 10⁻⁶. 11Ω, dendritic 1.2 × 10 11 Ω, serrated 6.8×10 10 Ω, a circle is only 2.3 × 10 9 Ω.

[0129] Star-shaped floating conductors offer the best overall performance: high insulation resistance, moderate coverage, and moderate manufacturing difficulty. Dendritic conductors have slightly better performance but are more complex to manufacture, while circular conductors are essentially ineffective.

[0130] Insulation resistance is positively correlated with deposition coverage (Pearson correlation coefficient r=0.96), proving that deposition coverage is a key indicator for measuring the effectiveness of floating conductors.

[0131] Because the star-shaped structure has six evenly distributed tips, it can capture migrating ions in multiple directions, making it the most adaptable.

[0132] Figures 6 to 8 Performance graphs are shown for different tip curvature radii (2μm, 5μm, 10μm, 20μm), corresponding to the data in Table 6; among them, Figure 6 The graph shows the insulation resistance performance over 500 hours for different tip curvature radii. Figure 7 The graph shows the electric field enhancement factor β performance for different tip curvature radii. Figure 8 A comparison chart of the standard deviations of insulation resistance measurements under different tip curvature radii.

[0133] from Figure 6 It can be seen that the insulation resistance is 5.6 × 10⁻⁶ when r = 2 μm. 11 Ω, r=5μm 4.0×10 11 Ω, r=10μm 1.2×10 11 Ω, r=20μm 1.8×10 9 Ω.

[0134] from Figure 7 It can be seen that the β values ​​are: β=18.5 when r=2μm, β=8.0 when r=5μm, β=4.5 when r=10μm, and β=2.75 when r=20μm.

[0135] Insulation resistance shows a strong positive correlation with the β value (r=0.99). When β>5 (i.e., r≤7μm), the insulation resistance can be maintained at 10 μm over 500 hours. 11 When the value is above Ω and β < 3 (r > 17.5 μm), the effect decreases sharply.

[0136] The recommended radius of curvature r ≤ 5 μm, where β ≥ 8, can achieve 4 × 10 11 Insulation resistance above Ω.

[0137] When r decreases from 5μm to 2μm, β increases from 8 to 18.5, but the insulation resistance only increases by 40%, resulting in diminishing marginal returns. Furthermore, 2μm requires electron beam lithography, which is too costly. Therefore, the optimal choice is r=5μm (balancing performance and cost).

[0138] Figures 9 to 11 The graphs show the improvement effect of floating conductors on four types of boards (Shengyi S1000-2M, Panasonic M6, Lianmao IT-180A, and Taiguang EM-827), corresponding to the data in Table 10; among them, Figure 9 This is a comparison chart of insulation resistance over 500 hours under conditions without floating conductors. Figure 10 This is a comparison chart of insulation resistance over 500 hours under conditions including a floating conductor. Figure 11 This is a graph showing the boost factor under conditions with and without floating conductors.

[0139] Shengyi S1000-2M: Island-free 3.2×10 4 Ω, with islands 5.1×10 11 Ω (increase by 1.6 × 10) 7 times).

[0140] Panasonic M6: Islandless 1.5×10 5 Ω, with islands 6.8×10 11 Ω (increase by 4.5 × 10) 6 times).

[0141] Lianmao IT-180A: Islandless 8.2×10 3 Ω, with islands 2.3×10 10 Ω (increase of 2.8 × 10) 6 times).

[0142] Taiguang EM-827: Islandless 6.5×10 4 Ω, with islands 4.2×10 11 Ω (increase by 6.5 × 10) 6 times).

[0143] Floating conductors significantly improve CAF resistance in all materials, with an improvement factor of 10. 6 ~10 7 Between times.

[0144] Even in conventional Dicy materials (Lienmao IT-180A), the presence of floating conductors can reduce the insulation resistance from 10 ohms over 500 hours. 3 Ω increased to 10 10 Ω, meeting most industry standards (typically requiring ≥10). 8 (Ω). This means that this solution can reduce reliance on expensive CAF-resistant sheets and lower material costs.

[0145] The best results were achieved with Shengyi S1000-2M and Panasonic M6, possibly due to the better compatibility between the PN curing agent and the open-fiber cloth.

[0146] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A CAF-resistant printed circuit board manufacturing process, characterized in that, The method includes the following steps: Step 1: Obtain the location information of adjacent vias and the pattern information of inner layer copper foil in the PCB inner layer design. In the corresponding area of ​​the dielectric layer between two adjacent vias, set at least one floating conductor that is not connected to any electrical network. The surface of the floating conductor has the tip of multiple sharp protrusion structures. Step 2: Using conventional inner core board etching process, floating conductor patterns are simultaneously fabricated while signal lines are being made, so that the floating conductors are of the same material and thickness as the inner copper foil, resulting in an inner core board containing floating conductors. Step 3: Press the inner core board containing the floating conductor into a multilayer board stack structure so that the floating conductor is encapsulated inside the dielectric layer and the vertical projection does not overlap with the drilling position of two adjacent vias to obtain the pressed inner core board. Step 4: Drill holes in the laminated inner core board according to the set drilling parameters to form vias, and obtain the drilled PCB semi-finished product; the drilling location should avoid the area where the floating conductor is located. Step 5: After drilling, the PCB semi-finished product is subjected to hole metallization, outer layer circuit fabrication, and solder mask coating to obtain a CAF-resistant printed circuit board containing a floating ion trapping structure.

2. The CAF-resistant printed circuit board manufacturing process according to claim 1, characterized in that, In step 1, the planar shape of the floating conductor is set to star-shaped, sawtooth-shaped, or dendritic, the radius of curvature r of the tip of the floating conductor is ≤ 5 μm, and the spacing p between adjacent protrusions is ≤ 20 μm.

3. The CAF-resistant printed circuit board manufacturing process according to claim 2, characterized in that, In step 1, the position of the floating conductor is set to satisfy the following relationship: Let the length of the line connecting the centers of two adjacent vias be L, the perpendicular distance from the center of the floating conductor to this line be d, and the diameter of the maximum circumscribed circle of the floating conductor be D. Then, the following holds: d ≤ L / 4 and D ≤ L / 3; Furthermore, the floating conductor is located near the perpendicular bisector of the line connecting the two vias, and the deviation Δ between its center and the perpendicular bisector satisfies: Δ ≤ 0.1×L.

4. The CAF-resistant printed circuit board manufacturing process according to claim 3, characterized in that, In step 2, the method for simultaneously creating the floating conductor pattern specifically includes: A negative photoresist pattern is formed on the copper foil of the inner core board using photolithography. The negative photoresist pattern contains both signal line patterns and floating conductor patterns, resulting in an inner core board with a negative photoresist pattern. The inner core board with negative photoresist pattern is etched with acidic etching solution to remove the copper foil that is not covered by photoresist. The remaining copper foil simultaneously forms signal lines and floating conductors, resulting in the etched inner core board. The photoresist is removed from the etched inner core board to obtain an inner core board with a floating conductor.

5. The CAF-resistant printed circuit board manufacturing process according to claim 4, characterized in that, In step 3, during the lamination process, the dielectric layer thickness on both sides of the floating conductor meets the minimum coverage requirement in the IPC-4101 standard: Let the thickness of the dielectric layer above the floating conductor be h. top The thickness of the underlying dielectric layer is h. bottom The maximum height of the tip of the floating conductor is h. protrusion Then it exists: h top ≥ h protrusion + 5 μm and h bottom ≥ h protrusion + 5 μm.

6. The CAF-resistant printed circuit board manufacturing process according to claim 5, characterized in that, In step 4, the method for drilling to avoid the area where the floating conductor is located includes: Set the minimum distance d between the drilling location and the outline of the floating conductor. clear satisfy: d clear ≥ t alignment + r drill + 0.05 mm; Among them, t alignment For the positioning tolerance of drilling equipment, r drill The value is the drill bit radius, and 0.05 mm is the recommended safety margin for the process.

7. The CAF-resistant printed circuit board manufacturing process according to claim 6, characterized in that, The method further includes step 6: After completing step 5, the obtained printed circuit board is subjected to accelerated aging test. The specific test conditions are: temperature 85℃, relative humidity 85%, and applied bias voltage V. bias = 100 V, test time t ≥ 500 hours; During the test, the insulation resistance R between two adjacent vias was recorded. iso The criteria for qualification are as follows: R iso ≥ 1×10 8 Ω and copper deposits were observed at the tip of the floating conductor under a scanning electron microscope.

8. The CAF-resistant printed circuit board manufacturing process according to claim 7, characterized in that, In the accelerated aging test, Faraday's law was used to evaluate the capture rate of copper ions by the floating conductor. The relationship between the mass m of deposited copper and the charge Q passing through is as follows: m = (Q × M) / (n × F); Where M is the molar mass of copper, n is the number of valence electrons in a copper ion, and F is the Faraday constant; The critical charge Q required for the sediment to cover the entire tip crit With the initial surface area A of the tip tip satisfy: Q crit = (ρ Cu × A tip × d min × n × F) / M; Where, ρ Cu For the density of copper, δ min Minimum deposition thickness required to effectively block CAF.

9. The CAF-resistant printed circuit board manufacturing process according to claim 8, characterized in that, The method further includes step 7: A floating conductor is connected to ground potential or a fixed potential via a high-impedance wire. The width w of the high-impedance wire is ≤ 0.025 mm, the length l is ≥ 0.5 mm, and the sheet resistance R of the high-impedance wire is... sq satisfy: R w = R sq × (l / w) ≥ 1 MΩ; This results in a leakage current I during operation of the floating conductor. leak = V bias / R w ≤ 1 nA.

10. The CAF-resistant printed circuit board manufacturing process according to claim 9, characterized in that, The method further includes step 8: For multiple different adjacent via pairs in the same product, multiple floating conductors are independently set, and each floating conductor is isolated from the others. The radius of curvature r of the tip of each floating conductor is also specified. tip Based on the actual electric field strength E at that location i Design to satisfy the electric field enhancement factor β i Relationship: β i = 1 + (h tip / r tip )； Among them, h tip For the tip height; To ensure that capture takes precedence over CAF growth, the following conditions must be met: β i × And i ≥ E CAFthreshold ; Among them, E CAFthreshold Let be the critical electric field strength of the dielectric material at a given temperature and humidity. Then determine r i The upper limit is: r i ≤ h i / [ (E CAFthreshold / E i ) - 1 ]。

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