Memory and electronic device

Abstract

The embodiments of the present disclosure provide a memory and an electronic device, the memory comprising: a vertically stacked structure having L levels, comprising a storage array structure and a first signal transmission structure arranged along a first horizontal direction; in each level, the storage array structure comprises a plurality of first word lines, and the first signal transmission structure comprises a plurality of first transistors, a first connection part, P second transistors and P second connection parts; the first connection part is respectively coupled with the plurality of first word lines through the plurality of first transistors, and the first connection part is respectively coupled with the P second connection parts through the P second transistors; the first signal transmission structure further comprises P connection part groups and N lead-out structures, each connection part group comprises L second connection parts stacked vertically; K i second connection parts in the i th connection part group are respectively coupled with K i lead-out structures in the N lead-out structures, and the first connection part in each level is coupled with at least one lead-out structure through at least one second connection part.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and an electronic device. Background Technology

[0002] Traditional memory chips are fabricated based on two-dimensional planes, with memory cells arranged on a single plane. However, with the increasing demand for higher capacity and smaller size memory, traditional two-dimensional planar memory technology faces physical and performance limitations.

[0003] To address these issues, three-dimensional (3D) memory technology emerged. It achieves higher storage density by stacking multiple layers of memory cells vertically. This stacking structure can significantly increase the storage capacity of memory chips while maintaining a relatively small chip size. Furthermore, 3D memory utilizes advanced manufacturing processes and materials to improve data transfer speeds and energy efficiency.

[0004] As the number of stacked layers in the vertical direction of the memory increases, the parasitic capacitance of the word lines also increases, affecting the memory's storage speed. Summary of the Invention

[0005] This disclosure provides a memory and an electronic device that at least improves the memory's storage speed.

[0006] This disclosure provides a memory in some embodiments, including: a vertically stacked structure having L levels, the vertically stacked structure including a memory array structure and a first signal transmission structure arranged along a first horizontal direction; in each level, the memory array structure includes multiple first word lines, the first signal transmission structure includes multiple first transistors, a first connection portion, P second transistors, and P second connection portions; the multiple first word lines extend along the first horizontal direction and are spaced apart along a second horizontal direction, the second horizontal direction intersecting the first horizontal direction, the first connection portions are coupled to the multiple first word lines respectively through the multiple first transistors, and the first connection portions are coupled to the P second connection portions respectively through the P second transistors; the first signal transmission structure further includes P connection portion groups and N lead-out structures, each connection portion group including L vertically stacked second connection portions; K in the i-th connection portion group i The second connecting part and K in the N lead-out structures i Each lead-out structure is coupled to the others, and the first connection portion in each level is coupled to at least one lead-out structure through at least one second connection portion; wherein i, L, P, N, K i All are positive integers, i is any positive integer from 1 to P, L≥3, P≥2, L≤N<2L, K i <L,

[0007] In some embodiments, the corresponding K in the i-th connecting part group i Each lead-out structure is coupled to K. i The second connection is located in the continuous K i In each level.

[0008] In some embodiments, the first connection portion in each layer is coupled to an outgoing structure via a second connection portion.

[0009] In some embodiments, the K in the a-th connecting part group is related to the K i Each lead-out structure is coupled to K. a The second connection is located in the continuous K a In each level, the K in the b-th connection group corresponds to... i Each lead-out structure is coupled to K. b The second connection is located in the continuous K b In each level, the continuous K a Each level and the continuous K b Each level shares at least two consecutive levels, where a and b are any positive integers from 1 to P, and a is not equal to b. a ≥3, K b ≥3.

[0010] In some embodiments, the continuous K a Each level and the continuous K b Each level shares two consecutive levels.

[0011] In some embodiments, K1 = K2 = ... = K P .

[0012] In some embodiments, P > 2, K2 = K3 = ... = K P-1 =2K1=2K P .

[0013] In some embodiments, the geometric center of the top surface of each lead-out structure and the geometric center of the second connecting portion coupled thereto are substantially the same distance in the second horizontal direction.

[0014] In some embodiments, the first signal transmission structure includes a plurality of first transistor groups, each first transistor group including L vertically stacked first transistors, the L first transistors in each first transistor group sharing a first gate line extending in a vertical direction, the L first transistors including L first semiconductor layers arranged at intervals in a vertical direction surrounding the first gate line, a first gate dielectric layer disposed between the L first semiconductor layers and the first gate line, the vertical direction being the direction of the L layers stacking; the first signal transmission structure includes P second transistor groups, each second transistor group including L vertically stacked second transistors, the L second transistors in each second transistor group sharing a second gate line extending in a vertical direction, the L second transistors including L second semiconductor layers arranged at intervals in a vertical direction surrounding the second gate line, a second gate dielectric layer disposed between the L second semiconductor layers and the second gate line.

[0015] In some embodiments, the storage array structure further includes: multiple bit lines extending in a vertical direction, the vertical direction being the direction of the L-level stacking; and multiple storage cells, wherein each storage cell is coupled to a corresponding first word line and a corresponding bit line respectively.

[0016] In some embodiments, the vertically stacked structure further includes a second signal transmission structure located on opposite sides of the memory array structure. In each level, the second signal transmission structure includes a plurality of third transistors, a third connection portion, Q fourth transistors, and Q fourth connection portions. The third connection portions are coupled to the plurality of first word lines via the plurality of third transistors, and are coupled to the Q fourth connection portions via the Q fourth transistors. The second signal transmission structure further includes Q additional connection portion groups and M additional lead-out structures. Each additional connection portion group includes L vertically stacked fourth connection portions. The M additional lead-out structures are coupled to the M fourth connection portions in the Q additional connection portion groups, and the third connection portion in each level is coupled to at least one additional lead-out structure via at least one fourth connection portion. Wherein, Q and M are both positive integers, Q ≥ 2, and L ≤ M < 2L.

[0017] In some embodiments, the second signal transmission structure is axially symmetric or centrally symmetric to the first signal transmission structure.

[0018] In some embodiments, the vertically stacked structure further includes a second signal transmission structure, which is located on opposite sides of the memory array structure as the first signal transmission structure. In each level, the second signal transmission structure includes a plurality of third transistors, a third connection portion, and Q fourth connection portions. The third connection portions are coupled to the plurality of first word lines through the plurality of third transistors, and are coupled to the Q fourth connection portions respectively. The second signal transmission structure further includes Q additional connection portion groups and M additional lead-out structures. Each additional connection portion group includes L vertically stacked fourth connection portions. The M additional lead-out structures are coupled to the M fourth connection portions in the Q additional connection portion groups respectively. Furthermore, the third connection portion in each level is coupled to at least one additional lead-out structure through at least one fourth connection portion. Wherein, Q and M are both positive integers, Q≥2, L≤M<2L.

[0019] In some embodiments, Q = P, M = N.

[0020] In some embodiments, the vertical stacking structure further includes a second signal transmission structure, which is located on opposite sides of the memory array structure as the first signal transmission structure; in each layer, the second signal transmission structure includes a plurality of third transistors and a third connection portion; the third connection portion is coupled to the plurality of first word lines respectively through the plurality of third transistors; the second signal transmission structure further includes an additional lead-out structure, which is coupled to the third connection portion in the L layers respectively.

[0021] In some embodiments, the vertically stacked structure further includes a second signal transmission structure, which is located on opposite sides of the memory array structure. In each level, the memory array structure includes multiple second word lines, and the second signal transmission structure includes multiple third transistors, a third connection portion, Q fourth transistors, and Q fourth connection portions. The multiple second word lines extend along a first horizontal direction, and the multiple second word lines and the multiple first word lines are alternately arranged along a second horizontal direction. The third connection portions are coupled to the multiple second word lines respectively through the multiple third transistors, and are coupled to the Q fourth connection portions respectively through the Q fourth transistors. The second signal transmission structure further includes Q additional connection portion groups and M additional lead-out structures, each additional connection portion group including L vertically stacked fourth connection portions. The M additional lead-out structures are respectively coupled to the M fourth connection portions in the Q additional connection portion groups, and the third connection portion in each level is coupled to at least one additional lead-out structure through at least one fourth connection portion. Wherein, Q and M are both positive integers, Q≥2, and L≤M<2L.

[0022] Other embodiments of this disclosure also provide an electronic device, including a processor; and a memory, wherein the memory is coupled to the processor, and the memory includes the memory described in any of the foregoing embodiments.

[0023] The technical solution provided in this disclosure has at least the following advantages:

[0024] In the memory technical solution provided in this disclosure embodiment, in each level, the memory array structure includes multiple first word lines, and the first signal transmission structure includes multiple first transistors, a first connection portion, P second transistors, and P second connection portions; the multiple first word lines extend along a first horizontal direction and are spaced apart along a second horizontal direction, the second horizontal direction intersects the first horizontal direction, the first connection portion is coupled to the multiple first word lines respectively through multiple first transistors, and the first connection portion is coupled to the P second connection portions respectively through P second transistors; the first signal transmission structure also includes P connection portion groups and N lead-out structures, each connection portion group includes L vertically stacked second connection portions; K in the i-th connection portion group i K in the second connecting part and N lead-out structures i Each lead-out structure is coupled separately, and the first connection portion in each level is coupled to at least one lead-out structure through at least one second connection portion. Simultaneously, by controlling the on / off state of different first transistors, the first connection portion can be electrically connected to the corresponding selected first word line through only one first transistor; similarly, by controlling the on / off state of different second transistors, the first connection portion can be electrically connected to the corresponding second connection portion through only one second transistor. Therefore, compared to a scheme where the first word line is directly coupled to the first connection portion and the first connection portion is directly coupled to the second connection portion, the load on the selected first word line is less, and the overall parasitic capacitance for the selected first word line is significantly reduced, thereby improving the read / write speed of the memory and enhancing storage performance. Attached Figure Description

[0025] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1This is a top view of a memory structure in related technologies;

[0027] Figure 2 A partial three-dimensional structural diagram of a memory provided in some embodiments of this disclosure;

[0028] Figure 3 A partial top view of the memory structure provided in some embodiments of this disclosure;

[0029] Figure 4 A partial top view of the memory structure provided in some embodiments of this disclosure;

[0030] Figure 5 A top view of the second connection portion and lead-out structure in a memory provided in some embodiments of this disclosure;

[0031] Figure 6 A top view of the second connection portion and lead-out structure in a memory provided for other embodiments of this disclosure;

[0032] Figure 7 for Figure 3 A partial cross-sectional view of the first transistor group cut along the Y direction;

[0033] Figure 8 for Figure 3 A cross-sectional view of the second transistor group cut along the Y direction.

[0034] Figure 9 A top view of a memory provided in some embodiments of this disclosure;

[0035] Figure 10 Another top view schematic diagram of the memory provided in some embodiments of this disclosure;

[0036] Figure 11 Another top view schematic diagram of a memory provided in some embodiments of this disclosure;

[0037] Figure 12 Another top view schematic diagram of the memory provided in some embodiments of this disclosure;

[0038] Figure 13 Block diagrams of electronic devices provided in some embodiments of this disclosure. Detailed Implementation

[0039] As can be seen from the background technology, the storage speed of existing 3D memory needs to be improved.

[0040] Figure 1 This is a top view schematic diagram of a memory structure in related technologies. (Reference) Figure 1The memory includes an array region 01 and a stepped region 02. The array region 01 contains multiple memory arrays and has multiple stacked levels in a vertical direction. Each level includes multiple word lines 11 located in the array region 01, bit lines 12 located on opposite sides of the word lines 11, and capacitor structures 13. Each level also includes a first connection portion 14 and a second connection portion 15 located in the stepped region. The second connection portion 15 is coupled to at least two word lines 11 via the first connection portion 14, and the first connection portion 14 is located between the second connection portion 15 and the word lines 11. The memory also includes multiple lead-out structures 16, which are coupled to corresponding second connection portions 15 to apply voltage to corresponding at least two word lines 11.

[0041] At least two second connection portions 15 connect multiple word lines 11 via the same first connection portion 114. When one word line 11 is selected for read / write operations, that word line 11 is electrically connected to multiple other word lines 11 and multiple second connection portions 15 via the first connection portion 14, resulting in a large overall parasitic capacitance and thus a large RC delay, affecting the read / write speed of the memory. Figure 1 For example, the first connecting part 14 is coupled to four word lines 11 and two second connecting parts 15. If the first word line 11 is selected, then three word lines, one first connecting part 14 and two second connecting parts 15 are connected to the selected word line 11.

[0042] To address or improve the aforementioned technical problems, this disclosure provides a memory in which a first transistor is disposed between a first connection portion and a first word line, and a second transistor is disposed between the first connection portion and a second connection portion. The first connection portion is coupled to multiple first word lines via multiple first transistors, and the first connection portion is coupled to P second connection portions via P second transistors. The first transistor coupled to the selected first word line is turned on, while the remaining first transistors are turned off. Conversely, the second transistor coupled to the second connection portion that provides a control signal to the selected first word line is turned on, while the remaining second transistors are turned off. Thus, other unselected first word lines are not coupled to the selected first word line, and the remaining second connection portions are not coupled to the selected first word line. This reduces the overall parasitic capacitance for the selected first word line, thereby improving the read / write speed of the memory.

[0043] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0044] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0045] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0046] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0047] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the embodiments of this disclosure and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. For example, if the device or element in the illustration is inverted, then the element described as "below," "under," "below," or "bottom" of other elements or features will be oriented "above" or "top" of said other elements or features. Therefore, the term "below" may, depending on the context in which the term is used, encompass both above and below orientations, which will be obvious to those skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0048] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. Furthermore, when describing a component as "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor on a portion of the edge of the entire surface.

[0049] In the description of the embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. The formation or placement of a second component above or on a first component, or on the surface of a first component, or on one side of a first component, may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be placed between the first and second components, thereby preventing direct contact between the first and second components. For simplicity and clarity, various components may be drawn at different scales. In the drawings, some layers / components may be omitted for simplicity. Unless otherwise specified, the formation or placement of a second component on the surface of a first component refers to direct contact between the first and second components. The term "component" can refer to a layer, film, region, portion, structure, etc.

[0050] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0051] Figure 2 This is a partial three-dimensional structural diagram of a memory provided in some embodiments of this disclosure. Figure 3 This is a partial top view of a memory structure provided in some embodiments of this disclosure. Figure 4 This is another partial top view schematic diagram of the memory provided in some embodiments of this disclosure. It should be noted that, for ease of illustration, Figure 2 The diagram only shows a portion of the memory array structure and does not show the first signal transmission structure.

[0052] Reference Figure 2 and Figure 3 The memory includes a vertically stacked structure with L levels. The vertically stacked structure includes a memory array structure 10 arranged along a first horizontal direction Y and a first signal transmission structure 20. Each of the L levels is stacked along a vertical direction Z, where L is a positive integer and L≥3.

[0053] In each level, the memory array structure 10 includes multiple first word lines WL1, and the first signal transmission structure includes multiple first transistors M1, a first connection portion 101, P second transistors M2, and P second connection portions 102. Here, P is a positive integer and P ≥ 2.

[0054] Multiple first word lines WL1 extend along the first horizontal direction Y and are spaced apart along the second horizontal direction X. The second horizontal direction X intersects with the first horizontal direction Y. The first connection part 101 is coupled to the multiple first word lines WL1 through multiple first transistors M1 respectively. The first connection part 101 is coupled to P second connection parts 102 through P second transistors M2 respectively.

[0055] The first signal transmission structure 20 also includes P connection groups and N lead-out structures 100, each connection group including L vertically stacked second connection parts 102. In the i-th connection group, K... i The second connecting part 102 and K in the N lead-out structures 100 i Each lead-out structure is coupled to the others, and the first connection portion 101 in each level is coupled to at least one lead-out structure 100 through at least one second connection portion 102. Wherein, i, L, P, N, K i All are positive integers, i is any positive integer from 1 to P, L≥3, P≥2, L≤N<2L, K i <L,

[0056] It should be noted that, for ease of illustration, Figure 3 The first connecting portion 101 is coupled to four first word lines WL1, and the first connecting portion 101 is coupled to two second connecting portions 102. This embodiment does not limit the number of first word lines WL1 coupled to the first connecting portion 101, nor does it limit the number of second connecting portions 102 coupled to the first connecting portion 101, as long as the aforementioned i, L, P, N, K are satisfied. i The relationship between them is sufficient.

[0057] The memory can be Dynamic Random Access Memory (DRAM). It can also be FeRAM (Ferroelectric Random Access Memory), PCM (Phase Change Material) memory, or MRAM (Magnetoresistive Random Access Memory), etc.

[0058] The first signal transmission structure 20 is used to couple the first word line WL1 in each level to the corresponding lead-out structure 100, so as to apply a corresponding control voltage to the corresponding first word line WL1 through the lead-out structure 100. Each connection group includes L second connection portions 102 stacked along the vertical direction Z, and each second connection portion 102 corresponds to at least two first word lines WL1 in the same level, and each second connection portion 102 corresponds to a first connection portion 101 in the same level. Each second connection portion 102 in each connection group is coupled to the corresponding first connection portion 101 in the same level through a second transistor M2.

[0059] The storage array structure 10 also includes multiple bit lines BL, which extend along the vertical direction Z, where the vertical direction Z is the direction of L-level stacking. The storage array structure 10 also includes multiple storage cells, wherein each storage cell is coupled to a corresponding first word line WL1 and a corresponding bit line BL.

[0060] Among them, the same bit line BL is coupled to multiple memory cells stacked in the vertical direction Z, and the same first word line WL1 is coupled to multiple memory cells at the same level.

[0061] like Figure 2 and Figure 3 As shown, in each level, the bit lines BL coupled to adjacent memory cells can be independent of each other. In some other possible implementations, such as... Figure 4 As shown, in order to further reduce the size of the memory, adjacent memory cells in each level can be coupled to the same bit line BL.

[0062] In each layer, the capacitor structure CAP includes a first electrode and a second electrode disposed opposite each other, and a capacitor dielectric layer located between the first electrode and the second electrode; in the same memory cell, the first electrode of the capacitor structure CAP is coupled to the access transistor. Capacitor structures in adjacent memory cells may share a second electrode.

[0063] Multiple first word lines WL1 can be some or all of the word lines in the memory array structure 10 at each level. Some word lines can be odd-numbered word lines or even-numbered word lines in the memory array structure 10 ordered in ascending natural numbers, or at least two adjacent word lines in the memory array structure 10.

[0064] like Figure 3 and Figure 4 As shown, multiple first word lines WL1 can be several word lines arranged consecutively in the memory array structure 10 of each level.

[0065] The first word line WL1 is also called the local word line, and one of the first connecting part 101 or the second connecting part 102 is also called the common word line.

[0066] In some embodiments, the first connecting portion 101 is in the shape of a ring. In other embodiments, the first connecting portion 101 may also be in the shape of a complete strip.

[0067] In some embodiments, the second connecting portion 102 is in the shape of a ring. In other embodiments, the second connecting portion 102 may also be in the shape of a complete strip.

[0068] The first connection portion 101 is coupled to the first word line WL1 via the first transistor M1. Specifically, the first transistor M1 has a first control terminal, a first connection terminal, and a second connection terminal. The first connection terminal and the second connection terminal are respectively the source or drain of the first transistor M1. The first transistor M1 responds to a signal from the first control terminal to turn the first connection terminal and the second connection terminal on or off. The first connection terminal is electrically connected to the first word line WL1, and the second connection terminal is electrically connected to the first connection portion 101. If the first connection terminal and the second connection terminal are on, the first connection portion 101 is electrically connected to the first word line WL1; if the first connection terminal and the second connection terminal are off, the first connection portion 101 is disconnected from the first word line WL1.

[0069] In each level, the first connection portion 101 can be coupled to at least two first word lines WL1 through corresponding first transistors M1, wherein each first word line WL1 is coupled to the first connection portion 101 through a corresponding first transistor M1. For example... Figure 3 As shown, in some specific examples, the first connection portion 101 is coupled to the four first word lines WL1 through corresponding first transistors M1.

[0070] In each layer, the first signal transmission structure 20 may include a plurality of first connection portions 101 spaced apart in the second horizontal direction X. In some examples, the first signal transmission structure 20 may also include only one first connection portion 101 in each layer.

[0071] The first connection portion 101 is coupled to P second connection portions 102 via P second transistors M2, meaning that each second transistor M2 has a second control terminal, a third connection terminal, and a fourth connection terminal. The third connection terminal and the fourth connection terminal are respectively the source or drain of the second transistor M2. The second transistor M2 responds to a signal from the second control terminal to turn the third connection terminal and the fourth connection terminal on or off. The third connection terminal is electrically connected to the first connection portion 101, and the fourth connection terminal is electrically connected to the corresponding second connection portion 102. If the third connection terminal and the fourth connection terminal are on, the first connection portion 101 is electrically connected to the corresponding second connection portion 102; if the third connection terminal and the fourth connection terminal are off, the first connection portion 101 is disconnected from the corresponding second connection portion 102.

[0072] In each level, the first connection portion 101 can be coupled to at least two second connection portions 102 via corresponding second transistors M2, wherein each second connection portion 102 is coupled to the first connection portion 101 via a corresponding second transistor M2. For example... Figure 3 As shown, in some specific examples, the first connection portion 101 is coupled to two second connection portions 102 via corresponding second transistors M2.

[0073] Each connection group includes L vertically stacked second connection portions 102, meaning each connection group includes one second connection portion 102 located in each level. A portion of the second connection portions 102 in any connection group are coupled to a corresponding lead-out structure 100 to provide control signals to the corresponding second connection portion 102 via the lead-out structure 100, thereby providing control signals to the corresponding first word line WL1. For example, K in the i-th connection group... i The second connecting portion 102 is coupled to the corresponding lead-out structure 100, K i Less than L.

[0074] The i-th connecting part group corresponds to K i Each lead-out structure is coupled to K. i The second connecting part 102 can be located in a continuous K i In each level. K i The second connecting part 102 and K in the N lead-out structures i Each lead-out structure 100 is coupled to the first connection portion 101 in each level, and the first connection portion 101 in each level is coupled to at least one lead-out structure 100 through at least one second connection portion 102.

[0075] In a specific example, with L = 30 and K = 30, iTaking P=10 and P=3 as examples, there are a total of 3 connection groups, and each connection group includes 30 vertically stacked second connection parts 102. The first connection group corresponds to the first level to the 10th level, the second connection group corresponds to the 11th level to the 20th level, and the third connection group corresponds to the 21st level to the 30th level. The second connection parts 102 located in the first connection group in the first level to the 10th level are coupled to the corresponding lead-out structures 100 in the 10 lead-out structures 100. The second connection parts 120 located in the second connection group in the 11th level to the 20th level are coupled to the corresponding lead-out structures 100 in the 10 lead-out structures 100. The second connection parts 120 located in the third connection group in the 21st level to the 30th level are coupled to the corresponding lead-out structures 100 in the 10 lead-out structures 100. In some embodiments, the first connection portion 101 in each level can be coupled to a lead-out structure 100 via a second connection portion 102.

[0076] In some embodiments, the K in the a-th connecting part group is related to the K a Each lead-out structure is coupled to K. a The second connecting part 102 is located in the continuous K a In each level, the K in the b-th connection group corresponds to... b Each lead-out structure is coupled to K. b The second connection is located in the continuous K b In each level, and consecutive K a Each level and continuous K b Each level shares at least two consecutive levels, where a and b are any positive integers from 1 to P, and a is not equal to b.

[0077] In a specific example, using L = 30, Ki = 10, and P = 3 as an example, there are three connection groups, and each connection group includes 30 vertically stacked second connection parts 102. The three connection groups are, in order, the first connection group, the second connection group, and the third connection group. The first connection group includes second connection parts 102 from level 1 to level 11, the second connection group includes second connection parts 102 from level 10 to level 21, and the third connection group includes second connection parts 102 from level 20 to level 30. The first and second connection groups share level 10 and level 11, and the second and third connection groups share level 20 and level 21.

[0078] K consecutively in the a-th connecting part group a K consecutively in the level and the b-th connection group b Each level shares a continuous level, which is the Kth level. mLevel and Kth m+1 Taking levels as an example, Ka levels include level 1 to level K. m+1 Hierarchy, K b Each level includes the Kth level. m Level, Kth m+1 Level up to K n The hierarchy, where m is a positive integer greater than 1 and n is a positive integer greater than m+1, operates on the following principle:

[0079] If the Kth m The first word line WL1 corresponding to the layer is selected. The second transistor corresponding to the a-th connection group and the first transistor corresponding to the selected first word line WL1 are both turned on, and the K-th word line in the a-th connection group is connected via the corresponding lead-out structure 100. m The second connection 102 corresponding to the level provides a control signal, which is transmitted to the Kth connection in the a-th connection group via the corresponding lead-out structure 100. m+1 Level and Kth m-1 The second connection portion 102 corresponding to the level provides a reference signal, so that the Kth connection portion in the a-th connection portion group... m+1 Level and Kth m-1 The corresponding second connection portion 102 and first connection portion 101 of the hierarchy, as well as the two word lines WL1 adjacent to the selected word line WL1 in the vertical direction Z, are at a constant reference level, thereby enabling the Kth word line in the a-th connection portion group to pass through. m The parasitic capacitance that the second connection part 102 corresponding to the level is subjected to when providing control signals is relatively small, thereby further improving the storage performance of the memory.

[0080] If the Kth m+1 The first word line WL1 corresponding to the level is selected. The second transistor corresponding to the b-th connection group and the first transistor corresponding to the selected first word line WL1 are both turned on, and the K-th word line in the b-th connection group is connected via the corresponding lead-out structure 100. m+1 The second connection part 102 corresponding to the level provides a control signal, which is sent from the corresponding lead-out structure 100 to the Kth connection part in the b-th connection part group. m Level and Kth m+2 The second connection portion 102 corresponding to each level provides a reference signal, so that the Km level and the Kth level in the b-th connection portion group are respectively provided with reference signals. m+2 The second connecting part 102 and the first connecting part 101 corresponding to the level, as well as the two word lines WL1 adjacent to the selected word line WL1 in the vertical direction Z, are at a constant reference level, thereby enabling the Kth word line in the b-th connecting part group to pass through. m+1 The parasitic capacitance that the second connection part 102 corresponding to the level is subjected to when providing control signals is relatively small, thereby further improving the storage performance of the memory.

[0081] In a specific example, consecutive K a Each level and continuous K b Each level can share two consecutive levels.

[0082] Figure 5 This is a top view schematic diagram of the second connection portion and lead-out structure in a memory provided in some embodiments of this disclosure. Figure 6 A top view of the second connection portion and lead-out structure in a memory provided for other embodiments of this disclosure.

[0083] refer to Figure 5 In some embodiments, K1 = K2 = ... = K P In other words, for the second connecting portion 102 of each connecting portion group, the corresponding lead-out structure 100 is provided on the same side of the second connecting portion 102. That is, each connecting portion group has a corresponding lead-out structure 100 on both opposite sides.

[0084] refer to Figure 6 In other embodiments, P > 2, and K2 = K3 = ... = K P-1 =2K1=2K P In other words, for all connection groups except the first and Pth connection groups, the lead-out structure 100 corresponding to the second connection 102 of each connection group is provided on the same side of the second connection 102. In the first and Pth connection groups, the lead-out structures corresponding to the second connection 102 of each connection group are provided on opposite sides of the second connection 102. That is, the first connection group has a corresponding lead-out structure 100 on the side facing the second connection group, the Pth connection group has a corresponding lead-out structure 100 on the side facing the (P-1)th connection group, and except for the first and Pth connection groups, the other connection groups have corresponding lead-out structures 100 on opposite sides.

[0085] The lead-out structure 100 may include conductive plugs, and each conductive plug is electrically connected to a corresponding second connection portion 102. For example, the lead-out structure 100 is located on at least one side of the second connection portion 102 coupled thereto in the second horizontal direction X.

[0086] refer to Figures 3 to 6 The geometric center of the top surface of each lead-out structure 100 is approximately equidistant from the geometric center of the second connecting portion 102 coupled to it in the second horizontal direction X. The projection of the lead-out structure 100 in the vertical direction can be square or circular, and the geometric center of the top surface of the lead-out structure 100 refers to the center of this projection; the geometric center of the second connecting portion 102 refers to the center of the projection of the second connecting portion 102 in the vertical direction.

[0087] "The distance is basically the same" means that the distances are the same, or the difference in distances is within the allowable range of difference, which can be caused by manufacturing process deviations.

[0088] Figure 7 for Figure 3 A partial cross-sectional view of the first transistor group cut along the Y direction. Figure 7 The schematic diagram of the first transistor is shown.

[0089] refer to Figure 7 The first signal transmission structure 20 includes a plurality of first transistor groups, each first transistor group including L first transistors M1 stacked vertically, the L first transistors M1 in each first transistor group sharing a first gate line 201 extending in a vertical direction, the L first transistors M1 including L first semiconductor layers 202 arranged at intervals in a vertical direction around the first gate line 201, a first gate dielectric layer 203 disposed between the L first semiconductor layers 202 and the first gate line 201, the vertical direction being the direction of the L-level stacking.

[0090] The semiconductor material used in the first semiconductor layer 202 can be the same as the material of the channel region in the memory array, for example, it can be a metal oxide semiconductor material (such as IGZO, indium gallium zinc oxide) or silicon. The first transistor M1 includes a source and a drain, one of which is electrically contacted with the first word line WL1, and the other of which is electrically contacted with the first connection portion.

[0091] In addition, the first transistor M1 has a ring channel structure (CAA, Channel all around), which helps to reduce the volume occupied by the first transistor M1.

[0092] Continue to refer to Figure 7 The side of the first gate line 201 located between adjacent first semiconductor layers 202 may have a protruding portion.

[0093] Figure 8 for Figure 3 A cross-sectional view of the second transistor group cut along the Y direction. Figure 8 The schematic diagram of the second transistor is shown.

[0094] refer to Figure 8The first signal transmission structure 20 includes P second transistor groups, each second transistor group including L second transistors M2 stacked vertically, the L second transistors M2 in each second transistor group sharing a second gate line 211 extending in the vertical direction, the L second transistors M2 including L second semiconductor layers 212 surrounding the second gate line 211 and arranged at intervals in the vertical direction, and a second gate dielectric layer 213 disposed between the L second semiconductor layers 212 and the second gate line 211.

[0095] The semiconductor material used in the second semiconductor layer 212 can be the same as the material used in the channel region of the memory array, for example, it can be a metal oxide semiconductor material (such as IGZO, indium gallium zinc oxide) or silicon. The second transistor M2 includes a source and a drain, one of which is electrically contacted with the second connection portion, and the other of which is electrically contacted with the first connection portion.

[0096] In addition, the second transistor M2 has a ring channel structure (CAA, Channel all around), which helps to reduce the volume occupied by the second transistor M2.

[0097] Continue to refer to Figure 8 The side of the second gate line 211 located between adjacent second semiconductor layers 212 may have a protruding portion.

[0098] Figure 9 This is a top view of the memory structure provided in some embodiments of this disclosure.

[0099] refer to Figure 9 In some embodiments, the vertical stacking structure further includes a second signal transmission structure 30, which is located on opposite sides of the first signal transmission structure 20 in the memory array structure 10. In each level, the second signal transmission structure 30 includes a plurality of third transistors M3, a third connection portion 103, Q fourth transistors M4, and Q fourth connection portions 104. The third connection portions 103 are coupled to a plurality of first word lines WL1 via the plurality of third transistors M3, and the third connection portions are coupled to Q fourth transistors M4 via the Q fourth transistors M4. Each fourth connection portion 104 is coupled to the second signal transmission structure 30, which further includes Q additional connection portion groups and M additional lead-out structures 200. Each additional connection portion group includes L vertically stacked fourth connection portions 104. The M additional lead-out structures are coupled to the M fourth connection portions 104 in the Q additional connection portion groups respectively. Furthermore, the third connection portion 103 in each level is coupled to at least one additional lead-out structure 200 through at least one fourth connection portion 104. Wherein, Q and M are both positive integers, Q≥2, L≤M<2L.

[0100] The descriptions of the third transistor M3, the third connection portion 103, the fourth transistor M4, the fourth connection portion 104, and the additional lead-out structure 200 can be found in the detailed descriptions of the corresponding first transistor M1, the first connection portion 101, the second transistor M2, the second connection portion 102, and the lead-out structure 100, and will not be repeated here.

[0101] In some embodiments, the second signal transmission structure 30 and the first signal transmission structure 20 are axially symmetrical with respect to the memory array structure 10. In other embodiments, the second signal transmission structure 30 and the first signal transmission structure 20 may also be centrally symmetrical with respect to the memory array structure 10.

[0102] For example, the first signal transmission structure 20 is used to provide a control signal to the selected first word line WL1, while the second signal transmission structure 30 is used to provide a reference signal.

[0103] Figure 10 This is a top view of the memory structure provided in some embodiments of this disclosure.

[0104] refer to Figure 10 In some embodiments, the vertically stacked structure further includes a second signal transmission structure 30, which is located on opposite sides of the memory array structure 10, along with the first signal transmission structure 20. In each level, the second signal transmission structure 30 includes a plurality of third transistors M3, a third connection portion 103, and Q fourth connection portions 104. The third connection portion 103 is coupled to a plurality of first word lines WL1 via the plurality of third transistors M3, and is coupled to the Q fourth connection portions 104. The second signal transmission structure 30 also includes Q additional connection portion groups and M additional lead-out structures 200. Each additional connection portion group includes L vertically stacked fourth connection portions 104, and the M additional lead-out structures 200 are coupled to the M fourth connection portions 104 in the Q additional connection portion groups. Furthermore, the third connection portion 103 in each level is coupled to at least one additional lead-out structure 200 via at least one fourth connection portion 104. Wherein, Q and M are both positive integers, Q ≥ 2, and L ≤ M < 2L.

[0105] The third connecting portion 103 and the fourth connecting portion 104 are coupled through direct contact. For a description of the third transistor M3, please refer to the description of the first transistor M1 above. For a description of the third connecting portion 103, the fourth connecting portion 104 and the additional lead-out structure 200, please refer to the detailed descriptions of the first connecting portion 101, the second connecting portion 102 and the lead-out structure 100 above, and will not be repeated here.

[0106] In some embodiments, Q = P, M = N. For example, the first signal transmission structure 20 is used to provide a control signal to the selected first word line WL1, while the second signal transmission structure 30 is used to provide a reference signal.

[0107] Figure 11 This is a top view of the memory structure provided in some embodiments of this disclosure.

[0108] refer to Figure 11 In some embodiments, the vertical stacking structure further includes a second signal transmission structure 30, which is located on opposite sides of the memory array structure 10, along with the first signal transmission structure 20. In each layer, the second signal transmission structure 30 includes a plurality of third transistors M3 and a third connection portion 103. The third connection portion 103 is coupled to a plurality of first word lines WL1 through the plurality of third transistors M3. The second signal transmission structure 30 also includes an additional lead-out structure 200, which is coupled to the third connection portion 103 in L layers.

[0109] For a description of the third transistor M3, please refer to the foregoing detailed description of the first transistor M1, which will not be repeated here.

[0110] For example, the first signal transmission structure 20 is used to provide a control signal to the selected first word line WL1, while the second signal transmission structure 30 is used to provide a reference signal.

[0111] Figure 12 This is a top view of the memory structure provided in some embodiments of this disclosure.

[0112] refer to Figure 12The vertically stacked structure also includes a second signal transmission structure 30, which is located on opposite sides of the memory array structure 10, along with the first signal transmission structure 20. In each level, the memory array structure 10 includes multiple second word lines WL2, and the second signal transmission structure 30 includes multiple third transistors M3, a third connection portion 103, Q fourth transistors, and Q fourth connection portions 104. The multiple second word lines WL2 extend along a first horizontal direction, and the multiple second word lines WL2 and multiple first word lines WL1 are alternately arranged along a second horizontal direction. The third connection portion 103 connects to the multiple second word lines WL2 via the multiple third transistors M3. Lines WL2 are respectively coupled, and the third connection part 103 is respectively coupled to Q fourth connection parts 104 through Q fourth transistors; the second signal transmission structure 30 also includes Q additional connection part groups and M additional lead-out structures 200, each additional connection part group includes L vertically stacked fourth connection parts 104; the M additional lead-out structures 200 are respectively coupled to the M fourth connection parts 104 in the Q additional connection part groups, and the third connection part 103 in each level is coupled to at least one additional lead-out structure 200 through at least one fourth connection part 104; wherein, Q and M are both positive integers, Q≥2, L≤M<2L.

[0113] The structures in the second signal transmission structure 30 are basically the same as those in the first signal transmission structure 20. The main difference is that the structures in the first signal transmission structure 20 are used to couple with the first word line WL1, while the structures in the second signal transmission structure 30 are used to couple with the second word line WL2. Therefore, the descriptions of the third transistor M3, the third connection portion 103, the fourth transistor M4, the fourth connection portion 104, and the additional lead-out structure 200 can be referred to the detailed descriptions of the first transistor M1, the first connection portion 101, the second transistor M2, the second connection portion 102, and the lead-out structure 100, and will not be repeated here.

[0114] In the above embodiment, a first transistor M1 is provided between the first connection portion 101 and the first word line WL1, and a second transistor M2 is provided between the first connection portion 101 and the second connection portion 102. This can significantly reduce the overall parasitic capacitance of the selected first word line in the memory, thereby improving the read and write performance of the memory.

[0115] Accordingly, this disclosure also provides an electronic device. Figure 13 A block diagram of an electronic device provided according to an embodiment of this disclosure. (See reference...) Figure 13 The electronic device includes a processor 301 and a memory 302, the memory 302 being coupled to the processor 301, and the memory 302 including the memory provided in any of the foregoing embodiments.

[0116] The processor 301 described above can refer to one or more processors. For example, processor 301 may include one or more central processing units (CPUs), or it may include a CPU and a graphics processing unit (GPU), or it may include an application processor and a coprocessor (e.g., a microcontroller unit or neural network processor). When processor 301 includes multiple processors, these multiple processors may be integrated on the same chip or may be independent chips. A processor may include one or more physical cores, where a physical core is the smallest processing module.

[0117] As illustrated, the processor 301 can be implemented in at least one of the following hardware forms: Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

[0118] Processor 301 may integrate one or a combination of several of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a modem.

[0119] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A memory, characterized in that, include: A vertically stacked structure having L levels, the vertically stacked structure including a storage array structure and a first signal transmission structure arranged along a first horizontal direction; In each level, the storage array structure includes multiple first word lines, and the first signal transmission structure includes multiple first transistors, a first connection portion, P second transistors, and P second connection portions; The plurality of first word lines extend along the first horizontal direction and are spaced apart along the second horizontal direction, the second horizontal direction intersects the first horizontal direction, the first connection portion is coupled to the plurality of first word lines respectively through the plurality of first transistors, and the first connection portion is coupled to the P second connection portions respectively through the P second transistors; The first signal transmission structure further includes P connection groups and N lead-out structures, each connection group including L vertically stacked second connection parts; K in the i-th connecting part group i The second connecting part and K in the N lead-out structures i Each lead-out structure is coupled to the other, and the first connection portion in each level is coupled to at least one lead-out structure through at least one second connection portion; Where i, L, P, N, K i All are positive integers, i is any positive integer from 1 to P, L≥3, P≥2, L≤N<2L, K i <L, 2. The memory according to claim 1, characterized in that, The i-th connecting part group corresponds to K i Each lead-out structure is coupled to K. i The second connection is located in the continuous K i In each level.

3. The memory according to claim 2, characterized in that, The first connection in each level is coupled to a lead-out structure via a second connection.

4. The memory according to claim 2, characterized in that, The K in the a-th connecting part group a Each lead-out structure is coupled to K. a The second connection is located in the continuous K a In each level, the K in the b-th connection group corresponds to... b Each lead-out structure is coupled to K. b The second connection is located in the continuous K b In each level, the continuous K a Each level and the continuous K b Each level shares at least two consecutive levels, where a and b are any positive integers from 1 to P, and a is not equal to b. a ≥3, K b ≥3.

5. The memory according to claim 4, characterized in that, The continuous K a Each level and the continuous K b Each level shares two consecutive levels.

6. The memory according to any one of claims 1 to 5, characterized in that, K1=K2=…=K P 。 7. The memory according to any one of claims 1 to 5, characterized in that, P>2,K2=K3=…=K P-1 =2K1=2K P 。 8. The memory according to claim 1, characterized in that, The geometric center of the top surface of each lead-out structure and the geometric center of the second connecting part coupled thereto are approximately the same distance in the second horizontal direction.

9. The memory according to any one of claims 1-5, characterized in that, The first signal transmission structure includes a plurality of first transistor groups, each first transistor group including L first transistors stacked vertically, the L first transistors in each first transistor group sharing a first gate line extending in a vertical direction, the L first transistors including L first semiconductor layers surrounding the first gate line and spaced apart in a vertical direction, a first gate dielectric layer being disposed between the L first semiconductor layers and the first gate line, the vertical direction being the direction of stacking the L layers; The first signal transmission structure includes P second transistor groups, each second transistor group including L second transistors stacked vertically, the L second transistors in each second transistor group sharing a second gate line extending in a vertical direction, the L second transistors including L second semiconductor layers arranged at intervals in a vertical direction around the second gate line, and a second gate dielectric layer disposed between the L second semiconductor layers and the second gate line.

10. The memory according to any one of claims 1 to 5, characterized in that, The storage array structure also includes: Multiple bit lines, which extend in a vertical direction, the vertical direction being the direction in which the L levels are stacked; Multiple memory cells, wherein each memory cell is coupled to a corresponding first word line and a corresponding bit line.

11. The memory according to any one of claims 1 to 5, characterized in that, The vertical stacking structure also includes a second signal transmission structure, which is located on opposite sides of the storage array structure as the first signal transmission structure. In each level, the second signal transmission structure includes a plurality of third transistors, a third connection portion, Q fourth transistors and Q fourth connection portions, wherein the third connection portion is coupled to the plurality of first word lines respectively through the plurality of third transistors, and the third connection portion is coupled to the Q fourth connection portions respectively through the Q fourth transistors; The second signal transmission structure further includes Q additional connection groups and M additional lead-out structures. Each additional connection group includes L vertically stacked fourth connection parts. The M additional lead-out structures are respectively coupled to the M fourth connection parts in the Q additional connection groups. Furthermore, the third connection part in each level is coupled to at least one additional lead-out structure through at least one fourth connection part. Where Q and M are both positive integers, Q≥2, L≤M<2L.

12. The memory according to claim 11, characterized in that, The second signal transmission structure is axially or centrally symmetrical with the first signal transmission structure.

13. The memory according to any one of claims 1 to 5, characterized in that, The vertical stacking structure further includes a second signal transmission structure, which is located on opposite sides of the storage array structure as the first signal transmission structure. In each level, the second signal transmission structure includes a plurality of third transistors, a third connection portion and Q fourth connection portions. The third connection portion is coupled to the plurality of first word lines through the plurality of third transistors, and the third connection portion is coupled to the Q fourth connection portions respectively. The second signal transmission structure further includes Q additional connection groups and M additional lead-out structures. Each additional connection group includes L vertically stacked fourth connection parts. The M additional lead-out structures are respectively coupled to the M fourth connection parts in the Q additional connection groups. Furthermore, the third connection part in each level is coupled to at least one additional lead-out structure through at least one fourth connection part. Where Q and M are both positive integers, Q≥2, L≤M<2L.

14. The memory according to claim 13, characterized in that, Q = P, M = N.

15. The memory according to any one of claims 1 to 5, characterized in that, The vertical stacking structure further includes a second signal transmission structure, which is located on opposite sides of the storage array structure as the first signal transmission structure. In each layer, the second signal transmission structure includes a plurality of third transistors and a third connection portion; The third connection portion is coupled to the multiple first word lines respectively through the multiple third transistors; The second signal transmission structure further includes an additional lead-out structure, which is coupled to the third connection portion in each of the L layers.

16. The memory according to any one of claims 1 to 5, characterized in that, The vertical stacking structure further includes a second signal transmission structure, which is located on opposite sides of the storage array structure as the first signal transmission structure. In each level, the memory array structure includes multiple second word lines, and the second signal transmission structure includes multiple third transistors, a third connection portion, Q fourth transistors, and Q fourth connection portions; The plurality of second character lines extend along the first horizontal direction, and the plurality of second character lines and the plurality of first character lines are arranged alternately along the second horizontal direction; The third connection portion is coupled to the plurality of second word lines respectively through the plurality of third transistors, and the third connection portion is coupled to the Q fourth connection portions respectively through the Q fourth transistors; The second signal transmission structure further includes Q additional connection groups and M additional lead-out structures, each additional connection group including L vertically stacked fourth connection parts; The M additional lead-out structures are respectively coupled to the M fourth connection parts in the Q additional connection part groups, and the third connection part in each level is coupled to at least one additional lead-out structure through at least one fourth connection part. Where Q and M are both positive integers, Q≥2, L≤M<2L.

17. An electronic device, characterized in that, include: processor; as well as A memory, wherein the memory is coupled to the processor, the memory comprising the memory according to any one of claims 1-16.

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