Memory and method of forming the same, electronic device
Patent Information
- Application Number
- CN202510550624.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2026-10-30
AI Technical Summary
[0002]在三维存储器中，每层存储单元中的字线需要连接至阶梯结构中对应的台阶，以通过对应的台阶进行驱动；随着存储单元堆叠层数和列数的增加，字线和台阶的连接难度也相应增加，使得存储器的形成难度较高
[0055]这里，由于信号控制区域设置在阵列区域的两侧，并且信号控制区域上设置的选通晶体管组贯穿沿第三方向排列的多个字线，从而可以通过控制字线两端的选通晶体管组开启或关闭，来控制是否对该列字线进行驱动；进一步地，由于选通晶体管组可以控制沿第三方向排列的多个字线，从而使得沿第二方向排列的一行字线可以连接至同一个台阶，进而可以通过选通晶体管组和台阶共同选定需要驱动的字线；如此，减少了台阶的数量，不仅使得字线和台阶的连接难度较小，还可以减少阶梯结构占用的面积，有利于存储器的进一步微缩。
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Figure CN123021641A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a memory and a method of forming the same, and an electronic device. Background Technology
[0002] In three-dimensional memory, the word lines in each layer of memory cells need to be connected to the corresponding steps in the stepped structure to be driven. As the number of stacked layers and columns of memory cells increases, the difficulty of connecting the word lines and steps also increases, making the formation of the memory more challenging. In addition, since the stepped structure occupies a large area in the total array, typically more than 10% of the total array area, it is not conducive to further miniaturization of the memory. Summary of the Invention
[0003] In view of the above, embodiments of the present disclosure provide a memory and a method for forming the same, as well as an electronic device.
[0004] In a first aspect, embodiments of this disclosure provide a memory, the memory comprising:
[0005] The substrate includes an array region and two signal control regions located on opposite sides of the array region along a first direction.
[0006] Multiple word lines located on the array region; the multiple word lines are arranged along a second direction and a third direction, and extend along the first direction to the two signal control regions;
[0007] A plurality of gating transistor groups are located on the signal control region; the plurality of gating transistor groups are arranged along the second direction and extend along the third direction; each of the gating transistor groups includes a plurality of gating transistors spaced apart along the third direction, and the corresponding word lines are truncated by the gating transistors;
[0008] Wherein, the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.
[0009] In some embodiments, the gating transistor group includes:
[0010] A first gate structure is formed to cut off the corresponding word line; the first gate structure includes a first gate conductive layer and a first gate dielectric layer, the first gate dielectric layer surrounds the sidewall of the first gate conductive layer and is located between the word line and the first gate conductive layer; a semiconductor layer surrounds a portion of the surface of the first gate dielectric layer and connects the sidewalls on both sides of the cut-off word line.
[0011] The plurality of first gate conductive layers arranged along the third direction are interconnected to form a gate line.
[0012] In some embodiments, the semiconductor layer is two semi-circular rings or a closed ring.
[0013] In some embodiments, the memory further includes: a stepped structure and a plurality of first connection structures located on one of the signal control regions;
[0014] The plurality of first connection structures are arranged along the third direction and extend along the second direction, and each of the first connection structures is connected to the first end of the plurality of word lines arranged along the second direction;
[0015] The stepped structure, located on the side of the first connection structure away from the gate transistor group, includes multiple steps; each step is electrically connected to the corresponding first connection structure.
[0016] In some embodiments, the memory further includes:
[0017] Multiple conductive pillars extend along the third direction; each conductive pillar is located on the top surface of the corresponding step.
[0018] In some embodiments, the memory further includes a second connection structure located on another of the signal control regions;
[0019] The second connection structure extends along the second direction and the third direction and is connected to the second end of each of the word lines; the first end and the second end are the two ends of the word line along the first direction.
[0020] In some embodiments, the memory further includes: a plurality of memory cells and a plurality of bit lines located on the array region;
[0021] The plurality of storage cells are arranged along the first direction and the second direction and stacked along the third direction; the plurality of storage cells arranged along the first direction are connected to the word line;
[0022] The plurality of bit lines are arranged along the first direction and the second direction and extend along the third direction; the plurality of memory cells arranged along the third direction are connected to the bit lines.
[0023] In some embodiments, the storage unit includes:
[0024] An access transistor includes an active layer and a second gate structure located on the middle surface of the active layer; the second gate structure includes a second gate dielectric layer and a second gate conductive layer sequentially located on the middle surface of the active layer, and a plurality of second gate conductive layers arranged along the first direction are connected to form the word line;
[0025] A capacitor structure is connected to one end of the active layer along the second direction; the bit line is connected to the other end of the active layer along the second direction.
[0026] Secondly, embodiments of this disclosure provide a method for forming a memory, the method comprising:
[0027] A substrate is provided; the substrate includes an array region and two signal control regions located on opposite sides of the array region along a first direction;
[0028] Multiple word lines are formed on the array region; the multiple word lines are arranged along a second direction and a third direction, and extend along the first direction to the two signal control regions;
[0029] A plurality of gating transistor groups are formed on the signal control region; the plurality of gating transistor groups are arranged along the second direction and extend along the third direction, and each of the gating transistor groups passes through a plurality of word lines arranged along the third direction;
[0030] Wherein, the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.
[0031] In some embodiments, the sidewalls of each word line are covered with a first isolation structure, and the gate transistor group includes a plurality of gate transistors spaced apart along the third direction; the gate transistors can be formed by the following steps:
[0032] At least each word line located on the signal control region is etched along the third direction to form a plurality of first etched grooves arranged along the second direction and extending along the third direction; each first etched groove cuts off the plurality of word lines arranged along the third direction.
[0033] The first isolation structure is laterally etched through the first etched groove to form the first lateral groove;
[0034] A semiconductor layer is formed in the first transverse groove; the semiconductor layer connects to the sidewalls on both sides where the word line is cut off;
[0035] In the first etched groove, a first gate dielectric layer and a first gate conductive layer are sequentially formed; the first gate dielectric layer and the first gate conductive layer constitute a first gate structure, and the semiconductor layer and the first gate structure constitute the gate transistor.
[0036] The plurality of first gate conductive layers arranged along the third direction are interconnected to form a gate line.
[0037] In some embodiments, forming a plurality of word lines located on the array region includes:
[0038] On the array region, a plurality of active layers are formed, arranged along the first direction and the second direction and stacked along the third direction;
[0039] A second gate structure is formed on the surface of the middle part of the active layer;
[0040] The second gate structure includes a second gate dielectric layer and a second gate conductive layer located sequentially on the middle surface of the active layer; a plurality of second gate conductive layers arranged along the first direction are connected and extend along the first direction to the two signal control regions to form the word line.
[0041] In some embodiments, the method further includes:
[0042] On the array region, a plurality of bit lines are formed, arranged in the first and second directions and extending along the third direction; the bit lines are connected to one end of the active layer along the second direction; and,
[0043] On the array region, a plurality of capacitor structures are formed, arranged along the first direction and the second direction and stacked along the third direction; the capacitor structure is connected to the other end of the corresponding active layer along the second direction; the active layer, the corresponding second gate structure and the corresponding capacitor structure constitute a memory cell.
[0044] In some embodiments, the method further includes:
[0045] On one of the signal control regions, a plurality of first connection structures are formed, arranged along the third direction and extending along the second direction; each of the first connection structures is connected to a first end of a plurality of word lines arranged along the second direction;
[0046] A stepped structure is formed on the side of the first connection structure away from the gate transistor group; the stepped structure includes a plurality of steps arranged sequentially along the third direction; the dimensions of the plurality of steps decrease sequentially in their extension direction from bottom to top along the third direction; each step is connected to the corresponding first connection structure.
[0047] In some embodiments, the method further includes:
[0048] On the top surface of each step, a conductive post extending in the third direction is formed.
[0049] In some embodiments, the method further includes:
[0050] On another of the signal control regions, a second connection structure is formed extending along the second direction and the third direction; the second connection structure is connected to the second end of each of the word lines; the first end and the second end are the two ends of the word line along the first direction.
[0051] Thirdly, embodiments of this disclosure provide an electronic device, including:
[0052] Processor; and,
[0053] The memory described in any of the above embodiments is coupled to the processor.
[0054] This disclosure provides a memory and a method for forming the same, as well as an electronic device. The memory includes: a substrate; the substrate includes an array region and two signal control regions located on opposite sides of the array region along a first direction; a plurality of word lines located on the array region; the plurality of word lines arranged along a second direction and a third direction, and extending along the first direction to the two signal control regions; a plurality of gate transistor groups located on the signal control regions; the plurality of gate transistor groups arranged along the second direction and extending along the third direction; each gate transistor group includes a plurality of gate transistors spaced apart along the third direction, which truncate corresponding word lines.
[0055] Here, since the signal control area is located on both sides of the array area, and the gating transistor group on the signal control area runs through multiple word lines arranged along the third direction, the driving of a column of word lines can be controlled by turning the gating transistor group at both ends of the word line on or off. Furthermore, since the gating transistor group can control multiple word lines arranged along the third direction, a row of word lines arranged along the second direction can be connected to the same step. Thus, the word line to be driven can be selected by the gating transistor group and the step together. In this way, the number of steps is reduced, which not only makes the connection between word lines and steps easier, but also reduces the area occupied by the stepped structure, which is beneficial for further miniaturization of the memory. Attached Figure Description
[0056] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.
[0057] Figure 1 A schematic diagram of the memory structure provided for related technologies;
[0058] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of this disclosure;
[0059] Figure 3 This is a schematic diagram of the structure of a gating transistor provided in an embodiment of the present disclosure;
[0060] Figure 4 This is a schematic diagram of another gating transistor provided in an embodiment of the present disclosure;
[0061] Figure 5 A schematic diagram of another memory structure provided in an embodiment of this disclosure;
[0062] Figure 6 This is a schematic diagram of the structure of another memory provided in an embodiment of the present disclosure;
[0063] Figure 7 A schematic diagram of another memory structure provided in an embodiment of this disclosure;
[0064] Figure 8 A schematic flowchart illustrating a memory formation method provided in an embodiment of this disclosure;
[0065] Figures 9-14 This is a schematic diagram of the structure during the formation process of the memory provided in the embodiments of this disclosure;
[0066] Figures 15-17 This is a schematic diagram of another memory formation process provided by an embodiment of the present disclosure;
[0067] Figure 18 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation
[0068] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0069] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0070] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0071] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0072] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0073] Please refer to Figure 1 The illustration shows a three-dimensional memory 10 in the related art, where word lines 11 in each memory cell are connected to a corresponding step 121 in a stepped structure 12. A voltage is applied to the corresponding step 121 through a conductive structure 13 to drive the word lines 11. Figure 1 Only word line 11 is shown as an example; memory cells, isolation structures, etc., are not shown. Figure 1 As can be seen, with the increase in the number of stacked layers and columns of memory cells, the number of steps 121 and conductive structures 13 also increases. For example, in the figure, the number of steps 121 and conductive structures 13 are both 21. This not only increases the difficulty of connecting word lines 11 and steps 121, making the formation of memory 10 more difficult, but also increases the coupling between steps 121 (or conductive structures 13), resulting in lower performance of memory 10. In addition, since the stepped structure 12 occupies a large area in the total array, typically more than 10% of the total array area, it is not conducive to further miniaturization of the memory.
[0074] Understandably, in Figure 1 In the middle, adjacent word lines 11 are actually insulated from each other, that is, Figure 1 The insulating layer between adjacent word lines 11 is omitted. Similarly, for the sake of simplicity, some common insulating / dielectric layers may also be omitted in the other figures of this disclosure.
[0075] The memory and its formation method in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0076] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. These three directions may include a first (X-axis) direction, a second (Y-axis) direction, and a third (Z-axis) direction. The Z-axis direction can be a direction perpendicular to the plane where the substrate is located; the X-axis and Y-axis directions are two perpendicular directions on the plane where the substrate is located, wherein the X-axis direction can be the direction in which the letter lines extend.
[0077] This disclosure provides a memory 100, such as... Figure 2 As shown, the memory 100 includes: a substrate 110; the substrate 110 includes an array region A and two signal control regions B located on opposite sides of the array region A along the X-axis direction; a plurality of word lines 120 located on the array region A; the plurality of word lines 120 are arranged along the Y-axis direction and the Z-axis direction and extend along the X-axis direction to the two signal control regions B; a plurality of gate transistor groups 130 located on the signal control regions B; the plurality of gate transistor groups 130 are arranged along the Y-axis direction and extend along the Z-axis direction, and each gate transistor group 130 passes through the plurality of word lines 120 arranged along the Z-axis direction.
[0078] In this embodiment of the disclosure, the substrate 110 may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), etc.
[0079] In this embodiment of the disclosure, please continue to refer to Figure 2 Different functional structures are set on array region A and signal control region B respectively. For example, array region A is provided with a memory array, which can be composed of word lines 120, bit lines and capacitor structures; signal control region B is provided with a signal control structure, which can be composed of a group of gate transistors 130, a ladder structure and a connection structure.
[0080] In this embodiment of the disclosure, please continue to refer to Figure 2 Word lines 120 are used to connect multiple memory cells arranged along the X-axis. The number of layers and columns of word lines 120 can be set according to the number of layers and columns of memory cells (not shown), for example, Figure 2 The word line 120 has 7 layers and 3 columns. Here, the word line 120 extends along the X-axis, that is, the word line 120 is horizontal. This allows multi-layer stacked memory cells to be interconnected through word lines on the same plane, improving the integration of the memory 100.
[0081] In addition, the material of the word line 120 can be any one or any combination of conductive materials such as cobalt (Co), titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, nickel (Ni), tungsten (W), platinum (Pt), molybdenum (Mo), ruthenium (Ru), and palladium (Pd).
[0082] In this embodiment, since the signal control region B is located on both sides of the array region A, and the gating transistor group 130 on the signal control region B passes through multiple word lines 120 arranged along the Z-axis direction, the driving of a column of word lines 120 can be controlled by turning the gating transistor group 130 at both ends of the word line 120 on or off. Furthermore, since the gating transistor group 130 can control multiple word lines 120 arranged along the Z-axis direction, a row of word lines 120 arranged along the Y-axis direction can be connected to the same step (not shown). Thus, the word line 120 to be driven can be selected by the gating transistor group 130 and the step together. In this way, the number of steps is reduced, which not only makes the connection between the word line 120 and the step easier, but also reduces the area occupied by the stepped structure, which is beneficial to the further miniaturization of the memory 100.
[0083] Next, please refer to Figures 3 to 7 The memory 100 is described in detail; among them, Figures 3 to 7 It includes a 3D view, a side view, and a top view.
[0084] In some embodiments, please refer to Figure 3 and Figure 4 The selection transistor group 130 includes a plurality of selection transistors 130' arranged at intervals along the Z-axis, which cut off the corresponding word lines 120. It can be understood that each selection transistor 130' cuts off the corresponding word line 120 and is connected to the two sides of the cut-off word line 120.
[0085] In some embodiments, please refer to Figure 3 and Figure 4The gate transistor 130' includes: a first gate structure and a semiconductor layer 133; the first gate structure includes a first gate conductive layer 131 and a first gate dielectric layer 132, the first gate structure (i.e., the first gate conductive layer 131 and the first gate dielectric layer 132) cuts off the corresponding word line 120; the first gate dielectric layer 132 surrounds the sidewall of the first gate conductive layer 131 and is located between the word line 120 and the first gate conductive layer 131; a plurality of semiconductor layers 133 are arranged at intervals along the Z-axis direction; the semiconductor layers 133 surround a portion of the surface of the first gate dielectric layer 132 and connect the sidewalls on both sides of the cut-off word line 120.
[0086] It should be noted that, for the sake of clarity in describing the structure and connection method of the gating transistor group 130, Figure 3 and Figure 4 Only one group of gating transistors 130 and its word line 120 are shown.
[0087] In this embodiment of the disclosure, please continue to refer to Figure 3 and Figure 4 Multiple first gate conductive layers 131 arranged along the Z-axis are interconnected to form a gate line. Additionally, multiple first gate dielectric layers 132 arranged along the Z-axis can be interconnected (e.g., ...). Figure 3 and Figure 4 (As shown), they can also be independent of each other.
[0088] In this embodiment, the first gate conductive layer 131 is a columnar shape extending along the Z-axis, and its cross-sectional area in the X-axis and Y-axis directions can be circular (e.g., ...). Figure 3 and Figure 4 (As shown), it can also be any shape that can be achieved, such as a square.
[0089] In this embodiment of the disclosure, please continue to refer to Figure 3 and Figure 4 The first gate dielectric layer 132 surrounds all sidewalls of the first gate conductive layer 131; in some other embodiments, the first gate dielectric layer 132 may also surround only a portion of the sidewalls of the first gate conductive layer 131. Additionally, please refer to... Figure 3 and Figure 4 The first gate dielectric layer 132 is also located between the word line 120 and the first gate conductive layer 131. In this way, the word line 120 and the first gate conductive layer 131 can be isolated by the first gate dielectric layer 132 to prevent the word line 120 and the first gate conductive layer 131 from being electrically connected.
[0090] In this embodiment of the disclosure, please refer to Figure 3 The semiconductor layer 133 surrounds the entire surface of the first gate dielectric layer 132; please refer to Figure 4The semiconductor layer 133 may also surround a portion of the surface of the first gate dielectric layer 132. Furthermore, since the plurality of semiconductor layers 133 are spaced apart along the Z-axis direction (see reference...), Figure 3 or Figure 4 (See the left figure in the figure), and connects the sidewalls of the word lines 120 on both sides of the first gate dielectric layer 132 along the X-axis direction, so that each word line 120 is connected to only one corresponding semiconductor layer 133, thereby avoiding electrical connection between adjacent word lines 120.
[0091] Additionally, please refer to Figure 3 Semiconductor layer 133 can be two semi-rings, and semiconductor layer 133 connects to the sidewalls of word line 120 in the Y-axis direction; or, please refer to Figure 4 The semiconductor layer 133 can be a closed ring, and the semiconductor layer 133 connects the sidewalls of the word line 120 in the X-axis direction. It can be understood that the first gate conductive layer 131 and the first gate dielectric layer 132 simultaneously cut off the word line 120, and the semiconductor layer 133 connects the two ends of the cut-off word line 120.
[0092] Further, please refer to Figure 2 and Figure 3 The working principle of the selection transistor group 130 is as follows: when a turn-off voltage is provided to the selection line (i.e., the first gate conductive layer 131), there is no conductive channel in the semiconductor layer 133, so the word line 120 is cut off; when a turn-on voltage is provided to the selection line (i.e., the first gate conductive layer 131), the semiconductor layer 133 is turned on by the electric field, so the two ends of the cut word line 120 can be turned on through the semiconductor layer 133.
[0093] In this embodiment, the material of the first gate conductive layer 131 can be any one or any combination of conductive materials such as cobalt, titanium, titanium nitride, tantalum, tantalum nitride, nickel, tungsten, platinum, molybdenum, ruthenium, and palladium. The material of the first gate dielectric layer 132 can be silicon oxide or other suitable materials. The material of the semiconductor layer 133 can be a semiconductor material such as silicon or germanium, or a metal oxide material, such as indium gallium zinc oxide (IGZO) or indium tin oxide (ITO).
[0094] In some embodiments, please refer to Figure 5 and Figure 6The memory 100 further includes: a stepped structure and a plurality of first connection structures 140 located on a signal control region B; the plurality of first connection structures 140 are arranged along the Z-axis direction and extend along the Y-axis direction, and each first connection structure 140 is connected to a first end of a plurality of word lines 120 arranged along the Y-axis direction; the stepped structure is located on the side of the first connection structure 140 away from the gate transistor group 130 and includes a plurality of steps 141; each step 141 is electrically connected to the corresponding first connection structure 140.
[0095] In this embodiment of the disclosure, please continue to refer to Figure 5 and Figure 6 Each first connection structure 140 connects multiple word lines (three in the figure) arranged along the Y-axis direction, so that step 141 can simultaneously apply voltage to multiple word lines arranged along the Y-axis direction through the corresponding first connection structure 140.
[0096] Furthermore, multiple steps 141 (7 in the figure) are arranged sequentially along the Z-axis and their dimensions decrease sequentially along the Y-axis, thereby enabling the first connection structure 140 of the multi-layer stack to be brought out with the minimum step area. In this way, the wiring in the memory 100 can be reduced, and the memory 100 can be miniaturized.
[0097] In this embodiment, by setting the selection transistor group 130 to conduct multiple word lines arranged in the Z-axis direction, the first connection structure 140 can simultaneously connect multiple word lines arranged in the Y-axis direction, thereby allowing the step 141 to simultaneously apply voltage to the multiple word lines arranged in the Y-axis direction. Specifically, by conducting the column containing the target word line (i.e., the word line to be driven) through the selection transistor group 130, and applying voltage to the row containing the target word line through the step 141, only the target word line is simultaneously conducted and voltage is applied, thus being driven.
[0098] Compared to existing technologies where each character line requires a step to lead out (such as...), Figure 1 As shown, in this embodiment of the present disclosure, a row of word lines (i.e., multiple word lines arranged along the Y-axis) can be led out through a step 141; thus, not only can the area of the stepped structure be significantly reduced (from >10% to less than 1%), but each step 141 can also have stronger driving capability, thereby increasing the number of memory cells connected to the word lines 120 and improving the integration density of the memory 100. In addition, a smaller number of steps 141 can reduce the complexity of the photolithography mask.
[0099] It should be noted that although the connection structure (i.e., the first connection structure and the second connection structure) and the gating transistor also occupy a portion of the area, the area occupied by the connection structure and the gating transistor is much smaller than the area reduced by the stepped structure. Therefore, the structure in the embodiments of this disclosure can realize the miniaturization of the memory.
[0100] In some embodiments, please refer to Figure 5 and Figure 6 The memory 100 also includes a plurality of conductive posts 150, all extending along the Z-axis direction; each conductive post 150 is located on the top surface of the corresponding step 141.
[0101] In this embodiment, by reducing the number of steps 141, the density of the conductive posts 150 is reduced, thereby decreasing the coupling between the conductive posts 150. External voltage (i.e., electrical signals) can be transmitted to the corresponding steps 141 through the conductive posts 150.
[0102] In some embodiments, please refer to Figure 5 and Figure 6 The memory 100 further includes a second connection structure 160 located on another signal control region B; the second connection structure 160 extends along the Y-axis and Z-axis directions and is connected to the second end of each word line 120; the first end and the second end are the two ends of the word line 120 along the X-axis direction.
[0103] In this embodiment of the disclosure, word line 120 needs to maintain a low voltage level when it is not selected, and switch to a high voltage level when word line 120 is selected (i.e., target word line) to ensure normal operation of the memory cell, reduce power consumption and avoid signal interference.
[0104] In implementation, in the initial state, the selection transistor groups 130 of the second terminals of all word lines 120 (connected to the second connection structure 160) are turned on, and the selection transistor groups 130 of the first terminals of all word lines 120 (connected to the first connection structure 140) are turned off. A low-level voltage is provided to all word lines 120 through the second connection structure 160, so that all word lines 120 are in a low-level state. In the working state, the selection transistor groups 130 of the second terminal of the target word line (connected to the second connection structure 160) are turned off, the selection transistor groups 130 of the first terminal of the target word line (connected to the first connection structure 140) are turned on, and the remaining selection transistor groups 130 remain in the initial state. At the same time, a high-level voltage is applied to the row where the target word line is located through the step 141, thus achieving a high-level voltage for the target word line and a low-level voltage for the remaining word lines.
[0105] In this embodiment of the disclosure, the materials of the first connecting structure 140, the step 141, the conductive post 150, and the second connecting structure 160 can be any one or any combination of conductive materials such as cobalt, titanium, titanium nitride, tantalum, tantalum nitride, nickel, tungsten, platinum, molybdenum, ruthenium, and palladium.
[0106] In some embodiments, please refer to Figure 7The memory 100 further includes: a plurality of memory cells 170 and a plurality of bit lines 180 located on array region A; the plurality of memory cells 170 are arranged along the X-axis and Y-axis directions and stacked along the Z-axis direction; the plurality of memory cells 170 arranged along the X-axis direction are connected to word lines 120; the plurality of bit lines 180 are arranged along the X-axis and Y-axis directions and extend along the Z-axis direction; the plurality of memory cells 170 arranged along the Z-axis direction are connected to bit lines 180.
[0107] In this embodiment of the disclosure, the material of bit line 180 can be any one or any combination of conductive materials such as cobalt, titanium, titanium nitride, tantalum, tantalum nitride, nickel, tungsten, platinum, molybdenum, ruthenium, and palladium.
[0108] It should be noted that, for ease of understanding, Figure 7 A column was shown Figure 6 The structure in the dashed area shown is not illustrated, and steps and conductive pillars are not shown.
[0109] In some embodiments, please refer to Figure 7 The memory cell 170 includes an access transistor and a capacitor structure 173. The access transistor includes an active layer 171 and a second gate structure 172 located on the middle surface of the active layer 171. The second gate structure 172 includes a second gate dielectric layer 172a and a second gate conductive layer 172b sequentially located on the middle surface of the active layer 171. A plurality of second gate conductive layers 172b arranged along the X-axis are connected to form a word line 120. The capacitor structure 173 is connected to one end of the active layer 171 along the Y-axis; a bit line 180 is connected to the other end of the active layer 171 along the Y-axis.
[0110] In this embodiment of the present disclosure, the active layer 171 includes a channel, and source and drain electrodes located on both sides of the channel along the Y-axis direction; wherein, the active layer 171 may be a single-channel structure (e.g., Figure 7 As shown), a dual-channel structure, etc. The second gate structure 172 is located on the channel surface of the active layer 171; wherein, the second gate structure 172 can be a single-gate structure, a dual-gate structure (as shown), etc. Figure 7 (as shown) or a full-ring gate structure, etc.
[0111] In this embodiment of the disclosure, please continue to refer to Figure 7 Bit line 180 is connected to the source of active layer 171. Capacitor structure 173 is connected to the drain of active layer 171; wherein, capacitor structure 173 includes a first electrode connected to the source, and a dielectric layer and a second electrode sequentially located on the surface of the first electrode.
[0112] In this embodiment, the capacitor structure 173 extends along the Y-axis, meaning it is arranged horizontally. This horizontal arrangement reduces the likelihood of tipping or breaking, thus improving the stability of the capacitor structure. Furthermore, multiple horizontal capacitor structures 173 can be stacked to form a three-dimensional memory, thereby increasing the memory's integration density and enabling miniaturization. In other embodiments, the capacitor structure 173 can be any other achievable structure, and this disclosure is not limiting in this regard.
[0113] In this embodiment, the active layer 171 can be made of semiconductor materials such as silicon and germanium, or it can be made of metal oxide materials, such as IGZO or ITO. The second gate dielectric layer 172a can be made of silicon oxide or other suitable materials. The materials of the first electrode and the second electrode can include metal nitrides or metal silicides, such as titanium nitride; the dielectric layer can include high-k dielectric materials, such as lanthanum oxide, aluminum oxide, hafnium oxide, etc.
[0114] In this embodiment of the present disclosure, the memory 100 further includes an isolation structure (not shown) located between adjacent conductive structures; for example, between the first connection structures 141, between memory cells 170, etc.; the isolation structure can reduce the generation of leakage current. The material of the isolation structure can be any suitable material.
[0115] In addition, this disclosure also provides a method for forming a memory 100. Figure 8 This is a flowchart illustrating the method for forming a memory 100 according to an embodiment of the present disclosure, as shown below. Figure 8 As shown, the method of the memory 100 includes steps S110 to S130.
[0116] Step S110, provide as follows Figure 9 The substrate 110 shown includes an array region A and two signal control regions B located on opposite sides of the array region A along the X-axis direction.
[0117] Step S120: Multiple word lines 120 are formed on array region A; the multiple word lines 120 are arranged along the Y-axis and Z-axis directions and extend along the X-axis to two signal control regions B.
[0118] In some embodiments, the word line 120 can be formed by the following steps: in such a way as Figure 9 On the array region A shown, multiple active layers are formed, arranged along the X-axis and Y-axis directions and stacked along the Z-axis direction (see reference). Figure 7 A second gate structure is formed on the surface of the middle part of the active layer (see reference). Figure 7The second gate structure includes a second gate dielectric layer 172a and a second gate conductive layer 172b located sequentially on the middle surface of the active layer; a plurality of second gate conductive layers 172b arranged along the X-axis direction are connected and extend along the X-axis direction to two signal control regions B to form word lines 120.
[0119] It should be noted that the embodiments disclosed herein are illustrated using the example of forming three columns of word lines 120 arranged along the Y-axis direction; Figure 10 Only the structure on the signal control region B is shown. The structure on the array region A can be formed according to any suitable process method, and this disclosure does not limit it. The specific structure on the array region A can be understood from the above embodiments, and will not be repeated here.
[0120] In some embodiments, the method of forming the memory 100 further includes: forming a plurality of bit lines arranged in the X-axis and Y-axis directions and extending along the Z-axis direction on the array region A (see reference). Figure 7 The bit line is connected to one end of the active layer along the Y-axis; and multiple capacitor structures are formed on array region A, arranged along the X-axis and Y-axis and stacked along the Z-axis (see reference). Figure 7 The capacitor structure is connected to the other end of the corresponding active layer along the Y-axis; the active layer, the corresponding second gate structure, and the corresponding capacitor structure constitute a memory cell.
[0121] In this embodiment of the disclosure, please refer to Figure 10 Each character line 120 has its sidewall covered by a first isolation structure 191, and adjacent character lines 120 are filled with a second isolation structure 192. The first isolation structure 191 and the second isolation structure 192 constitute as follows: Figure 10 The isolation structure 190 is shown.
[0122] In this embodiment, the first isolation structure 191 can be made of silicon nitride, and the second isolation structure 192 can be made of silicon oxide. This ensures that the second isolation structure 192 is not etched while the first isolation structure 191 is being etched. In other embodiments, the first isolation structure 191 and the second isolation structure 192 can also be made of other materials with different etching selectivity ratios.
[0123] In step S130, a plurality of selection transistor groups 130 are formed on the signal control region B; the plurality of selection transistor groups 130 are arranged along the Y-axis direction and extend along the Z-axis direction, and each selection transistor group 130 passes through a plurality of word lines 120 arranged along the Z-axis direction.
[0124] In some embodiments, the gate transistor group 130 includes a plurality of gate transistors 130' spaced apart along the Z-axis direction; to form the above-mentioned... Figure 3Taking the selected transistor 130' shown as an example, the selected transistor 130' can be formed by the following steps: etching at least each word line 120 located on the signal control region B along the Z-axis direction to form a plurality of such words arranged along the Y-axis direction and extending along the Z-axis direction. Figure 11 The first etched groove 130a is shown; each first etched groove 130a cuts off multiple word lines 120 arranged along the Z-axis direction. The first isolation structure 191 is laterally etched through the first etched groove 130a to form... Figure 12 The first transverse groove 130b shown; in the first transverse groove 130b, a structure is formed as follows Figure 13 The semiconductor layer 133 shown has its sidewalls truncated on both sides of the word line 120; here, the semiconductor layer 133 can be two semi-annular shapes (see top view for reference). Figure 3 Semiconductor layer 133 connects word line 120 to the sidewall in the Y-axis direction.
[0125] Next, in the first etched groove 130a, as shown in the figure, are formed sequentially. Figure 14 The diagram shows a first gate dielectric layer 132 and a first gate conductive layer 131. The first gate dielectric layer 132 and the first gate conductive layer 131 constitute a first gate structure, and the semiconductor layer 133 and the first gate structure (i.e., the first gate dielectric layer 132 and the first gate conductive layer 131) constitute a gate transistor 130'. Multiple first gate conductive layers 131 arranged along the Z-axis are interconnected to form a gate line; simultaneously, multiple first gate dielectric layers 132 arranged along the Z-axis can also be interconnected.
[0126] In this embodiment, the working principle of the selection transistor 130' is as follows: when a turn-off voltage is provided to the first gate conductive layer 131 (i.e., the selection line), there is no conductive channel in the semiconductor layer 133, so the word line 120 is cut off; when a turn-on voltage is provided to the first gate conductive layer 131 (i.e., the selection line), the semiconductor layer 133 is turned on by the electric field, so that the two ends of the cut-off word line 120 can be turned on through the semiconductor layer 133.
[0127] The deposition processes involved in the embodiments of this disclosure include, but are not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD). The growth processes involved include, but are not limited to, vapor phase epitaxy (VPE). The etching processes described in the embodiments of this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.
[0128] In some embodiments, the method of forming the memory 100 further includes: forming a plurality of first connection structures arranged along the Z-axis direction and extending along the Y-axis direction on a signal control region B (see reference). Figure 7 Each first connection structure is connected to the first end of a plurality of word lines 120 arranged along the Y-axis; a stepped structure is formed on the side of the first connection structure 140 away from the gate transistor group 130 (see reference). Figure 6 The stepped structure includes multiple steps 141 arranged sequentially along the Z-axis; the dimensions of the multiple steps 141 decrease sequentially in their extension direction from bottom to top along the Z-axis; each step 141 is connected to a corresponding first connecting structure 140.
[0129] In some embodiments, the method of forming the memory 100 further includes: forming conductive pillars 150 extending along the Z-axis direction on the top surface of each step 141 (see reference). Figure 6 ).
[0130] In some embodiments, the method of forming the memory 100 further includes: forming a second connection structure 160 extending along the Y-axis and Z-axis directions on another signal control region B; the second connection structure 160 is connected to a second end of each word line 120; the first end and the second end are the two ends of the word line 120 along the X-axis direction.
[0131] In this embodiment, since the signal control region B is located on both sides of the array region A, and the gating transistor group 130 on the signal control region B passes through multiple word lines 120 arranged along the Z-axis direction, the driving of a column of word lines 120 can be controlled by turning the gating transistor group 130 at both ends of the word line 120 on or off. Furthermore, since the gating transistor group 130 can control multiple word lines 120 arranged along the Z-axis direction, a row of word lines 120 arranged along the Y-axis direction can be connected to the same step (not shown). Thus, the word line 120 to be driven can be selected by the gating transistor group 130 and the step together. In this way, the number of steps is reduced, which not only makes the connection between the word line 120 and the step easier, but also reduces the area occupied by the stepped structure, which is beneficial to the further miniaturization of the memory 100.
[0132] This disclosure also provides embodiments such as Figure 4 The method for forming the memory 100 shown. Figures 15 to 17 This is a schematic diagram of the formation process of another memory 100 provided in an embodiment of the present disclosure.
[0133] Step S110, provide as follows Figure 9 The substrate 110 shown includes an array region A and two signal control regions B located on opposite sides of the array region A along the X-axis direction.
[0134] Step S120: Multiple word lines 120 are formed on array region A; the multiple word lines 120 are arranged along the Y-axis and Z-axis directions and extend along the X-axis to two signal control regions B.
[0135] In step S130, a plurality of selection transistor groups 130 are formed on the signal control region B; the plurality of selection transistor groups 130 are arranged along the Y-axis direction and extend along the Z-axis direction, and each selection transistor group 130 passes through a plurality of word lines 120 arranged along the Z-axis direction.
[0136] In implementation, the gate transistor group 130 includes a plurality of gate transistors 130' arranged at intervals along the Z-axis direction; such as Figure 4 The shown gate transistor 130' can be formed by the following steps: etching at least each word line 120 located on the signal control region B along the Z-axis direction to form a plurality of such words arranged along the Y-axis direction and extending along the Z-axis direction. Figure 15 The first etched groove 130a is shown; each first etched groove 130a cuts off multiple word lines 120 arranged along the Z-axis direction. Through the first etched groove 130a, the first isolation structure 191 and the word lines 120 are etched laterally to form a shape as shown. Figure 15 The first transverse groove 130b shown; in the first transverse groove 130b, a structure is formed as follows Figure 16 The semiconductor layer 133 shown has its sidewalls truncated on both sides of the word line 120; here, the semiconductor layer 133 can be a closed ring (see top view for reference). Figure 4 The semiconductor layer 133 connects the word line 120 to the sidewall in the X-axis direction.
[0137] Next, in the first etched groove 130a, as shown in the figure, are formed sequentially. Figure 17 The diagram shows a first gate dielectric layer 132 and a first gate conductive layer 131; the first gate dielectric layer 132 and the first gate conductive layer 131 constitute a first gate structure, and the semiconductor layer 133 and the first gate structure (i.e., the first gate dielectric layer 132 and the first gate conductive layer 131) constitute a gate transistor 130'. The plurality of first gate conductive layers 131 arranged along the Z-axis direction are interconnected; simultaneously, the plurality of first gate dielectric layers 132 arranged along the Z-axis direction can also be interconnected.
[0138] The memory formed by the forming method provided in this embodiment is similar to the memory in the above embodiments. For technical features not disclosed in detail in this embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.
[0139] This disclosure also provides an electronic device, Figure 18This is a schematic diagram of the structure of an electronic device 300 provided in an embodiment of the present disclosure, as shown below. Figure 18 As shown, the electronic device 300 includes: a processor 310; and a memory 100 in any of the above embodiments; wherein the memory is coupled to the processor.
[0140] In some embodiments, the electronic device includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.
[0141] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.
[0142] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.
[0143] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A memory, characterized in that, include: The substrate includes an array region and two signal control regions located on opposite sides of the array region along a first direction. Multiple word lines located on the array region; The plurality of word lines are arranged along the second direction and the third direction, and extend along the first direction to the two signal control areas; A plurality of gating transistor groups are located on the signal control region; the plurality of gating transistor groups are arranged along the second direction and extend along the third direction; each of the gating transistor groups includes a plurality of gating transistors spaced apart along the third direction, and the corresponding word lines are truncated by the gating transistors; Wherein, the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.
2. The memory according to claim 1, characterized in that, The gating transistor includes: A first gate structure is used to cut off the corresponding word line; the first gate structure includes a first gate conductive layer and a first gate dielectric layer, the first gate dielectric layer surrounds the sidewall of the first gate conductive layer and is located between the word line and the first gate conductive layer; A semiconductor layer, surrounding a portion of the surface of the first gate dielectric layer and connecting the sidewalls on both sides where the word line is cut off; The plurality of first gate conductive layers arranged along the third direction are interconnected to form a gate line.
3. The memory according to claim 2, characterized in that, The semiconductor layer is either two semi-circular or a closed ring.
4. The memory according to claim 1, characterized in that, The memory further includes: a stepped structure and a plurality of first connection structures located on one of the signal control regions; The plurality of first connection structures are arranged along the third direction and extend along the second direction, and each of the first connection structures is connected to the first end of the plurality of word lines arranged along the second direction; The stepped structure, located on the side of the first connection structure away from the gating transistor group, includes multiple steps; each step is electrically connected to the corresponding first connection structure.
5. The memory according to claim 4, characterized in that, The memory also includes: Multiple conductive pillars extend along the third direction; each conductive pillar is located on the top surface of the corresponding step.
6. The memory according to claim 4, characterized in that, The memory further includes a second connection structure located on another of the signal control regions; The second connection structure extends along the second direction and the third direction and is connected to the second end of each of the word lines; the first end and the second end are the two ends of the word line along the first direction.
7. The memory according to claim 1, characterized in that, The memory further includes: a plurality of memory cells and a plurality of bit lines located on the array region; The plurality of storage cells are arranged along the first direction and the second direction and stacked along the third direction; the plurality of storage cells arranged along the first direction are connected to the word line; The plurality of bit lines are arranged along the first direction and the second direction and extend along the third direction; the plurality of memory cells arranged along the third direction are connected to the bit lines.
8. The memory according to claim 7, characterized in that, The storage unit includes: An access transistor includes an active layer and a second gate structure located on the middle surface of the active layer; the second gate structure includes a second gate dielectric layer and a second gate conductive layer sequentially located on the middle surface of the active layer, and a plurality of second gate conductive layers arranged along the first direction are connected to form the word line; A capacitor structure is connected to one end of the active layer along the second direction; the bit line is connected to the other end of the active layer along the second direction.
9. A method for forming a memory, characterized in that, The method includes: A substrate is provided; the substrate includes an array region and two signal control regions located on opposite sides of the array region along a first direction; Multiple word lines are formed on the array region; the multiple word lines are arranged along a second direction and a third direction, and extend along the first direction to the two signal control regions; A plurality of gating transistor groups are formed on the signal control region; the plurality of gating transistor groups are arranged along the second direction and extend along the third direction, and each of the gating transistor groups passes through a plurality of word lines arranged along the third direction; Wherein, the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.
10. The method for forming a memory according to claim 9, characterized in that, Each word line has a sidewall covered by a first isolation structure, and the gate transistor group includes a plurality of gate transistors spaced apart along the third direction; the gate transistors can be formed by the following steps: At least each word line located on the signal control region is etched along the third direction to form a plurality of first etched grooves arranged along the second direction and extending along the third direction; each first etched groove cuts off the plurality of word lines arranged along the third direction. The first isolation structure is laterally etched through the first etched groove to form the first lateral groove; A semiconductor layer is formed in the first transverse groove; the semiconductor layer connects to the sidewalls on both sides where the word line is cut off; In the first etched groove, a first gate dielectric layer and a first gate conductive layer are sequentially formed; the first gate dielectric layer and the first gate conductive layer constitute a first gate structure, and the semiconductor layer and the first gate structure constitute the gate transistor. The plurality of first gate conductive layers arranged along the third direction are interconnected to form a gate line.
11. The method for forming a memory according to claim 9, characterized in that, Forming multiple word lines located on the array region includes: On the array region, a plurality of active layers are formed, arranged along the first direction and the second direction and stacked along the third direction; A second gate structure is formed on the surface of the middle part of the active layer; The second gate structure includes a second gate dielectric layer and a second gate conductive layer located sequentially on the middle surface of the active layer; a plurality of second gate conductive layers arranged along the first direction are connected and extend along the first direction to the two signal control regions to form the word line.
12. The method for forming a memory according to claim 11, characterized in that, The method further includes: On the array region, a plurality of bit lines are formed, arranged in the first and second directions and extending along the third direction; the bit lines are connected to one end of the active layer along the second direction; and, On the array region, a plurality of capacitor structures are formed, arranged along the first direction and the second direction and stacked along the third direction; the capacitor structure is connected to the other end of the corresponding active layer along the second direction; the active layer, the corresponding second gate structure and the corresponding capacitor structure constitute a memory cell.
13. The method for forming a memory according to claim 9, characterized in that, The method further includes: On one of the signal control regions, a plurality of first connection structures are formed, arranged along the third direction and extending along the second direction; each of the first connection structures is connected to a first end of a plurality of word lines arranged along the second direction; A stepped structure is formed on the side of the first connection structure away from the gate transistor group; the stepped structure includes a plurality of steps arranged sequentially along the third direction; the dimensions of the plurality of steps decrease sequentially in their extension direction from bottom to top along the third direction; each step is connected to the corresponding first connection structure.
14. The method for forming a memory according to claim 13, characterized in that, The method further includes: On the top surface of each step, a conductive post extending in the third direction is formed; On another of the signal control regions, a second connection structure is formed extending along the second direction and the third direction; the second connection structure is connected to the second end of each of the word lines; the first end and the second end are the two ends of the word line along the first direction.
15. An electronic device, characterized in that, include: processor; as well as A memory, wherein the memory is coupled to the processor, the memory comprising the memory according to any one of claims 1-7.