Semiconductor structure and method of forming the same, electronic device

Abstract

The embodiments of the present disclosure provide a semiconductor structure and a forming method thereof, and an electronic device; the semiconductor structure comprises: a substrate; the substrate comprises an array region and a step region located on a side of the array region along a first direction; a plurality of first conductor groups located on the array region; the plurality of first conductor groups are arranged along a second direction and a third direction and extend to the step region along the first direction; each conductor group comprises a plurality of first conductive lines arranged along the second direction and extending along the first direction; a plurality of step structures located on the step region; the plurality of step structures are arranged along the second direction, each step structure comprises a plurality of steps arranged along the third direction; and the first conductor group is connected to a corresponding step.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same, and electronic devices. Background Technology

[0002] With the increasing demands for integration and storage capacity from various electronic devices, three-dimensional (3D) stacked semiconductor structures have emerged.

[0003] In related technologies, the number of memory cells that a single word line can control is increased by increasing the length of the word line in the semiconductor structure, thereby improving the integration density of the semiconductor structure. However, as the word line length increases, the parasitic capacitance and resistance on the word line also increase, resulting in a larger signal delay at the memory cell at the end of the word line, which in turn reduces the performance of the semiconductor structure. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for forming the same, and an electronic device.

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0006] Substrate; the substrate includes an array region and a stepped region located on one side of the array region along a first direction;

[0007] A plurality of first conductor groups are located on the array region; the plurality of first conductor groups are arranged along a second direction and a third direction and extend along the first direction to the step region; each first conductor group includes a plurality of first conductive lines arranged along the second direction and extending along the first direction;

[0008] Multiple stepped structures are located on the stepped area; the multiple stepped structures are arranged along the second direction, and each stepped structure includes multiple steps arranged along the third direction; the first wire group is connected to a corresponding step;

[0009] Wherein, the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

[0010] In some embodiments, each of the first conductor groups further includes:

[0011] A connection structure extending along the second direction, the connection structure being connected between a plurality of first conductive lines arranged along the second direction and the corresponding steps.

[0012] In some embodiments, the semiconductor structure further includes:

[0013] A plurality of memory cells are located on the array region; the memory cells are arranged along the first direction and the second direction and stacked along the third direction; each of the first conductive lines is electrically connected to the plurality of memory cells arranged along the first direction.

[0014] In some embodiments, the semiconductor structure further includes:

[0015] A plurality of second conductor groups are located on the array region; the plurality of second conductor groups are arranged along the first direction and the second direction and extend along the third direction;

[0016] The storage cells, which are connected to a plurality of first wire groups arranged along the third direction, are connected to a plurality of second wire groups arranged along the first direction.

[0017] In some embodiments, the second conductor group includes:

[0018] A plurality of second conductive lines are arranged along the second direction and extend along the third direction; each of the second conductive lines is connected to a plurality of the memory cells arranged along the third direction.

[0019] In some embodiments, multiple second conductive lines located in the same second conductor group are connected to different signal interconnects.

[0020] In some embodiments, one of the second conductive lines in each of the second conductor groups arranged along the second direction is connected to the same signal interconnect.

[0021] In some embodiments, the array region and the stepped region are arranged alternately along the first direction;

[0022] Along the first direction, every two adjacent columns of the first conductor group are connected to the same stepped structure.

[0023] In some embodiments, the step connected to the first conductor group and the step connected to the first conductor group adjacent to the second direction are located in different step regions.

[0024] In some embodiments, the storage unit includes:

[0025] Access transistor; the access transistor includes an active layer extending along the second direction and a gate structure located on the middle surface of the active layer; the gate structure includes a gate dielectric layer and a gate metal layer sequentially located on the middle surface of the active layer, and a plurality of the gate metal layers arranged along the first direction are connected to form the first conductive line.

[0026] In some embodiments, the storage unit further includes:

[0027] A capacitor structure is connected to one end of the active layer along the second direction; the second conductive line is connected to the other end of the active layer along the second direction.

[0028] In some embodiments, the capacitor structure includes:

[0029] A first electrode layer connected to one end of the active layer along the second direction, and a dielectric layer and a second electrode layer sequentially covering the first electrode layer.

[0030] In some embodiments, two adjacent memory cells arranged along the second direction share the second conductive line, and / or two adjacent memory cells arranged along the second direction share the second electrode layer.

[0031] In a second aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising:

[0032] A substrate is provided; the substrate includes an array region and a stepped region located on one side of the array region along a first direction;

[0033] A plurality of first conductor groups are formed on the array region; the plurality of first conductor groups are arranged along a second direction and a third direction and extend along the first direction to the step region; each first conductor group includes a plurality of first conductive lines arranged along the second direction and extending along the first direction;

[0034] Multiple stepped structures are formed on the stepped area; the multiple stepped structures are arranged along the second direction, and each stepped structure includes multiple steps arranged along the third direction; the first wire group is connected to a corresponding step;

[0035] Wherein, the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

[0036] Thirdly, embodiments of this disclosure provide an electronic device, including: a semiconductor structure as described in any of the above embodiments, or a semiconductor structure formed according to the semiconductor structure formation method described in the above embodiments.

[0037] This disclosure provides a semiconductor structure and a method for forming the same, as well as an electronic device. The semiconductor structure includes: a substrate; the substrate includes an array region and a stepped region located on one side of the array region along a first direction; a plurality of first conductive wire groups located on the array region; the plurality of first conductive wire groups are arranged along a second direction and a third direction, and extend along the first direction to the stepped region; each conductive wire group includes a plurality of first conductive lines arranged along the second direction and extending along the first direction; a plurality of stepped structures located on the stepped region; the plurality of stepped structures are arranged along the second direction, and each stepped structure includes a plurality of steps arranged along a third direction; the first conductive wire groups are connected to a corresponding step.

[0038] Here, since the first conductor group includes a plurality of first conductive lines arranged along the second direction and extending along the first direction, and the first conductor group is connected to the corresponding step, the plurality of first conductive lines in the first conductor group can be controlled through the corresponding step; thus, without reducing the total length of the plurality of first conductive lines in the first conductor group, the length of a single first conductive line is reduced, thereby reducing the parasitic capacitance and resistance on the first conductive line, reducing signal delay, and improving the performance of the semiconductor structure. Attached Figure Description

[0039] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0040] Figures 1 to 12 This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0041] Figure 13 A schematic flowchart illustrating a semiconductor structure formation method provided in this embodiment of the disclosure;

[0042] Figure 14 This is a schematic diagram of the structure during the formation process of the memory provided in the embodiments of this disclosure;

[0043] Figure 15 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0044] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0045] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0046] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] The semiconductor structure and its formation method in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0050] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. These three directions may include the X-axis, Y-axis, and Z-axis. The Z-axis direction can be a direction perpendicular to the plane where the substrate is located; the X-axis and Y-axis directions are two perpendicular directions on the plane where the substrate is located, wherein the X-axis direction can be the direction in which the first conductive line extends.

[0051] This disclosure provides a semiconductor structure 100, such as... Figure 1 As shown, the semiconductor structure 100 includes: a substrate 110; the substrate 110 includes an array region A and a stepped region B located on one side of the array region A along the X-axis direction; a plurality of first conductive wire groups 120 located on the array region A; the plurality of first conductive wire groups 120 are arranged along the Y-axis direction and the Z-axis direction and extend to the stepped region B along the X-axis direction; each first conductive wire group 120 includes a plurality of first conductive lines 121 arranged along the Y-axis direction and extending along the X-axis direction; a plurality of stepped structures 130 located on the stepped region B; the plurality of stepped structures 130 are arranged along the Y-axis direction, and each stepped structure 130 includes a plurality of steps 131 arranged along the Z-axis direction; the first conductive wire groups 120 are connected to a corresponding step 131.

[0052] In this embodiment of the disclosure, the substrate 110 may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), etc.

[0053] Please refer to the embodiments disclosed herein. Figure 1 Different functional structures are set on array region A and step region B respectively. For example, array region A is provided with a storage array, which can be composed of storage cells, a first wire group 120, a second wire group and a capacitor structure; step region B is provided with a step structure 130.

[0054] In this embodiment, since the first conductor group 120 is connected to the corresponding step 131, and the first conductor group 120 includes a plurality of first conductive lines 121 arranged along the Y-axis and extending along the X-axis, the step 131 can simultaneously control the multiple first conductive lines 121 to be turned on or off. Furthermore, each first conductive line 121 is used to connect multiple memory cells arranged along the X-axis. Without reducing the number of memory cells that can be controlled simultaneously, the number of memory cells connected by a single first conductive line 121 is lower, that is, the length of a single first conductive line 121 is lower. This reduces the parasitic capacitance and resistance on a single first conductive line, reduces signal delay, and improves the performance of the semiconductor structure.

[0055] In this embodiment of the disclosure, the number of the first conductor group 120 and the number of the first conductive wires 121 in the first conductor group 120 can be set according to actual needs. For example... Figure 1 As shown, when the number of layers of the storage cell (not shown) is 5 and the number of columns is 4, if each first conductor group 120 needs to control two rows of storage cells arranged along the Y-axis direction at the same time, the number of first conductive lines 121 included in each first conductor group 120 can be 2, so the number of layers of the first conductor group 120 can be 5 and the number of columns can be 2.

[0056] It should be noted that in this embodiment of the present disclosure, the first conductive line 121 can be a word line, and the stepped structure 130 can be a word line step. In other embodiments, the first conductive line 121 can also be a bit line, and the stepped structure 130 can be a bit line step.

[0057] In addition, the material of the first conductive wire 121 (i.e. the first conductor group 120) can be any one or any combination of conductive materials such as cobalt (Co), titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, nickel (Ni), tungsten (W), platinum (Pt) and palladium (Pd).

[0058] Please refer to the embodiments disclosed herein. Figure 1 The first wire group 120 extends along the X-axis direction, that is, the first wire group 120 is horizontal. This enables multi-layer stacked memory cells to be interconnected through word lines on the same plane, thereby improving the integration of the semiconductor structure 100.

[0059] Next, please refer to Figures 2 to 12 The semiconductor structure 100 is described in detail; among them, Figures 2 to 12 It includes a 3D view, a side view, and a top view.

[0060] First, the first conductor group 120 will be described in detail. In some embodiments, please refer to... Figure 2 ,or Figure 3 and Figure 4 The first conductor group 120 further includes a connecting structure 122 extending along the Y-axis direction, the connecting structure 122 connecting between a plurality of first conductive lines 121 arranged along the Y-axis direction and the corresponding steps 131.

[0061] Please refer to the embodiments disclosed herein. Figure 2 ,or Figure 3 and Figure 4 Each connection structure 122 connects to multiple first conductive lines 121 arranged along the Y-axis (two are shown in the figure), so that step 131 can simultaneously apply voltage to multiple first conductive lines 121 arranged along the Y-axis through the corresponding connection structure 122.

[0062] Here, the material of each connecting structure 122 can be any one or any combination of conductive materials such as cobalt, titanium, titanium nitride, tantalum, tantalum nitride, nickel, tungsten, platinum and palladium.

[0063] Furthermore, the stepped structure 130 can be any suitable structure. For example, please refer to... Figure 2 The top view of the stepped structure 130 is ring-shaped. This allows multiple steps 131 (five shown in the illustration) to be distributed on both sides of the ring along the X-axis, thereby reducing the density of the steps 131 along the Z-axis, thus reducing crosstalk between signals and improving the performance of the semiconductor structure. For example, please refer to... Figure 3 and Figure 4 The top view of the stepped structure 130 is a straight line. This allows multiple steps 131 (5 in the figure) to be arranged sequentially along the Z-axis and their dimensions to decrease sequentially along the Y-axis. This enables the multi-layer stacked connection structure 122 (i.e., the first wire group 120) to be led out with the minimum step area. This reduces the wiring in the semiconductor structure 100 and enables the miniaturization of the semiconductor structure 100.

[0064] It should be noted that, Figure 4 Only exemplary examples are shown in the text. Figure 3 A first conductor group 120 is stacked along the Z-axis direction, and the isolation structure between the first conductor groups 120 is not shown.

[0065] In this embodiment of the disclosure, voltage can be applied simultaneously to multiple first conductive lines 121 arranged in the Y-axis direction via the step 131; thus, the number of first conductive lines 121 that can be driven simultaneously by the step 131 is increased, thereby reducing the number of steps 131, which in turn can significantly reduce the area of ​​the stepped structure and improve the integration density of the semiconductor structure 100. In addition, a smaller number of steps 131 can reduce the complexity of the photolithography mask.

[0066] Next, based on the above Figure 2 Based on the semiconductor structure shown, the layout of the first wire group 120 (i.e., the first conductive line 121) is described in detail. In some embodiments, please refer to... Figure 5 or Figure 6 The array region A and the stepped region B are arranged alternately along the X-axis; every two adjacent columns of the first conductor group 120 along the X-axis are connected to the same stepped structure 130.

[0067] Please refer to the embodiments disclosed herein. Figure 5 or Figure 6 The connection of two adjacent first guide groups 120 along the X-axis to the same step structure 130 means that every two adjacent first guide groups 120 along the X-axis share the same step 131.

[0068] In this embodiment of the disclosure, since every two adjacent first conductor groups 120 along the X-axis are connected to the same step 131, and each first conductor group 120 includes a plurality of first conductive lines 121 arranged along the Y-axis (two are shown in the figure), on the one hand, the number of first conductive lines 121 that can be driven simultaneously by the step 131 is increased; on the other hand, the space in the semiconductor structure 100 can be effectively utilized, and the miniaturization of the semiconductor structure is further realized.

[0069] It should be noted that in some embodiments, please refer to Figure 7 The first wire group 120 can also be connected only to the corresponding step structure 130, that is, each step structure 130 is only used to drive the corresponding first wire group 120. In this way, the fabrication difficulty when connecting the first wire group 120 to the step structure 130 can be reduced.

[0070] In this embodiment of the disclosure, please refer to Figure 5 or Figure 7 The step 131 connected to the first conductor group 120 and the step 131 connected to the first conductor group 120 adjacent to it along the Y-axis are located on the same step region B. This reduces the complexity and difficulty of the semiconductor structure 100 layout design.

[0071] In some embodiments, please refer to Figure 6 The step 131 connected by the first guide group 120 and the step 131 connected by the first guide group 120 adjacent to each other along the Y-axis are located on different step areas B.

[0072] In this way, the stepped structures 130 corresponding to adjacent first conductor groups 120 along the Y-axis direction can be staggered in the X-axis direction, for example... Figure 6 As shown in the stepped structures 130a and 130b, this layout allows for more space to be added to the stepped structure 130.

[0073] Specifically, with Figure 6 Taking the stepped structures 130a, 130b, and 130c shown as examples, since the stepped structures 130b and 130a (and 130c) are set on adjacent step regions B, the space between the stepped structures 130a and 130c is larger, which can increase the size of the stepped structures 130a and 130c, that is, increase the distance between adjacent signals (i.e., signals in the conductive pillars connected to the steps) and reduce signal coupling.

[0074] It should be noted that, Figure 6The outermost first guide group 120 along the X-axis direction only shows one corresponding step structure (i.e. step). In fact, the outermost first guide group 120 along the X-axis direction can also share the step structure.

[0075] Finally, based on the above Figure 2 Based on the structure shown, other structures in semiconductor structure 100 will be described in detail. In some embodiments, please refer to... Figure 8 and Figure 9 The semiconductor structure 100 further includes: a plurality of memory cells 140 located on the array region A; the memory cells 140 are arranged along the X-axis and Y-axis directions and stacked along the Z-axis direction; each first conductive line 121 is electrically connected to the plurality of memory cells 140 arranged along the X-axis direction.

[0076] It should be noted that, Figure 8 and Figure 9 The example described uses four memory cells connected by the first conductive line 121; in reality, the number of memory cells 140 connected by each first conductive line 121 could be, for example, 512, etc. Furthermore, Figure 9 Only one first wire group 120 is shown, and the storage unit 140 and the second wire group 150 connected thereto.

[0077] In related technologies, since the maximum number of memory cells 140 connected in series with each first conductive line 121 is limited, for example, when the first conductive line 121 is a word line, the number of memory cells 140 connected in series with the first conductive line 121 can be 1024. At this time, the parasitic capacitance and resistance of the farthest end of the first conductive line 121 (the end away from the step) are large, and the signal is prone to delay. If the number of memory cells 140 connected in series with the first conductive line 121 is reduced, the integration density of the semiconductor structure 100 will be reduced.

[0078] In this embodiment, by connecting multiple first conductive lines 121 in parallel to form a first conductor group 120, and connecting the first conductor group 120 to the corresponding step, the number of memory cells connected to each first conductive line 121 can be reduced while ensuring that the number of memory cells controlled simultaneously remains unchanged; for example, Figure 8 In the process, when the two first conductive lines 121 are connected in parallel, each first conductive line 121 can connect 512 memory cells (only 4 are shown in the figure). This ensures that the total number of memory cells controlled at the same time remains unchanged (1024), while reducing the length of the first conductive line 121, thereby reducing the delay of the signal of the memory cell connected at the farthest end.

[0079] Additionally, when it is necessary to increase the number of control storage cells at the same step, the number of first conductive lines 121 connected in series can be increased, that is, the number of first conductive lines 121 in a first conductor group 120, such as... Figure 10 As shown, the number of first conductive wires 121 in a first conductor group 120 can be three, etc. Alternatively, it can be as follows: Figure 5 and Figure 6 As shown, adjacent first conductor groups 120 can share the same step; thus, each step can control 4 first conductor groups 120. When each first conductive line 121 connects 512 memory cells, a total of 2048 memory cells can be controlled simultaneously, which increases the number of memory cells connected and thus improves the integration of the semiconductor structure.

[0080] In some embodiments, please refer to Figure 8 and Figure 9 The semiconductor structure 100 further includes: a plurality of second wire groups 150 located on the array region A; the plurality of second wire groups 150 are arranged along the X-axis and Y-axis directions and extend along the Z-axis direction; wherein, a plurality of memory cells 140 connected to a plurality of first wire groups 120 arranged along the Z-axis direction are connected to a plurality of second wire groups 150 arranged along the X-axis direction.

[0081] In some embodiments, please refer to Figure 8 and Figure 9 The second conductor group 150 includes a plurality of second conductive lines 151 arranged along the Y-axis and extending along the Z-axis; each second conductive line 151 is connected to a plurality of storage cells 140 arranged along the Z-axis.

[0082] In this embodiment of the present disclosure, the first conductive line 121 can be a word line, and the second conductive line 151 can be a bit line. In other embodiments, the first conductive line 121 can also be a bit line, and the second conductive line 151 can also be a word line.

[0083] In this embodiment of the disclosure, the material of the second conductive wire 151 can be any one or any combination of conductive materials such as cobalt, titanium, titanium nitride, tantalum, tantalum nitride, nickel, tungsten, platinum and palladium.

[0084] In this embodiment of the disclosure, the number of second conductive wires 151 in each second conductor group 150 is equal to the number of first conductive wires 121 in the corresponding first conductor group 120; for example, please refer to... Figure 8 and Figure 9 When the number of first conductive wires 121 in the first conductor group 120 is 2, the number of second conductive wires 151 in each corresponding second conductor group 150 is also 2. For example, please refer to... Figure 10When the number of first conductive wires 121 in the first conductor group 120 is 3, the number of second conductive wires 151 in each corresponding second conductor group 150 is also 3.

[0085] Please continue to refer to this. Figure 8 and Figure 9 Since multiple first conductive lines 121 in each first conductor group 120 are controlled through the same step, in order to avoid multiple memory cells (such as those connected to the same first conductor group 120 and arranged along the Y-axis direction) Figure 8 The two memory cells shown in the dashed area are simultaneously turned on or off, and multiple second conductive lines 151 located in the same second conductor group 150 are connected to different signal interconnects 160.

[0086] For example, Figure 8 The two memory cells shown in the dashed area are connected to two different signal interconnects 160 respectively. In this way, when one signal interconnect 160 and one step 131 (i.e. the first wire group 120) are turned on, only one memory cell 140 is selected, thereby ensuring the performance of the semiconductor structure.

[0087] For example, please refer to Figure 10 When the same second conductor group 150 includes three second conductive lines 151, the three second conductive lines 151 are respectively connected to three signal interconnects 160. In this way, when one signal interconnect 160 and one step 131 (i.e. the first conductor group 120) are turned on, only one memory cell 140 is selected, thereby ensuring the performance of the semiconductor structure.

[0088] In some embodiments, please refer to Figure 8 and Figure 9 A second conductive line 151 located in each second conductor group 150 arranged along the Y-axis direction is connected to the same signal interconnect 160.

[0089] For example, please refer to Figure 8 In the two second conductor groups 150 arranged along the Y-axis, the first second conductor 151 is connected to the signal interconnection line 160 on the left, and the second second conductor 151 is connected to the signal interconnection line 160 on the right. Thus, the first second conductor 151 in the second conductor group 150 arranged along the Y-axis can be selected (i.e., read and write) simultaneously through the signal interconnection line 160 on the left; the second second conductor 151 in the second conductor group 150 arranged along the Y-axis can be selected (i.e., read and write) simultaneously through the signal interconnection line 160 on the right.

[0090] In some embodiments, please refer to Figure 8 and Figure 9The memory cell 140 includes an access transistor and a capacitor structure 143. The access transistor includes an active layer 141 extending along the Y-axis and a gate structure 142 located on the middle surface of the active layer 141. The gate structure 142 includes a gate dielectric layer 1421 and a gate metal layer 1422 sequentially located on the middle surface of the active layer 141. A plurality of gate metal layers 1422 arranged along the X-axis are connected to form a first conductive line 121.

[0091] Please refer to the embodiments disclosed herein. Figure 9 The active layer 141 includes a channel, and source and drain electrodes located on both sides of the channel along the Y-axis; wherein, the active layer 141 can be a single-channel structure (e.g., Figure 9 As shown), dual-channel structures, etc. The gate structure 142 is located on the channel surface of the active layer 141; wherein, the gate structure 142 can be a single-gate structure (such as...). Figure 9 (as shown), dual-gate structure or full-ring gate structure, etc.

[0092] In some embodiments, please refer to Figure 8 and Figure 9 The storage cell 140 further includes: a capacitor structure 143 connected to one end of the active layer 141 along the Y-axis; and a second conductive line 151 connected to the other end of the active layer 141 along the Y-axis.

[0093] Please refer to the embodiments disclosed herein. Figure 8 and Figure 9 The second conductive line 151 is connected to the source of the active layer 141. The capacitor structure 143 is connected to the drain of the active layer 141.

[0094] In some embodiments, the capacitor structure 143 includes: a first electrode layer 1431 connected to one end of the active layer 141 along the Y-axis, and a dielectric layer 1432 and a second electrode layer 1433 sequentially covering the first electrode layer 1431 (see reference). Figure 12 ).

[0095] In this embodiment, the capacitor structure 143 extends along the Y-axis, meaning it is arranged horizontally. This horizontal arrangement reduces the likelihood of tipping or breaking, thus improving the stability of the capacitor structure. Furthermore, multiple horizontal capacitor structures 143 can be stacked to form a three-dimensional semiconductor structure, thereby increasing the integration density of the semiconductor structure and achieving miniaturization. In other embodiments, the capacitor structure 143 can be any other achievable structure, and this disclosure is not limiting in this regard.

[0096] In this embodiment, the active layer 141 can be made of semiconductor materials such as silicon and germanium, or it can be made of metal oxide materials, such as IGZO or ITO. The gate dielectric layer 1421 can be made of silicon oxide or other suitable materials. The materials of the first electrode layer and the second electrode layer can include metal nitrides or metal silicides, such as titanium nitride; the material of the dielectric layer can include high-k dielectric materials, such as lanthanum oxide, aluminum oxide, hafnium oxide, etc.

[0097] In some embodiments, two adjacent memory cells 140 arranged along the Y-axis share a second conductive line 151, and / or two adjacent memory cells 140 arranged along the Y-axis share a second electrode layer 1433.

[0098] In this embodiment of the disclosure, please refer to Figure 11 and Figure 12 Two adjacent memory cells 140 connected to the same first conductor group 120 (or second conductor group 150) and arranged along the Y-axis share the second electrode layer 1433. Since only one memory cell 140 is selected when a signal interconnect 160 and a step 131 (i.e., the first conductor group 120) are connected, reading data from the capacitor structure will not affect the data in adjacent memory cells even if they share the second electrode layer 1433. This effectively utilizes the space in the semiconductor structure, further achieving miniaturization of the semiconductor structure. In other embodiments, two adjacent memory cells 140 connected to adjacent first conductor groups 120 (or second conductor groups 150) and arranged along the Y-axis can also share the second electrode layer 1433.

[0099] Please refer to the embodiments disclosed herein. Figure 11 and Figure 12 The second conductive line 151 is shared by two adjacent memory cells 140 that are connected to different first conductive lines 120 (or second conductive lines 150) and arranged along the Y-axis. In other words, the shared second conductive line 151 connects to memory cells corresponding to different first conductive lines 120. This avoids the simultaneous on or off of multiple memory cells (two shown in the figure) connected to the same first conductive line 120 and arranged along the Y-axis.

[0100] It should be noted that, Figure 12 Only shown in Figure 11 A column of storage cells arranged along the Y-axis (e.g.) Figure 11 (As shown by the dashed line area).

[0101] In this embodiment of the disclosure, two adjacent memory cells 140 arranged along the Y-axis share a second conductive line 151, and / or two adjacent memory cells 140 arranged along the Y-axis share a second electrode layer 1433, which can effectively utilize the space in the semiconductor structure 100 and further realize the miniaturization of the semiconductor structure.

[0102] In this embodiment of the disclosure, the semiconductor structure 100 further includes an isolation structure (not shown) located between adjacent conductive structures; for example, between connection structures 122, between memory cells 140, etc.; the isolation structure can reduce the generation of leakage current. The material of the isolation structure can be any suitable material.

[0103] In addition, this disclosure also provides a method for forming a semiconductor structure 100, such as... Figure 13 As shown, the method for forming the semiconductor structure 100 includes steps S110 to S130.

[0104] Step S110, provide as follows Figure 14 The substrate 110 shown includes an array region A and a stepped region B located on one side of the array region A along the X-axis direction.

[0105] In this embodiment of the disclosure, the substrate 110 may be a silicon substrate, or may include other semiconductor elements, such as germanium, or include semiconductor compounds, such as silicon carbide, gallium arsenide, etc.

[0106] Please refer to the embodiments disclosed herein. Figure 14 Different functional structures can be formed on array region A and step region B, respectively. For example, a memory array can be formed on array region A, which can consist of memory cells, a first wire group, a second wire group, and a capacitor structure; a stepped structure can be formed on step region B.

[0107] Step S120: Form multiple arrays located on array region A, such as... Figure 14 The first conductor group 120 shown; a plurality of first conductor groups 120 are arranged along the Y-axis and Z-axis directions and extend along the X-axis direction to the step region B; each first conductor group 120 includes a plurality of first conductive lines 121 arranged along the Y-axis direction and extending along the X-axis direction.

[0108] In this embodiment of the disclosure, the embodiments of the disclosure are configured to form the above-described embodiments. Figure 8 and Figure 9 The following explanation uses the first conductor group 120 (i.e., the first conductive line 121) as an example; the first conductive line 121 can be formed by the following steps: in such a way... Figure 14 On the array region A shown, multiple active layers 141 are formed, arranged along the X-axis and Y-axis directions and stacked along the Z-axis direction (see reference). Figure 9 A gate structure 142 is formed on the surface of the middle part of the active layer (see reference). Figure 9 The gate structure 142 includes a gate dielectric layer 1421 and a gate conductive layer 1422 sequentially located on the middle surface of the active layer; a plurality of gate conductive layers 1422 arranged along the X-axis are connected and extend along the X-axis to the step region B, forming a structure as shown in the figure. Figure 14 The first conductive line 121 is shown.

[0109] Please refer to the embodiments disclosed herein. Figure 14 The method for forming a semiconductor structure further includes: forming a plurality of connection structures 122 arranged along the Z-axis and extending along the Y-axis on the step region B; each connection structure 122 is connected to a plurality of first conductive lines 121 arranged along the Y-axis, thereby the connection structure 122 and the corresponding plurality of first conductive lines 121 constitute a first conductor group 120. For example, as Figure 14 Each connection structure 122 shown is connected to two first conductive lines 121 arranged along the Y-axis direction, so that the connection structure 122 and the corresponding two first conductive lines 121 constitute a first conductor group 120.

[0110] In this embodiment, each first conductive line 121 is used to connect multiple memory cells arranged along the X-axis. Without reducing the number of memory cells that can be simultaneously controlled, the number of memory cells connected by a single first conductive line 121 is lower, meaning the length of a single first conductive line 121 is shorter. This reduces parasitic capacitance and resistance on a single first conductive line, reduces signal delay, and improves the performance of the semiconductor structure. Furthermore, the first wire group 120 extends along the X-axis, meaning it is horizontal. This allows for the interconnection of multi-layered stacked memory cells via word lines on the same plane, improving the integration density of the semiconductor structure 100.

[0111] Step S130, forming multiple such structures located on step area B. Figure 8 The stepped structure 130 shown; multiple stepped structures 130 are arranged along the Y-axis direction, and each stepped structure 130 includes multiple steps 131 arranged along the Z-axis direction; the first wire group 120 is connected to a corresponding step 131.

[0112] In this embodiment of the present disclosure, a stepped structure 130 is formed on one side of the connecting structure 122; the stepped structure 130 includes a plurality of steps 131 arranged sequentially along the Z-axis direction; each step 131 is connected to the corresponding connecting structure 122. Here, the number of steps in the stepped structure 130 is the same as the number of layers of the connecting structure 122 (i.e., the first conductor group 120).

[0113] In this embodiment of the disclosure, the stepped structure 130 can be any suitable structure. For example, please refer to... Figure 8 The top view of the stepped structure 130 is annular. This allows multiple steps 131 (five shown in the illustration) to be distributed on both sides of the annulus along the X-axis, thereby reducing the density of the steps 131 along the Z-axis, thus reducing crosstalk between signals and improving the performance of the semiconductor structure. Alternatively, the top view of the stepped structure 130 may be linear (see reference...). Figure 3 and Figure 4 The interconnects are arranged sequentially along the Z-axis and their dimensions decrease sequentially along the Y-axis, thereby enabling the multi-layer stacked interconnect structure 122 (i.e., the first wire group 120) to be led out with the minimum step area. In this way, the wiring in the semiconductor structure 100 can be reduced, and the semiconductor structure 100 can be miniaturized.

[0114] In this embodiment of the disclosure, voltage can be applied to multiple first conductive lines 121 arranged in the Y-axis direction simultaneously through the step 131; thus, the number of first conductive lines 121 that can be driven simultaneously by the step 131 is increased, thereby reducing the number of steps 131, which in turn can significantly reduce the area of ​​the stepped structure and improve the integration of the semiconductor structure 100.

[0115] Please refer to the embodiments disclosed herein. Figure 8 and Figure 9 The method for forming a semiconductor structure further includes: forming a plurality of second wire groups 150 on an array region A; the plurality of second wire groups 150 are arranged along the X-axis and Y-axis directions and extend along the Z-axis direction; wherein a plurality of memory cells 140 connected to a plurality of first wire groups 120 arranged along the Z-axis direction are connected to a plurality of second wire groups 150 arranged along the X-axis direction.

[0116] Please continue to refer to this. Figure 8 and Figure 9 The second conductor group 150 includes a plurality of second conductive lines 151 arranged along the Y-axis and extending along the Z-axis; each second conductive line 151 is connected to a plurality of storage cells 140 arranged along the Z-axis.

[0117] In some embodiments, two adjacent memory cells 140 arranged along the Y-axis can share the second conductive line 151; for example, please refer to... Figure 11 and Figure 12The second conductive line 151 is shared by two adjacent memory cells 140 that are connected to different first conductive lines 120 (or second conductive lines 150) and arranged along the Y-axis. In other words, the shared second conductive line 151 simultaneously connects to memory cells corresponding to different first conductive lines 120. This avoids the simultaneous activation or deactivation of multiple memory cells (two shown in the figure) connected to the same first conductive line 120 and arranged along the Y-axis. Simultaneously, it effectively utilizes the space within the semiconductor structure 100, further enabling the miniaturization of the semiconductor structure.

[0118] In this embodiment of the disclosure, the method for forming a semiconductor structure further includes: forming a plurality of capacitor structures 143 arranged along the X-axis and Y-axis directions and stacked along the Z-axis direction on the array region A (see reference). Figure 9 The capacitor structure is connected to the other end of the corresponding active layer along the Y-axis; the active layer 141, the corresponding gate structure 142, and the corresponding capacitor structure 143 constitute a... Figure 8 and Figure 9 The storage unit 140 shown.

[0119] In this embodiment, the capacitor structure 143 includes: a first electrode layer 1431 connected to one end of the active layer 141 along the Y-axis, and a dielectric layer 1432 and a second electrode layer 1433 sequentially covering the first electrode layer 1431 (see reference). Figure 12 ).

[0120] In some embodiments, two adjacent memory cells 140 arranged along the Y-axis share a second electrode layer 1433. For example, please refer to [reference needed]. Figure 11 and Figure 12 Two adjacent memory cells 140 connected to the same first conductive line group 120 (or second conductive line group 150) and arranged along the Y-axis share the second electrode layer 1433. Since only one memory cell 140 is selected when a second conductive line and a step 131 (i.e., the first conductive line group 120) are connected, reading data from the capacitor structure will not affect the data in adjacent memory cells even if they share the second electrode layer 1433. This effectively utilizes the space in the semiconductor structure, further achieving miniaturization of the semiconductor structure. In other embodiments, two adjacent memory cells 140 connected to adjacent first conductive line groups 120 (or second conductive line groups 150) and arranged along the Y-axis can also share the second electrode layer 1433.

[0121] Please refer to the embodiments disclosed herein. Figure 8 and Figure 9The method for forming the semiconductor structure 100 further includes forming a plurality of signal interconnects 160 extending along the Y-axis and arranged along the X-axis; wherein a plurality of second conductive lines 151 located in the same second conductor group 150 are connected to different signal interconnects 160. In this way, the simultaneous on or off of a plurality of first conductive lines 121 in the first conductor group 120 can be avoided, thus ensuring the performance of the semiconductor device.

[0122] In this embodiment of the disclosure, the method for forming the semiconductor structure 100 further includes: forming an isolation structure (not shown), the isolation structure being located between adjacent conductive structures; for example, between connection structures 122, between memory cells 140, etc.

[0123] It should be noted that the structure on the semiconductor structure 100 can be formed according to any suitable process method, and this disclosure does not limit it; the specific structure of the semiconductor structure 100 should be understood based on the above embodiments, and will not be repeated here.

[0124] The semiconductor structure formed by the semiconductor structure formation method provided in this disclosure is similar to the semiconductor structure in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0125] This disclosure also provides an electronic device. Figure 15 This is a schematic diagram of the structure of an electronic device 200 provided in an embodiment of the present disclosure, as shown below. Figure 15 As shown, the electronic device 200 includes: a processor 210; and any of the semiconductor structures 100 in the above embodiments; wherein the semiconductor structure is coupled to the processor.

[0126] In some embodiments, the electronic device includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.

[0127] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0128] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0129] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; the substrate includes an array region and a stepped region located on one side of the array region along a first direction; Multiple first wire groups located on the array region; The plurality of first conductor groups are arranged along a second direction and a third direction and extend along the first direction to the stepped area; each first conductor group includes a plurality of first conductive wires arranged along the second direction and extending along the first direction; Multiple stepped structures are located on the stepped area; the multiple stepped structures are arranged along the second direction, and each stepped structure includes multiple steps arranged along the third direction; the first wire group is connected to a corresponding step; Wherein, the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

2. The semiconductor structure according to claim 1, characterized in that, Each of the first conductor groups further includes: A connection structure extending along the second direction, the connection structure being connected between a plurality of first conductive lines arranged along the second direction and the corresponding steps.

3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure also includes: A plurality of memory cells are located on the array region; the memory cells are arranged along the first direction and the second direction and stacked along the third direction; each of the first conductive lines is electrically connected to the plurality of memory cells arranged along the first direction.

4. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure also includes: A plurality of second conductor groups are located on the array region; the plurality of second conductor groups are arranged along the first direction and the second direction and extend along the third direction; The storage cells, which are connected to a plurality of first wire groups arranged along the third direction, are connected to a plurality of second wire groups arranged along the first direction.

5. The semiconductor structure according to claim 4, characterized in that, The second conductor group includes: A plurality of second conductive lines are arranged along the second direction and extend along the third direction; each of the second conductive lines is connected to a plurality of the memory cells arranged along the third direction.

6. The semiconductor structure according to claim 5, characterized in that, Multiple second conductive lines located in the same second conductor group are connected to different signal interconnects.

7. The semiconductor structure according to claim 6, characterized in that, A second conductive line located in one of the second groups of conductors arranged along the second direction is connected to the same signal interconnect.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that, The array region and the stepped region are arranged alternately along the first direction; Along the first direction, every two adjacent columns of the first conductor group are connected to the same stepped structure.

9. The semiconductor structure according to claim 8, characterized in that, The steps connected by the first conductor group and the steps connected by the first conductor group adjacent to each other along the second direction are located in different step areas.

10. The semiconductor structure according to claim 5, characterized in that, The storage unit includes: Access transistor; the access transistor includes an active layer extending along the second direction and a gate structure located on the middle surface of the active layer; the gate structure includes a gate dielectric layer and a gate metal layer sequentially located on the middle surface of the active layer, and a plurality of the gate metal layers arranged along the first direction are connected to form the first conductive line.

11. The semiconductor structure according to claim 10, characterized in that, The storage unit further includes: A capacitor structure is connected to one end of the active layer along the second direction; the second conductive line is connected to the other end of the active layer along the second direction.

12. The semiconductor structure according to claim 11, characterized in that, The capacitor structure includes: A first electrode layer connected to one end of the active layer along the second direction, and a dielectric layer and a second electrode layer sequentially covering the first electrode layer.

13. The semiconductor structure according to claim 12, characterized in that, Two adjacent memory cells arranged along the second direction share the second conductive line, and / or two adjacent memory cells arranged along the second direction share the second electrode layer.

14. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided; the substrate includes an array region and a stepped region located on one side of the array region along a first direction; A plurality of first conductor groups are formed on the array region; the plurality of first conductor groups are arranged along a second direction and a third direction and extend along the first direction to the step region; each first conductor group includes a plurality of first conductive lines arranged along the second direction and extending along the first direction; Multiple stepped structures are formed on the stepped area; the multiple stepped structures are arranged along the second direction, and each stepped structure includes multiple steps arranged along the third direction; the first wire group is connected to a corresponding step; Wherein, the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

15. An electronic device, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 13, or the semiconductor structure formed according to the method for forming a semiconductor structure as described in claim 14.

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