Semiconductor device and method of manufacturing the same, electronic device

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor device comprises sequentially forming a buffer layer, a first signal line, a first dielectric layer, a second signal line and a second dielectric layer, the first signal line comprising a first conductive layer, a second conductive layer and a third conductive layer; forming a via hole stopping at the second conductive layer; forming an initial first protective layer and an initial second protective layer which sequentially conformally cover the via hole; forming a second protective layer covering the side wall of the via hole; removing the initial first protective layer covering the bottom surface of the via hole and the side surface of the second conductive layer to obtain a first protective layer; exposing the second conductive layer at the bottom side surface of the via hole; etching the second conductive layer to obtain a groove arranged around the periphery of the bottom of the via hole; removing the first protective layer; and forming a semiconductor layer, a gate insulating layer and a gate which sequentially conformally cover and fill the groove and the via hole. The application realizes the effect of increasing the contact area of the semiconductor layer and the first signal line and reducing the contact resistance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] This application addresses the shortcomings of existing methods by proposing a semiconductor device and its manufacturing method, as well as an electronic device, to solve the technical problem of high contact resistance between the metal-oxide-semiconductor and the sidewall source-drain metal in transistor structures with a fully encircling channel region.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: A buffer layer, a first signal line, a first dielectric layer, a second signal line, and a second dielectric layer are sequentially formed on one side of the substrate. The first signal line includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially moved away from the substrate. A via is formed that penetrates the second dielectric layer, the second signal line, the first dielectric layer, and the third conductive layer, and terminates at the second conductive layer; An initial first protective layer and an initial second protective layer are formed that sequentially conformally cover the through-hole and the second dielectric layer; Remove the initial second protective layer located outside the through hole and above the bottom surface of the through hole to obtain a second protective layer covering the sidewall of the through hole; Based on the second protective layer, the initial first protective layer covering the bottom surface of the through hole and the side surface of the second conductive layer is removed to obtain the first protective layer; Remove the second protective layer to expose the second conductive layer at the bottom side of the through hole; Based on the via and the first protective layer, the second conductive layer is etched to obtain an annular groove surrounding the bottom periphery of the via; the etching rate of the second conductive layer is greater than the etching rates of the first conductive layer and the third conductive layer. Remove the first protective layer; A semiconductor layer, a gate insulating layer, and a gate are formed that sequentially conformally cover and fill the groove and the via.

[0006] Optionally, the initial second protective layer located outside the through hole and above the bottom surface of the through hole is removed to obtain a second protective layer covering the sidewall of the through hole, comprising: Based on the dry etching process, the initial second protective layer on the top surface of the second dielectric layer and the bottom surface of the via is removed, exposing the initial first protective layer at the bottom of the via, thus obtaining a second protective layer covering the sidewall of the via.

[0007] Optionally, the method for manufacturing the semiconductor device further includes at least one of the following: The first conductive layer and the third conductive layer comprise metal compound materials, and the second conductive layer comprises a metal material; The material of the first protective layer includes nitrides; The material of the second protective layer includes polycrystalline silicon.

[0008] Optionally, the method for manufacturing the semiconductor device further includes any one of the following: The first signal line has a three-layer structure, where the first conductive layer and the third conductive layer are made of the same material, and the second conductive layer is made of a different material than the first conductive layer and the second conductive layer; or, the first conductive layer and the third conductive layer are all made of different materials. Alternatively, the first signal line may have a double-layer structure, where the second conductive layer and the third conductive layer are made of the same material, and the first conductive layer is made of a different material than the first conductive layer. Alternatively, the first signal line may be a single-layer structure, with the first conductive layer, the second conductive layer, and the third conductive layer all made of the same material.

[0009] Optionally, based on the through-hole and the first protective layer, the second conductive layer is etched to obtain an annular groove surrounding the bottom periphery of the through-hole, including: Under the protection of the first protective layer covering at least a portion of the first dielectric layer, the second signal line, and a portion of the second dielectric layer, the second conductive layer is wet-etched through the via to obtain the annular groove surrounding the bottom periphery of the via, such that the bottom surface of the via and the bottom surface of the groove both expose the first conductive layer, and the top surface of the groove exposes the third conductive layer.

[0010] Optionally, a semiconductor layer, a gate insulating layer, and a gate are formed to sequentially conformally cover and fill the via and the groove, including: An initial semiconductor layer and an initial gate insulating layer are sequentially formed to cover the groove, the via, and the second dielectric layer. An initial gate layer is formed that fills the grooves and the vias and covers the initial gate insulating layer; Form an initial gate interconnect layer covering the initial gate layer; Based on the patterning process, the initial gate connection layer, the initial gate layer, the gate insulating layer, and the initial semiconductor layer covering the surface of the second dielectric layer are removed to obtain a semiconductor layer, a gate insulating layer, and a gate that conformally cover and fill the vias and the grooves, as well as a gate connection structure covering the gate.

[0011] Secondly, embodiments of this application provide a semiconductor device, including: A buffer layer, a first signal line, a first dielectric layer, a second signal line, and a second dielectric layer are sequentially disposed on one side of a substrate; the first signal line extends along a first direction parallel to the substrate, and the second signal line extends along a second direction parallel to the substrate, wherein the first direction and the second direction intersect; the first signal line includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially moving away from the substrate. The via sequentially penetrates the second dielectric layer, the second signal line, the first dielectric layer, and the third conductive layer, and terminates at the second conductive layer; A groove is located in the second conductive layer, communicates with the through hole, and is arranged around the periphery of the through hole; A semiconductor layer, a gate insulating layer, and a gate are sequentially conformally covered and filled in the groove and the via.

[0012] Optionally, the semiconductor layer located at the bottom of the via covers and contacts the first conductive layer; The semiconductor layer located in the groove sequentially covers and contacts the first conductive layer exposed on the bottom surface of the groove, the second conductive layer exposed on the side surface of the groove, and the third conductive layer exposed on the top surface of the groove.

[0013] Optionally, the first signal line is the source and the second signal line is the drain.

[0014] Thirdly, embodiments of this application provide an electronic device, including: A semiconductor device manufactured using the semiconductor device manufacturing method described above; or, Semiconductor devices as described above.

[0015] The beneficial technical effects of the technical solutions provided in this application include: In this embodiment, the first signal line is designed as a stacked structure including a first conductive layer, a second conductive layer, and a third conductive layer. Under the protection of the second protective layer, only the first protective layer covering the bottom and top of the via is removed, exposing the second conductive layer on the side of the bottom of the via, while the second signal line is still protected by the first protective layer. Due to the design of a suitable film material and etching process, the etching rate of the second conductive layer is greater than that of the first and third conductive layers, and the second conductive layer is etched laterally more quickly, forming an annular groove that surrounds the bottom of the via and communicates with the via. The subsequently formed semiconductor layer covers the groove and the sidewall of the via, so that the contact surface between the semiconductor layer and the first signal line includes the bottom, top, and side surfaces of the groove.

[0016] Compared to related technologies where the semiconductor layer only covers the sidewall of the via (corresponding to the sidewall of the groove in this application), this application increases the area of ​​the annular top surface and annular bottom surface of the groove, thereby increasing the contact area between the semiconductor layer and the first signal line that serves as the source and drain of the transistor. This can reduce the contact resistance between the semiconductor layer and the first signal line, thereby increasing the turn-on current Ion and improving device performance.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application; Figures 2 to 19 This is a schematic diagram showing the structure at the end of each step in a semiconductor device manufacturing method provided in this application embodiment. Explanation of reference numerals in the attached figures: 10-Substrate; 21-Buffer layer; 22-First dielectric layer; 23-Second dielectric layer; 24-Third dielectric layer; 30 - First signal line; 31 - First conductive layer; 32 - Second conductive layer; 33 - Third conductive layer; 40 - Second signal line; 51 - Through hole; 52-Groove; 521-Bottom surface; 522-Top surface; 523-Side surface; 61-First protective layer; 611-Initial first protective layer; 62-Second protective layer; 621-Initial second protective layer; 71-Semiconductor layer; 711-Initial semiconductor layer; 72-Gate insulating layer; 721-Initial gate insulating layer; 73-Gate; 731-Initial gate layer; 74-Gate connection structure; 741-Initial gate connection layer. Detailed Implementation

[0019] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0020] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in the specification of this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" can be implemented as "A," or as "B," or as "A and B."

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0022] The relevant technologies are explained below: Semiconductor oxides, as channel materials, can be deposited on any material surface and possess high on / off ratio characteristics. Many international research institutions and companies are conducting research on their application in DRAM devices. Among them, the vertical-ring channel transistor (VRF) is considered the most promising device structure for industrialization due to its small area and ease of stacking. Furthermore, the use of IGZO (Indium Gallium Zinc Oxide) as a channel material has been widely studied due to its ultra-low leakage current. However, in transistor structures with a fully encircling channel region, the limited contact area between IGZO and the sidewall source / drain metals leads to relatively high contact resistance.

[0023] The semiconductor devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in related technologies.

[0024] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0025] This application provides a method for manufacturing a semiconductor device, and the flowchart of the method is shown below. Figure 1 As shown, the structural schematic diagrams of the semiconductor device manufacturing method at different processes are as follows: Figures 2 to 19 As shown, the method for manufacturing this semiconductor device includes: S101: A buffer layer 21, a first signal line 30, a first dielectric layer 22, a second signal line 40, and a second dielectric layer 23 are sequentially formed on one side of the substrate 10. The first signal line 30 includes a first conductive layer 31, a second conductive layer 32, and a third conductive layer 33 that are sequentially moved away from the substrate 10.

[0026] S102: Form a via 51 that penetrates the second dielectric layer 23, the second signal line 40, the first dielectric layer 22 and the third conductive layer 33 and stops at the second conductive layer 32.

[0027] S103: Form an initial first protective layer 611 and an initial second protective layer 621 that sequentially conformally cover the through hole 51 and the second dielectric layer 23.

[0028] S104: Remove the initial second protective layer 621 located outside the through hole 51 and above the bottom surface of the through hole 51 to obtain a second protective layer 62 covering the sidewall of the through hole 51.

[0029] S105: Based on the second protective layer 62, remove the initial first protective layer 611 covering the bottom surface of the through hole 51 and the side surface of the second conductive layer 32 to obtain the first protective layer 61.

[0030] S106: Remove the second protective layer 62 to expose the second conductive layer 32 at the bottom side of the through hole 51.

[0031] S107: Based on the through hole 51 and the first protective layer 61, the second conductive layer 32 is etched to obtain an annular groove 52 surrounding the bottom periphery of the through hole 51; the etching rate of the second conductive layer 32 is greater than the etching rates of the first conductive layer 31 and the third conductive layer 33.

[0032] S108: Remove the first protective layer 61.

[0033] S109: Form a semiconductor layer 71, a gate insulating layer 72, and a gate 73 that sequentially conformally cover and fill the groove 52 and the via 51.

[0034] This application addresses the problem of high contact resistance between the metal-oxide-semiconductor and the sidewall source / drain metal in transistor structures with a fully encircling channel region in related technologies, and proposes a novel method for manufacturing semiconductor devices.

[0035] In this embodiment, the first signal line 30 is designed as a stacked structure including a first conductive layer 31, a second conductive layer 32, and a third conductive layer 33. Under the protection of the second protective layer 62, only the first protective layer 61 covering the bottom and top of the via 51 is removed, exposing the second conductive layer 32 at the bottom side 523 of the via 51, while the second signal line 40 is still protected by the first protective layer 61. Due to the design of a suitable film material and etching process, the etching rate of the second conductive layer 32 is greater than that of the first conductive layer 31 and the third conductive layer 33. The second conductive layer 32 is etched laterally faster, forming an annular groove 52 surrounding the bottom of the via 51 and communicating with the via 51. The subsequently formed semiconductor layer 71 covers the groove 52 and the sidewall of the via 51, so that the contact surface between the semiconductor layer 71 and the first signal line 30 includes the bottom surface 521, the top surface 522, and the side surface 523 of the groove 52.

[0036] Compared to the related technologies where the semiconductor layer 71 only covers the sidewall of the via 51 (corresponding to the sidewall 523 of the groove 52 in this application), this application increases the area of ​​the annular top surface 522 and the annular bottom surface 521 of the groove 52, thereby increasing the contact area between the semiconductor layer 71 and the first signal line 30, which serves as the source and drain of the transistor. This can reduce the contact resistance between the semiconductor layer 71 and the first signal line 30, thereby increasing the turn-on current Ion and improving device performance.

[0037] Optionally, in the embodiments of this application, such as Figure 2-5 As shown, in step S101, a buffer layer 21, a first signal line 30, a first dielectric layer 22, a second signal line 40, and a second dielectric layer 23 are sequentially formed on one side of the substrate 10, including: A buffer layer 21 is formed on one side of the substrate 10. Optionally, the material of the buffer layer 21 includes, but is not limited to, oxides (such as SiO or SiO2).

[0038] Next, a first signal line 30 and a first dielectric layer 22 covering the first signal line 30 and the buffer layer 21 are sequentially formed on the side of the buffer layer 21 away from the substrate 10, resulting in the following: Figure 2-3 The diagram shows a schematic of the membrane structure.

[0039] Optionally, in this embodiment, the first signal line 30 is a three-layer stacked structure, including a first conductive layer 31, a second conductive layer 32, and a third conductive layer 33 that are sequentially located away from the substrate 10.

[0040] Optionally, in some alternative embodiments, the first conductive layer 31 and the third conductive layer 33 are made of the same material, while the second conductive layer 32 is made of a different material than the first conductive layer 31 and the third conductive layer 33.

[0041] In some alternative embodiments, the first conductive layer 31, the third conductive layer 33, and the second conductive layer 32 are all made of different materials.

[0042] Optionally, the first signal line 30 may also be a double-layer structure composed of two different materials, including a first conductive layer 31 and a second conductive layer 32 that are sequentially away from the substrate 10, and the etching rate of the same chemical solution on the second conductive layer 32 is greater than the etching rate on the first conductive layer 31, so that the first conductive layer 31 acts as a barrier layer when etching the second conductive layer 32, preventing the first signal line 30 from being etched through.

[0043] Optionally, the first signal line 30 can also be a single-layer structure made of the same material, in which case the first conductive layer 31, the third conductive layer 33, and the second conductive layer 32 are all made of the same material. When the first signal line 30 is a single-layer structure, it is necessary to precisely control the depth of etching the via 51 and the groove 52 to avoid the bottom of the first signal line 30 being etched through.

[0044] Optionally, the thickness of the first conductive layer 31 and the third conductive layer 33 is less than the thickness of the second conductive layer 32.

[0045] Optionally, the first conductive layer 31 and the third conductive layer 33 include, but are not limited to, metal compound materials, and the second conductive layer 32 includes, but is not limited to, metal materials.

[0046] In this embodiment, the materials of the first conductive layer 31 and the third conductive layer 33 include, but are not limited to, titanium nitride (TiN), and the materials of the second conductive layer 32 include, but are not limited to, tungsten (W).

[0047] In other embodiments, the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 can all be other conductive materials. As long as they meet the performance requirements of this application, this application does not impose any restrictions on them.

[0048] Next, a second signal line 40 and a second dielectric layer 23 covering the second signal line 40 and the first dielectric layer 22 are sequentially formed on one side of the first dielectric layer 22, resulting in the following: Figure 4-5 The diagram shows a schematic of the membrane structure.

[0049] Optionally, in this embodiment, the first signal line 30 extends along a first direction parallel to the substrate 10, and the second signal line 40 extends along a second direction parallel to the substrate 10. The first direction and the second direction are perpendicular, thereby providing a better conductive path, reducing resistance, and improving the speed and energy efficiency of the device. Positioning the first signal line 30 and the second signal line 40 perpendicularly in a plane parallel to the substrate 10 can also reduce short-channel effects and improve the control capability of the gate 73.

[0050] Optionally, in the embodiments of this application, the material of the substrate 10 includes, but is not limited to, silicon; the materials of the first dielectric layer 22 and the second dielectric layer 23 include, but are not limited to, oxides (such as SiO or SiO2); and the material of the second signal line 40 includes, but is not limited to, TiN.

[0051] Optionally, in step S102, forming a via 51 that penetrates the second dielectric layer 23, the second signal line 40, the first dielectric layer 22, and the third conductive layer 33 and terminates at the second conductive layer 32 includes: Based on a patterning process, a via 51 is etched that penetrates the second dielectric layer 23, the second signal line 40, the first dielectric layer 22, and the third conductive layer 33, and stops at the second conductive layer 32. This exposes the second conductive layer 32 and the third conductive layer 33 on the side surface of the bottom of the via 51, resulting in... Figure 6 The diagram shows the membrane structure. Through-hole 51 defines the location of the channel to be formed.

[0052] Optionally, such as Figure 7-13 As shown, in step S103, the formation of an initial first protective layer 611 and an initial second protective layer 621 that sequentially conformally cover the through-hole 51 and the second dielectric layer 23 includes: An initial first protective layer 611 is deposited to form a conformal covering of the via 51 and the second dielectric layer 23. Optionally, the material of the initial first protective layer 611 includes, but is not limited to, nitrides (such as SiN).

[0053] Next, an initial second protective layer 621 is deposited to form a conformal overlay on the initial first protective layer 611, resulting in... Figure 7 The diagram shows a schematic of the membrane structure.

[0054] Optionally, the material of the initial second protective layer 621 may include, but is not limited to, polysilicon.

[0055] Optionally, in this embodiment of the application, the initial first protective layer 611 and the initial second protective layer 621 can be deposited by ALD (Atomic Layer Deposition) process.

[0056] Optionally, in step S104, the initial second protective layer 621 located outside the through hole 51 and above the bottom surface of the through hole 51 is removed to obtain a second protective layer 62 covering the sidewall of the through hole 51, including: Based on a dry etching process, the initial second protective layer 621 exposed on the surface is fully etched to remove the top surface of the initial first protective layer 611 and the bottom surface of the through hole 51, exposing the initial first protective layer 611 at the bottom of the through hole 51 and the initial first protective layer 611 on the top surface of the second dielectric layer 23, resulting in a second protective layer 621 covering the sidewall of the through hole 51. Figure 8 The diagram shows a schematic of the membrane structure.

[0057] Optionally, in step S105, based on the second protective layer 62, the initial first protective layer 611 covering the bottom surface of the through hole 51 and the side surface of the second conductive layer 32 is removed to obtain the first protective layer 61, which includes: Based on the blocking effect of the second protective layer 62 covering the sidewall of the via 51, and based on the wet etching process, the initial first protective layer 611 exposed on the surface of the second dielectric layer 23 and the bottom surface of the via 51 is fully etched, so that part of the initial first protective layer 611 covering the bottom surface of the via 51 and the surface of the second dielectric layer 23 is removed. Furthermore, due to the diffusion effect of the chemical solution, part of the initial first protective layer 611 between the second protective layer 62 and the side of the second conductive layer 32 at the bottom of the via 51 and part of the initial first protective layer 611 between the second protective layer 62 and the second dielectric layer 23 at the top of the via 51 are also removed, thereby obtaining at least a partial first protective layer 61 covering the first dielectric layer 22, the second signal line 40, and part of the second dielectric layer 23, exposing the second conductive layer 32 at the bottom surface of the via 51, resulting in... Figure 9 The diagram shows a schematic of the membrane structure.

[0058] Optionally, when selecting the first chemical solution for etching the initial first protective layer 711, the etching rate of the first chemical solution on the initial first protective layer 611 is greater than the etching rate on the second protective layer 62, thereby ensuring that only the initial first protective layer 611 is etched, while the second protective layer 62 is not etched or is etched more slowly.

[0059] Optionally, in one embodiment, the first protective layer 61 at least covers the second signal line 40, the first dielectric layer 22 and the third conductive layer 33, in which case the bottom end of the first protective layer 61 is lower than or flush with the bottom surface of the third conductive layer 33.

[0060] Optionally, in another embodiment, the first protective layer 61 at least covers the second signal line 40, that is, the top end of the etched first protective layer 61 is higher than or flush with the top surface of the second signal line 40, and the bottom end of the first protective layer 61 is lower than or flush with the bottom surface of the second signal line 40.

[0061] It is understood that in this embodiment, the bottom end and bottom surface refer to the side of a structure that is closer to the substrate in the third direction, and the top end and top surface refer to the side of a structure that is farther away from the substrate in the third direction. For example, the bottom end of the first protective layer 61 being lower than the bottom surface of the third conductive layer 33 means that in the third direction, the side of the first protective layer 61 that is closer to the substrate is closer to the substrate than the side of the third conductive layer 33 that is closer to the substrate.

[0062] Optionally, in step S106, the second protective layer 62 is removed to expose the second conductive layer 32 at the bottom side of the through hole 51.

[0063] Based on a wet etching process, the second protective layer 62 covering the sidewall of the via 51 is completely etched, thereby removing the entire second protective layer 62 and exposing the first protective layer 61 and the second conductive layer 32 at the bottom side of the via 51, resulting in the following... Figure 10 The diagram shows a schematic of the membrane structure.

[0064] Optionally, when selecting the second chemical solution for etching the second protective layer 62, the etching rate of the second chemical solution on the second protective layer 62 is made greater than the etching rate on the first protective layer 61, thereby ensuring that only the second protective layer 62 is etched, while the first protective layer 61, which at least partially covers the first dielectric layer 22, the second signal line 40 and part of the second dielectric layer 23, is not etched or is etched more slowly.

[0065] Optionally, such as Figure 11-12 As shown, Figure 12 for Figure 11 A partial enlarged view of the groove 52 shows that in step S107, based on the through hole 51 and the first protective layer 61, the second conductive layer 32 is etched to obtain an annular groove 52 surrounding the bottom periphery of the through hole 51, including: Under the protection of the first protective layer 61, the second conductive layer 32 is wet-etched through the through-hole 51, thereby forming an annular groove 52 around the through-hole 51. This exposes the first conductive layer 31 on both the bottom surface of the through-hole 51 and the bottom surface 521 of the groove 52, exposes the third conductive layer 33 on the top surface 522 of the groove 52, and exposes the second conductive layer 32 on the side surface 523 of the groove 52, resulting in the desired effect. Figure 11 The diagram shows a schematic of the membrane structure.

[0066] It should be noted that, as Figure 12 As shown, the side surface 523 of the groove 52 refers to the surface extending along a third direction perpendicular to the substrate 10, and the top surface 522 and bottom surface 521 of the groove 52 both refer to the surfaces extending along a first direction parallel to the substrate 10.

[0067] In this embodiment, the etching rate of the second conductive layer 32 is set to be greater than that of the first conductive layer 31 and the third conductive layer 33, so that the etching selection of the second conductive layer 32 and the first conductive layer 31 or the third conductive layer 33 is relatively large. Thus, when etching the second conductive layer 32 to form the groove 52, the etching rate of the first conductive layer 31 and the third conductive layer 33 is slower. The first conductive layer 31 and the third conductive layer 33 act as barrier layers, defining the upper and lower limits of etching the second conductive layer 32 to avoid piercing the first conductive layer 31 and causing an open circuit.

[0068] Optionally, in step S108, removing the first protective layer 61 includes removing the first protective layer 61 that at least covers the second signal line 40 using a wet etching process, to obtain... Figure 13 The diagram shows a schematic of the membrane structure.

[0069] Optionally, such as Figure 14-18 As shown, in step S109, a semiconductor layer 71, a gate insulating layer 72, and a gate 73 are formed to sequentially conformally cover and fill the groove 52 and the via 51, including: An initial semiconductor layer 711 is deposited using an ALD process, so that the initial semiconductor layer 711 conformally covers the surfaces of the groove 52, the via 51, and the second dielectric layer 23, resulting in... Figure 14 The diagram shows a schematic of the membrane structure.

[0070] Optionally, in the embodiments of this application, the material of the initial semiconductor layer 711 includes, but is not limited to, IGZO.

[0071] Next, an initial gate insulating layer 721 is formed by depositing a gate insulating material using an ALD process to form an initial gate insulating layer 721 that conformally covers the sidewalls 523 of the groove 52, the sidewalls of the via 51, and the surface of the second dielectric layer 23, thus obtaining the initial gate insulating layer 721 of the initial semiconductor layer 711. Figure 15 The diagram shows a schematic of the membrane structure.

[0072] Optionally, the gate insulating material includes, but is not limited to, HK (High-K, high dielectric constant materials, including dielectrics with a dielectric constant k greater than or equal to 3.9) materials. In the embodiments of this application, the gate insulating material includes hafnium oxide (HfO).

[0073] Next, gate material is deposited using an ALD process to form an initial gate layer 731 that fills the interior of the recess 52 and the via 51 and covers the initial gate insulating layer 721, resulting in... Figure 16 The diagram shows a schematic of the membrane structure.

[0074] Optionally, the gate material includes, but is not limited to, indium zinc oxide (IZO).

[0075] Next, an initial gate interconnect layer 741 covering the initial gate layer 731 is deposited using an ALD process, resulting in... Figure 17 The diagram shows a schematic of the membrane structure.

[0076] Optionally, in this embodiment, the material of the initial gate connection layer 741 includes, but is not limited to, TiN.

[0077] Next, based on the patterning process, the initial gate connection layer 741, initial gate layer 731, gate insulating layer 72, and initial semiconductor layer 711 covering the surface of the second dielectric layer 23 are removed, resulting in a semiconductor layer 71, gate insulating layer 72, and gate 73 that conformally cover and fill the vias 51 and grooves 52, and a gate connection structure 74 covering the gate 73, thus obtaining... Figure 18 The diagram shows a schematic of the membrane structure.

[0078] In this embodiment, the semiconductor layer 71, the gate insulating layer 72, the gate 73, and the gate connection structure 74 are patterned and formed together, which can improve the manufacturing efficiency of semiconductor devices.

[0079] In other embodiments, the parasitic semiconductor layer 71 may be etched away first, and then an initial gate connection layer 741 covering the initial gate layer 731 may be deposited using the ALD process as described in the above embodiments. Finally, based on the patterning process, the semiconductor layer 71, the gate insulating layer 72 and the gate 73 that conformally cover and fill the vias 51 and the grooves 52, as well as the gate connection structure 74 covering the gate 73, may be etched in one step.

[0080] In this embodiment, an annular groove 52 surrounding the via 51 is formed inside the first signal line 30. The top surface 522 of the groove 52 exposes the third conductive layer 33, and the bottom surface 521 of the groove 52 exposes the first conductive layer 31. The deposited semiconductor layer 71 covers the bottom surface and sidewalls of the via 51, as well as the bottom surface 521, top surface 522, and side surface 523 of the groove 52. Compared with the related technology where the semiconductor layer 71 only covers the bottom surface and sidewalls of the via 51 (corresponding to only covering the side surface 523 of the groove 52 in this application), this increases the semiconductor layer 71 that contacts the bottom surface 521 and top surface 522 of the groove 52, and increases the contact area between the semiconductor layer 71 and the first signal line 30. This can reduce the contact resistance between the first signal line 30 and the semiconductor layer 71, increase the turn-on current Ion, and improve device performance.

[0081] Optionally, such as Figure 19 As shown, after obtaining the semiconductor layer 71, gate insulating layer 72, and gate 73 that conformally cover and fill the vias 51 and the recesses 52, and the gate connection structure 74 covering the gate 73, the structure includes: Based on the deposition process, a third dielectric layer 24 is formed covering the gate connection structure 74, part of the gate 73 and the second dielectric layer 23.

[0082] Next, planarization is performed using CMP (Chemical Mechanical Polishing) to grind the surface of the third dielectric layer 24 flat, making the third dielectric layer 24 flush with the surface of the gate connection structure 74, resulting in the desired surface finish. Figure 19 The diagram shows a schematic of the membrane structure.

[0083] Optionally, in this embodiment, the material of the third dielectric layer 24 includes, but is not limited to, oxide.

[0084] Based on the same inventive concept, this application also provides a semiconductor device, including a buffer layer 21, a first signal line 30, a first dielectric layer 22, a second signal line 40, and a second dielectric layer 23 sequentially disposed on one side of a substrate 10. The first signal line 30 extends along a first direction parallel to the substrate 10, and the second signal line 40 extends along a second direction parallel to the substrate 10, the first direction and the second direction intersecting; the first signal line 30 includes a first conductive layer 31, a second conductive layer 32, and a third conductive layer 33 sequentially moving away from the substrate 10.

[0085] The semiconductor device of this application also includes a via 51 that passes through the second dielectric layer 23, the second signal line 40, the first dielectric layer 22 and the third conductive layer 33 in sequence and stops at the second conductive layer 32, and a groove 52 located in the second conductive layer 32, communicating with the via 51 and surrounding the via 51.

[0086] Optionally, in this embodiment, the first signal line 30 forms a stacked structure including a first conductive layer 31, a second conductive layer 32, and a third conductive layer 33. In this application, the etching rate of the second conductive layer 32 is set to be greater than the etching rates of the first conductive layer 31 and the third conductive layer 33, so that the first conductive layer 31 and the third conductive layer 33 act as barrier layers, defining the upper and lower limits of etching the second conductive layer 32, avoiding etching through the first conductive layer 31, and forming an annular groove 52 communicating with the through hole 51 between the first conductive layer 31 and the third conductive layer 33.

[0087] The semiconductor device of this application also includes a semiconductor layer 71, a gate insulating layer 72, and a gate 73 that are sequentially conformally covered and filled in the recess 52 and the via 51.

[0088] Optionally, the semiconductor layer 71 located at the bottom of the through hole 51 covers and contacts the first conductive layer 31; the semiconductor layer 71 located in the groove 52 sequentially covers and contacts the first conductive layer 31 exposed on the bottom surface 521 of the groove 52, the second conductive layer 32 exposed on the side surface 523 of the groove 52, and the third conductive layer 33 exposed on the top surface 522 of the groove 52.

[0089] In this embodiment, an annular groove 52 communicating with a via 51 is formed within the first signal line 30, thereby causing the semiconductor layer 71 to cover the groove 52 and the via 51. The portion of the semiconductor layer 71 that contacts the first signal line 30 includes the top surface 522, the bottom surface 521, and the side surface 523 of the groove 52. Compared with related technologies, this increases the portion that contacts the annular top surface 522 and the annular bottom surface 521 of the groove 52, thus increasing the contact area between the semiconductor layer 71 and the first signal line 30. This reduces the contact resistance between the first signal line 30 and the semiconductor layer 71, increases the turn-on current Ion, and improves device performance.

[0090] Optionally, the first signal line 30 can be the source and the second signal line 40 can be the drain; or, the first signal line 30 can be the drain and the second signal line 40 can be the source. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the source and drain are sometimes interchanged. Therefore, in this application, unless otherwise specified, the source and drain can be interchanged.

[0091] The related technology discloses the effect of source-drain resistance on the total resistance under different voltage application methods when the source-drain contact is asymmetrical. When a positive voltage is applied to the drain, the total resistance = source resistance + channel resistance.

[0092] The related technology also discloses that when the contact area between the source and the semiconductor layer 71 increases, the source resistance and drain resistance decrease by more than 10 times, and when a positive voltage is applied to the drain terminal, the turn-on current Ion increases by 32 times.

[0093] Therefore, in a preferred embodiment of this application, the first signal line 30 is designed as the source and the second signal line 40 is designed as the drain.

[0094] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes: a semiconductor device manufactured using the semiconductor device manufacturing method described above; or, a semiconductor device as described above.

[0095] It should be noted that since the electronic devices in the embodiments of this application include semiconductor devices manufactured using the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, the electronic devices in the embodiments of this application also have the above-mentioned beneficial effects of the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, which will not be repeated here.

[0096] In some optional embodiments of this application, the electronic device includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include, for example, memory in a computer, and is not limited thereto.

[0097] By applying the embodiments of this application, at least the following beneficial effects can be achieved: In this embodiment, the first signal line 30 is designed as a stacked structure including a first conductive layer 31, a second conductive layer 32, and a third conductive layer 33. Under the protection of the second protective layer 62, only the first protective layer 61 covering the bottom and top of the via 51 is removed, exposing the second conductive layer 32 at the bottom side 523 of the via 51, while the second signal line 40 is still protected by the first protective layer 61. Due to the design of a suitable film material and etching process, the etching rate of the second conductive layer 32 is greater than that of the first conductive layer 31 and the third conductive layer 33. The second conductive layer 32 is etched laterally faster, forming an annular groove 52 surrounding the bottom of the via 51 and communicating with the via 51. The subsequently formed semiconductor layer 71 covers the groove 52 and the sidewall of the via 51, so that the contact surface between the semiconductor layer 71 and the first signal line 30 includes the bottom surface 521, the top surface 522, and the side surface 523 of the groove 52.

[0098] Compared to the related technologies where the semiconductor layer 71 only covers the sidewall of the via 51 (corresponding to the sidewall 523 of the groove 52 in this application), this application increases the area of ​​the annular top surface 522 and the annular bottom surface 521 of the groove 52, thereby increasing the contact area between the semiconductor layer 71 and the first signal line 30, which serves as the source and drain of the transistor. This can reduce the contact resistance between the semiconductor layer 71 and the first signal line 30, thereby increasing the turn-on current Ion and improving device performance.

[0099] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0100] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0101] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0102] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0103] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A buffer layer, a first signal line, a first dielectric layer, a second signal line, and a second dielectric layer are sequentially formed on one side of the substrate. The first signal line includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially moved away from the substrate. A via is formed that penetrates the second dielectric layer, the second signal line, the first dielectric layer, and the third conductive layer, and terminates at the second conductive layer; An initial first protective layer and an initial second protective layer are formed that sequentially conformally cover the through-hole and the second dielectric layer; Remove the initial second protective layer located outside the through hole and above the bottom surface of the through hole to obtain a second protective layer covering the sidewall of the through hole; Based on the second protective layer, the initial first protective layer covering the bottom surface of the through hole and the side surface of the second conductive layer is removed to obtain the first protective layer; Remove the second protective layer to expose the second conductive layer at the bottom side of the through hole; Based on the via and the first protective layer, the second conductive layer is etched to obtain an annular groove surrounding the bottom periphery of the via; the etching rate of the second conductive layer is greater than the etching rates of the first conductive layer and the third conductive layer. Remove the first protective layer; A semiconductor layer, a gate insulating layer, and a gate are formed that sequentially conformally cover and fill the groove and the via.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, It also includes at least one of the following: The first conductive layer and the third conductive layer comprise metal compound materials, and the second conductive layer comprises a metal material; The material of the first protective layer includes nitrides; The material of the second protective layer includes polycrystalline silicon.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Also includes any of the following: The first signal line has a three-layer structure, where the first conductive layer and the third conductive layer are made of the same material, and the second conductive layer is made of a different material than the first conductive layer and the second conductive layer; or, the first conductive layer and the third conductive layer are all made of different materials. Alternatively, the first signal line may have a double-layer structure, where the second conductive layer and the third conductive layer are made of the same material, and the first conductive layer is made of a different material than the first conductive layer. Alternatively, the first signal line may be a single-layer structure, with the first conductive layer, the second conductive layer, and the third conductive layer all made of the same material.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Based on the second protective layer, the initial first protective layer covering the bottom surface of the via and the side surface of the second conductive layer is removed to obtain a first protective layer, comprising: Based on the wet etching process, after removing the initial first protective layer covering the top surface of the second dielectric layer and the bottom surface of the via, the initial first protective layer between the second protective layer and the side surface of the second conductive layer at the bottom of the via is removed, resulting in the first protective layer covering at least part of the first dielectric layer, the second signal line and part of the second dielectric layer, exposing the second conductive layer at the bottom surface of the via.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, Based on the through-hole and the first protective layer, the second conductive layer is etched to obtain an annular groove surrounding the bottom periphery of the through-hole, including: Under the protection of the first protective layer covering at least a portion of the first dielectric layer, the second signal line, and a portion of the second dielectric layer, the second conductive layer is wet-etched through the via to obtain the annular groove surrounding the bottom periphery of the via, such that the bottom surface of the via and the bottom surface of the groove both expose the first conductive layer, and the top surface of the groove exposes the third conductive layer.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Forming a semiconductor layer, a gate insulating layer, and a gate that sequentially conformally cover and fill the via and the groove, including: An initial semiconductor layer and an initial gate insulating layer are sequentially formed to cover the groove, the via, and the second dielectric layer. An initial gate layer is formed that fills the grooves and vias and covers the initial gate insulating layer. Form an initial gate connection layer covering the initial gate layer; Based on the patterning process, the initial gate connection layer, the initial gate layer, the gate insulating layer, and the initial semiconductor layer covering the surface of the second dielectric layer are removed to obtain a semiconductor layer, a gate insulating layer, and a gate that conformally cover and fill the vias and the grooves, as well as a gate connection structure covering the gate.

7. A semiconductor device, characterized in that, include: A buffer layer, a first signal line, a first dielectric layer, a second signal line, and a second dielectric layer are sequentially disposed on one side of the substrate; The first signal line extends along a first direction parallel to the substrate, and the second signal line extends along a second direction parallel to the substrate. The first direction and the second direction intersect and are both parallel to the substrate. The first signal line includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially moved away from the substrate. The via sequentially penetrates the second dielectric layer, the second signal line, the first dielectric layer, and the third conductive layer, and terminates at the second conductive layer; A groove is located in the second conductive layer, communicates with the through hole, and is arranged around the periphery of the through hole; A semiconductor layer, a gate insulating layer, and a gate are sequentially conformally covered and filled in the groove and the via.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor layer located at the bottom of the via covers and contacts the first conductive layer; The semiconductor layer located in the groove sequentially covers and contacts the first conductive layer exposed on the bottom surface of the groove, the second conductive layer exposed on the side surface of the groove, and the third conductive layer exposed on the top surface of the groove.

9. The semiconductor device according to claim 7, characterized in that, The first signal line is the source, and the second signal line is the drain.

10. An electronic device, characterized in that, include: Semiconductor devices manufactured using the manufacturing method described in any one of claims 1 to 6; or, The semiconductor device as described in any one of claims 7 to 9.

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