Semiconductor structure, preparation method thereof and electronic device

Abstract

The embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof. The semiconductor structure comprises at least one group of first transistors, second transistors and a storage node. The first transistors and the second transistors have a shared word line. The shared word line extends along a first direction. The first direction is perpendicular to the plane of the substrate. The first transistors at least comprise a first semiconductor layer. The first semiconductor layer surrounds at least part of the shared word line. The second transistors at least comprise a second semiconductor layer. The second semiconductor layer is located on the side of the first semiconductor layer away from the shared word line and surrounds part of the first semiconductor layer. The storage node is connected with the first semiconductor layer and is located between the first semiconductor layer and the second semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and its preparation method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, the structure comprising:

[0005] At least one set of first transistors, second transistors, and a memory node, wherein the first transistors and the second transistors have a common word line extending along a first direction perpendicular to the plane of the substrate;

[0006] The first transistor includes at least: a first semiconductor layer surrounding at least a portion of the common word line;

[0007] The second transistor includes at least: a second semiconductor layer located on the side of the first semiconductor layer away from the common word line and surrounding a portion of the first semiconductor layer, and the memory node being connected to the first semiconductor layer and located between the first semiconductor layer and the second semiconductor layer.

[0008] In some embodiments, the first semiconductor layer includes at least a first polar region and a second polar region, the first polar region and the second polar region being disposed opposite each other in a third direction, and the second polar region being connected to the memory node; wherein, the third direction is parallel to the plane of the substrate.

[0009] In some embodiments, the second semiconductor layer includes at least a first sub-part and two second sub-parts connected to both ends of the first sub-part. Along a second direction, the first electrode region is located between the ends of the two second sub-parts away from the first sub-part. The second direction is parallel to the plane of the substrate and intersects with the third direction.

[0010] In some embodiments, the structure comprising the first transistor, the second transistor, and the memory node includes multiple groups stacked in a first direction and spaced apart in a second and third direction. The semiconductor structure further includes:

[0011] Multiple bit lines and multiple source lines are located on both sides of the first transistor, the second transistor, and the memory node along a third direction. The bit lines and source lines extend along a second direction and are distributed at intervals in the first direction and the third direction.

[0012] Along the second direction, the bit line is connected to a plurality of first polar regions and a plurality of second sub-regions of the second semiconductor layer, and the source line is connected to a plurality of first sub-regions of the second semiconductor layer.

[0013] In some embodiments, the first transistor further includes a first gate dielectric layer located between the common word line and the first semiconductor layer;

[0014] The second transistor further includes a second gate dielectric layer located between the memory node and the second semiconductor layer.

[0015] In some embodiments, the semiconductor structure further includes a filler layer located between the first semiconductor layer and the second semiconductor layer, partially surrounding the first semiconductor layer and contacting the memory node;

[0016] The second semiconductor layer surrounds the fill layer and the memory node.

[0017] In some embodiments, the material of the first semiconductor layer includes a metal oxide, and the material of the second semiconductor layer includes silicon, silicon germanium, and germanium.

[0018] This disclosure also provides a method for fabricating a semiconductor structure, the method comprising:

[0019] Substrate provided:

[0020] A second semiconductor layer for forming a second transistor is formed on the substrate, and a memory node is formed thereon, wherein the second semiconductor layer is disposed adjacent to the memory node;

[0021] A first semiconductor layer and a common word line are formed on the side of the memory node away from the second semiconductor layer. The first semiconductor layer is connected to the memory node and located between the memory node and the common word line. The first semiconductor layer surrounds the common word line, and the common word line extends along a first direction.

[0022] Wherein, the first direction is perpendicular to the plane of the substrate. In some embodiments, the first transistor and the second transistor comprise multiple groups, the multiple groups of the first transistor and the second transistor are stacked in a direction perpendicular to the plane of the substrate, and arranged in an array along the second direction and the third direction, the second direction and the third direction being parallel to the plane of the substrate and intersecting each other, the fabrication method further comprising, before forming the second semiconductor layer of the second transistor on the substrate:

[0023] A stacked layer comprising alternating and repeating first and second sublayers is formed on the substrate, and openings and isolation trenches are formed through at least a portion of the stacked layer. The openings are spaced apart along a second direction and a third direction. The isolation trenches extend along the second direction and are located between adjacent openings in the third direction. Each isolation trench includes a first sub-trench located in the middle in the third direction and two second sub-trenches located on both sides of the first sub-trench. The first sub-trench is located between two adjacent openings in the third direction, and the second sub-trenches are located on both sides of two adjacent openings in the third direction.

[0024] The second sublayer exposed by the isolation trench is removed, and the first sublayer is thinned to form a first gap; at least the first gap is filled with a first dielectric layer and the isolation trench is filled with a sacrificial layer;

[0025] The portion of the first sublayer exposed by the opening is removed to form a first void structure around the opening, with the remaining first sublayer located at least at the bottom of the opening and on the side of the first void structure adjacent to the first sub-groove.

[0026] In some embodiments, the second semiconductor layer forming the second transistor includes:

[0027] A second semiconductor layer is formed on the surface of the first sub-layer in the first void structure, and at least a sacrificial layer is formed in the opening and the first void structure;

[0028] After forming the second semiconductor layer and before forming the first semiconductor layer of the first transistor and the common word line, the fabrication method further includes:

[0029] Based on the first sub-groove, remove the first sub-layer remaining above the first sub-layer at the bottom of the stack; and remove a portion of the sacrificial layer around the opening and form a fill layer at the location where the sacrificial layer is removed;

[0030] A conductive layer is formed on the surface of the second semiconductor layer adjacent to the first sub-trench and on the surface of the second semiconductor layer adjacent to the second sub-trench.

[0031] At least the opening and the area where the first void structure is located are opened, and a storage node is formed on the sidewall of the exposed area opposite to the filling layer;

[0032] A first semiconductor layer and a common word line are formed on the side of the memory node away from the second semiconductor layer, including:

[0033] At least a channel material layer and a common word line are formed sequentially on the sidewalls of the filling layer and the storage node;

[0034] The portion of the channel material layer located between adjacent first void structures along a first direction is removed to form the first semiconductor layer.

[0035] In some embodiments, removing the first sublayer remaining above the bottommost first sublayer of the stacked layers based on the first sub-trench includes:

[0036] At least the sacrificial layer located in the first sub-trench is removed to expose the surface of the first sub-layer at the bottom of the stack, and a protective layer is formed on the surface of the first sub-layer at the bottom of the stack; the first sub-layer above the protective layer is removed to form a second void structure around the first sub-trench and a second gap around the opening structure, and a second dielectric layer is filled in the second gap and part of the second void structure, and a sacrificial layer is filled in at least the first sub-trench;

[0037] Forming the filling layer includes:

[0038] At least open the location of the second sub-groove, remove a portion of the sacrificial layer around the opening, and form a fill layer at the location where the sacrificial layer was removed.

[0039] After forming the conductive layer and before forming the storage node, the fabrication method further includes:

[0040] A third dielectric layer is formed in the first sub-trench and a sacrificial layer is formed in the second sub-trench.

[0041] In some embodiments, after filling at least the first dielectric layer in the first gap and filling the sacrificial layer in the isolation trench, and before removing the portion of the first sublayer exposed by the opening to form a first void structure around the opening, the fabrication method further includes:

[0042] Remove the sacrificial layer located in the second sub-trench to expose the first dielectric layer and the first sub-layer located on the sidewall of the second sub-trench:

[0043] Laterally remove a portion of the first sublayer to form a third void structure, the third void structure not exposing the sidewalls of the opening;

[0044] A preset material layer is formed, which covers the sidewalls of the material layer exposed by the first sub-groove and the third void structure;

[0045] After forming a second semiconductor layer on the surface of the first sublayer in the first void structure, and before forming at least a sacrificial layer in the opening and the first void structure, the fabrication method further includes:

[0046] A second gate dielectric layer and a sacrificial layer are sequentially formed on the surface of the second semiconductor layer, and a predetermined material layer is formed at least on the surface of the sacrificial layer.

[0047] In some embodiments, after forming the filler layer and before forming the conductive layer, the preparation method further includes:

[0048] A doping process is performed on the second semiconductor layer;

[0049] After forming the conductive layer and before forming the third dielectric layer in the first sub-trench and the sacrificial layer in the second sub-trench, the fabrication method further includes:

[0050] The preset material layer is formed at least on the surfaces of the conductive layer and the protective layer;

[0051] Forming a third dielectric layer in the first sub-trench and forming a sacrificial layer in the second sub-trench; including:

[0052] The sacrificial layer is formed in the first sub-trench and the second sub-trench, the sacrificial layer covering the surface of the conductive layer and the protective layer and at least filling the unfilled area of ​​the isolation trench;

[0053] Remove the sacrificial layer and the protective layer located in the first sub-trench, and fill with the third dielectric layer.

[0054] In some embodiments, after forming the memory node and before sequentially forming at least a channel material layer and a common word line on the fill layer and the sidewall of the memory node, the fabrication method further includes:

[0055] The first dielectric layer located between adjacent first void structures along the first direction is etched to form a fourth void structure;

[0056] The fourth void structure is filled with a sacrificial material layer;

[0057] After forming at least a channel material layer and a common word line sequentially on the fill layer and the sidewall of the memory node, a first semiconductor layer is formed by removing the portion of the channel material layer located between adjacent first void structures along a first direction, including:

[0058] At least the area where the second sub-groove is located is opened; exposing the preset material layer;

[0059] The preset material layer, the first dielectric layer located on the side of the sacrificial material layer adjacent to the second sub-trench, and the sacrificial material layer are removed to form a fifth void structure;

[0060] The channel material layer exposed by the fifth void structure is removed to form the first semiconductor layer.

[0061] This disclosure also provides an electronic device, including a semiconductor structure as described in any of the above embodiments, or including a semiconductor structure formed by the preparation method described in any of the above embodiments.

[0062] The semiconductor structure and its fabrication method provided in this disclosure include: at least one set of first transistors, second transistors, and a memory node; the first transistors and the second transistors have a common word line extending along a first direction perpendicular to the plane of the substrate; the first transistor includes at least a first semiconductor layer surrounding at least a portion of the common word line; the second transistor includes at least a second semiconductor layer located on the side of the first semiconductor layer away from the common word line and surrounding a portion of the first semiconductor layer; the memory node is connected to the first semiconductor layer and located between the first semiconductor layer and the second semiconductor layer.

[0063] Understandably, in the embodiments of this disclosure, a first transistor and a second transistor can form a memory cell structure, wherein the first transistor can be used as a write transistor and the second transistor can be used as a read transistor. Furthermore, in the embodiments of this disclosure, the second semiconductor layer of the second transistor is arranged around a portion of the first semiconductor layer, allowing the two transistors of a memory cell to be conditionally located in the same area. Compared to stacking two transistors vertically or separating them horizontally in two different areas, the semiconductor structure provided in the embodiments of this disclosure has a smaller space or area footprint for each memory cell, both in terms of volume and substrate area. This helps to obtain a greater number of memory cells in the same size space or on the same size substrate plane, thereby effectively improving storage density.

[0064] Details of one or more embodiments of this disclosure will be set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0065] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 This is a partial structural schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0067] Figure 2 This is a three-dimensional structural diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0068] Figure 3 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0069] Figure 4 A flowchart illustrating the preparation method provided in the embodiments of this disclosure;

[0070] Figures 5 to 52 A process flow diagram of a method for fabricating a semiconductor structure provided in this disclosure embodiment; wherein, Figure 16 , Figure 18 , Figure 28 , Figure 30 , Figure 37 , Figure 39 , Figure 41 , Figure 47 , Figure 49 and Figure 51 This is a top view schematic diagram showing a detailed cross-sectional view of the semiconductor structure along a direction parallel to the substrate plane during the fabrication process. Figures 5 to 15 , Figure 17 , Figures 19 to 27 , Figure 29 , Figures 31 to 36 , Figure 38 , Figure 40 , Figures 42 to 46 , Figure 48 , Figure 50 and Figure 52 For semiconductor structures along during the fabrication process Figure 3 Detailed sectional views in the A1-A2, B1-B2 and C1-C2 directions;

[0071] Figure 53 for Figure 52A partially enlarged view of the provided semiconductor structure along the A1-A2 direction;

[0072] Figure 54 for Figure 52 A magnified view of a portion of the semiconductor structure along the C1-C2 direction. Detailed Implementation

[0073] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0074] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0075] In the accompanying drawings, for clarity, the dimensions of layers, areas, components, and their relative dimensions may be exaggerated. The same reference numerals denote the same components throughout.

[0076] It should be understood that when a component or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various components, parts, areas, layers, and / or portions, these components, parts, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, area, layer, or portion from another component, part, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first component, part, area, layer, or portion discussed below may be referred to as a second component, part, area, layer, or portion. And the discussion of a second component, part, area, layer, or portion does not imply that the first component, part, area, layer, or portion necessarily exists in this disclosure.

[0077] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one component or feature shown in the figure and other components or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the component or feature described as “below,” “under,” or “below” other components or features will be oriented “above” other components or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0078] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, components, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, components, parts, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0079] Dynamic Random Access Memory (DRAM) is the core of modern computer hierarchical storage systems. It acts as a buffer and speed match between high-speed, low-density Static Random Access Memory (SRAM) and low-speed, high-density external memory. The 2TOC (Two Transistor One Capacitor) architecture is a capacitor-free DRAM technology consisting of two transistors, eliminating the need for separate capacitors. This greatly simplifies the DRAM manufacturing process, saves costs, and increases storage density.

[0080] However, existing 2T0C semiconductor devices still suffer from low storage density and poor read performance.

[0081] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0082] This disclosure provides a semiconductor structure, which includes:

[0083] At least one set of first transistors, second transistors, and a memory node, wherein the first transistors and the second transistors have a common word line extending along a first direction perpendicular to the plane of the substrate;

[0084] The first transistor includes at least: a first semiconductor layer surrounding at least a portion of the common word line;

[0085] The second transistor includes at least: a second semiconductor layer located on the side of the first semiconductor layer away from the common word line and surrounding a portion of the first semiconductor layer, and the memory node being connected to the first semiconductor layer and located between the first semiconductor layer and the second semiconductor layer.

[0086] Understandably, in the embodiments of this disclosure, a first transistor and a second transistor can form a memory cell structure, wherein the first transistor can be used as a write transistor and the second transistor can be used as a read transistor. Furthermore, in the embodiments of this disclosure, the second semiconductor layer of the second transistor is arranged around a portion of the first semiconductor layer, allowing the two transistors of a memory cell to be conditionally located in the same area. Compared to stacking two transistors vertically or separating them horizontally in two different areas, the semiconductor structure provided in the embodiments of this disclosure has a smaller space or area footprint for each memory cell, both in terms of volume and substrate area. This helps to obtain a greater number of memory cells in the same size space or on the same size substrate plane, thereby effectively improving storage density.

[0087] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0088] Figure 1 This is a partial structural schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a three-dimensional structural diagram of the semiconductor structure provided in the embodiments of this disclosure; Figure 3 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0089] The semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0090] like Figures 1 to 3 As shown, the semiconductor structure includes:

[0091] The device comprises at least one set of first transistors Ta, second transistors Tb, and a memory node SN. The first transistors Ta and Tb have a common word line WL, which extends along a first direction X, perpendicular to the plane of the substrate 10. The first transistor Ta includes at least a first semiconductor layer 11, which surrounds at least a portion of the common word line WL. The second transistor Tb includes at least a second semiconductor layer 12, which is located on the side of the first semiconductor layer 11 away from the common word line WL and surrounds a portion of the first semiconductor layer 11. The memory node SN is connected to the first semiconductor layer 11 and is located between the first semiconductor layer 11 and the second semiconductor layer 12.

[0092] Understandably, in the embodiments of this disclosure, a first transistor Ta and a second transistor Tb can form a memory cell structure, wherein the first transistor Ta can be used as a write transistor and the second transistor Tb can be used as a read transistor. The inclusion of a shared word line in this memory cell structure helps reduce the space occupied by the memory cell in terms of size or substrate area, thus contributing to increased storage density.

[0093] This disclosure does not specifically limit the constituent material of the substrate 10. As an example, the substrate can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0094] In some specific embodiments, the substrate 10 may be a single-crystal silicon substrate.

[0095] In some embodiments, the material of the common word line WL includes, but is not limited to, conductive material tungsten (W), and may also be copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), protactinium (Pa), platinum (Pt), silver (Ag), gold (Au), as well as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive metal nitrides such as titanium nitride (TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors such as doped polycrystalline silicon, conductive metal oxide semiconductors such as indium tin oxide, ITO, IZO, and other conductive materials.

[0096] In some embodiments, the material of the first semiconductor layer 11 includes a metal oxide material, such as indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is relatively small (leakage current less than or equal to 10). -15A This ensures a low refresh rate for the dynamic memory. The material of the second semiconductor layer 12 includes silicon-containing materials, silicon, silicon-germanium, or germanium, such as silicon-germanium (SiGe), silicon (Si), and other semiconductor materials.

[0097] In this embodiment, a silicon-containing single crystal material (or silicon, silicon-germanium, or germanium) is selected as the material of the second semiconductor layer 12, that is, when used as the read channel, the large change window of the threshold voltage (Vth) of the read transistor can be significantly improved, which helps to improve the read accuracy of the 2T0C memory structure and enhance the competitive advantage of the three-dimensional 2T0C structure.

[0098] In some embodiments, the second semiconductor layer 12 may be fabricated by first forming a stacked layer, then removing the material of the stacked layer on the region where the second semiconductor layer 12 is disposed, and then forming the second semiconductor layer 12 by epitaxial deposition. That is, in the embodiments of this disclosure, the formation of the second semiconductor layer 12 adopts a secondary epitaxial operation, which makes the second semiconductor layer 12 highly controllable in terms of formation process, channel thickness, and channel height along the first direction X. This helps to obtain the required information such as the required materials and size parameters of the second semiconductor layer 12 according to actual needs, and helps to improve the read performance of the semiconductor structure.

[0099] However, this is not the only one. In some other embodiments, the second semiconductor layer 12 may also be germanium (Ge) or a metal oxide material, such as IGZO, ITO, InO, etc.

[0100] It should be noted that the metal oxide material can be ITO or InSnOx (Indium Tin Oxide), IWO or InWO (Indium Tungsten Oxide), ZnOx (Zinc Oxide), InOx (Indium Oxide), In2O3 (Indium Oxide), SnO2 (Tin Dioxide), TiOx (Tin Dioxide), ZnxOyNz (Zinc Nitride Oxide), MgxZnyOz (Magnesium Zinc Oxide), InxZnyOz (Indium Zinc Oxide), InxGayZnzOa (Indium Gallium Zinc Oxide), ZrxInyZnzOa (Zirconium Indium Zinc Oxide), HfxInyZnzOa (Hafnium Indium Zinc Oxide), etc. Indium Zinc Oxide, SnxInyZnzOa (Tin Indium Zinc Oxide), AlxSnyInzZnaOd (Aluminum Tin Indium Zinc Oxide), SixInyZnzOa (Silicon Indium Zinc Oxide), ZnxSnyOz (Zinc Tin Oxide), AlxZnySnzOa (Aluminum Indium Tin Oxide), GaxZnySnzOa (Gallium Indium Tin Oxide), ZrxZnySnzOa (Zirconium Indium Tin Oxide), InGaSiO (Indium Gallium Silicon Oxide), IAZO (Indium Aluminum Zinc Oxide), IGO (Indium Gallium... Materials such as indium gallium oxide (IGAO), indium zinc oxide (IZO), and indium zinc oxide (IZOx) are acceptable, as long as the leakage current of the transistor meets the requirements. The specific requirements can be adjusted according to the actual situation.

[0101] In some embodiments, the first transistor Ta and the second transistor Tb comprise multiple sets, which are stacked in a first direction X perpendicular to the plane of the substrate 10.

[0102] In some specific embodiments, in addition to being stacked in the first direction X perpendicular to the plane of the substrate 10, multiple sets of first transistors Ta and second transistors Tb can also be arranged in an array structure along the second direction Y and the third direction Z parallel to the plane of the substrate, without being specifically limited here.

[0103] In some embodiments, the number of layers of multiple sets of first transistors Ta and second transistors Tb stacked along the first direction X can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, a dozen, several dozen, hundreds or even more layers. No specific limitation is made here, and it can be flexibly set according to the actual situation.

[0104] In some embodiments, the region of the common word line WL surrounded by the first semiconductor layer 11 can be defined as the gate structure G, which is applied to both the first transistor Ta and the second transistor Tb.

[0105] It is understandable that, regardless of whether the number of layers of the multiple sets of first transistors Ta and second transistors Tb stacked along the first direction X is one or more, the second semiconductor layer 12 of the second transistor Tb is arranged around a portion of the first semiconductor layer 11, so that the two transistors of a memory cell can be conditionally arranged in the same area. Compared with the method of stacking the first transistors Ta and second transistors Tb in a vertical direction, or the method of arranging the first transistors Ta and second transistors Tb in a horizontal direction on two areas, the semiconductor structure provided in this disclosure has significant advantages in terms of both volume occupation and substrate planar area occupation for a single memory cell. Through the improvement of the structural arrangement, a single memory cell can have a smaller space occupation or area occupation, which helps to obtain a larger number of memory cells in the same size space area or on the same size substrate plane, thereby effectively improving the storage density.

[0106] Continue to refer to Figures 1 to 3 In some embodiments, the first semiconductor layer 11 includes at least a first polar region D1 and a second polar region D2, the first polar region D1 and the second polar region D2 are disposed opposite each other in the third direction Z, and the second polar region D2 is connected to the memory node SN; wherein, the third direction Z is parallel to the plane of the substrate 10, and the area of ​​the sidewall region of the common word line WL surrounded by the second semiconductor layer 12 is larger than the area of ​​the sidewall region of the common word line WL surrounded by the memory node SN.

[0107] Understandably, in this embodiment, the first semiconductor layer 11 is arranged around the common word line WL, while the second semiconductor layer 12 is not arranged around the entire outer periphery of the common word line WL, but rather around a portion of its outer periphery. That is, the second semiconductor layer 12 is not arranged in a mirror-symmetric manner relative to the direction parallel to the second direction Y. Similarly, the fact that the area of ​​the sidewall region of the common word line WL surrounded by the second semiconductor layer 12 is larger than the area of ​​the sidewall region of the common word line WL surrounded by the storage node SN means that the storage node SN is also not a mirror-symmetric structure relative to the direction parallel to the second direction Y. Understandably, the asymmetrical structure of both the second semiconductor layer 12 and the storage node SN helps the storage cells to perform their storage functions normally while significantly reducing the space or planar dimensions occupied by the storage cells. This helps to improve the storage density of the semiconductor structure, giving it a significant advantage in cell size in three-dimensional integration.

[0108] Meanwhile, in this embodiment, although the second semiconductor layer 12 adopts an asymmetric structure, it still covers the area of ​​the first semiconductor layer 11 except for the area in contact with the bit line BL structure, and still has a certain channel length. This can also be understood as the second semiconductor layer 12 taking into account both reducing space size and planar area occupation, while also considering channel length. This ensures that while increasing storage density, the semiconductor structure does not increase manufacturing difficulty or cause adverse factors such as short-channel effects.

[0109] In some embodiments, the second semiconductor layer 12 includes at least a first sub-part 121 and two second sub-parts 122 connected to both ends of the first sub-part 121. Along the second direction Y, the first pole region D1 is located between the ends S1 of the two second sub-parts 122 away from the first sub-part 121. The second direction Y is parallel to the plane of the substrate 10 and intersects with the third direction Z.

[0110] In some embodiments, the structure consisting of the first transistor Ta, the second transistor Tb, and the memory node SN comprises multiple groups stacked in a first direction X and spaced apart in a second direction Y and a third direction Z. The semiconductor structure further includes:

[0111] Multiple bit lines BL and multiple source lines SL are located on both sides of the first transistor Ta, the second transistor Tb, and the memory node SN along the third direction Z. The bit lines BL and source lines SL extend along the second direction Y and are spaced apart on the first direction X and the third direction Z.

[0112] Along the second direction Y, the bit line BL is connected to a plurality of first polar regions D1 and a plurality of second sub-sections 122 of the second semiconductor layer 12, and the source line SL is connected to a plurality of first sub-sections 121 of the second semiconductor layer 12.

[0113] Here, the materials of bit line BL and source line SL can be the same as those of word line WL, which will not be elaborated here.

[0114] Here, the first electrode region D1 of the first semiconductor layer 11 and the two second sub-regions 122 of the second semiconductor layer 12 are connected to the same conductive line, i.e., the bit line BL. This enables the sharing of write bit lines and read bit lines in the semiconductor structure provided in this embodiment. This helps to further improve storage density and reduce costs based on the above.

[0115] like Figures 1 to 3 As shown, in some embodiments, the first transistor Ta further includes a first gate dielectric layer 13 located between the common word line WL and the first semiconductor layer 11, and the second transistor Tb further includes a second gate dielectric layer 14 located between the memory node SN and the second semiconductor layer 12.

[0116] In some embodiments, the materials of the first gate dielectric layer 13 and the second gate dielectric layer 14 may include dielectric materials, such as a low dielectric constant material or a high dielectric constant material. In some embodiments, it may be a high dielectric constant material.

[0117] In some specific embodiments, the high dielectric constant material layer may include, but is not limited to, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), hafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and / or praseodymium oxide (Pr2O3), etc.

[0118] In some embodiments, the materials of the first gate dielectric layer 13 and the second gate dielectric layer 14 may be the same or different. Specifically, they can be flexibly selected according to the actual situation, and no specific limitation is made here.

[0119] In some specific embodiments, the material of the first gate dielectric layer 13 may include oxides, such as silicon oxide, hafnium oxide, etc., and the material of the second gate dielectric layer 14 may include nitrides, oxides, such as silicon nitride, silicon oxide, etc.

[0120] In some embodiments, the formation process of the first gate dielectric layer 13 may include an in-situ water vapor growth process (ISSG).

[0121] In some embodiments, the semiconductor structure further includes a filling layer Lc, which is located between the first semiconductor layer 11 and the second semiconductor layer 12, partially surrounds the first semiconductor layer 11 and is in contact with the memory node SN.

[0122] The second semiconductor layer 12 surrounds the fill layer Lc and the memory node SN.

[0123] In some embodiments, the semiconductor structure further includes an isolation layer 15 located on the side of the second sub-section 122 of the second semiconductor layer 12 away from the second gate dielectric layer 14.

[0124] In some embodiments, the material of the filling layer Lc includes, but is not limited to, any suitable insulating material, such as nitrides, like silicon nitride. The material of the insulating layer 15 may be the same as or different from the material of the filling layer Lc, and no specific limitation is made herein.

[0125] In this embodiment of the disclosure, the write transistor (first transistor Ta) and the read transistor (second transistor Tb) in the memory cell share a common word line WL. Information read and write operations can be completed using MOS transistors of opposite types for write and read transistors. The read and write process for the selected memory cell is as follows:

[0126] During the writing of a "1", a positive voltage (e.g., V) is applied to the common word line WL. W The write channel is opened, and a high voltage (e.g., 1V) is applied to the bit line BL. The charge is stored in the corresponding memory node SN. Since the read tube requires a negative voltage to open, it is not turned on at this time to avoid leakage. During the read process, a negative voltage (e.g., -V) is applied to the common word line WL. W The potential of the storage node SN becomes negative through capacitive coupling, the read tube is turned on, and the information value "1" is read according to the current at this time.

[0127] During the writing of "0", a positive voltage is applied to the common word line WL to open the write channel, and a low voltage (e.g., 0V) is applied to the bit line BL. The charge is stored in the low storage node SN. Since the read tube requires a negative voltage to open, the read tube is not turned on at this time to avoid leakage. During the reading process, a negative voltage is applied to the common word line WL, which affects the potential of the storage node SN to become negative through capacitive coupling, thus turning on the read tube. Based on the current at this time, the information value "0" is read out.

[0128] During the above process, no voltage (e.g., 0V) is applied to the source line SL, and no voltage (e.g., 0V) is applied to the common word line WL of the unselected memory cell.

[0129] It should be noted that the above read / write process is illustrated using an NMOS transistor for the write transistor and a PMOS transistor for the read transistor. This can be understood as follows: when the write transistor is a PMOS transistor and the read transistor is an NMOS transistor, the read / write process can be achieved by adjusting the direction of the applied bias voltage (i.e., the positive or negative direction of the voltage pulse signal). In other words, the presence of the common word line can control the opening or closing of the first semiconductor layer 11 during the write operation, enabling data writing. Simultaneously, during the read operation, the common word line can prevent the write transistor from accidentally turning on by applying a reverse voltage, thus facilitating a smooth read operation.

[0130] This disclosure also provides a method for fabricating a semiconductor structure, such as... Figure 4 As shown, the preparation method includes the following steps:

[0131] Step S101: Provide a substrate:

[0132] Step S102: Form a second semiconductor layer of the second transistor and a memory node on the substrate, wherein the second semiconductor layer is disposed adjacent to the memory node;

[0133] Step S103: A first semiconductor layer of the first transistor is formed on the side of the memory node away from the second semiconductor layer, and a common word line is formed. The first semiconductor layer is connected to the memory node and located between the memory node and the common word line. The first semiconductor layer surrounds the common word line, and the common word line extends along the first direction.

[0134] The first direction is perpendicular to the plane of the substrate.

[0135] It should be understood that, although Figure 4 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 4 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0136] Figures 5 to 52 A process flow diagram of a method for fabricating a semiconductor structure provided in this disclosure embodiment; wherein, Figure 16 , Figure 18 , Figure 28 , Figure 30 , Figure 37 , Figure 39 , Figure 41 , Figure 47 , Figure 49 and Figure 51 This is a top view schematic diagram showing a detailed cross-sectional view of the semiconductor structure along a direction parallel to the substrate plane during the fabrication process. Figures 5 to 15 , Figure 17 , Figures 19 to 27 , Figure 29 , Figures 31 to 36 , Figure 38 , Figure 40 , Figures 42 to 46 , Figure 48 , Figure 50 and Figure 52 For semiconductor structures along during the fabrication process Figure 3 Detailed sectional views in the A1-A2, B1-B2 and C1-C2 directions; Figure 53 for Figure 52 A partially enlarged view of the provided semiconductor structure along the A1-A2 direction; Figure 54 for Figure 52 A magnified view of a portion of the semiconductor structure along the C1-C2 direction.

[0137] The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0138] First, execute step S101, as follows: Figure 5 As shown, a substrate 10 is provided.

[0139] This disclosure does not specifically limit the constituent materials of the substrate 10. As an example, the substrate can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0140] In some specific embodiments, the substrate 10 may be a single-crystal silicon substrate.

[0141] Next, proceed to step S102, as follows: Figures 6 to 41 As shown, a second semiconductor layer 12 is formed on the substrate 10 for the second transistor Tb, and a memory node SN is formed thereon. The second semiconductor layer 12 is disposed adjacent to the memory node SN.

[0142] In some embodiments, such as Figure 2 , Figures 5 to 10 , Figures 14 to 16 As shown, the first transistor Ta and the second transistor Tb comprise multiple sets, which are stacked in a first direction X perpendicular to the plane of the substrate 10 and arranged in an array along a second direction Y and a third direction Z. The second direction Y and the third direction Z are parallel to the plane of the substrate 10 and intersect each other. Before forming the second semiconductor layer 12 of the second transistor Tb on the substrate 10, the fabrication method further includes:

[0143] A stacked layer ST, comprising alternating and repeating first sublayers a1 and second sublayers a2, is formed on a substrate 10. An opening H and an isolation trench T are formed penetrating at least a portion of the stacked layer ST. The openings H are spaced apart along a second direction Y and a third direction Z. The isolation trench T extends along the second direction Y and is located between adjacent openings H in the third direction Z. The isolation trench T includes a first sub-trench T1 located in the middle along the third direction Z, and two second sub-trenches T2 located on both sides of the first sub-trench T1. The first sub-trench T1 is located between two adjacent openings H along the third direction Z, and the second sub-trench T2 is located on both sides of two adjacent openings H along the third direction Z (see details). Figures 5 to 7 );

[0144] The second sublayer a2 exposed by the isolation trench T is removed, and the first sublayer a1 is thinned to form the first gap K1; at least the first gap K1 is filled with the first dielectric layer L1, and the isolation trench T is filled with the sacrificial layer La (see details). Figures 8 to 10 );

[0145] The portion of the first sublayer a1 exposed by the opening H is removed to form a first void structure E1 surrounding the opening H. The remaining first sublayer a1 is located at least at the bottom of the opening H and on the side of the first void structure E1 adjacent to the first sub-trench T1 (see details). Figures 14 to 16 ).

[0146] In some embodiments, the material of the first sub-layer a1 may include, but is not limited to, a silicon layer, such as an epitaxial silicon layer, and the material of the second sub-layer a2 may include, but is not limited to, a silicon-germanium layer (SiGe). In some embodiments, the number of layers of the first sub-layer a1 and the second sub-layer a2 stacked on the substrate 10 is not limited to the number shown in the figures, and can be flexibly selected according to the actual situation. For example, it can be 2 layers, 3 layers, 4 layers, 5 layers, 6 layers, 7 layers, 8 layers, 9 layers, 10 layers, a dozen layers, dozens of layers, or even more layers, etc., without further limitation.

[0147] In some embodiments, when forming the first void structure E1 around the opening H, it can be obtained by performing a lateral etching process on the first sublayer a1. In this step, the size of the first sublayer a1 removed by the lateral etching process in the third direction Z can account for 50% to 80% or 50% to 90% of the size of the first sublayer a1 in the third direction Z between the opening H and the first sub-trench T1, for example, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, etc., without specific limitation.

[0148] In some embodiments, after forming the opening H, a fourth dielectric layer L4 may be filled into the opening H. In some specific embodiments, the fourth dielectric layer L4 may include two sublayers, one of which is in contact with the opening H and may be made of a nitride material, such as silicon nitride, and the other sublayer is located on the surface of the aforementioned sublayer and serves as a dummy filling material layer to fill the opening H. This sublayer may be made of an oxide material, such as silicon oxide.

[0149] In some embodiments, the shape of the opening H can be circular, elliptical, polygonal, or irregular. When it is a polygon, it can further include triangles, squares (rectangles or squares), other quadrilaterals, or polygons with more sides, etc., without specific limitations.

[0150] In some embodiments, such as Figure 5 As shown, after the stacked layer ST is formed, in order to protect other locations of the already formed stacked layer ST that do not need to be processed temporarily during subsequent etching and other process steps, a first protective material layer 171 can be formed on the top of the stacked layer ST.

[0151] Similarly, in subsequent processes, after completing one process step, the above method can be used to protect the formed structure or material. For example, after completing... Figure 9 The process operation steps and filling completion Figure 10 After the sacrificial layer La, such as Figure 10 As shown, the preparation method may include:

[0152] After the sacrificial layer La is filled, the upper surface of the structure is planarized (CMP) to obtain a flat surface;

[0153] The second protective material layer 172 is substrateed on the smooth surface obtained in the above steps, and,

[0154] In the following Figure 34 After forming the conductive line EL and filling the sacrificial layer La in the isolation trench T, a third protective material layer 173 can also be formed on top, after performing... Figure 35The operation step of replacing the sacrificial layer La in the first sub-trench T1 with the third dielectric layer L3, and after this step, continuing to form a fourth protective material layer 174 on top of the obtained structure.

[0155] It is understood that in the preparation method provided in the embodiments of this disclosure, after any process involving material filling is completed, the above-described process operations can be performed with reference to the above content to better protect the obtained structure. The execution process can be directly referred to the above content or flexibly adjusted according to the actual situation, and no further limitations are imposed here.

[0156] In some embodiments, the material of the first protective material layer 171 includes, but is not limited to, a nitride layer, such as silicon nitride; the materials of the second protective material layer 172 and the third protective material layer 173 can both be oxide materials, such as silicon oxide; and the material of the fourth protective material layer 174 can include a nitride material, such as silicon nitride. These material layers can protect the previously formed structure in areas where no processing operations are required during the fabrication of the semiconductor structure. The selection of the material for the protective material layer can have a selective etching ratio with other materials forming the structure first, and there are no excessive limitations on the specific material selection.

[0157] In some embodiments, the material of the sacrificial layer La may include, but is not limited to, at least one of amorphous silicon or polycrystalline silicon.

[0158] In some embodiments, the material of the first dielectric layer L1 may include, but is not limited to, oxide materials, such as silicon oxide.

[0159] In some embodiments, an opening H and an isolation trench T are formed that penetrate at least a portion of the stacked layer ST. The opening is spaced apart along the second direction Y and the third direction Z. The isolation trench T extends along the second direction Y and is located between adjacent openings H in the third direction Z. The structure exposed at the bottom of the opening H and the isolation trench T can include various cases, such as exposing the first sublayer a1 located at the bottom layer of the stacked layer ST, or exposing the surface of the substrate 10. The specific choice can be made flexibly according to the actual situation, and no specific limitation is made here.

[0160] In some embodiments, such as Figures 11 to 13 As shown, after filling at least the first gap K1 with the first dielectric layer L1 and filling the isolation trench T with the sacrificial layer La, and before removing the portion of the first sublayer a1 exposed by the opening H to form the first void structure E1 located around the opening H, the fabrication method further includes:

[0161] Remove the sacrificial layer La located in the second sub-trench T2 to expose the first dielectric layer L1 and the first sub-layer a1 located on the sidewall of the second sub-trench T2 (see details). Figure 11 ):

[0162] Laterally removing a portion of the first sublayer a1 to form a third void structure E3, the third void structure E3 does not expose the sidewall of the opening H (see details). Figure 12 );

[0163] A preset material layer XL is formed, which covers the sidewalls of the material layer exposed by the first sub-trench T1 and the third void structure E3 (see details). Figure 13 ).

[0164] In some embodiments, the material of the preset material layer XL may include, but is not limited to, an oxide layer, such as silicon oxide.

[0165] It is understood that in the embodiments of this disclosure, the method of first forming a preset material layer XL and then forming a sacrificial layer La can increase the etching selectivity between the sacrificial layer La and the preset material layer XL during the subsequent removal of the sacrificial layer La and opening of the target area, thereby preventing damage or over-etching of the surrounding material layers that do not need to be etched during the removal of the sacrificial layer La.

[0166] It should be noted that, in order to illustrate the arrangement or relationship between other structures in the accompanying drawings, the pre-set material layer XL may be omitted in some drawings and not explicitly shown. However, in actual operation, the etching selectivity between this material and the sacrificial layer La or other materials can be increased by forming this material. This helps to prevent over-etching when removing the sacrificial layer La or other materials to open the area that needs to be opened, thereby helping to obtain the target structure with the desired morphology after the process steps are performed.

[0167] In some embodiments, such as Figures 17 to 54 As shown, the second semiconductor layer 12 forming the second transistor Tb includes:

[0168] A second semiconductor layer 12 is formed on the surface of the first sublayer a1 in the first gap structure E1, and at least a sacrificial layer La is formed in the opening H and the first gap structure E1 (see details). Figures 17 to 20 );

[0169] After forming the second semiconductor layer 12 and before forming the first semiconductor layer 11 of the first transistor Ta and the common word line WL, the fabrication method further includes:

[0170] Based on the first sub-trench T1, the first sub-layer a1 retained above the bottommost first sub-layer a1 of the stacked layer ST is removed; and a portion of the sacrificial layer La around the opening H is removed, and a filling layer Lc is formed at the location where the sacrificial layer La is removed (see details). Figures 26 to 30 ,in, Figure 28 for Figure 27 (Top view diagram);

[0171] A conductive layer EL is formed on the surface of the second semiconductor layer 12 adjacent to the first sub-trench T1 and on the surface of the second semiconductor layer 12 adjacent to the second sub-trench T2 (see details). Figures 26 to 33 , Figure 30 For the previous appendix Figure 29 (Top view diagram);

[0172] At least open the area containing the opening H and the first void structure E1, and in the exposed area, the sidewall region Q2 on the side opposite to the filling layer Lc ( Figure 39 The storage node SN is formed on top of the above (please refer to the details). Figures 36 to 41 ,in, Figure 37 for Figure 36 Top view, Figure 39 for Figure 38 Top view and Figure 41 for Figure 40 (Top view);

[0173] A first semiconductor layer 11 is formed on the side of the memory node SN away from the second semiconductor layer 12, and a common word line WL is formed, including:

[0174] At least a channel material layer 11a and a common word line WL are sequentially formed on the sidewalls of the fill layer Lc and the storage node SN (see details). Figures 42 to 44 ,in Figure 44 The image in the upper right corner is an enlarged view of the region corresponding to Q3 in section A1-A2;

[0175] The portion of the channel material layer 11a located between adjacent first void structures E1 along the first direction X is removed to form the first semiconductor layer 11 (see details). Figures 43 to 54 ,in, Figure 47 for Figure 46 Top view, Figure 49 for Figure 48 Top view, Figure 51 for Figure 50 (Top view).

[0176] In some embodiments, removing the first sublayer a1 retained above the bottommost first sublayer a1 of the stacked layers ST based on the first sub-trench T1 includes:

[0177] At least the sacrificial layer La located in the first sub-trench T1 is removed to expose the surface of the first sub-layer a1 located at the bottom of the stacked layers ST, and a protective layer P is formed on the surface of the first sub-layer a1 located at the bottom of the stacked layers ST; the first sub-layer a1 located above the protective layer P is removed to form a second void structure E2 located around the first sub-trench T1, and a second gap K2 located around the opening H structure along the second direction (refer to...). Figure 23 (See the C1-C2 cross-sectional view in the diagram), and fill the second gap K2 and part of the second void structure E2 with the second dielectric layer L2, and at least fill the first sub-trench T1 with the sacrificial layer La (see the diagram for details). Figures 21 to 25 );

[0178] Forming the filling layer Lc includes:

[0179] At least open the location of the second sub-trench T2, and remove part of the sacrificial layer La around the opening H to form region Q1 (see details). Figure 28 And a filling layer Lc is formed at the location where the sacrificial layer La is removed (see details). Figure 29 and Figure 30 ),

[0180] After forming the conductive layer EL and before forming the storage node SN, the fabrication method further includes: forming a third dielectric layer L3 in the first sub-trench T1 and forming a sacrificial layer La in the second sub-trench T2 (see details). Figures 34 to 35 ).

[0181] In some embodiments, such as Figure 23 and Figure 24 As shown, after forming the second void structure E2 and before filling the second dielectric layer L2, the preparation method further includes:

[0182] An initial isolation layer 15a is formed, which is located on the sidewall of the second semiconductor layer 12 adjacent to the first sub-trench T1, and on the surface of the first dielectric layer exposed by the first sub-trench T1 and the second void structure E2.

[0183] like Figure 25 As shown, the preparation method further includes the following steps before forming the third dielectric layer L3:

[0184] The portion of the initial isolation layer 15a located on the surface of the second semiconductor layer 12 and exposed by the first sub-trench T1 is removed, and the portion of the initial isolation layer 15a located on the surface of the first dielectric layer L1 protruding from the second dielectric layer L2 is removed to form the isolation layer 15.

[0185] Here, the material of the isolation layer 15 includes, but is not limited to, nitride materials, such as silicon nitride. The presence of the isolation layer 15 can... Figure 32As shown, in the area where the isolation trench T is located, the position of the second sub-trench T2 acts as an etching barrier layer during etching to prevent damage or over-etching of the previously formed second dielectric layer L2.

[0186] In some embodiments, such as Figure 28 As shown, the ratio of the area occupied by the sacrificial layer La removed when forming the filling layer Lc to the area of ​​the sacrificial layer La removed when forming the storage node SN plus the area of ​​the sacrificial layer La removed when forming the filling layer Lc is between 1 / 5 and 1 / 2, and no specific limit is made here.

[0187] In some embodiments, when the second dielectric layer L2 is filled in part of the second void structure E2, the second gap K2 is also filled with the second dielectric layer L2. In addition, the second dielectric layer L2 located in the first sub-trench T1 can be obtained by filling it first and then performing a wet process to etch away part of the second dielectric layer L2 back and forth.

[0188] In some specific embodiments, the size of the etched portion in the third direction Z can account for 50% to 80% or 50% to 90% of the size in the same direction in the second void structure E2, such as 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, etc., without being specifically limited here.

[0189] In some embodiments, such as Figure 42 and Figure 43 As shown, after forming the memory node SN, and before forming at least the channel material layer 11a and the common word line WL sequentially on the fill layer Lc and the sidewall of the memory node SN, the fabrication method further includes:

[0190] For the adjacent first gap structure E1 along the first direction X (which can be understood as in) Figure 42 In the region filled by bit line BL and source line SL, the first dielectric layer L1 is etched. The remaining sidewalls of the first dielectric layer L1 are recessed inward relative to the sidewalls of the conductive layer EL and the memory node SN in a direction parallel to the plane of the substrate 10 to form the fourth void structure E4 (see details). Figure 42 );

[0191] The fourth void structure E4 is filled with a sacrificial material layer Lb (see details). Figure 43 ).

[0192] In some embodiments, such as Figure 44 As shown, at least a channel material layer 11a and a common word line WL are sequentially formed on the sidewalls of the fill layer Lc and the storage node SN (see reference for details). Figures 36 to 44 ),include:

[0193] A channel material layer 11a is formed, which covers the sidewalls of the opening H and the fourth void structure E4;

[0194] A first gate dielectric layer 13 is formed, which covers the sidewall of the channel material layer 11a;

[0195] A common word line WL is formed, which covers the sidewall of the first gate dielectric layer 13 and fills the area of ​​the opening H that is not filled.

[0196] In some embodiments, such as Figure 17 and Figure 18 As shown, after forming the second semiconductor layer 12 on the side of the first sublayer a1 retained in the first void structure E1, and before forming at least the sacrificial layer La in the opening H and the first void structure E1, the fabrication method further includes;

[0197] A second gate dielectric layer 14 and a sacrificial layer La are sequentially formed on the surface of the second semiconductor layer, and a predetermined material layer XL (not shown) is formed on at least the surface of the sacrificial layer La.

[0198] In some embodiments, an in-situ vapor growth process (ISSG) can be used to form a second gate dielectric layer 14 on the surface of the second semiconductor layer 12, which can obtain a second gate dielectric layer 14 with better quality and help improve the performance of the memory cell.

[0199] In some embodiments, the material of the first semiconductor layer 11 includes a metal oxide material, such as indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small, thereby ensuring a low refresh rate of the dynamic memory. The material of the second semiconductor layer 12 includes one of silicon-containing materials, silicon, silicon germanium, or germanium, such as silicon germanium (SiGe), silicon (Si), and other semiconductor materials.

[0200] In this embodiment of the disclosure, when a silicon-containing single crystal material (or silicon-germanium or germanium) is selected as the material of the second semiconductor layer 12, that is, when it is used as the read channel, the large change window of the threshold voltage (Vth) of the read transistor can be significantly improved, which helps to improve the read accuracy of the 2T0C memory structure and enhance the competitive advantage of the three-dimensional 2T0C structure.

[0201] In some embodiments, the second semiconductor layer 12 can be fabricated by first forming a stacked layer, then removing the material of the stacked layer in the area where the second semiconductor layer 12 needs to be formed, and then forming the second semiconductor layer 12 by epitaxial deposition. That is, in the embodiments of this disclosure, the formation of the second semiconductor layer 12 adopts a secondary epitaxial operation, which makes the second semiconductor layer 12 highly controllable in terms of formation process, channel thickness, and channel height along the first direction X. This helps to obtain the required information such as the required materials and size parameters of the second semiconductor layer 12 according to actual needs, and helps to improve the read performance of the semiconductor structure.

[0202] Understandably, in this embodiment, a first transistor Ta and a second transistor Tb can form a memory cell structure, wherein the first transistor Ta can be used as a write transistor and the second transistor Tb can be used as a read transistor. The inclusion of a common word line WL in this memory cell structure helps reduce the space occupied by the memory cell or the planar area of ​​the substrate 10, thus contributing to increased storage density. Furthermore, the presence of the common word line WL allows control of the opening and closing of the first semiconductor layer 11 during write operations, enabling data writing. Simultaneously, during read operations, the common word line WL can prevent accidental opening of the write transistor by applying a reverse voltage, facilitating smooth read operations.

[0203] In some embodiments, the conductive layer EL can be used as a bit line BL (adjacent to the second sub-trench T2) and a source line SL (adjacent to the first sub-trench T1) depending on its position, with the bit line BL and the source line SL extending along the second direction Y.

[0204] In some embodiments, when the opening H or the isolation trench T exposes the surface of the substrate 10, the formation of the protective layer P can be obtained by referring to the process when the opening H or the isolation trench T exposes the first sublayer a1 located at the bottom of the stacked layer ST, which will not be described in detail here.

[0205] In some embodiments, such as Figures 32 to 35 As shown, after forming the filling layer Lc and before forming the conductive layer EL, the fabrication method further includes:

[0206] Perform a doping process on the second semiconductor layer 12 (see details). Figure 32 );

[0207] After forming the conductive layer EL, and before forming the third dielectric layer L3 in the first sub-trench T1 and the sacrificial layer La in the second sub-trench T2, the fabrication method further includes:

[0208] At least a predetermined material layer XL is formed on the surface of the conductive layer EL and the protective layer P (not explicitly shown in the figure; the step may occur in...). Figure 33 and Figure 34 (between the process steps);

[0209] A third dielectric layer L3 is formed in the first sub-trench T1 and a sacrificial layer La is formed in the second sub-trench T2; including:

[0210] A sacrificial layer La is formed in the first sub-trench T1 and the second sub-trench T2. The sacrificial layer La covers the surface of the conductive layer EL and the protective layer P and at least fills the area where the isolation trench T is located (see details). Figure 34 );

[0211] Remove the sacrificial layer La and the protective layer P located in the first sub-trench T1, and fill with the third dielectric layer L3 (see details). Figure 35 ).

[0212] Continue to refer to Figure 32 and Figure 33 In some embodiments, after performing a doping process on the second semiconductor layer 12 and before forming the conductive layer EL, the method further includes a process for forming a metal silicide (not shown) to form an ohmic contact and reduce the resistance between the second semiconductor layer 12 and the subsequently formed metal layer.

[0213] In some embodiments, such as Figures 45 to 51 As shown, after at least a channel material layer 11a and a common word line WL are sequentially formed on at least the sidewalls of the fill layer Lc and the memory node SN, the portion of the channel material layer located between adjacent first void structures E1 along the first direction X is removed to form the first semiconductor layer 11, including:

[0214] At least open the area where the second sub-trench T2 is located; expose the preset material layer XL (not shown in the figure) (see details). Figure 45 );

[0215] The preset material layer XL located between adjacent bit lines BL along the first direction, the first dielectric layer L1 located on the side of the sacrificial material layer Lb adjacent to the second sub-trench T2, and the sacrificial material layer Lb are removed to form the fifth void structure E5 (see details). Figures 46 to 51 ,in Figure 50 The image in the upper right corner is an enlarged view of the Q4 region in section A1-A2;

[0216] Remove the channel material layer 11a exposed by the fifth void structure E5 to form the first semiconductor layer 11 (see details). Figure 50 and Figure 51 ).

[0217] In some embodiments, such as Figures 46 to 50 As shown, Figure 50 For along Figure 49 A top view of the cross-section along the D1-D2 direction, forming the fifth void structure E5, including;

[0218] like Figure 46 As shown, the remaining first dielectric layer L1 located on the side of the second sub-trench T2 adjacent to the opening H is removed, exposing the sidewalls of the sacrificial material layer Lb; at this time, as Figure 47 As shown, Figure 47 For along Figure 46 A top view of the cross-section in the D1-D2 direction, showing that the channel material layer 11a remains connected in the first direction X.

[0219] like Figure 48 and Figure 49 As shown, Figure 48 The image in the upper right corner is a magnified view of the area enclosed by the dashed line in section C1-C2. Figure 49 For along Figure 48 A top view of the cross-section along the D1-D2 direction, removing the exposed first dielectric layer L1 to form the initial fifth void structure E5a;

[0220] like Figure 50 and Figure 51 As shown, the sacrificial material layer Lb exposed by the initial fifth void structure E5a is removed to obtain the fifth void structure E5, and then the channel material layer 11a exposed by the fifth void structure E5 is removed to obtain the first semiconductor layer 11.

[0221] In some embodiments, the number of layers of multiple sets of first transistors Ta and second transistors Tb stacked along the first direction X can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, a dozen, several dozen, hundreds or even more layers. No specific limitation is made here, and it can be flexibly set according to the actual situation.

[0222] In some embodiments, the region of the common word line WL surrounded by the first semiconductor layer 11 can be defined as the gate structure G, which participates in the composition of the first transistor Ta and the second transistor Tb.

[0223] It is understandable that, regardless of whether the number of layers of the multiple sets of first transistors Ta and second transistors Tb stacked along the first direction X is one or more, the second semiconductor layer 12 of the second transistor Tb is arranged around a portion of the first semiconductor layer 11, so that the two transistors of a memory cell can be conditionally arranged in the same area. Compared with the method of stacking the first transistors Ta and second transistors Tb in a vertical direction, or the method of arranging the first transistors Ta and second transistors Tb in a horizontal direction on two areas, the semiconductor structure provided in this disclosure has significant advantages in terms of both volume occupation and substrate planar area occupation for a single memory cell. Through the improvement of the structural arrangement, a single memory cell can have a smaller space occupation or area occupation, which helps to obtain a larger number of memory cells in the same size space area or on the same size substrate plane, thereby effectively improving the storage density.

[0224] This disclosure also provides an electronic device, including the semiconductor structure of any of the above embodiments, or including a semiconductor structure formed by the preparation method of any of the above embodiments.

[0225] In some embodiments, the electronic device may include, but is not limited to, a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank. It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to the 2TOC structure of 3D DRAM or other semiconductor devices, and is not limited thereto. The embodiments of the semiconductor device fabrication method provided in this disclosure and the embodiments of the semiconductor devices belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0226] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: At least one set of first transistors, second transistors, and a memory node, wherein the first transistors and the second transistors have a common word line extending along a first direction perpendicular to the plane of the substrate; The first transistor includes at least: a first semiconductor layer surrounding at least a portion of the common word line; The second transistor includes at least: a second semiconductor layer located on the side of the first semiconductor layer away from the common word line and surrounding a portion of the first semiconductor layer, and the memory node being connected to the first semiconductor layer and located between the first semiconductor layer and the second semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that, The first semiconductor layer includes at least a first polar region and a second polar region, the first polar region and the second polar region being disposed opposite each other in a third direction, and the second polar region being connected to the memory node; wherein, the third direction is parallel to the plane of the substrate.

3. The semiconductor structure according to claim 2, characterized in that, The second semiconductor layer includes at least a first sub-part and two second sub-parts connected to both ends of the first sub-part. Along a second direction, the first electrode region is located between the ends of the two second sub-parts away from the first sub-part. The second direction is parallel to the plane of the substrate and intersects with the third direction.

4. The semiconductor structure according to claim 3, characterized in that, The structure comprising the first transistor, the second transistor, and the memory node includes multiple groups stacked in a first direction and spaced apart in a second and third direction. The semiconductor structure further includes: Multiple bit lines and multiple source lines are located on both sides of the first transistor, the second transistor, and the memory node along a third direction. The bit lines and source lines extend along a second direction and are distributed at intervals in the first direction and the third direction. Along the second direction, the bit line is connected to a plurality of first polar regions and a plurality of second sub-regions of the second semiconductor layer, and the source line is connected to a plurality of first sub-regions of the second semiconductor layer.

5. The semiconductor structure according to claim 1, characterized in that, The first transistor further includes a first gate dielectric layer, which is located between the common word line and the first semiconductor layer; The second transistor further includes a second gate dielectric layer located between the memory node and the second semiconductor layer.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a filling layer located between the first semiconductor layer and the second semiconductor layer, partially surrounding the first semiconductor layer and contacting the memory node; The second semiconductor layer surrounds the fill layer and the memory node.

7. The structure according to any one of claims 1-6, characterized in that, The material of the first semiconductor layer includes metal oxide, and the material of the second semiconductor layer includes silicon, silicon germanium, and germanium.

8. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: Substrate provided: A second semiconductor layer for forming a second transistor and a memory node are formed on the substrate, wherein the second semiconductor layer is disposed adjacent to the memory node; A first semiconductor layer and a common word line are formed on the side of the memory node away from the second semiconductor layer. The first semiconductor layer is connected to the memory node and located between the memory node and the common word line. The first semiconductor layer surrounds the common word line, and the common word line extends along a first direction. Wherein, the first direction is perpendicular to the plane of the substrate.

9. The preparation method according to claim 8, characterized in that, The first transistor and the second transistor comprise multiple sets, which are stacked in a direction perpendicular to the plane of the substrate and arranged in an array along a second direction and a third direction. The second direction and the third direction are parallel to the plane of the substrate and intersect each other. Before forming the second semiconductor layer of the second transistor on the substrate, the fabrication method further comprises: A stacked layer comprising alternating and repeating first and second sublayers is formed on the substrate, and openings and isolation trenches are formed through at least a portion of the stacked layer. The openings are spaced apart along a second direction and a third direction. The isolation trenches extend along the second direction and are located between adjacent openings in the third direction. Each isolation trench includes a first sub-trench located in the middle in the third direction and two second sub-trenches located on both sides of the first sub-trench. The first sub-trench is located between two adjacent openings in the third direction, and the second sub-trenches are located on both sides of two adjacent openings in the third direction. The second sublayer exposed by the isolation trench is removed, and the first sublayer is thinned to form a first gap; at least the first gap is filled with a first dielectric layer and the isolation trench is filled with a sacrificial layer; The portion of the first sublayer exposed by the opening is removed to form a first void structure around the opening, with the remaining first sublayer located at least at the bottom of the opening and on the side of the first void structure adjacent to the first sub-groove.

10. The preparation method according to claim 9, characterized in that, The second semiconductor layer forming the second transistor includes: A second semiconductor layer is formed on the surface of the first sub-layer in the first void structure, and at least a sacrificial layer is formed in the opening and the first void structure; After forming the second semiconductor layer and before forming the first semiconductor layer of the first transistor and the common word line, the fabrication method further includes: Based on the first sub-groove, remove the first sub-layer remaining above the first sub-layer at the bottom of the stack; and remove a portion of the sacrificial layer around the opening and form a fill layer at the location where the sacrificial layer is removed; A conductive layer is formed on the surface of the second semiconductor layer adjacent to the first sub-trench and on the surface of the second semiconductor layer adjacent to the second sub-trench. At least the opening and the area where the first void structure is located are opened, and a storage node is formed on the sidewall of the exposed area opposite to the filling layer; A first semiconductor layer and a common word line are formed on the side of the memory node away from the second semiconductor layer, including: At least a channel material layer and a common word line are formed sequentially on the sidewalls of the filling layer and the storage node; The portion of the channel material layer located between adjacent first void structures along a first direction is removed to form the first semiconductor layer.

11. The preparation method according to claim 10, characterized in that, Removing the first sublayer remaining above the bottommost first sublayer of the stacked layers based on the first sub-trench includes: At least the sacrificial layer located in the first sub-trench is removed to expose the surface of the first sub-layer at the bottom of the stack, and a protective layer is formed on the surface of the first sub-layer at the bottom of the stack; the first sub-layer above the protective layer is removed to form a second void structure around the first sub-trench and a second gap around the opening structure, and a second dielectric layer is filled in the second gap and part of the second void structure, and a sacrificial layer is filled in at least the first sub-trench; Forming the filling layer includes: At least open the location of the second sub-groove, remove a portion of the sacrificial layer around the opening, and form a fill layer at the location where the sacrificial layer was removed. After forming the conductive layer and before forming the storage node, the fabrication method further includes: A third dielectric layer is formed in the first sub-trench and a sacrificial layer is formed in the second sub-trench.

12. The preparation method according to claim 11, characterized in that, After filling the first dielectric layer in the first gap and the sacrificial layer in the isolation trench, and before removing the portion of the first sublayer exposed by the opening to form a first void structure around the opening, the fabrication method further includes: Remove the sacrificial layer located in the second sub-trench to expose the first dielectric layer and the first sub-layer located on the sidewall of the second sub-trench: Laterally remove a portion of the first sublayer to form a third void structure, the third void structure not exposing the sidewalls of the opening; A preset material layer is formed, which covers the sidewalls of the material layer exposed by the first sub-groove and the third void structure; After forming a second semiconductor layer on the surface of the first sublayer in the first void structure, and before forming at least a sacrificial layer in the opening and the first void structure, the fabrication method further includes: A second gate dielectric layer and a sacrificial layer are sequentially formed on the surface of the second semiconductor layer, and a predetermined material layer is formed at least on the surface of the sacrificial layer.

13. The preparation method according to claim 12, characterized in that, After forming the filling layer and before forming the conductive layer, the preparation method further includes: A doping process is performed on the second semiconductor layer; After forming the conductive layer and before forming the third dielectric layer in the first sub-trench and the sacrificial layer in the second sub-trench, the fabrication method further includes: The preset material layer is formed at least on the surfaces of the conductive layer and the protective layer; Forming a third dielectric layer in the first sub-trench and forming a sacrificial layer in the second sub-trench; including: The sacrificial layer is formed in the first sub-trench and the second sub-trench, the sacrificial layer covering the surface of the conductive layer and the protective layer and at least filling the unfilled area of ​​the isolation trench; Remove the sacrificial layer and the protective layer located in the first sub-trench, and fill with the third dielectric layer.

14. The preparation method according to claim 13, characterized in that, After the memory node is formed, and before at least one channel material layer and a common word line are sequentially formed on the fill layer and the sidewall of the memory node, the fabrication method further includes: The first dielectric layer located between adjacent first void structures along the first direction is etched to form a fourth void structure; The fourth void structure is filled with a sacrificial material layer; After forming at least a channel material layer and a common word line sequentially on the fill layer and the sidewall of the memory node, a first semiconductor layer is formed by removing the portion of the channel material layer located between adjacent first void structures along a first direction, including: At least the area where the second sub-groove is located is opened; exposing the preset material layer; The preset material layer, the first dielectric layer located on the side of the sacrificial material layer adjacent to the second sub-trench, and the sacrificial material layer are removed to form a fifth void structure; The channel material layer exposed by the fifth void structure is removed to form the first semiconductor layer.

15. An electronic device, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 7, or the semiconductor structure formed by the preparation method as described in any one of claims 8 to 14.

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