Three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device includes a substrate including a cell array region and an extension region; a semiconductor pattern provided on the cell array region of the substrate and extending in a first direction substantially parallel to an upper surface of the substrate; a word line surrounding the semiconductor pattern and extending in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction; an isolation structure extending on the cell array region and the extension region in the second direction; and a shield structure penetrating the isolation structure. The isolation structure is provided between the semiconductor patterns on the cell array region. The isolation structure and the shield structure each include different materials from each other.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0056429, filed on April 29, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a three-dimensional semiconductor device and a method for manufacturing the same, and more specifically, to a three-dimensional semiconductor device having improved electrical properties. Background Technology

[0003] Semiconductor devices have attracted attention as important components in the electronics industry due to their characteristics such as miniaturization, versatility, and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices for storing logic data, semiconductor logic devices for computing and processing logic data, and hybrid semiconductor devices that include memory components and logic components.

[0004] Recently, with the increasing speed and low power consumption of electronic devices, the built-in semiconductor devices also require high operating speeds, low operating voltages, and / or similar characteristics. To meet these requirements, semiconductor devices with higher integration levels are needed. However, as semiconductor devices become more integrated, their electrical characteristics and manufacturing yield may decrease. Therefore, extensive research is underway to improve the electrical characteristics and manufacturing yield of semiconductor devices. Summary of the Invention

[0005] The disclosed embodiments can provide a three-dimensional semiconductor device with improved electrical characteristics and reliability, and a method for manufacturing the same.

[0006] According to embodiments of the disclosed concept, a three-dimensional semiconductor device may include: a substrate including a cell array region and an extension region; a semiconductor pattern disposed on the cell array region of the substrate and extending along a first direction substantially parallel to the upper surface of the substrate; word lines surrounding the semiconductor pattern and extending along a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction; an isolation structure extending along the second direction on the cell array region and the extension region; and a shielding structure penetrating the isolation structure, wherein the isolation structure is disposed between the semiconductor patterns on the cell array region, and wherein the isolation structure and the shielding structure each comprise different materials from each other.

[0007] According to embodiments of the disclosed concept, a three-dimensional semiconductor device may include: a substrate including a cell array region and an extension region; a semiconductor pattern disposed on the cell array region of the substrate and extending along a first direction substantially parallel to the upper surface of the substrate; word lines surrounding the semiconductor pattern and extending along a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction; a capacitor structure on one side of each of the semiconductor patterns; a bit line on the other side of each of the semiconductor patterns; an isolation structure extending along the second direction on the cell array region and the extension region; and a shielding structure penetrating the isolation structure, wherein at least a portion of the shielding structure overlaps with the extension region in a planar view.

[0008] According to embodiments of the disclosed concept, a three-dimensional semiconductor device may include: a substrate including a cell array region and an extension region; a semiconductor pattern extending along a first direction substantially parallel to an upper surface of the substrate; word lines surrounding the semiconductor pattern and extending along a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction; bit lines extending along a third direction substantially perpendicular to the upper surface of the substrate at a first edge portion of the semiconductor pattern; a capacitor structure at a second edge portion of the semiconductor pattern; an isolation structure extending along the second direction over the cell array region and the extension region; and a shielding structure penetrating the isolation structure, wherein the isolation structure includes a first isolation structure disposed adjacent to the first edge portion of the semiconductor pattern and a second isolation structure disposed adjacent to the second edge portion of the semiconductor pattern, wherein the shielding structure includes a first shielding structure extending into the first isolation structure and a second shielding structure extending into the second isolation structure, and wherein the first isolation structure and the second isolation structure each include a material with an etch selectivity different from that of the first shielding structure and the second shielding structure.

[0009] According to embodiments of the disclosed concept, a method of manufacturing a semiconductor device may include: preparing a substrate including a first region and a second region; forming a semiconductor pattern extending along a first direction on the first region of the substrate; forming an isolation structure extending across the first and second regions along a second direction substantially perpendicular to the first direction between the semiconductor patterns; forming a shielding structure penetrating the isolation structure; forming word lines extending along the second direction and surrounding the semiconductor pattern on the first region of the substrate; and forming a capacitor structure connected to one side of the semiconductor pattern, wherein the shielding structure may include a material with an etch selectivity different from that of the isolation structure.

[0010] According to embodiments of the disclosed concept, forming word lines may include: removing a portion of an isolation structure on a first region to form an open region; forming a conductive layer surrounding a semiconductor pattern on the first region; and patterning the conductive layer.

[0011] According to embodiments of the disclosed concept, the method of manufacturing a three-dimensional semiconductor device may further include forming a gate interconnect on a second region of a substrate prior to forming a capacitor structure, wherein forming the gate interconnect may include removing a portion of an isolation structure on the second region to form an open region and forming the gate interconnect on the second region.

[0012] According to some embodiments, removing a portion of the isolation structure on the second region may include performing a wet etching process until one end of the shielding structure is exposed.

[0013] According to some embodiments, forming a capacitor structure may include removing a portion of a semiconductor pattern and forming a capacitor structure on the semiconductor pattern. Attached Figure Description

[0014] Figure 1 This is a circuit diagram illustrating a three-dimensional semiconductor device according to some embodiments of the disclosed concept.

[0015] Figure 2A , Figure 2B and Figure 2C This is a perspective view of a three-dimensional semiconductor device based on some embodiments of the disclosed concept.

[0016] Figure 3 This is a plan view showing the cell array region of a three-dimensional semiconductor device according to some embodiments of the disclosed concept.

[0017] Figure 4 It is based on some embodiments of the disclosed concept. Figure 3 The cross-sectional view taken by line AA′.

[0018] Figure 5 It is based on some embodiments of the disclosed concept. Figure 3 The cross-sectional view taken from line BB′.

[0019] Figure 6 It is based on some embodiments of the disclosed concept. Figure 3 The cross-sectional view taken by line CC′.

[0020] Figure 7 This is a plan view showing the cell array region of a three-dimensional semiconductor device according to some embodiments of the disclosed concept.

[0021] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17This is a cross-sectional view illustrating a process for manufacturing a three-dimensional semiconductor device according to some embodiments of the disclosed concept.

[0022] Figure 18 This is a plan view showing the cell array region of a three-dimensional semiconductor device according to some embodiments of the disclosed concept.

[0023] Figure 19 It is based on some embodiments of the disclosed concept. Figure 18 The cross-sectional view of the line DD′.

[0024] Figure 20 It is based on some embodiments of the disclosed concept. Figure 18 The cross-sectional view of the line EE′. Specific Implementation

[0025] Example embodiments of the disclosed concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are illustrated.

[0026] Figure 1 This is a circuit diagram illustrating a three-dimensional semiconductor device according to some embodiments of the disclosed concept.

[0027] Reference Figure 1 The three-dimensional semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0028] The memory cell array 1 may include word lines WL, bit lines BL, source lines SL, and memory cells MC. The memory cells MC may be arranged in three dimensions, and each memory cell MC may be connected to a word line WL, a bit line BL, and a source line SL. According to some embodiments, each memory cell MC may consist of a transistor including a memory layer (or data storage layer).

[0029] The row decoder 2 can decode addresses input from external sources and can select one of the word lines WL of the memory cell array 1. The address decoded by the row decoder 2 can be provided to the row driver (not shown), and the row driver can supply voltage to the selected word line WL and the unselected word line WL in response to the control of the control circuit.

[0030] The readout amplifier 3 can sense, amplify, and output the voltage difference between the selected bit line BL and the reference bit line based on the address decoded by the column decoder 4.

[0031] The column decoder 4 can provide a data transfer path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can select any one of the bit lines BL by decoding the address input from the external source.

[0032] Control logic 5 can generate control signals to control the operation of writing data to or reading data from memory cell array 1.

[0033] Figure 2A , Figure 2B and Figure 2C This is a perspective view of a three-dimensional semiconductor device based on some embodiments of the disclosed concept.

[0034] Reference Figure 2A The three-dimensional semiconductor device may include a substrate 100, a peripheral circuit structure PS on the substrate 100, and a cell array structure CS on the peripheral circuit structure PS.

[0035] The peripheral circuit structure PS may include core circuitry and peripheral circuitry (SWD / PERI) formed on substrate 100. The core circuitry and peripheral circuitry may include reference... Figure 1 The described row decoder 2 and column decoder 4 (see Figure 1 ), Readout amplifier (S / A) 3 (see Figure 1 ) and control logic 5 (see Figure 1 ).

[0036] The substrate 100 may be plate-shaped, extending along a plane defined by a first direction D1 and a second direction D2. In this specification, the first direction D1 and the second direction D2 may be parallel to the upper surface of the substrate 100 and may intersect each other. The peripheral circuit structure PS and the cell array structure CS may be sequentially stacked on the substrate 100 in a third direction D3 perpendicular to the upper surface of the substrate 100.

[0037] The cell array structure CS may include bit lines BL, source lines SL, word lines WL, and memory cells MC between them. Each memory cell MC may be connected to a word line WL, a bit line BL, and a source line SL.

[0038] Reference Figure 2B The semiconductor device may include a cell array structure CS on a substrate 100 and a peripheral circuit structure PS on the cell array structure CS. The cell array structure CS may be disposed between the substrate 100 and the peripheral circuit structure PS. The peripheral circuit structure PS may include a core and peripheral circuitry.

[0039] Reference Figure 2C The semiconductor device may have a chip-to-chip (C2C) structure. The peripheral circuit structure PS may include a first substrate 100a. A lower metal pad LMP may be disposed on the uppermost portion of the peripheral circuit structure PS. The lower metal pad LMP may be electrically connected to the core and peripheral circuitry. The lower metal pad LMP may be bonded to the upper metal pad UMP of the cell array structure CS.

[0040] The cell array structure CS may include a second substrate 200a, and an upper metal pad UMP may be disposed on the bottom portion of the cell array structure CS. The upper metal pad UMP may be electrically connected to the bit line BL, the source line SL, and the word line WL. The upper metal pad UMP may be electrically connected to the memory cell MC.

[0041] Figure 3 This is a plan view showing the cell array region of a three-dimensional semiconductor device according to some embodiments of the disclosed concept. Figure 4 It is based on some embodiments of the disclosed concept. Figure 3 The cross-sectional view taken by line AA′. Figure 5 It is based on some embodiments of the disclosed concept. Figure 3 The cross-sectional view taken from line BB′. Figure 6 It is based on some embodiments of the disclosed concept. Figure 3 The cross-sectional view taken by line CC′.

[0042] Reference Figures 3 to 6 The three-dimensional semiconductor device according to some embodiments of the disclosed concept may include a substrate 100. The substrate 100 may be, for example, a semiconductor substrate. The semiconductor substrate may be, for example, a silicon substrate.

[0043] The substrate 100 may include a cell array region CER and an extended region EXR. The cell array region CER and the extended region EXR may be adjacent to each other in a second direction D2. In this specification, the cell array region CER and the extended region EXR may also be referred to as a first region and a second region.

[0044] like Figure 4 As shown, the unit array structure CS can be disposed on the substrate 100. Figure 4 In the illustration, a cell array structure CS is shown on substrate 100, but the illustration is not limited thereto. As an example, multiple cell array structures CS may be arranged adjacent to each other in a first direction D1 or a second direction D2. Hereinafter, for the sake of convenience, a single cell array structure CS will be described, but the following description can also be applied to other cell array structures CS.

[0045] A cell array structure CS may include semiconductor patterns SP, word lines WL, and peripheral components surrounding them. Each element will be described in detail below.

[0046] The semiconductor pattern SP can be spaced apart from the substrate 100 in a third direction D3. In other words, the semiconductor pattern SP can be floated from the substrate 100. The semiconductor pattern SP can extend on the substrate 100 along a first direction D1. As an example, the semiconductor pattern SP can have a strip shape extending along the first direction D1.

[0047] The semiconductor pattern SP can include at least one of single-crystal semiconductors, polycrystalline semiconductors, oxide semiconductors, and two-dimensional materials. As an example, a single-crystal semiconductor can be single-crystal silicon. As an example, a polycrystalline semiconductor can be polycrystalline silicon. As an example, an oxide semiconductor can be indium gallium zinc oxide (IGZO). As an example, a two-dimensional material can be MoS2, WS2, MoSe2, or WSe2.

[0048] Multiple semiconductor patterns SP can be set. The semiconductor patterns SP can be spaced apart from each other in a first direction D1 and a third direction D3. The semiconductor patterns SP set along the third direction D3 can overlap each other vertically. The sidewalls of the semiconductor patterns SP set along the third direction D3 can be aligned with each other.

[0049] The semiconductor pattern SP may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 spaced apart from each other in a first direction D1 relative to the bit line BL. The first semiconductor pattern SP1 may be configured to be spaced apart from each other along a second direction D2 and a third direction D3. The second semiconductor pattern SP2 may be configured to be spaced apart from each other along a second direction D2 and a third direction D3.

[0050] Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include a first edge portion EA1 and a second edge portion EA2 spaced apart in a first direction D1, and a channel region CH between them. The channel region CH may overlap with a word line WL in a third direction D3. The first edge portion EA1 may be connected to a bit line BL. The second edge portion EA2 may be connected to a capacitor structure CAP. As an example, each of the first edge portion EA1 and the second edge portion EA2 of the semiconductor pattern SP may include an impurity region in which impurities (e.g., N-type or P-type impurities) are doped. The impurity region may constitute the source / drain region of a transistor. In this specification, the first edge portion EA1 and the second edge portion EA2 may also be referred to as one end or the other end of the semiconductor pattern SP.

[0051] Word lines WL can surround the channel region CH of the semiconductor pattern SP and extend along the second direction D2. Multiple word lines WL can be provided. Word lines WL can be spaced apart from each other in the third direction D3. In some other examples, word lines WL can extend on one side of multiple semiconductor patterns SP arranged along the second direction D2, and the cell array structure can include a single-gate structure. In some other examples, word lines WL can include two elements, each extending on the upper and lower surfaces of multiple semiconductor patterns SP arranged along the second direction D2, and the cell array structure can include a dual-gate structure.

[0052] At least one word line WL may extend from the cell array region CER to the extension region EXR to form a gate connection line GL. Although not shown, the word line WL extending to the extension region EXR may have a stepped structure in a cross-sectional view along the second direction D2. Although not shown, contacts may be connected to each end of the gate connection line GL forming the stepped structure. In an embodiment, the word line WL extending to the extension region EXR may not form a stepped structure, and the ends of the gate connection line GL may be arranged and overlapped along the third direction D3.

[0053] The word line WL may include a gate insulating pattern GI surrounding a channel region CH of a semiconductor pattern SP and a gate electrode GE extending along a second direction D2 on the gate insulating pattern GI.

[0054] As an example, the gate electrode GE can be a single layer or a composite layer. As an example, the gate insulating pattern GI can include silicon oxide. As an example, the gate electrode GE can include Ti, TiN, TiSiN, TiON, W, WN, Mo, MoN, MoO. x N y At least one of Ta, TaN, PolySi, Li, Na, K, Cs, Rb, Sr, Ba, Ca, Ce, Sm, Eu, Mg, Sc, Y, Hf, Tl, As, La, Nd, Gd, Tb, Lu, Th, U, Mn, Al, Ga, In, Pb, Cd, Bi, and Zr.

[0055] Bit line BL can be disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. Bit line BL can be disposed on one side of the first semiconductor pattern SP1 and the second semiconductor pattern SP2. Specifically, bit line BL can extend along a third direction D3 on the side surface of the first edge portion EA1 of the first semiconductor pattern SP1 and the first edge portion EA1 of the second semiconductor pattern SP2.

[0056] The bit line BL can be a single layer comprising one material or a composite layer comprising two or more materials. As an example, the bit line BL can include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), and a metal silicide (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0057] Interlayer insulating layers (ILDs) can be interposed between word lines (WLs) spaced apart along a third direction (D3), and they can be separated. Interlayer insulating layers (ILDs) can also be interposed between semiconductor patterns (SPs) spaced apart along a third direction (D3).

[0058] A gap filler layer GF can be interposed between semiconductor patterns SP that are spaced apart from each other along a third direction D3. The gap filler layer GF can be disposed between a word line WL and a capacitor structure CAP. The gap filler layer GF may include, for example, an insulating material. According to some embodiments, an interlayer insulating layer ILD may be disposed instead of the gap filler layer GF.

[0059] The interlayer insulating layer (ILD) and the gap filling layer (GF) may each include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0060] The capacitor structure CAP can be disposed on the opposite side of the first semiconductor pattern SP1 and the second semiconductor pattern SP2. Specifically, the capacitor structure CAP can be disposed on the side surface of the second edge portion EA2 of the semiconductor patterns SP which are spaced apart from each other along the third direction D3. That is, the capacitor structure CAP can be connected to the second edge portion EA2 of the semiconductor pattern SP.

[0061] However, the capacitor structure CAP may not be disposed on some semiconductor patterns SP adjacent to the extended region EXR. In this case, the length of the semiconductor pattern SP in the first direction D1 may be longer than the length of another semiconductor pattern SP connected to the capacitor structure CAP in the first direction D1.

[0062] The capacitor structure CAP may include a first electrode ET1, a second electrode ET2, a dielectric layer DL, and a plate electrode PE covering them. Multiple first electrodes ET1 may be provided, and the multiple first electrodes ET1 may be spaced apart from each other on a third direction D3. A second electrode ET2 may be provided on the first electrode ET1, and the dielectric layer DL may be provided between the first electrode ET1 and the second electrode ET2. The first electrode ET1 and the second electrode ET2 may be spaced apart by the dielectric layer DL. The plate electrode PE may be provided on the second electrode ET2. Due to the provision of the capacitor structure CAP, the three-dimensional semiconductor device according to the embodiments of the disclosed concept can be a dynamic random access memory (DRAM).

[0063] Each of the first electrode ET1 and the second electrode ET2 may include a conductive material. As an example, each of the first electrode ET1 and the second electrode ET2 may include at least one of the following: doped silicon (Si), doped silicon germanium (SiGe), metallic materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), metal nitrides (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), titanium silicon nitride (e.g., TiSiN), titanium aluminum nitride (such as TiAlN), tantalum aluminum nitride (such as TaAlN), conductive oxides (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo), and metal silicides. Each of the first electrode ET1 and the second electrode ET2 may be a monolayer made of a single material or a composite layer comprising two or more materials.

[0064] As an example, the dielectric layer DL may include at least one of metal oxides such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3 and TiO2, and dielectric materials with perovskite structures such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT and PLZT.

[0065] As another example, the capacitor structure CAP can be a variable resistance pattern capable of switching between two resistance states via an electrical pulse. In this case, the capacitor structure CAP can include phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials whose crystallization state changes according to the amount of current.

[0066] Although not shown, a silicide pattern may be disposed between the first electrode ET1 and the semiconductor pattern SP. The silicide pattern may include metal silicides (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0067] The isolation structure 101 can extend along the second direction D2 on the cell array region CER and the extension region EXR. The isolation structure 101 can be disposed between adjacent semiconductor patterns SP along the first direction D1.

[0068] Specifically, the isolation structure 101 may include a first isolation structure 101a disposed adjacent to a first edge portion EA1 of the semiconductor pattern SP and a second isolation structure 101b disposed adjacent to a second edge portion EA2 of the semiconductor pattern SP. The first isolation structure 101a and the second isolation structure 101b may be spaced apart in a first direction D1. The number of the first isolation structure 101a and the second isolation structure 101b is not limited to those shown.

[0069] On the cell array region CER, a first isolation structure 101a can be disposed between capacitor structures CAP spaced apart along the first direction D1. For example... Figure 5 As shown, the first isolation structure 101a can be disposed on the first edge portion EA1 of the semiconductor pattern SP. In the cell array region CER, the bit line BL can penetrate the second isolation structure 101b.

[0070] The first isolation structure 101a and the second isolation structure 101b may include insulating materials. As an example, the first isolation structure 101a and the second isolation structure 101b may include silicon oxide.

[0071] A shielding structure 111 can be provided that penetrates the isolation structure 101. In a plan view, at least a portion of the shielding structure 111 may overlap with the extended region EXR. The shielding structure 111 may have a strip extending along a second direction D2. The shielding structure 111 may be configured to be spaced apart from the bit line BL. In some embodiments, the shielding structure 111 may include a portion disposed along a first direction D1 between two adjacent gate interconnects GL.

[0072] The shielding structure 111 may include a first shielding structure 111a extending into the first isolation structure 101a and a second shielding structure 111b extending into the second isolation structure 101b. That is, the first shielding structure 111a can penetrate the first isolation structure 101a, and the second shielding structure 111b can penetrate the second isolation structure 101b.

[0073] Specifically, the first shielding structure 111a can extend along the second direction D2 on the cell array region CER and the extension region EXR. The second shielding structure 111b can extend along the second direction D2 on the extension region EXR.

[0074] In the plan view, a portion of the first shielding structure 111a may overlap with the word line WL along any line extending in the first direction D1. The second shielding structure 111b may overlap with the bit line BL along any line extending in the second direction D2. One end 111aE of the first shielding structure 111a may be placed closer to the capacitor structure CAP than one end 111bE of the second shielding structure 111b.

[0075] In the plan view, one end 111aE of the first shielding structure 111a may not be aligned with one end 111bE of the second shielding structure 111b. In some embodiments, a plurality of first shielding structures 111a and a plurality of second shielding structures 111b may be alternately placed along the first direction D1. In some embodiments, one end 111aE of the plurality of first shielding structures 111a may be located in the cell array region CER, and one end 111bE of the plurality of second shielding structures 111b may be located in the extension region EXR. In some embodiments, one end 111aE of the plurality of first shielding structures 111a and one end 111bE of the plurality of second shielding structures 111b may be alternately arranged to be staggered from each other along the first direction D1.

[0076] The capacitor structure CAP located closest to the extension region EXR can be placed further away from the extension region EXR than one end 111aE of the first shielding structure 111a and one end 111bE of the second shielding structure 111b.

[0077] In other words, the capacitor structure CAP may not overlap with the first shielding structure 111a and the second shielding structure 111b in the plan view. The first shielding structure 111a may overlap with the remaining semiconductor patterns SP in the semiconductor pattern SP that are not connected to the capacitor structure CAP in the first direction D1.

[0078] The height of the shielding structure 111 can be greater than the height of the isolation structure 101. For example... Figure 5 and Figure 6 As shown, the first shielding structure 111a and the second shielding structure 111b can extend into the substrate 100 through the first isolation structure 101a and the second isolation structure 101b. That is, the first shielding structure 111a and the second shielding structure 111b can each penetrate the upper portion of the substrate 100. From a horizontal perspective, the first isolation structure 101a can be disposed between the gap filling layer GF and the first shielding structure 111a.

[0079] The first isolation structure 101a and the second isolation structure 101b may each comprise a material having an etch selectivity different from that of the first shielding structure 111a and the second shielding structure 111b. As an example, the first shielding structure 111a and the second shielding structure 111b may comprise silicon nitride.

[0080] Reference Figures 3 to 6 The substrate 100 of the three-dimensional semiconductor device according to some embodiments of the disclosed concept may further include an extension region EXR adjacent to the cell array region CER in the second direction D2. The arrangement and design of the extension region EXR are not limited and can be freely changed and combined.

[0081] The interconnect structure SS can be disposed on the extended region EXR. The interconnect structure SS may include a plurality of gate interconnect lines GL and interlayer insulating layers ILD alternately stacked on the substrate 100. Each of the gate interconnect lines GL and interlayer insulating layers ILD may extend along a first direction D1. Each of the gate interconnect lines GL of the interconnect structure SS may be connected to the gate electrode GE of each of the word lines WL of the cell array structure CS.

[0082] At least a portion of the shielding structure 111 may overlap with the gate connection line GL in the first direction D1. As an example, one end 111aE of the first shielding structure 111a may be located between the capacitor structure CAP and the gate connection line GL. The other end of the first shielding structure 111a may overlap with the gate connection line GL.

[0083] The insulating layer 120 may cover the connection structure SS. The insulating layer 120 may include, for example, an insulating material.

[0084] Figure 7 This is a plan view showing the cell array region of a three-dimensional semiconductor device according to some embodiments of the disclosed concept.

[0085] Reference Figure 7 In some embodiments, the first shielding structure 111a may not include the portion located in the cell array region CER. For example, the first shielding structure 111a may not include the portion overlapping with the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first direction D1. One end of each of the shielding structures 111 may be aligned in the first direction D1. In some embodiments, one end of each of the shielding structures 111 may be aligned at the boundary between the extension region EXR and the cell array region CER.

[0086] Specifically, one end 111aE of the first shielding structure 111a and one end 111bE of the second shielding structure 111b can be aligned with any line extending along the first direction D1 between the extended region EXR and the cell array region CER. That is, the first shielding structure 111a and the second shielding structure 111b may not extend on the cell array region CER.

[0087] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 This is a cross-sectional view illustrating a process for manufacturing a three-dimensional semiconductor device according to some embodiments of the disclosed concept. Specifically, Figure 8 , Figure 10 , Figure 12 and Figure 14 It is along Figure 3 The cross-sectional view taken from line BB′. Figure 16 It is along Figure 3 A cross-sectional view taken from the centerline AA′. Figure 17 It is along Figure 3 A cross-sectional view taken from the centerline CC′. Figure 9 , Figure 11 , Figure 13 and Figure 15 It corresponds to Figure 3 Floor plan.

[0088] Reference Figure 8 Substrate 100 can be fabricated. Substrate 100 may include, for example: Figure 3 The cell array region CER and the extended region EXR are shown. However, Figure 8 Only the cell array region CER is shown.

[0089] The sacrificial layer (SAL) and active layer (ACL) can be alternately stacked on the substrate 100. The sacrificial layer (SAL) and active layer (ACL) can be formed on the cell array region (CER) and the extension region (EXR). The sacrificial layer (SAL) and active layer (ACL) can be formed by repeatedly performing epitaxial processes. Along the third direction D3, the thickness of the sacrificial layer (SAL) can be greater than the thickness of the active layer (ACL), but is not limited to this.

[0090] Each of the sacrificial layer (SAL) and the active layer (ACL) may comprise a semiconductor material. The sacrificial layer (SAL) may comprise a material that can be etch-selectively etched relative to the active layer (ACL). Therefore, even if the sacrificial layer (SAL) is removed during a removal process, the active layer (ACL) may not be removed or may be removed only minimally. As an example, the active layer (ACL) may comprise silicon, and the sacrificial layer (SAL) may comprise silicon-germanium.

[0091] Reference Figure 9 and Figure 10 An etching process can be performed to remove a portion of the sacrificial layer SAL and the active layer ACL. As a result of performing the etching process, a first semiconductor pattern SP1 and a second semiconductor pattern SP2 spaced apart from each other on the first direction D1 can be formed from the active layer ACL. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may each include a first edge portion EA1 and a second edge portion EA2 spaced apart on the first direction D1, and a channel region CH between them.

[0092] Subsequently, an isolation structure 101 can be formed on the regions of the removed portions of the sacrificial layer SAL and the active layer ACL. Forming the isolation structure 101 may include filling the regions of the removed portions of the sacrificial layer SAL and the active layer ACL with silicon oxide.

[0093] The isolation structure 101 may include a first isolation structure 101a and a second isolation structure 101b. The first isolation structure 101a and the second isolation structure 101b may be spaced apart from each other in a first direction D1. The first isolation structure 101a and the second isolation structure 101b may each extend in a third direction D3.

[0094] Subsequently, the sacrificial layer SAL can be removed, and a gap-filling layer GF can be formed in the region between the first semiconductor patterns SP1 spaced along the third direction D3 and the region between the second semiconductor patterns SP2 spaced along the third direction D3. Removing the sacrificial layer SAL can, for example, include a wet etching process.

[0095] Reference Figure 11 and Figure 12 A shielding structure 111 that penetrates the isolation structure 101 can be formed. Forming the shielding structure 111 may include removing a portion of the isolation structure 101 and the upper portion of the substrate 100, and filling the area where the isolation structure 101 and the upper portion of the substrate 100 are removed with silicon nitride. At this time, when a portion of the isolation structure 101 and the upper portion of the substrate 100 are removed, the inner surface of the isolation structure 101 and one surface of the substrate 100 can be exposed.

[0096] The shielding structure 111 may extend in the second direction D2 and the third direction D3. The shielding structure 111 may include a first shielding structure 111a that penetrates the first isolation structure 101a and a second shielding structure 111b that penetrates the second isolation structure 101b.

[0097] A first shielding structure 111a can be formed along the second direction D2 on the cell array region CER and the extended region EXR. A second shielding structure 111b can be formed along the second direction D2 on the extended region EXR.

[0098] Reference Figure 13 and Figure 14 A portion of the gap filler layer GF can be removed. At this time, a portion of the second isolation structure 101b on the cell array region CER can also be removed to form the open region OP. According to some embodiments, removing a portion of the second isolation structure 101b may include performing a wet etching process until one end of the second shielding structure 111b is exposed.

[0099] Then, word lines WL can be formed on the region where the gap fill layer GF has been removed. Word lines WL can be formed between semiconductor patterns SP. Word lines WL may include a gate insulating pattern GI and a gate electrode GE. The gate insulating pattern GI and the gate electrode GE can be formed as part of the semiconductor pattern SP. In this case, forming the gate electrode GE may include forming a conductive layer and a patterned conductive layer.

[0100] In a comparative example, the isolation structure may have internal voids, and when a gate electrode is formed on the cell array region CER or a cleaning process is performed, gate electrode material or cleaning chemicals may permeate into the extension region EXR through these voids. However, the second shielding structure 111b according to an embodiment of the disclosed concept can fill the internal space of the second isolation structure 101b in the extension region EXR adjacent to the cell array region CER, thereby preventing conductive material or chemicals included in the gate electrode GE from permeating the cell array region CER into the extension region EXR.

[0101] Subsequently, an interlayer insulating layer (ILD) can be formed between the spaced-apart gate electrodes GE. The interlayer insulating layer (ILD) can extend to the extended region EXR of the substrate 100.

[0102] Reference Figure 15 , Figure 16 and Figure 17 It can reform in Figure 13 The second isolation structure 101b is removed. The bit line BL can be formed through the second isolation structure 101b. For example... Figure 16 As shown, bit line BL can be connected to the first edge portion EA1 of semiconductor pattern SP.

[0103] After bit lines BL are formed in a portion of the cell array region CER exposed by the second shielding structure 111b, an opening can be made in a portion of the extended region EXR through the first shielding structure 111a, and a connection structure SS can be formed.

[0104] In some embodiments, a portion of the first isolation structure 101a on the extended region EXR may be removed to form an open region OP. As an example, removing a portion of the first isolation structure 101a may include performing a wet etching process until one end of the first shielding structure 111a is exposed. After removing the gap fill layer GF through the open region OP to form an empty space, conductive material may be filled to form a plurality of gate interconnects GL.

[0105] In a comparative example, the first isolation structure 101a may have internal voids, and conductive material forming the gate connection line GL or cleaning chemicals may permeate into the cell array region CER through these voids. However, according to the embodiment of the disclosed concept, the first shielding structure 111a fills the internal space of the first isolation structure 101a in the cell array region CER adjacent to the extension region EXR, thereby preventing conductive material or chemicals included in the gate connection line GL from permeating the extension region EXR into the cell array region CER. A covering insulating layer 120 may be formed on the connection structure SS.

[0106] Refer again Figure 3 A portion of the removed first isolation structure 101a can be reformed. Then, a portion of the gap-filling layer GF and the semiconductor pattern SP can be removed to form a capacitor structure CAP. At this time, the first shielding structure 111a extending into the first isolation structure 101a can prevent material forming the capacitor structure CAP from permeating from the cell array region CER to the extended region EXR through the gaps in the first isolation structure 101a.

[0107] Figure 18 This is a plan view showing the cell array region of a three-dimensional semiconductor device according to some embodiments of the disclosed concept. Figure 19 It is based on some embodiments of the disclosed concept. Figure 18 The cross-sectional view of the line DD′. Figure 20 It is based on some embodiments of the disclosed concept. Figure 18 The cross-sectional view of the line EE′.

[0108] Reference Figures 18 to 20 The three-dimensional semiconductor device according to some embodiments of the disclosed concept may further include a pad LE surrounding the lower and side surfaces of each of the first shielding structure 111a and the second shielding structure 111b. A portion of the pad LE may be disposed between the isolation structure 101 and the shielding structure 111. The lower portion of the pad LE may contact the substrate 100. That is, the remaining portion of the pad LE may be disposed between the substrate 100 and the shielding structure 111. Figure 18 As shown, the pad LE can also be placed on the side of the bit line BL.

[0109] The pad LE may comprise the same material as the first isolation structure 101a and the second isolation structure 101b. As an example, the pad LE may comprise silicon oxide.

[0110] According to Figures 18 to 20 In the case of a three-dimensional semiconductor device, as described above Figure 11 and Figure 12In the process, prior to the process of forming the shielding structure 111, the device can be formed by depositing silicon oxide on the inner wall of the exposed isolation structure 101 and the surface of the substrate 100.

[0111] The three-dimensional semiconductor device according to embodiments of the disclosed concept may include an isolation structure disposed between semiconductor patterns and a shielding structure penetrating the isolation structure. Here, the shielding structure is disposed between the cell array region and the extended region, and may include a material with an etch selectivity different from that of the isolation structure.

[0112] As a result, the shielding structure can prevent material from components formed on the cell array region from penetrating into the extended region, or vice versa, during the fabrication process of a three-dimensional semiconductor device. Consequently, the reliability of the fabrication process for three-dimensional semiconductor devices is improved, and the electrical characteristics of the three-dimensional semiconductor device can be improved and ensured.

[0113] While embodiments of the invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the invention can be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims

1. A three-dimensional semiconductor device, comprising: The substrate includes a cell array region and an extended region; A semiconductor pattern disposed on the cell array region of the substrate and extending along a first direction substantially parallel to the upper surface of the substrate; Word lines that surround the semiconductor pattern and extend in a second direction that is substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction; An isolation structure that extends along the second direction over the cell array region and the extended region; as well as A shielding structure that penetrates the isolation structure. The isolation structure is disposed between the semiconductor patterns on the cell array region, and The isolation structure and the shielding structure each comprise different materials.

2. The three-dimensional semiconductor device according to claim 1, wherein: The isolation structure comprises silicon oxide, and The shielding structure comprises silicon nitride.

3. The three-dimensional semiconductor device according to claim 1, further comprising a gate connection line located on the extended region. in, At least a portion of the shielding structure overlaps with the gate connection line in the first direction.

4. The three-dimensional semiconductor device according to claim 1, wherein, The shielding structure has stripes extending along the second direction in the plan view.

5. The three-dimensional semiconductor device according to claim 1, wherein, The shielding structure extends through the isolation structure and into the substrate.

6. The three-dimensional semiconductor device of claim 1, further comprising a capacitor structure connected to at least one of the semiconductor patterns. in, The shielding structure overlaps with the remaining semiconductor pattern of the semiconductor pattern that is not connected to the capacitor structure in the first direction in the plan view.

7. The three-dimensional semiconductor device according to claim 6, in, The capacitor structure, positioned closest to the extended region, is placed further away from the extended region in the plan view than the end of the shielding structure located on the cell array region.

8. The three-dimensional semiconductor device according to claim 1, in: Multiple isolation structures and shielding structures are provided to be spaced apart in the first direction, and One end of each of the shielding structures is aligned in the first direction.

9. The three-dimensional semiconductor device of claim 1, further comprising a bit line connected to one end of each of the semiconductor patterns. in: The bit line extends along a third direction substantially perpendicular to the upper surface of the substrate, and The shielding structure is configured to be spaced apart from the bit line.

10. A three-dimensional semiconductor device, comprising: The substrate includes a cell array region and an extended region; A semiconductor pattern disposed on the cell array region of the substrate and extending along a first direction substantially parallel to the upper surface of the substrate; Word lines that surround the semiconductor pattern and extend in a second direction that is substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction; A capacitor structure, located on one side of each of the semiconductor patterns; Bit lines, which are on the other side of each of the semiconductor patterns; An isolation structure that extends along the second direction over the cell array region and the extended region; as well as A shielding structure that penetrates the isolation structure. In this configuration, at least a portion of the shielding structure overlaps with the extended region in the plan view.

11. The three-dimensional semiconductor device according to claim 10, in: The isolation structure comprises silicon oxide, and The shielding structure comprises silicon nitride.

12. The three-dimensional semiconductor device according to claim 10, in: The isolation structure includes a first isolation structure and a second isolation structure spaced apart from each other in the first direction. The shielding structure includes a first shielding structure that penetrates the first isolation structure and a second shielding structure that penetrates the second isolation structure, and The first isolation structure is disposed between capacitors spaced apart along the first direction.

13. The three-dimensional semiconductor device according to claim 12, wherein, A portion of the first shielding structure overlaps with the word line in the first direction.

14. The three-dimensional semiconductor device according to claim 12, wherein, The second shielding structure overlaps with the bit line along the second direction.

15. The three-dimensional semiconductor device according to claim 12, wherein, One end of the first shielding structure is placed closer to the capacitor structure than one end of the second shielding structure.

16. A three-dimensional semiconductor device, comprising: The substrate includes a cell array region and an extended region; A semiconductor pattern extending along a first direction substantially parallel to the upper surface of the substrate; Word lines that surround the semiconductor pattern and extend in a second direction that is substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction; Bit lines extend along a third direction substantially perpendicular to the upper surface of the substrate on a first edge portion of the semiconductor pattern; A capacitor structure located on the second edge portion of the semiconductor pattern; An isolation structure that extends along the second direction over the cell array region and the extended region; as well as A shielding structure that penetrates the isolation structure. in: The isolation structure includes a first isolation structure disposed adjacent to the first edge portion of the semiconductor pattern and a second isolation structure disposed adjacent to the second edge portion of the semiconductor pattern. The shielding structure includes a first shielding structure extending into the first isolation structure and a second shielding structure extending into the second isolation structure, and The first isolation structure and the second isolation structure each include a material having an etch selectivity that is different from that of the first shielding structure and the second shielding structure.

17. The three-dimensional semiconductor device according to claim 16, in: The first shielding structure extends along the second direction over the cell array region and the extended region, and The second shielding structure extends along the second direction in the extended region in the plan view.

18. The three-dimensional semiconductor device of claim 16, further comprising pads surrounding the side surfaces and lower surfaces of the first shielding structure and the second shielding structure.

19. The three-dimensional semiconductor device according to claim 16, wherein, One end of the first shielding structure and one end of the second shielding structure are aligned in the first direction.

20. The three-dimensional semiconductor device of claim 18, further comprising a connection structure located on the extended region. in: The connection structure includes a plurality of gate connection lines and an interlayer insulating layer alternately stacked on the substrate. One end of the first shielding structure is located between the capacitor structure and the gate connection line, and The other end of the first shielding structure overlaps with the gate connection line in the first direction in the plan view.

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