Semiconductor device including etch stop layer

Abstract

A semiconductor device can include a polish stop layer, an etch stop layer on an upper surface of the polish stop layer, a semiconductor pattern on an upper surface of the etch stop layer, the semiconductor pattern extending in a first direction, a word line on at least a portion of an upper surface or a lower surface of the semiconductor pattern, the word line extending in a second direction that intersects the first direction, a bit line extending in a third direction that intersects the first and second directions and connected to a first end of the semiconductor pattern, and a data storage element connected to a second end of the semiconductor pattern opposite the first end. An insulating material of the polish stop layer can be different from an insulating material of the etch stop layer.

Description

Cross-references to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0056484, filed on April 29, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Some embodiments of this disclosure relate to a semiconductor device. Background Technology

[0003] Technologies are being developed to increase the integration density of semiconductor devices. For two-dimensional semiconductor memory devices, the integration density can be primarily determined by the area occupied by a single memory cell, and this aspect of the integration density is influenced by the level of fine patterning technology.

[0004] However, the integration density of two-dimensional semiconductor devices is increasing, but still limited, because fine patterning techniques may require expensive equipment. Therefore, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0005] According to some embodiments of this disclosure, a semiconductor device with improved reliability can be provided.

[0006] According to some embodiments of this disclosure, a semiconductor device with improved electrical performance can be provided.

[0007] According to some embodiments of this disclosure, a semiconductor device may include: a polishing stop layer; an etch stop layer located on an upper surface of the polishing stop layer; a semiconductor pattern located on the upper surface of the etch stop layer, the semiconductor pattern extending in a first direction; a word line located on at least a portion of the upper or lower surface of the semiconductor pattern, the word line extending in a second direction intersecting the first direction; a bit line extending upward in a third direction intersecting the first and second directions and connected to a first end of the semiconductor pattern; and a data storage element connected to a second end of the semiconductor pattern opposite to the first end, wherein the insulating material of the polishing stop layer is different from the insulating material of the etch stop layer.

[0008] According to some embodiments of this disclosure, a semiconductor device may include: a cell structure; and a peripheral circuit structure located on an upper surface of the cell structure, wherein the cell structure includes: a polishing stop layer comprising an insulating material; an etch stop layer located on the upper surface of the polishing stop layer, the etch stop layer comprising an insulating material different from the insulating material of the polishing stop layer; a semiconductor pattern located on the upper surface of the etch stop layer and extending in a first direction; word lines located on at least a portion of the upper or lower surface of the semiconductor pattern, the word lines extending in a second direction intersecting the first direction; bit lines extending upward in a third direction intersecting the first and second directions and connected to a first end of the semiconductor pattern; a data storage element connected to a second end of the semiconductor pattern opposite to the first end; and a cell wiring structure located on the bit lines and connected to the word lines, and wherein the peripheral circuit structure includes: a peripheral substrate; a peripheral circuit wiring layer located on the peripheral substrate and connected to the cell wiring structure; and a peripheral circuit located between the peripheral circuit wiring layer and the peripheral substrate and connected to the peripheral circuit wiring layer.

[0009] According to some embodiments of this disclosure, a semiconductor device may include: a first unit structure; a second unit structure located on an upper surface of the first unit structure; and a peripheral circuit structure located on the upper surface of the second unit structure, wherein each of the first unit structure and the second unit structure includes: an etch stop layer comprising an insulating material; a semiconductor pattern located on the upper surface of the etch stop layer and extending in a first direction; a word line located on at least a portion of the upper or lower surface of the semiconductor pattern, the word line extending in a second direction intersecting the first direction; a bit line extending upward in a third direction intersecting the first and second directions and connected to a first end of the semiconductor pattern; and a data storage element, which The second cell structure is connected to a second end opposite to the first end of the semiconductor pattern. The first cell structure further includes a polishing stop layer located below the etch stop layer of the first cell structure. The polishing stop layer includes an insulating material different from the insulating material of the etch stop layer of the first cell structure. The second cell structure further includes a cell wiring structure located on the bit lines of the second cell structure and connected to the word lines of the first and second cell structures. The peripheral circuit structure includes: a peripheral substrate; a peripheral circuit wiring layer located on the peripheral substrate and connected to the cell wiring structure of the second cell structure; and a peripheral circuit located between the peripheral circuit wiring layer and the peripheral substrate and connected to the peripheral circuit wiring layer. Attached Figure Description

[0010] Figure 1 This is a plan view of a semiconductor device according to an embodiment.

[0011] Figure 2 It is along Figure 1 A cross-sectional view taken from line A–A'.

[0012] Figure 3 It is along Figure 1 The cross-sectional view taken by line B–B'.

[0013] Figures 4 to 8 This is a diagram used to explain a method of manufacturing a semiconductor device according to an embodiment.

[0014] Figure 9 and Figure 10 This is a cross-sectional view of a semiconductor device according to other embodiments.

[0015] Figures 11 to 21 This is a diagram illustrating a method of manufacturing a semiconductor device according to other embodiments. Detailed Implementation

[0016] In the following, various non-limiting exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the embodiments of the present disclosure. Embodiments of the present disclosure may be implemented in many different forms and are not limited to the exemplary embodiments described herein.

[0017] To clearly explain various aspects of this disclosure, parts irrelevant to the description may be omitted, and throughout the specification, the same reference numerals are used for the same or similar parts.

[0018] Furthermore, for ease of explanation, the dimensions and thicknesses of each component shown in the accompanying drawings may be arbitrarily depicted, and therefore this disclosure is not limited to what is shown. Thicknesses may be enlarged to clearly illustrate the various layers and regions in the drawings. And in the drawings, the thicknesses of some layers and regions may be exaggerated for ease of explanation.

[0019] Furthermore, when a portion such as a layer, membrane, region, or plate is described as being "above" or "on" another portion, this includes not only the case where it is "directly above" said other portion, but also the case where other portions exist in between. Conversely, when a portion is described as being "directly above" another portion, there are no other portions in between. Additionally, "above" a reference portion means being located above or below that reference portion, and does not necessarily mean being "above" in a direction opposite to gravity.

[0020] Furthermore, whenever a part is described as "including" a component throughout the specification, unless otherwise expressly stated, this does not mean that it excludes other components, but rather that it may include other components.

[0021] Additionally, throughout the instruction manual, "in a plan view" means when viewing the target portion from above, and "in a cross-section" means when viewing the target portion from the side in a vertically cut cross-section.

[0022] Figure 1 This is a plan view of a semiconductor device according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 3 It is along Figure 1 The cross-sectional view taken by line B-B'. (Refer to...) Figures 1 to 3 The semiconductor device described according to the embodiments may be included Figure 9 and Figure 10 In the unit structure CS, the first unit structure CS1, and the second unit structure CS2.

[0023] Reference Figures 1 to 3 The semiconductor device according to the embodiment may include a polishing stop layer 110, an etch stop layer 120, a bit line BL, a semiconductor pattern SP, a word line WL, and a data storage element DS.

[0024] The semiconductor device according to the embodiment may not include Figures 4 to 7 The substrate 100. During the process of manufacturing a semiconductor device according to the embodiment, the substrate 100 may be removed. For example, the substrate 100 may be removed by a polishing process. The polishing stop layer 110 may be used as a stop layer in the polishing process for removing the substrate 100.

[0025] The polishing stop layer 110 may have a shape extending in a first direction DR1 and a second direction DR2. The polishing stop layer 110 may have an upper surface parallel to the first direction DR1 and the second direction DR2. Here, the second direction DR2 may be a direction intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. The upper surface of the polishing stop layer 110 may have a flat shape.

[0026] The polishing stop layer 110 may include an insulating material. For example, the polishing stop layer 110 may include, but is not limited to, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon oxycarbonitrile (SiOCN).

[0027] The etch stop layer 120 may be located on the polishing stop layer 110. The etch stop layer 120 may have a shape extending in a first direction DR1 and a second direction DR2. The etch stop layer 120 may have an upper surface parallel to the first direction DR1 and the second direction DR2. The upper surface of the etch stop layer 120 may have a flat shape.

[0028] The etch stop layer 120 may include an insulating material. For example, the etch stop layer 120 may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiOC), silicon oxynitride (SiON), silicon carbonitride (SiOCN), hafnium oxide (HfO2), zirconium oxide (ZrO2), and beryllium oxide (BeO).

[0029] The polishing stop layer 110 and the etching stop layer 120 may comprise insulating materials that are different from each other. The polishing stop layer 110 and the etching stop layer 120 may comprise materials that have different etching rates under the same conditions. For example, the polishing stop layer 110 may comprise at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon carbonitride (SiOCN), hafnium oxide (HfO2), zirconium oxide (ZrO2), and beryllium oxide (BeO).

[0030] Bit line BL can be located on etch stop layer 120. Bit line BL can have the form of extending on a third direction DR3. The third direction DR3 can be a direction that intersects with the first direction DR1 and the second direction DR2. For example, the third direction DR3 and the first direction DR1 can be orthogonal to each other, and the third direction DR3 and the second direction DR2 can be orthogonal to each other. For example, the third direction DR3 can be a direction perpendicular to the upper surface of etch stop layer 120.

[0031] Bit line BL may contact etch stop layer 120. The lower surface of bit line BL may contact the upper surface of etch stop layer 120. The lower surface of bit line BL may be located at the same level as the upper surface of etch stop layer 120 on third-direction DR3.

[0032] Bit line BL can be connected to multiple semiconductor patterns SP on opposite sides of bit line BL in a first direction DR1. The multiple semiconductor patterns SP can be positioned such that they are spaced apart from each other in a third direction DR3 on opposite sides of bit line BL in the first direction DR1. Bit line BL can be connected to one side of semiconductor pattern SP. Here, one side of semiconductor pattern SP can mean the side of semiconductor pattern SP connected to bit line BL, and the opposite side of semiconductor pattern SP can mean the side of semiconductor pattern SP connected to data storage element DS. Semiconductor pattern SP can be located between data storage element DS and bit line BL. Semiconductor pattern SP can be located between data storage element DS and bit line BL in the first direction DR1. For example, one side of semiconductor pattern SP can be referred to as the first side, and the opposite side of semiconductor pattern SP can be referred to as the second side.

[0033] Bit line BL can be positioned to overlap with semiconductor pattern SP in the first direction DR1. Bit line BL can be positioned not to overlap with semiconductor pattern SP in the second direction DR2, but is not limited thereto. For example, bit line BL can overlap with at least one end of semiconductor pattern SP in the second direction DR2.

[0034] One side of the bit line BL may contact, but is not limited to, the interlayer dielectric layer ILD and the second spacer 216 located between multiple semiconductor patterns SP on the third-direction DR3. For example, in some embodiments, additional insulating patterns may be arranged, or the interlayer dielectric layer ILD and the second spacer 216 may be formed from a single insulating pattern.

[0035] Multiple bit lines BL can be located on the etch stop layer 120. The multiple bit lines BL can be positioned spaced apart in a first direction DR1. Additionally, the multiple bit lines BL can be positioned spaced apart in a second direction DR2. Multiple semiconductor patterns SP, multiple word lines WL, and multiple data storage elements DS can be located between the multiple bit lines BL in the first direction DR1. A separation insulating pattern 218 can be located between the multiple bit lines BL in the second direction DR2.

[0036] Bit lines BL can include conductive materials. For example, bit lines BL can include doped semiconductor materials (such as doped silicon (Si) or doped germanium (Ge)), conductive metal nitrides (such as titanium nitride (TiN) or tantalum nitride (TaN)), metals (such as tungsten (W), titanium (Ti) or tantalum (Ta)) and metal semiconductor compounds (such as tungsten silicide (WSi)). x ), cobalt silicide (CoSi) x ) or titanium silicide (TiSi) x Any one of them.

[0037] The semiconductor pattern SP can be located on the etch stop layer 120. The semiconductor pattern SP can have a shape extending in the first direction DR1. For example, the semiconductor pattern SP can have a strip shape extending in the first direction DR1. The semiconductor pattern SP can be located between the bit line BL and the data storage element DS.

[0038] Here, one side of the semiconductor pattern SP can represent the side where the semiconductor pattern SP is connected to the bit line BL, and the opposite side of the semiconductor pattern SP can represent the side where the semiconductor pattern SP is connected to the data storage element DS. The semiconductor pattern SP can be located between the data storage element DS and the bit line BL. For example, one side of the semiconductor pattern SP can be referred to as the first side, and the opposite side of the semiconductor pattern SP can be referred to as the second side.

[0039] A semiconductor pattern SP can be connected to a bit line BL. One side of the semiconductor pattern SP can be connected to the bit line BL. One side of the semiconductor pattern SP can contact one side of the bit line BL. However, in some embodiments, one side of the semiconductor pattern SP can be surrounded by the bit line BL. In other words, in some embodiments, the semiconductor pattern SP can be connected to the bit line BL in a manner that partially protrudes into the bit line BL.

[0040] The opposite side of the semiconductor pattern SP can be connected to the data storage element DS. The opposite side of the semiconductor pattern SP can contact the first electrode 222 of the data storage element DS. The thickness of the semiconductor pattern SP on the third-direction DR3 can be less than the thickness of the first electrode 222 on the third-direction DR3, but is not limited thereto.

[0041] A portion of the semiconductor pattern SP may be surrounded by a word line WL. A portion of the upper surface of the semiconductor pattern SP may be covered by the word line WL. A portion of the lower surface of the semiconductor pattern SP may be covered by the word line WL. A portion of the side surface of the semiconductor pattern SP in the second direction DR2 may be covered by the word line WL. The semiconductor pattern SP may be positioned to penetrate the word line WL in the first direction DR1. A gate insulating pattern Gox may be located between the semiconductor pattern SP and the word line WL.

[0042] Multiple semiconductor patterns SP can be located on the etch stop layer 120. The multiple semiconductor patterns SP can be positioned spaced apart on a first direction DR1, a second direction DR2, and a third direction DR3. The multiple semiconductor patterns SP can be stacked and spaced apart from each other on the third direction DR3. For example, multiple semiconductor patterns SP connected to a bit line BL can be arranged to be spaced apart from each other on the third direction DR3. Additionally, multiple semiconductor patterns SP can be arranged to be spaced apart from each other on the first direction DR1 and the second direction DR2 along the bit line BL, which is arranged to be spaced apart from each other on the first direction DR1 and the second direction DR2. Bit lines BL or data storage elements DS can be located between the multiple semiconductor patterns SP on the first direction DR1. Word lines WL extending on the second direction DR2 can be located between the multiple semiconductor patterns SP on the second direction DR2. An interlayer dielectric layer ILD, an intermediate insulating layer 212, a first spacer 214, and a second spacer 216 can be located between the multiple semiconductor patterns SP on the third direction DR3.

[0043] The semiconductor pattern SP can include semiconductor materials. The semiconductor pattern SP can include oxide semiconductor materials. Oxide semiconductor materials can include materials such as IGZO (InGaZnO) and ZrO. xThe semiconductor pattern SP may include at least one selected from ZTO (ZnSnO), ITZO (InSnZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZnO, ZnON, YZO (yttrium-doped zinc oxide), InGaSiO, InO, SnO, TiO, ZnON, MgZnO, InZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, and ZrZnSnO, but is not limited thereto. In addition to at least one oxide semiconductor material selected from the above-mentioned oxide semiconductor materials, the semiconductor pattern SP may also include at least one dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H). Alternatively, the semiconductor pattern SP may include polycrystalline silicon. However, it is not limited thereto; the semiconductor pattern SP may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

[0044] A semiconductor pattern SP may include a channel region, a first impurity region, and a second impurity region. The first and second impurity regions may be regions of the semiconductor pattern SP that are doped with impurities. The first and second impurity regions may have n-type or p-type conductivity. For example, the first and second impurity regions may be located at each end of the semiconductor pattern SP in a first direction DR1. For example, the first impurity region of the semiconductor pattern SP may be connected to a bit line BL, and the second impurity region of the semiconductor pattern SP may be connected to a data storage element DS. A channel region may be located between the first and second impurity regions. The channel region of the semiconductor pattern SP may be surrounded by a word line WL.

[0045] The word line WL can be located on the semiconductor pattern SP. The word line WL can have a shape extending in the second direction DR2. For example, the word line WL can have a strip shape extending in the second direction.

[0046] For example, a word line WL can be positioned to surround a portion of a semiconductor pattern SP. The word line WL can extend in a second direction DR2 and surround a plurality of semiconductor patterns SP positioned spaced apart in the second direction DR2. The word line WL can surround at least a portion of the upper or lower surface of the semiconductor pattern SP. The word line WL can cover a portion of the upper surface of the semiconductor pattern SP. The word line WL can cover a portion of the lower surface of the semiconductor pattern SP. The word line WL can cover a portion of the side surface of the semiconductor pattern SP in the second direction DR2. The word line WL can cover the central region of the semiconductor pattern SP in the first direction DR1. The word line WL can cover the channel region located between a first impurity region and a second impurity region of the semiconductor pattern SP. The word line WL can have a form extending in the second direction DR2, and the semiconductor pattern SP can be arranged to penetrate the word line WL in the first direction DR1. In some embodiments, a pair of word lines WL can be arranged on the upper and lower surfaces of the semiconductor pattern SP, respectively.

[0047] The gate insulating pattern Gox can be located between the word line WL and the semiconductor pattern SP. The word line WL and the semiconductor pattern SP can be positioned to be separated by the gate insulating pattern Gox. The word line WL and the semiconductor pattern SP do not need to be in contact with each other.

[0048] Multiple word lines (WL) can be located on the etch stop layer 120. The multiple word lines (WL) can be positioned spaced apart from each other on a first direction DR1 and a third direction DR3. Bit lines (BL) or data storage elements (DS) can be located between the multiple word lines (WL) on the first direction DR1. An interlayer dielectric layer (ILD) can be located between the multiple word lines (WL) on the third direction DR3.

[0049] Word lines (WL) can include conductive materials. For example, word lines (WL) can include doped semiconductor materials (such as doped silicon (Si) or doped germanium (Ge)), conductive metal nitrides (such as titanium nitride (TiN) or tantalum nitride (TaN)), metals (such as tungsten (W), titanium (Ti), or tantalum (Ta)) and metal semiconductor compounds (such as tungsten silicide (WSi)). x ), cobalt silicide (CoSi) x ) or titanium silicide (TiSi) x Any one of them.

[0050] The data storage element DS can be connected to the semiconductor pattern SP. One side of the semiconductor pattern SP can be connected to the bit line BL, and the opposite side of the semiconductor pattern SP can be connected to the data storage element DS. The data storage element DS can extend in the first direction DR1.

[0051] Multiple data storage elements DS can be located on etch stop layer 120. The multiple data storage elements DS can be respectively connected to multiple semiconductor patterns SP. The multiple data storage elements DS can be positioned spaced apart from each other in a first direction DR1, a second direction DR2, and a third direction DR3. Semiconductor patterns SP and bit lines BL or plate electrodes PE can be located between the multiple data storage elements DS in the first direction DR1. Plate electrodes PE can be located between the multiple data storage elements DS in the third direction DR3. Plate electrodes PE can be located between the multiple data storage elements DS in the second direction DR2. However, the embodiments are not limited to this, and for example, the multiple data storage elements DS can be positioned continuously without being spaced apart from each other in the second direction DR2.

[0052] The data storage element DS may include a first electrode 222, a dielectric film 224, and a second electrode 226.

[0053] The first electrode 222 can be connected to the opposite side of the semiconductor pattern SP. One side of the first electrode 222 can be connected to the semiconductor pattern SP. Here, one side of the first electrode 222 can mean the side connected to the semiconductor pattern SP, and the opposite side of the first electrode 222 can mean the side positioned opposite to the side connected to the semiconductor pattern SP. The first electrode 222 can cover the opposite side of the semiconductor pattern SP. The first electrode 222 can contact the opposite side of the semiconductor pattern SP. The first electrode 222 can be located at substantially the same level as the semiconductor pattern SP in a third direction DR3. The first electrode 222 can be aligned parallel to the semiconductor pattern SP in a first direction DR1. According to some embodiments, the first electrode 222 can have a shape surrounding the opposite side of the semiconductor pattern SP.

[0054] The first electrode 222 may have a shape extending in the first direction DR1. The first electrode 222 may have a strip shape or a column shape extending in the first direction DR1, but is not limited thereto. For example, the first electrode 222 may have a cylindrical shape with a hollow center. The width of the first electrode 222 in the second direction DR2 and the thickness of the first electrode 222 in the third direction DR3 may be greater than the width of the semiconductor pattern SP in the second direction DR2 and the thickness of the semiconductor pattern SP in the third direction DR3, but is not limited thereto. For example, the width of the first electrode 222 in the second direction DR2 and the thickness of the first electrode 222 in the third direction DR3 may be substantially the same as the width of the semiconductor pattern SP in the second direction DR2 and the thickness of the semiconductor pattern SP in the third direction DR3.

[0055] Multiple first electrodes 222 may be located on the etch stop layer 120. The multiple first electrodes 222 may be respectively connected to opposite sides of multiple semiconductor patterns SP.

[0056] The first electrode 222 may include a conductive material. The first electrode 222 may include at least one of the following materials: metallic materials, such as titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), or ruthenium (Ru); conductive metal nitrides, such as titanium nitride (TiN), molybdenum nitride (MoN), vanadium nitride (VN), niobium nitride (NbN), or tantalum nitride (TaN); conductive metal oxides, such as ruthenium oxide (RuO). x ), Iridium oxide (IrO), Indium tin oxide (ITO), Molybdenum oxide (MoO) x ) and vanadium oxide (VO) x ); and doped semiconductor materials, such as doped silicon (doped Si) or doped germanium (doped Ge).

[0057] The dielectric film 224 may be located on the first electrode 222. The dielectric film 224 may be located between the first electrode 222 and the second electrode 226. The dielectric film 224 may be conformally located on the first electrode 222.

[0058] The dielectric film 224 may cover a portion of the upper surface, lower surface, and side surface of the first electrode 222. Additionally, the dielectric film 224 may cover the opposite side of the first electrode 222. Here, the opposite side of the first electrode 222 may refer to the side of the first electrode 222 opposite to the side where the first electrode 222 is connected to the semiconductor pattern SP.

[0059] Multiple data storage elements DS, positioned as spaced apart on a third-party DR3, can share a dielectric film 224.

[0060] The dielectric film 224 may be located on the intermediate insulating layer 212. The dielectric film 224 may be located on one side of the intermediate insulating layer 212 in the first direction DR1. The dielectric film 224 may be conformally located on the intermediate insulating layer 212 and the first electrode 222. Here, the intermediate insulating layer 212 may be positioned to cover the opposite side of the semiconductor pattern SP.

[0061] In one embodiment, the dielectric film 224 may extend on the third-direction DR3 to cover the side surface of the first connection pad 251 located on the plate electrode PE.

[0062] The dielectric film 224 may include an insulating material. The dielectric film 224 may include a silicon oxide film, a silicon nitride film, a high-k dielectric film having a dielectric constant higher than that of a silicon oxide film, or a combination thereof. Here, the high-k dielectric film may be made of a metal oxide or a metal nitride. For example, high-k dielectric films that can be used as dielectric film 224 may include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof.

[0063] The second electrode 226 may be located on the dielectric film 224. The second electrode 226 may be conformally located on the dielectric film 224. The second electrode 226 may be located in the space between a plurality of first electrodes 222 spaced apart on the third-direction DR3. A plurality of data storage elements DS positioned spaced apart on the third-direction DR3 may share a single second electrode 226.

[0064] In one embodiment, the second electrode 226 may extend on the third-direction DR3 to cover the side surface of the first connection pad 251 located on the plate electrode PE.

[0065] The second electrode 226 may include a conductive material. The second electrode 226 may include at least one of the following materials: metallic materials, such as titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), or ruthenium (Ru); conductive metal nitrides, such as titanium nitride (TiN), molybdenum nitride (MoN), vanadium nitride (VN), niobium nitride (NbN), or tantalum nitride (TaN); conductive metal oxides, such as ruthenium oxide (RuO). x ), Iridium oxide (IrO), Indium tin oxide (ITO), Molybdenum oxide (MoO) x ) and vanadium oxide (VO) x ); and doped semiconductor materials, such as doped silicon (doped Si) or doped germanium (doped Ge).

[0066] The semiconductor device according to the embodiment may further include an interlayer dielectric layer (ILD), a gate insulating pattern (Gox), an intermediate insulating layer (212), a first spacer (214), a second spacer (216), a separation insulating pattern (218), a plate electrode (PE), a shielding layer (230), an upper insulating layer (240), a first connection pad (251), and a second connection pad (252).

[0067] An interlayer dielectric layer (ILD) can be located on a third-direction DR3 between multiple semiconductor patterns (SPs). The ILD can be located on word lines (WLs). The ILD can be positioned to contact word lines (WLs). The ILD can be located on a first spacer 214. One end of the ILD can be surrounded by the first spacer 214. The ILD can be located on a second spacer 216. Opposite ends of the ILD can be surrounded by the second spacer 216. The ILD can be located between the first spacer 214 and a bit line (BL). For example, one side of the ILD can contact the bit line (BL), and the opposite side of the ILD can contact the first spacer 214.

[0068] The interlayer dielectric layer (ILD) may include an insulating material. By way of example, the interlayer dielectric layer (ILD) may include, but is not limited to, at least one of silicon oxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiON).

[0069] A gate insulating pattern Gox can be placed between a word line WL and a semiconductor pattern SP. The semiconductor pattern SP and the word line WL can be arranged to be spaced apart on a third direction DR3, with the gate insulating pattern Gox interposed between the semiconductor pattern SP and the word line WL. The gate insulating pattern Gox can contact the semiconductor pattern SP. The gate insulating pattern Gox can also be located between the first spacer 214 and the semiconductor pattern SP. The gate insulating pattern Gox can cover a portion of the upper surface of the semiconductor pattern SP. The gate insulating pattern Gox can cover a portion of the lower surface of the semiconductor pattern SP. The gate insulating pattern Gox can cover a portion of the side surface of the semiconductor pattern SP on the second direction DR2. The gate insulating pattern Gox can cover the central region of the semiconductor pattern SP on the first direction DR1. The gate insulating pattern Gox can cover the channel region located between the first impurity region and the second impurity region of the semiconductor pattern SP.

[0070] Additionally, in some embodiments, the gate insulating pattern Gox may also be located between the word line WL and the second spacer 216. For example, the gate insulating pattern Gox may have an "L" shape in a cross-section along the first direction DR1 and the third direction DR3, but is not limited thereto. For example, the gate insulating pattern Gox may have a strip shape extending along the semiconductor pattern SP in a cross-section along the first direction DR1 and the third direction DR3.

[0071] The gate insulating pattern Gox may include an insulating material. The gate insulating pattern Gox may include a silicon oxide film, a silicon oxynitride film, a high-k film having a dielectric constant higher than that of the silicon oxide film, or a combination thereof. Here, the high-k dielectric film may be made of a metal oxide or a metal oxynitride. For example, high-k dielectric films that can be used as the gate insulating pattern Gox may include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof.

[0072] The intermediate insulating layer 212 may cover the opposite side of the semiconductor pattern SP. The semiconductor pattern SP may be positioned to penetrate the intermediate insulating layer 212 in the first direction DR1. The intermediate insulating layer 212 may be located between the first spacer 214 and the data storage element DS. The intermediate insulating layer 212 may be located between the first spacer 214 and the dielectric film 224. Alternatively, the intermediate insulating layer 212 may also be located between the first spacer 214 and the semiconductor pattern SP. Furthermore, by way of example, the intermediate insulating layer 212 may have a "U" shape in a cross-section along the first direction DR1 and the third direction DR3, but is not limited thereto.

[0073] The first spacer 214 may be located between the word line WL and the data storage element DS. The first spacer 214 may be located between the intermediate insulating layer 212 and the word line WL. The first spacer 214 may be located between the intermediate insulating layer 212 and the interlayer dielectric layer ILD. The first spacer 214 may have the form of a portion surrounding the semiconductor pattern SP located between the word line WL and the data storage element DS.

[0074] The second spacer 216 may be located between the word line WL and the bit line BL. The second spacer 216 may have the form of a portion surrounding the semiconductor pattern SP located between the word line WL and the bit line BL. The second spacer 216 may surround one side of the semiconductor pattern SP. The gate insulating pattern Gox may be located between the second spacer 216 and the semiconductor pattern SP.

[0075] The first spacer 214 and the second spacer 216 can be located on opposite sides of the word line WL in the first direction DR1.

[0076] The intermediate insulating layer 212, the first spacer 214, and the second spacer 216 may comprise insulating materials. The intermediate insulating layer 212, the first spacer 214, and the second spacer 216 may comprise the same insulating material as each other. Alternatively, at least one of the intermediate insulating layer 212, the first spacer 214, and the second spacer 216 may comprise different insulating materials. For example, the intermediate insulating layer 212, the first spacer 214, and the second spacer 216 may comprise, but is not limited to, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbide (SiOC), and silicon oxynitride (SiON). The intermediate insulating layer 212, the first spacer 214, and the second spacer 216 may be formed independently.

[0077] The separation insulating pattern 218 may be located on the etch stop layer 120. The separation insulating pattern 218 may be in contact with the etch stop layer 120. The lower surface of the separation insulating pattern 218 may be located at the same level as the upper surface of the etch stop layer 120 on the third direction DR3. The separation insulating pattern 218 may be located between multiple bit lines BL spaced apart on the second direction DR2. The multiple bit lines BL may be electrically isolated from each other by the separation insulating pattern 218.

[0078] The upper surface of the separation insulation pattern 218 may be located above the upper surface of the bit line BL on the third-direction DR3, but is not limited thereto. For example, the upper surface of the separation insulation pattern 218 may be located at the same level as the upper surface of the bit line BL on the third-direction DR3. The upper surface of the separation insulation pattern 218 may be located at the same level as the upper surface of the shielding layer 230 on the third-direction DR3, but is not limited thereto. For example, the upper surface of the separation insulation pattern 218 may be located above the upper surface of the shielding layer 230. The separation insulation pattern 218 may have a form that extends on the third-direction DR3.

[0079] The plate electrode PE can be located on the etch stop layer 120. The plate electrode PE can be in contact with the etch stop layer 120. The lower surface of the plate electrode PE can be located at the same level as the upper surface of the etch stop layer 120 on the third-direction DR3.

[0080] A plate electrode PE may cover a data storage element DS. One plate electrode PE may cover multiple data storage elements DS. The plate electrode PE may cover a second electrode 226. The plate electrode PE may contact multiple second electrodes 226. The plate electrode PE may be located between multiple data storage elements DS spaced apart in a third direction DR3. The plate electrode PE may fill the space between multiple data storage elements DS positioned spaced apart in a third direction DR3. The plate electrode PE may be positioned spaced apart in a first direction DR1 and may be located between multiple data storage elements DS facing each other. The plate electrode PE may be positioned spaced apart in the first direction DR1 and may fill the space between multiple data storage elements DS facing each other. In some embodiments, the plate electrode PE may be considered as a component of the data storage element DS.

[0081] Shielding layer 230 may be located above multiple semiconductor patterns SP stacked on the third-direction DR3. Shielding layer 230 may be located above the uppermost semiconductor pattern SP. Shielding layer 230 may be located above multiple word lines WL stacked on the third-direction DR3. Shielding layer 230 may be located above the uppermost word line WL. Shielding layer 230 may be located on a data storage element DS stacked on the third-direction DR3. Shielding layer 230 may be located above a bit line BL. The lower surface of shielding layer 230 may be located at the same level as the upper surface of bit line BL on the third-direction DR3. Shielding layer 230 may be located on interlayer dielectric layers ILD spaced apart on the third-direction DR3. Shielding layer 230 may be located above the uppermost interlayer dielectric layer ILD spaced apart on the third-direction DR3.

[0082] The shielding layer 230 may have a shape extending in the first direction DR1. The shielding layer 230 may cover the side surfaces of the first connection pad 251 and the second connection pad 252. Additional insulating layers may be located between the shielding layer 230 and the first connection pad 251, and between the shielding layer 230 and the second connection pad 252. Figure 2 In the diagram, the lower surface of the shielding layer 230 and the upper surface of the uppermost interlayer dielectric layer ILD are shown in contact, but this is not a limitation. For example, other components may be additionally placed between the lower surface of the shielding layer 230 and the interlayer dielectric layer ILD.

[0083] The shielding layer 230 may include a semiconductor material. The shielding layer 230 may include, but is not limited to, polysilicon. For example, the shielding layer 230 may include an oxide semiconductor material. The oxide semiconductor material may include at least one selected from the following materials: IGZO (InGaZnO), ZrO xThe shielding layer 230 may include, but is not limited to, at least one oxide semiconductor material selected from the above-mentioned oxide semiconductor materials, such as ZTO (ZnSnO), ITZO (InSnZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZnO, ZnON, YZO (yttrium-doped zinc oxide), InGaSiO, InO, SnO, TiO, ZnON, MgZnO, InZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, and ZrZnSnO. In addition to at least one oxide semiconductor material selected from the above-mentioned oxide semiconductor materials, the shielding layer 230 may also include at least one dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H). Alternatively, the shielding layer 230 may include an insulating material, such as silicon oxide (SiO2) and silicon nitride (SiN).

[0084] The upper insulating layer 240 may be located on the shielding layer 230. Additionally, the upper insulating layer 240 may be located on the separate insulating pattern 218. The upper insulating layer 240 may cover the side surfaces of the first connection pad 251 and the second connection pad 252. The upper insulating layer 240 may include an insulating material. For example, the upper insulating layer 240 may include insulating materials such as, but not limited to, silicon oxide (SiO2) and silicon nitride (SiN).

[0085] exist Figure 2 In this diagram, the upper insulating layer 240 is shown as a single layer, but is not limited thereto. For example, the upper insulating layer 240 may comprise two or more insulating layers.

[0086] The second connection pad 252 may be located on the bit line BL. The first connection pad 251 may be located on the board electrode PE. The first connection pad 251 and the second connection pad 252 may be positioned to penetrate the shielding layer 230 and the upper insulating layer 240. The side surface of each of the plurality of first connection pads 251 may be covered by a dielectric film 224 and a second electrode 226. The dielectric film 224 and the second electrode 226 extending in the third direction DR3 may also be located between the first connection pad 251 and the shielding layer 230. In addition, the dielectric film 224 and the second electrode 226 may also be located between the first connection pad 251 and the upper insulating layer 240. The second connection pad 252 may be positioned along a plurality of bit lines BL that are positioned spaced apart in the second direction DR2.

[0087] The width of the second connection pad 252 in the second direction DR2 can be substantially the same as or similar to the width of the bit line BL in the second direction DR2. The upper surfaces of the first connection pad 251 and the second connection pad 252 can be located at the same level as the upper surface of the upper insulating layer 240 in the third direction DR3. According to some embodiments, an additional insulating layer can be located between the second connection pad 252 and the shielding layer 230.

[0088] The first connection pad 251 and the second connection pad 252 may include conductive materials. The first connection pad 251 and the second connection pad 252 may include at least one of the following materials: metallic materials, such as titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), or ruthenium (Ru); conductive metal nitrides, such as titanium nitride (TiN), molybdenum nitride (MoN), vanadium nitride (VN), niobium nitride (NbN), or tantalum nitride (TaN); conductive metal oxides, such as ruthenium oxide (RuO). x ), Iridium oxide (IrO), Indium tin oxide (ITO), Molybdenum oxide (MoO) x ) and vanadium oxide (VO) x ); and doped semiconductor materials, such as doped silicon (doped Si) or doped germanium (doped Ge).

[0089] Figures 4 to 8 This is a diagram used to explain a method of manufacturing a semiconductor device according to an embodiment.

[0090] Reference Figure 4 A polishing stop layer 110 may be formed on the substrate 100. An etch stop layer 120 may be formed on the polishing stop layer 110. For example, the polishing stop layer 110 and the etch stop layer 120 may be formed by deposition methods, but are not limited thereto. The substrate 100 may be referred to as a unit substrate, but may be removed in a later process.

[0091] Semiconductor material layer 310 and insulating material layer 320 can be alternately and repeatedly stacked on third-direction DR3 on etch stop layer 120. The thickness of semiconductor material layer 310 on third-direction DR3 can be greater than the thickness of insulating material layer 320 on third-direction DR3, but is not limited thereto.

[0092] For example, a semiconductor material layer 310 and an insulating material layer 320 can be formed on the etch stop layer 120 by a deposition method. For example, the semiconductor material layer 310 and the insulating material layer 320 can be formed by any of the atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD) methods, but are not limited thereto.

[0093] The semiconductor material layer 310 may include a semiconductor material. For example, the semiconductor material layer 310 may include polycrystalline silicon. However, the embodiments are not limited thereto, and the semiconductor material layer 310 may include materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), and oxide semiconductors. Here, the oxide semiconductor material may be formed from at least one material selected from: IGZO (InGaZnO), ZrO x ZTO (ZnSnO), ITZO (InSnZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZnO, ZnON, YZO (yttrium-doped zinc oxide), InGaSiO, InO, SnO, TiO, ZnON, MgZnO, InZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, and ZrZnSnO, but not limited to these. In addition to at least one oxide semiconductor material selected from the above-mentioned oxide semiconductor materials, the semiconductor material layer 310 may also include at least one dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H).

[0094] The insulating material layer 320 may include an insulating material. The insulating material layer 320 may include silicon oxide (SiO2). However, it is not limited to this, and the insulating material layer 320 may include other insulating materials such as silicon nitride (SiN), silicon oxynitride (SiON), etc.

[0095] The semiconductor material layer 310 and the insulating material layer 320 may comprise materials that are different from each other. The semiconductor material layer 310 and the insulating material layer 320 may comprise materials that have different etch rates under the same conditions. The semiconductor material layer 310 and the insulating material layer 320 may have different etch rates, and the insulating material layer 320 may be selectively removed in subsequent processes.

[0096] Next, refer to Figure 5 An upper insulating layer 240 can be formed on the uppermost semiconductor material layer 310, and a plurality of capping insulating layers 330 spaced apart in the first direction DR1 can be formed on the etch stop layer 120.

[0097] First, an upper insulating layer 240 can be formed on the uppermost semiconductor material layer 310 of the semiconductor material layer 310.

[0098] Next, the upper insulating layer 240, the semiconductor material layer 310, and the insulating material layer 320 can be patterned to form a plurality of first trenches TRC1 spaced apart in the first direction DR1 and having a depth in the third direction DR3. A portion of the upper surface of the etch stop layer 120 can be exposed by the plurality of first trenches TRC1. Subsequently, a capping insulating layer 330 comprising an insulating material can be formed within the plurality of first trenches TRC1. Here, according to some embodiments, an isolation pattern having a shape extending in the first direction DR1 can be located between the plurality of capping insulating layers 330 in the second direction DR2.

[0099] Multiple capping insulating layers 330 can be positioned spaced apart from each other in a first direction DR1. Additionally, multiple capping insulating layers 330 can be positioned spaced apart from each other in a second direction DR2. An upper insulating layer 240, a semiconductor material layer 310, and an insulating material layer 320 can be located between the multiple capping insulating layers 330 in the first direction DR1. An isolation pattern and an upper insulating layer 240 can be located between the multiple capping insulating layers 330 in the second direction DR2. The upper surface of the capping insulating layer 330 can be located at the same level as the upper surface of the upper insulating layer 240 in a third direction DR3, but is not limited thereto.

[0100] Next, refer to Figure 6 This allows for the removal of some of the multiple capping insulating layers 330. It also allows for the formation of an initial semiconductor pattern SP_P, a data storage element DS, a plate electrode PE, and a first connection pad 251.

[0101] First, among the plurality of capping insulating layers 330 spaced apart and arranged along the first direction DR1, capping insulating layers 330 positioned at every other location can be removed. For example, capping insulating layers 330 located at odd-numbered positions on the first direction DR1 can be removed. As another example, capping insulating layers 330 located at even-numbered positions on the first direction DR1 can be removed.

[0102] Next, the capping insulating layer 330 can be removed to expose the semiconductor material layer 310 and the insulating material layer 320 to the outside, and the insulating material layer 320 can be selectively removed. In this process, the isolation pattern that isolates the semiconductor material layer 310 on the second direction DR2 can also be removed.

[0103] Next, a thinning process can be performed to remove a portion of the semiconductor material layer 310 to form an initial semiconductor pattern SP_P. Through the thinning process, the semiconductor material layer 310 can be replaced with the initial semiconductor pattern SP_P by reducing at least one of its length in the first direction DR1, its width in the second direction DR2, and its thickness in the third direction DR3. In some embodiments, the thinning process of the semiconductor material layer 310 can be omitted. Multiple initial semiconductor patterns SP_P may have a shape extending from the capping insulating layer 330 in the first direction DR1.

[0104] Next, a first initial insulating layer 334 can be formed such that the first initial insulating layer 334 surrounds the capping insulating layer 330 and the opposite side surfaces of the plurality of initial semiconductor patterns SP_P in the first direction DR1.

[0105] Next, a portion of the initial semiconductor pattern SP_P and the first initial insulating layer 334 can be removed. Specifically, the ends of the initial semiconductor pattern SP_P covered by the first initial insulating layer 334 and the portions of the first initial insulating layer 334 covering the ends of the initial semiconductor pattern SP_P can be removed. In this process, the portion of the first initial insulating layer 334 overlapping the removed portion of the initial semiconductor pattern SP_P on the third direction DR3 can be retained. Furthermore, in this process, the length of the initial semiconductor pattern SP_P on the first direction DR1 can be shortened.

[0106] Next, a plurality of first electrodes 222 can be formed such that the plurality of first electrodes 222 are respectively connected to the ends of a plurality of initial semiconductor patterns SP_P, and a dielectric film 224 and a second electrode 226 can be formed sequentially such that the dielectric film 224 and the second electrode 226 conformally cover the plurality of first electrodes 222. The dielectric film 224 and the second electrode 226 can extend on the third-direction DR3 to the upper surface of the upper insulating layer 240.

[0107] Next, a plate electrode PE can be formed to cover a plurality of second electrodes 226. The plate electrode PE can be formed to fill the space between a plurality of opposing initial semiconductor patterns SP_P. The plate electrode PE can be formed such that its lowest surface contacts the etch stop layer 120. A first connection pad 251 can be formed on the plate electrode PE.

[0108] Next, refer to Figure 7 The remaining portion of the capping insulating layer 330 can be removed, the initial semiconductor pattern SP_P can be removed, and the semiconductor pattern SP can then be formed at the location of the initial semiconductor pattern SP_P.

[0109] First, the remaining portion of the capping insulating layer 330 can be selectively removed. Then, when the capping insulating layer 330 is removed, the ends of the initial semiconductor pattern SP_P can be exposed. The exposed ends of the initial semiconductor pattern SP_P can be defined as the ends of the initial semiconductor pattern SP_P that are connected to the data storage element DS in the first direction DR1.

[0110] Next, multiple initial semiconductor patterns SP_P can be selectively removed, and multiple semiconductor patterns SP can be formed at the locations where the initial semiconductor patterns SP_P were previously positioned. The initial semiconductor patterns SP_P and the semiconductor patterns SP can include semiconductor materials different from each other. By way of example, the initial semiconductor pattern SP_P can include polysilicon, and the semiconductor pattern SP can include an oxide semiconductor material, but is not limited thereto. Here, the oxide semiconductor material can be formed from at least one material selected from the following: IGZO (InGaZnO), ZrOx, ZTO (ZnSnO), ITZO (InSnZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZnO, ZnON, YZO (yttrium-doped zinc oxide), InGaSiO, InO, SnO, TiO, ZnON, MgZnO, InZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, and ZrZnSnO, but is not limited thereto. In addition to at least one oxide semiconductor material selected from the oxide semiconductor materials mentioned above, the semiconductor pattern SP may also include at least one material selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H).

[0111] Next, refer to Figure 8 It can form an intermediate insulating layer 212, a first spacer 214, a gate insulating pattern Gox, a word line WL, a second spacer 216, an interlayer dielectric layer ILD, a bit line BL, and a second connection pad 252 located on the bit line BL.

[0112] First, the first initial insulating layer 334 can be recessed in the direction toward the data storage element DS and the plate electrode PE, and an intermediate insulating layer 212 can be formed therein. When the first initial insulating layer 334 is recessed, a portion of the upper and lower surfaces of the semiconductor pattern SP and a portion of the side surface in the second direction DR2 can be exposed.

[0113] Next, a first spacer 214 and an interlayer dielectric layer ILD can be formed in the space formed in the recessed region of the first initial insulating layer 334, and a gate insulating pattern Gox, a word line WL, and a second spacer 216 can be formed sequentially.

[0114] Next, bit lines BL can be formed to connect to one side of the semiconductor pattern SP. Here, according to some embodiments, in forming... Figure 3 After the separation insulation pattern 218 is formed, bit lines BL can be formed. Therefore, multiple bit lines BL can be formed such that the multiple bit lines BL are spaced apart in the second direction DR2, and the separation insulation pattern 218 is located between the multiple bit lines BL.

[0115] Next, a second connection pad 252 can be formed on the bit line BL. The side surface of the second connection pad 252 on the bit line BL can be covered by a shielding layer 230 and an upper insulating layer 240. According to some embodiments, an additional insulating layer may be located between the second connection pad 252 and the shielding layer 230.

[0116] Next, the substrate 100 can be removed. For example, the substrate 100 can be removed by a polishing process. In the polishing process used to remove the substrate 100, a polishing stop layer 110 can be used as a stop layer.

[0117] Figure 9 and Figure 10 This is a cross-sectional view of a semiconductor device according to other embodiments.

[0118] Reference Figure 9 According to another embodiment, the semiconductor device may include a cell structure CS, a peripheral circuit structure PS, and at least one through-hole 532 connecting the cell structure CS and the peripheral circuit structure PS.

[0119] The unit structure CS may include references Figures 1 to 3 The semiconductor device described herein. For example, a cell structure CS may include a polishing stop layer 110, an etch stop layer 120, a word line WL, a gate insulating pattern Gox, a semiconductor pattern SP, and an interlayer dielectric layer ILD. Figure 1 Bit line BL, Figure 1 The data storage element DS, word line contact WLC, cell insulation layer 219, shielding layer 230, upper insulation layer 240, cell wiring structure CW, and cell buffer layer 430.

[0120] An etch stop layer 120 may be located on a polishing stop layer 110. Multiple word lines WL may be located on the etch stop layer 120. The multiple word lines WL may be positioned spaced apart on a third direction DR3, with an interlayer dielectric layer ILD located between the multiple word lines WL. The multiple word lines WL may be positioned around multiple semiconductor patterns SP spaced apart from each other on a second direction DR2. A gate insulating pattern Gox may be located between the word lines WL and the semiconductor patterns SP. A shielding layer 230 may be located on the multiple interlayer dielectric layers ILD and the multiple word lines WL. An upper insulating layer 240 may be located on the shielding layer 230.

[0121] The etch stop layer 120 may be located on the first surface of the polishing stop layer 110. The second surface of the polishing stop layer 110 may be the surface facing the first surface on the third-direction DR3. For example, the first surface of the polishing stop layer 110 may represent the upper surface of the polishing stop layer 110, and the second surface of the polishing stop layer 110 may represent the lower surface of the polishing stop layer 110. The first surface of the polishing stop layer 110 may be positioned to face the second surface of the peripheral substrate 510.

[0122] Word lines (WL) may be located on the first surface of etch stop layer 120. Semiconductor patterns (SP) may be located on the first surface of etch stop layer 120. Interlayer dielectric layers (ILD) may be located on the first surface of etch stop layer 120. Cell wiring structures (CW) may be located on the first surface of etch stop layer 120. Polishing stop layer 110 may be located on the second surface of etch stop layer 120. The first and second surfaces of etch stop layer 120 may be surfaces facing each other on a third-direction DR3. For example, the first surface of etch stop layer 120 may represent the upper surface of etch stop layer 120, and the second surface of etch stop layer 120 may represent the lower surface of etch stop layer 120. The first surface of etch stop layer 120 may be positioned to face the second surface of peripheral substrate 510.

[0123] Multiple interlayer dielectric layers (ILDs) and multiple word lines (WLs) can be alternately stacked on the third direction DR3. The ILDs and WLs can extend in the second direction DR2. The lengths of the multiple word lines (WLs) and ILDs spaced apart on the third direction DR3 can differ from each other in the second direction DR2. For example, the word line (WL) and ILD located at the lowest horizontal level on the third direction DR3 can have the largest length in the second direction DR2, and the lengths of the word lines (WLs) and ILDs in the second direction DR2 can gradually decrease towards the layers above them.

[0124] For example, the length of each of the multiple interlayer dielectric layer (ILD) in the second direction DR2 can be different. For example, the multiple interlayer dielectric layer (ILD) can extend to different extents in the second direction DR2. Among the multiple interlayer dielectric layer (ILD), the interlayer dielectric layer (ILD) located at the bottommost layer can extend the longest in the second direction DR2, and the extent of its extension in the second direction DR2 can become smaller as it moves upward in the third direction DR3, but is not limited thereto.

[0125] For example, the length of each of the multiple word lines WL in the second direction DR2 can be different. For example, the multiple word lines WL can extend to different extents in the second direction DR2. Among the multiple word lines WL, the word line WL located at the lowest level can extend the longest in the second direction DR2, and its extension in the second direction DR2 can become smaller as it goes up in the third direction DR3, but is not limited to this.

[0126] Each of the multiple word lines WL can be connected to a corresponding word line contact WLC. For example, each of the multiple word lines WL can be connected to the word line contact WLC in an area that does not overlap with other word lines WL on the third-direction DR3. The word line contact WLC can have the form of extending on the third-direction DR3. The cell insulation layer 219 can be positioned around one side of the word line contact WLC.

[0127] The word line contact WLC can penetrate the cell insulation layer 219, the shielding layer 230, and the upper insulation layer 240 and connect to the cell wiring structure CW located on the upper insulation layer 240. An additional insulation layer can be provided between the word line contact WLC and the shielding layer 230.

[0128] The unit wiring structure CW may include at least one first wiring 412, at least one via 414, at least one second wiring 416, and a unit wiring insulation layer 420.

[0129] The cell wiring structure CW may include multiple first wirings 412. Some of the multiple first wirings 412 may be connected to word line contacts WLC.

[0130] The unit wiring structure CW may include multiple second wirings 416. The second wirings 416 may be located above the first wirings 412.

[0131] The unit wiring structure CW may include multiple vias 414. The vias 414 may be located between the first wiring 412 and the second wiring 416. The vias 414 can connect the first wiring 412 and the second wiring 416. The vias 414 may have a shape extending in a third direction DR3.

[0132] The first wiring 412, the via 414, and the second wiring 416 may include conductive materials. By way of example, the first wiring 412, the via 414, and the second wiring 416 may include, but are not limited to, metals (such as copper (Cu), tungsten (W)), metal oxides, metal nitrides, or doped semiconductor materials.

[0133] The unit wiring insulating layer 420 may cover the first wiring 412, the via 414, and the second wiring 416. The unit wiring insulating layer 420 may include an insulating material. By way of example, the unit wiring insulating layer 420 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON).

[0134] exist Figure 9 In the diagram, the lower surfaces of the unit wiring insulation layer 420 and the first wiring 412 are shown at the same level on the third-direction DR3, and the upper surfaces of the unit wiring insulation layer 420 and the second wiring 416 are shown at the same level on the third-direction DR3, but are not limited thereto. In addition to the first wiring 412, the via 414, and the second wiring 416, the unit wiring structure CW may include additional wiring.

[0135] Cell buffer layer 430 may be located on cell wiring structure CW. Cell buffer layer 430 may be located between peripheral circuit structure PS and cell wiring structure CW. Cell buffer layer 430 may be configured to reduce stress generation at the interface between peripheral circuit structure PS and cell structure CS. Cell buffer layer 430 may be configured to provide bonding between peripheral circuit structure PS and cell structure CS. By way of example, cell buffer layer 430 may include, but is not limited to, adhesive materials. Cell buffer layer 430 may include insulating materials. By way of example, cell buffer layer 430 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON).

[0136] The peripheral circuit structure PS can be located on the unit structure CS. The peripheral circuit structure PS may include a peripheral substrate 510, a substrate insulating pattern 512, a peripheral circuit PC, a peripheral circuit insulating layer 520, a peripheral circuit wiring layer 530, and a peripheral circuit buffer layer 540.

[0137] The peripheral substrate 510 may include a semiconductor material. For example, the peripheral substrate 510 may be a semiconductor substrate comprising a semiconductor material, such as a single-crystal Si substrate, a silicon-germanium (Si-Ge) substrate, or a Si-on-insulator (SOI) substrate. As another example, the peripheral substrate 510 may be a semiconductor epitaxial layer comprising a semiconductor material. However, the type of the peripheral substrate 510 is not limited to this and can be varied in various ways.

[0138] The peripheral circuit PC can be located on the first surface of the peripheral substrate 510. The peripheral circuit insulating layer 520 can be located on the first surface of the peripheral substrate 510. The peripheral circuit buffer layer 540 can be located on the second surface of the peripheral substrate 510. The cell wiring structure CW can be located on the second surface of the peripheral substrate 510. The first and second surfaces of the peripheral substrate 510 can be surfaces facing away from each other on a third-direction DR3. For example, the first surface of the peripheral substrate 510 can represent the upper surface of the peripheral substrate 510, and the second surface of the peripheral substrate 510 can represent the lower surface of the peripheral substrate 510. The second surface of the peripheral substrate 510 can be positioned facing the first surface of the etch stop layer 120.

[0139] The substrate insulating pattern 512 may be located within the peripheral substrate 510. The substrate insulating pattern 512 may be positioned to penetrate the peripheral substrate 510 on the third-direction DR3. The substrate insulating pattern 512 may be located between the peripheral substrate 510 and the via 532. The substrate insulating pattern 512 may be positioned to cover a portion of the side surface of the via 532. The substrate insulating pattern 512 may electrically isolate the via 532 and the peripheral substrate 510.

[0140] The width of the substrate insulating pattern 512 in the first direction DR1 may decrease as it extends from the upper part to the lower part of the substrate insulating pattern 512 in the third direction DR3. Additionally, the substrate insulating pattern 512 may have a width in the second direction DR2 that decreases as it extends from the upper part to the lower part of the substrate insulating pattern 512 in the third direction DR3. In other words, the substrate insulating pattern 512 may have a width that increases in the first direction DR1 and / or the second direction DR2 as it extends from the lower part to the upper part of the substrate insulating pattern 512 in the third direction DR3.

[0141] The substrate insulating pattern 512 may include an insulating material. By way of example, the substrate insulating pattern 512 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON).

[0142] Peripheral circuitry PCs can be located on peripheral substrate 510. Multiple peripheral circuitry PCs can be located on peripheral substrate 510. Peripheral circuitry PCs can be connected to peripheral circuitry wiring layer 530.

[0143] The peripheral circuitry PC can be configured to drive components located within the cell structure CS. The peripheral circuitry PC can be circuitry performing logic operations and can consist of combinations of circuit elements such as transistors. For example, the peripheral circuitry PC can include, but is not limited to: a row decoder that selects rows of the memory cell array based on address signals; a column decoder that selects columns of the memory cell array based on address signals; a sense amplifier that reads and amplifies data from memory cells; and a word line driver that activates the word line of the selected row. For example, the peripheral circuitry PC can include a gate-all-around (GAA) structure where the four sides of the channel are surrounded by gate electrodes, or a multi-bridge channel field-effect transistor (MBCFET). TM The embodiments are not limited to this, and the peripheral circuit PC may have a FinFET structure, or may include a 3D stacked field-effect transistor (3DSFET) structure or a complementary field-effect transistor (CFET) structure.

[0144] The peripheral circuit insulating layer 520 may be located on the peripheral substrate 510. The peripheral circuit insulating layer 520 may cover a portion of the upper surface of the peripheral substrate 510 and a plurality of peripheral circuits PC. The peripheral circuit insulating layer 520 may include an insulating material. By way of example, the peripheral circuit insulating layer 520 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON).

[0145] The peripheral circuit wiring layer 530 may be located above the peripheral circuit PC. The peripheral circuit wiring layer 530 may be located on the peripheral circuit insulating layer 520. According to some embodiments, the peripheral circuit wiring layer 530 may include multiple wirings and multiple vias connecting the wirings. Additionally, the peripheral circuit wiring layer 530 may include an insulating layer covering the multiple wirings and the multiple vias.

[0146] The peripheral circuit buffer layer 540 may be located below the peripheral substrate 510. The peripheral circuit buffer layer 540 may be located on the lower surface of the peripheral substrate 510. The peripheral circuit buffer layer 540 may be located on the unit buffer layer 430. The peripheral circuit buffer layer 540 may be in contact with the peripheral substrate 510. The peripheral circuit buffer layer 540 may be in contact with the lower surface of the peripheral substrate 510.

[0147] The peripheral circuit buffer layer 540 may include an insulating material. By way of example, the peripheral circuit buffer layer 540 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON).

[0148] The via 532 can connect the peripheral circuit routing layer 530 and the cell routing structure CW. For example, the via 532 can connect the second wiring 416 of the cell routing structure CW to the wiring located within the peripheral circuit routing layer 530.

[0149] The via 532 may have a shape extending in the third direction DR3. Multiple vias 532 may be disposed within the semiconductor device. The via 532 may be positioned to penetrate the peripheral circuit wiring layer 530, the peripheral circuit insulating layer 520, the peripheral substrate 510, the peripheral circuit buffer layer 540, and the cell buffer layer 430 in the third direction DR3. The via 532 may be positioned to penetrate the substrate insulating pattern 512 located within the peripheral substrate 510. A portion of one side of the via 532 may be surrounded by the substrate insulating pattern 512.

[0150] The through hole 532 may have a width that decreases from the upper part to the lower part of the through hole 532 in the first direction DR1 and in the third direction DR3. Additionally, the through hole 532 may have a width that decreases from the upper part to the lower part of the through hole 532 in the second direction DR2 and in the third direction DR3.

[0151] Through-hole 532 may include a conductive material. By way of example, through-hole 532 may include any of the following materials: a doped semiconductor material, such as doped silicon (Si) or doped germanium (Ge); a conductive metal nitride, such as titanium nitride (TiN) or tantalum nitride (TaN); a metal, such as tungsten (W), titanium (Ti), or tantalum (Ta); and a metal semiconductor compound, such as tungsten silicide (WSi). x ), cobalt silicide (CoSi) x ) or titanium silicide (TiSi) x ).

[0152] Reference Figure 10 According to another embodiment, the semiconductor device may include a first unit structure CS1, a second unit structure CS2, and a peripheral circuit structure PS.

[0153] Figure 10 The description of the semiconductor device shown will focus on its relationship with... Figure 9 The description of the semiconductor device shown is substantially different in some parts.

[0154] The semiconductor device according to another embodiment may include a first unit structure CS1, a second unit structure CS2, a peripheral circuit structure PS, and a through-hole 532 connecting the second unit structure CS2 and the peripheral circuit structure PS.

[0155] although Figure 10 The illustration shows two stacked cell structures, but the embodiments are not limited thereto. For example, a semiconductor device according to another embodiment may have a structure in which three or more cell structures are stacked.

[0156] The first unit structure CS1 and the second unit structure CS2 may include Figures 1 to 3 The semiconductor device described herein may include part or all of its structure. For example, each of the first unit structure CS1 and the second unit structure CS2 may include an etch stop layer 120, a word line WL, a gate insulating pattern Gox, a semiconductor pattern SP, and an interlayer dielectric layer ILD. Figure 1 Bit line BL, Figure 1 Data storage elements such as DS.

[0157] The first cell structure CS1 may include a polishing stop layer 110. The first cell structure CS1 may not include the cell wiring structure CW and the cell buffer layer 430. Although Figure 10 The first unit structure CS1 shown does not include a shielding layer and an upper insulating layer, but the embodiments are not limited thereto. For example, in some embodiments, the first unit structure CS1 may include a shielding layer and an upper insulating layer.

[0158] For example, in a semiconductor device having three or more stacked cell structures, the bottommost cell structure may include a polishing stop layer.

[0159] According to some embodiments, multiple word lines WL of the first unit structure CS1 can be connected to corresponding word line contacts. Each of the multiple word lines WL of the first unit structure CS1 can be connected to the unit wiring structure CW included in the second unit structure CS2 through a corresponding word line contact. For example, the word line contact connected to the word line WL of the first unit structure CS1 can penetrate the unit insulating layer of the first unit structure CS1, the etch stop layer 120 of the second unit structure CS2, the unit insulating layer 219 of the second unit structure CS2, the shielding layer 230 of the second unit structure CS2, and the upper insulating layer 240 of the second unit structure CS2 on the third-direction DR3 to connect to the unit wiring structure CW of the second unit structure CS2.

[0160] The second unit structure CS2 may be located on the first unit structure CS1. The second unit structure CS2 may include a shielding layer 230, an upper insulating layer 240, a unit wiring structure CW, a unit buffer layer 430, word line contacts WLC, and a unit insulating layer 219. The second unit structure CS2 may not include the polishing stop layer 110.

[0161] For example, in a semiconductor device having three or more stacked cell structures, the topmost cell structure may include a cell wiring structure and a cell buffer layer.

[0162] The etch stop layer 120 of the second unit structure CS2 may include a plurality of third connection pads 253. The third connection pads 253 included in the etch stop layer 120 of the second unit structure CS2 may also be referred to as contact electrodes or similar terms. The plurality of third connection pads 253 of the etch stop layer 120 of the second unit structure CS2 may respectively connect the bit line BL of the first unit structure CS1 to the corresponding bit line BL of the second unit structure CS2.

[0163] The third connection pad 253 included in the etch stop layer 120 of the second unit structure CS2 may be surrounded on its sides by the etch stop layer 120 of the second unit structure CS2. The upper surface of the third connection pad 253 included in the etch stop layer 120 of the second unit structure CS2 may be connected to the bit line BL of the second unit structure CS2. The lower surface of the third connection pad 253 included in the etch stop layer 120 of the second unit structure CS2 may be connected to the bit line BL of the first unit structure CS1. The third connection pad 253 included in the etch stop layer 120 of the second unit structure CS2 may include conductive material.

[0164] The cell buffer layer 430 of the second cell structure CS2 can contact the peripheral circuit buffer layer 540 of the peripheral circuit structure PS. The peripheral circuit structure PS can be located on the second cell structure CS2. The peripheral circuit wiring layer 530 of the peripheral circuit structure PS can be connected to the cell wiring structure CW of the second cell structure CS2 through a via 532. The via 532 can be positioned to penetrate the peripheral circuit wiring layer 530, the peripheral circuit insulating layer 520, the peripheral substrate 510, the peripheral circuit buffer layer 540, and the cell buffer layer 430 of the second cell structure CS2.

[0165] Figures 11 to 21 This is a diagram illustrating a method of manufacturing a semiconductor device according to other embodiments. Figures 11 to 21 For ease of explanation, only a portion of the construction is shown, and the first unit structure CS1 and the second unit structure CS2 may include references. Figures 1 to 3 Some or all of the construction of the semiconductor device described.

[0166] Reference Figure 11 A polishing stop layer 110 can be formed on the substrate 100, and an etch stop layer 120 can be formed on the polishing stop layer 110.

[0167] Next, multiple semiconductor material layers 310 and multiple insulating material layers 320 can be alternately stacked on the etch stop layer 120. The semiconductor material layers 310 and insulating material layers 320 can be formed by deposition methods.

[0168] Next, refer to Figure 12Word lines WL, interlayer dielectric layer ILD, semiconductor pattern SP, and gate insulating pattern Gox can be formed on the etch stop layer 120. That is, the first unit structure CS1 can be formed on the substrate 100.

[0169] According to some embodiments, it can be formed on the etch stop layer 120. Figures 1 to 3 Components included in a semiconductor device. For example, they may be additionally formed on the etch stop layer 120. Figure 1 Bit line BL, Figure 1 Separated insulation pattern 218 Figure 1 Data storage element DS, Figure 1 The plate electrode PE, unit insulation layer and other insulation patterns.

[0170] Alternatively, for example, a shielding layer and an upper insulating layer may not be formed on the first unit structure CS1. The uppermost semiconductor material layer 310 among the plurality of semiconductor material layers 310 may be removed during the process of forming the first unit structure CS1. Alternatively, one of the insulating material layers 320 may be formed during the process of stacking the plurality of semiconductor material layers 310 and the plurality of insulating material layers 320 to position the insulating material layer 320 as the uppermost layer of the stacked structure.

[0171] However, the embodiments are not limited thereto, and in some embodiments, a shielding layer and an upper insulating layer may be formed on the first unit structure CS1. The shielding layer and the upper insulating layer may be formed such that the shielding layer and the upper insulating layer are located at the top layer of a stacked structure including a plurality of semiconductor material layers 310 and a plurality of insulating material layers 320.

[0172] Next, refer to Figure 13 An etch stop layer 120 can be formed on the first unit structure CS1 to form the second unit structure CS2. Additionally, a plurality of third connection pads 253 can be formed within the etch stop layer 120 on the first unit structure CS1. The plurality of third connection pads 253 can be formed to be respectively connected to the bit lines of the first unit structure CS1. The bit lines of the first unit structure CS1 and the bit lines to be formed later can be connected to each other through the plurality of third connection pads 253. Here, the third connection pads 253 may include conductive material.

[0173] Next, multiple semiconductor material layers 350 and multiple insulating material layers 360 can be alternately stacked on the etch stop layer 120. The semiconductor material layers 350 and the insulating material layers 360 can be formed by deposition methods.

[0174] Here, the semiconductor material layer 350 and the insulating material layer 360 can be used to form the first unit structure CS1. Figure 11The semiconductor material layer 310 and the insulating material layer 320 are essentially the same.

[0175] Next, refer to Figure 14 Word lines WL, interlayer dielectric layer ILD, semiconductor pattern SP, gate insulating pattern Gox, shielding layer 230 and upper insulating layer 240 can be formed on the etch stop layer 120 located on the first unit structure CS1.

[0176] According to some embodiments, it is possible to form Figures 1 to 3 The structure included in the semiconductor device. For example, it can be additionally formed on the etch stop layer 120 located on the first unit structure CS1. Figure 1 Bit line BL, Figure 1 Separated insulation pattern 218 Figure 1 Data storage element DS, Figure 1 The plate electrode PE and other insulating layers and insulating patterns.

[0177] Next, refer to Figure 15 Multiple word line contacts (WLCs) can be formed. Additionally, a unit wiring structure (CW) can be formed on the upper insulating layer 240.

[0178] Multiple word line contacts (WLCs) can be formed to connect to multiple word lines (WLs) located on the substrate 100. For example, each of the multiple word line contacts (WLCs) can be formed to extend from a corresponding word line (WL) to the upper surface of the upper insulating layer 240 on a third-direction DR3. The cell wiring structure CW to be formed later and the multiple word lines (WLs) of the first cell structure CS1 can be connected through the multiple word line contacts (WLCs). Furthermore, the cell wiring structure CW and the multiple word lines (WLs) of the second cell structure CS2 can be connected through the multiple word line contacts (WLCs).

[0179] Next, a cell wiring structure CW can be formed on the upper insulating layer 240. The cell wiring structure CW may include a first wiring 412, a via 414, a second wiring 416, and a cell wiring insulating layer 420. For example, the first wiring 412 of the cell wiring structure CW may be connected to at least one of a plurality of word line contacts WLC connected to a first cell structure CS1 and a second cell structure CS. The first wiring 412 and the second wiring 416 may be connected through a plurality of vias 414.

[0180] Next, refer to Figure 16 A cell buffer layer 430 can be formed on the cell wiring structure CW. The cell buffer layer 430 can be configured to contact the peripheral circuit structure PS formed later. For example, the cell buffer layer 430 can reduce stress that may occur at the interface between components, or it can be used as a layer for bonding.

[0181] At the same time, refer to Figure 17 A substrate insulating pattern 512, multiple peripheral circuits PC, and a peripheral circuit insulating layer 520 can be formed on the peripheral substrate 510.

[0182] First, a substrate insulating pattern 512 can be formed on the peripheral substrate 510. The substrate insulating pattern 512 can be formed to extend downward from the first surface of the peripheral substrate 510 in the third direction DR3. In other words, the substrate insulating pattern 512 can be formed within the peripheral substrate 510. For example, the substrate insulating pattern 512 can be formed such that its width in the first direction DR1 and the second direction DR2 decreases from top to bottom in the third direction DR3. That is, the substrate insulating pattern 512 can be formed such that its width in the first direction DR1 and the second direction DR2 increases from bottom to top in the third direction DR3.

[0183] Next, a plurality of peripheral circuit PCs and peripheral circuit insulating layers 520 can be formed. The plurality of peripheral circuit PCs can be formed on a peripheral substrate 510. The plurality of peripheral circuit PCs can be formed on a first surface of the peripheral substrate 510. The plurality of peripheral circuit PCs can be formed such that they do not overlap with the plurality of substrate insulating patterns 512 on the third-direction DR3.

[0184] Next, a peripheral circuit insulating layer 520 can be formed to cover a plurality of peripheral circuits PC. The peripheral circuit insulating layer 520 can be formed on a first surface of the peripheral substrate 510. The peripheral circuit insulating layer 520 can be formed to cover the first surface of the peripheral substrate 510. A second surface of the peripheral circuit insulating layer 520 can contact the peripheral substrate 510, and the first surface of the peripheral circuit insulating layer 520 can be the surface facing the second surface on a third-direction DR3.

[0185] For example, the first surface of the peripheral substrate 510 and the peripheral circuit insulating layer 520 can be represented on the upper surface of the third-direction DR3. Additionally, the second surface of the peripheral substrate 510 and the peripheral circuit insulating layer 520 can be represented on the lower surface of the third-direction DR3.

[0186] Next, refer to Figure 18 An adhesive layer 620 may be formed on the carrier substrate 610. The adhesive layer 620 may include an insulating material and may additionally include an adhesive material, but is not limited thereto.

[0187] Next, a peripheral substrate 510 and a plurality of peripheral circuit PCs can be placed on the carrier substrate 610. The plurality of peripheral circuit PCs can be arranged on the carrier substrate 610 such that the peripheral circuit insulating layer 520 contacts the adhesive layer 620. Here, the second surface of the peripheral circuit insulating layer 520 can contact the adhesive layer 620. That is, the peripheral substrate 510 and the plurality of peripheral circuit PCs can be arranged in an inverted state on the third-direction DR3.

[0188] Specifically, the peripheral substrate 510 can be arranged in an inverted state, with the first side facing down and the second side facing up. Therefore, the peripheral circuit insulating layer 520 can be located on the adhesive layer 620, and the peripheral substrate 510 can be located on the peripheral circuit insulating layer 520.

[0189] The thickness of the peripheral substrate 510 on the third-direction DR3 can be reduced by a polishing process. Here, the polishing process of the peripheral substrate 510 can be performed before the peripheral substrate 510 is placed on the carrier substrate 610, or the polishing process of the peripheral substrate 510 can be performed after the peripheral substrate is placed on the carrier substrate 610.

[0190] A peripheral circuit buffer layer 540 may be formed on the second surface of the peripheral substrate 510. The peripheral circuit buffer layer 540 may reduce stress that may occur at the interface between components, or may be used for bonding.

[0191] Next, refer to Figure 19 A carrier substrate 610 can be arranged such that the peripheral circuit buffer layer 540 contacts the unit buffer layer 430. Therefore, the peripheral circuit buffer layer 540 can be located on the unit buffer layer 430. In addition, the peripheral substrate 510 can be located on the peripheral circuit buffer layer 540. Furthermore, the adhesive layer 620 and the carrier substrate 610 can be located on the peripheral substrate 510.

[0192] In other words, the first surface of the peripheral substrate 510 can be arranged upward on the third-direction DR3, and the second surface of the peripheral substrate 510 can be arranged downward on the third-direction DR3.

[0193] The peripheral circuit PC, peripheral circuit buffer layer 540, adhesive layer 620, and carrier substrate 610 can be located on the first surface of the peripheral substrate 510. The cell buffer layer 430 and cell wiring structure CW can be located on the second surface of the peripheral substrate 510.

[0194] Next, refer to Figure 20The substrate 100, carrier substrate 610, and adhesive layer 620 can be removed. Specifically, the substrate 100 located on the second surface of the etch stop layer 120 and the polishing stop layer 110 can be removed. Additionally, the carrier substrate 610 and adhesive layer 620 located on the first surface of the peripheral substrate 510 can be removed. For example, the substrate 100, carrier substrate 610, and adhesive layer 620 can be removed by a polishing process.

[0195] Next, refer to Figure 21 A peripheral circuit wiring layer 530 and a plurality of through holes 532 connecting the peripheral circuit wiring layer 530 and the unit wiring structure CW can be formed on the peripheral circuit PC and the peripheral circuit insulating layer 520.

[0196] Multiple vias 532 can be formed to penetrate the peripheral circuit insulating layer 520, the peripheral substrate 510, the peripheral circuit buffer layer 540, and the unit buffer layer 430 in the third direction DR3. The vias 532 can be formed such that their width in the first direction DR1 and the second direction DR2 decreases from the top to the bottom of the via 532 in the third direction DR3. That is, the vias 532 can be formed such that their width in the first direction DR1 and the second direction DR2 increases from the bottom to the top in the third direction DR3.

[0197] The peripheral circuit wiring layer 530 can be formed to connect to a plurality of peripheral circuits PC located on the peripheral substrate 510. According to some embodiments, the peripheral circuit wiring layer 530 may include a plurality of wiring lines and a plurality of vias. In addition, the peripheral circuit wiring layer 530 may be connected to the cell wiring structure CW through a plurality of vias 532.

[0198] According to the embodiments mentioned above, since the etch stop layer 120 has a flat shape, there is no need for non-functional semiconductor patterns SP. Furthermore, since the substrate 100 can be removed using a polishing process that uses the polishing stop layer 110 as a stop layer, there is an advantage in keeping the overall height of the semiconductor device low. Additionally, there is an advantage that by arranging the peripheral circuit PC of the peripheral circuit structure PS such that the peripheral circuit PC is located on the peripheral substrate 510 rather than arranged upside down, the wiring of the cell structure CS can be constructed relatively easily.

[0199] According to some embodiments of this disclosure, a method of manufacturing a semiconductor device may include: forming a polishing stop layer on a substrate; forming an etch stop layer on the polishing stop layer; alternately stacking a plurality of semiconductor material layers and a plurality of insulating material layers on the etch stop layer; removing the plurality of insulating material layers to form a plurality of initial semiconductor patterns from the semiconductor material layers, and forming a plurality of data storage elements respectively connected to the initial semiconductor patterns and plate electrodes located on the plurality of data storage elements; removing the plurality of initial semiconductor patterns and forming semiconductor patterns; forming a plurality of word lines on portions of the upper and lower surfaces of corresponding semiconductor patterns in the semiconductor patterns, and forming a plurality of bit lines respectively connected to the ends of the semiconductor patterns; and removing the substrate.

[0200] In the method of manufacturing a semiconductor device according to the embodiment, a plurality of semiconductor material layers and a plurality of insulating material layers can be formed by a deposition process.

[0201] In the method of manufacturing a semiconductor device according to an embodiment, the plurality of semiconductor material layers may include polysilicon, and the plurality of insulating material layers may include insulating materials.

[0202] In a method of manufacturing a semiconductor device according to an embodiment, the semiconductor pattern may include an oxide semiconductor material.

[0203] In the method of manufacturing a semiconductor device according to an embodiment, the lower surfaces of the plurality of bit lines and the lower surfaces of the plate electrodes may be located at the same level as the upper surface of the etch stop layer.

[0204] According to some embodiments of this disclosure, a method of manufacturing a semiconductor device may include: forming a first unit structure, the first unit structure including a polishing stop layer on a substrate, an etch stop layer on the polishing stop layer, a plurality of semiconductor patterns on the etch stop layer, a plurality of word lines on portions of the upper and lower surfaces of corresponding semiconductor patterns in the semiconductor patterns, a plurality of interlayer dielectric layers between the word lines, a gate insulating pattern between the word lines and the semiconductor patterns, and a unit wiring structure on the word lines; forming a peripheral circuit structure on the first unit structure, the peripheral circuit structure including a peripheral substrate, a plurality of peripheral circuits on a first surface of the peripheral substrate, a peripheral circuit insulating layer on the peripheral circuits, and a peripheral circuit wiring layer on the peripheral circuit insulating layer; removing the substrate; and forming a plurality of vias connecting the unit wiring structure and the peripheral circuit wiring layer.

[0205] In the method of manufacturing a semiconductor device according to the embodiment, a plurality of word lines may be located on a first surface of an etch stop layer, a plurality of peripheral circuits may be located on a first surface of a peripheral substrate, a cell wiring structure may be located on a second surface of a peripheral substrate, and the first surface of the etch stop layer may be positioned to face the second surface of the peripheral substrate.

[0206] In a method of manufacturing a semiconductor device according to an embodiment, a plurality of vias may extend through a peripheral substrate, and the peripheral substrate may further include a substrate insulating pattern on the sidewalls of the vias.

[0207] In the method of manufacturing a semiconductor device according to the embodiment, the widths of the plurality of vias and the substrate insulating pattern may decrease toward the lower portion of the plurality of vias and the substrate insulating pattern, respectively.

[0208] In the method of manufacturing a semiconductor device according to the embodiments, the cell structure may further include a plurality of word line contacts that connect the cell wiring structure and a plurality of word lines, and a cell insulating layer on the plurality of word line contacts.

[0209] Although non-limiting exemplary embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the scope of the present disclosure is not limited thereto, and various modifications and improvements can be made by those skilled in the art within the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: Polishing stop layer, An etch stop layer is located on the upper surface of the polishing stop layer. A semiconductor pattern is located on the upper surface of the etch stop layer, and the semiconductor pattern extends in a first direction. A word line, located on at least a portion of the upper or lower surface of the semiconductor pattern, extends in a second direction intersecting the first direction. Bit lines, which extend upward at a third point intersecting the first and second directions, and are connected to a first end of the semiconductor pattern, and A data storage element, which is connected to a second end of the semiconductor pattern opposite to the first end. The insulating material of the polishing stop layer is different from that of the etching stop layer.

2. The semiconductor device according to claim 1, in, The semiconductor pattern includes an oxide semiconductor material.

3. The semiconductor device according to claim 1, further comprising: Plate electrodes, which are located on the data storage element, Wherein, the lower surface of the plate electrode is at the same level in the third direction as the upper surface of the etch stop layer in the third direction.

4. The semiconductor device according to claim 1, further comprising: Additional bit lines located on the upper surface of the etch stop layer, the additional bit lines being spaced apart from the bit lines in the second direction; A separate insulating pattern is positioned between the bit line and the additional bit line. Wherein, the lower surface of the separated insulating pattern is at the same level in the third direction as the upper surface of the etch stop layer in the third direction.

5. The semiconductor device according to claim 1, in, The upper surface of the etch stop layer extends parallel to the first and second directions and includes a planar shape.

6. The semiconductor device according to claim 1, wherein, The data storage element includes: A first electrode is connected to a second end of the semiconductor pattern; A second electrode, which is located on top of the first electrode; and A dielectric film is located between the first electrode and the second electrode.

7. A semiconductor device, comprising: Unit structure, and The peripheral circuit structure is located on the upper surface of the unit structure. The unit structure includes: The polishing stop layer includes an insulating material. An etch stop layer is located on the upper surface of the polishing stop layer, and the etch stop layer comprises an insulating material different from the insulating material of the polishing stop layer. A semiconductor pattern is located on the upper surface of the etch stop layer and extends in a first direction. A word line, located on at least a portion of the upper or lower surface of the semiconductor pattern, extends in a second direction intersecting the first direction. Bit lines extend upward at a third point intersecting the first and second directions, and are connected to a first end of the semiconductor pattern. A data storage element, which is connected to a second end of the semiconductor pattern opposite to the first end, and A cell wiring structure, which is located on the bit line and connected to the word line, and The peripheral circuit structure includes: Peripheral substrate, A peripheral circuit wiring layer, which is located on the peripheral substrate and connected to the cell wiring structure, and Peripheral circuitry, which is located between the peripheral circuitry wiring layer and the peripheral substrate and is connected to the peripheral circuitry wiring layer.

8. The semiconductor device according to claim 7, in, The semiconductor pattern of the unit structure includes oxide semiconductor material.

9. The semiconductor device according to claim 7, further comprising: Plate electrodes, which are located on the data storage element, Wherein, the lower surface of the plate electrode is at the same level in the third direction as the upper surface of the etch stop layer in the third direction.

10. The semiconductor device according to claim 7, further comprising: Additional bit lines located on the upper surface of the etch stop layer, the additional bit lines being spaced apart from the bit lines in the second direction; A separate insulating pattern is positioned between the bit line and the additional bit line. Wherein, the lower surface of the separated insulating pattern is at the same level in the third direction as the upper surface of the etch stop layer in the third direction.

11. The semiconductor device according to claim 7, in, The upper surface of the etch stop layer extends parallel to the first and second directions and includes a planar shape.

12. The semiconductor device of claim 7, further comprising: Through-holes extend through the peripheral substrate and connect the peripheral circuit wiring layer and the unit wiring structure.

13. The semiconductor device according to claim 7, in, The semiconductor pattern is located on the upper surface of the etch stop layer, and the polishing stop layer is located on the lower surface of the etch stop layer. The peripheral circuit is located on the first surface of the peripheral substrate, and the second surface of the peripheral substrate opposite to the first surface faces the upper surface of the etch stop layer.

14. A semiconductor device, comprising: First unit structure, The second unit structure is located on the upper surface of the first unit structure, and The peripheral circuit structure is located on the upper surface of the second unit structure. Each of the first unit structure and the second unit structure includes: An etch stop layer, which includes an insulating material, A semiconductor pattern is located on the upper surface of the etch stop layer and extends in a first direction. A word line, located on at least a portion of the upper or lower surface of the semiconductor pattern, extends in a second direction intersecting the first direction. Bit lines, which extend upward at a third point intersecting the first and second directions, and are connected to a first end of the semiconductor pattern, and A data storage element, which is connected to a second end of the semiconductor pattern opposite to the first end. The first unit structure further includes a polishing stop layer located below the etch stop layer of the first unit structure. The polishing stop layer comprises an insulating material different from the insulating material of the etch stop layer of the first unit structure. The second unit structure further includes a unit routing structure, which is located on the bit lines of the second unit structure and connected to the word lines of the first unit structure and the word lines of the second unit structure. The peripheral circuit structure includes: Peripheral substrate, A peripheral circuit wiring layer, which is located on the peripheral substrate and connected to the unit wiring structure of the second unit structure, and Peripheral circuitry is located between the peripheral circuitry wiring layer and the peripheral substrate, and is connected to the peripheral circuitry wiring layer.

15. The semiconductor device according to claim 14, in, The semiconductor patterns of the first unit structure and the second unit structure include oxide semiconductor materials.

16. The semiconductor device according to claim 14, in, The first unit structure includes a first plate electrode located on the data storage element of the first unit structure. The second unit structure includes a second plate electrode located on the data storage element of the second unit structure, wherein the lower surface of the first plate electrode of the first unit structure is at the same level in the third direction as the upper surface of the etch stop layer of the first unit structure in the third direction, and... Wherein, the lower surface of the second plate electrode of the second unit structure is at the same level in the third direction as the upper surface of the etch stop layer of the second unit structure in the third direction.

17. The semiconductor device according to claim 14, in, The first unit structure also includes: A first additional bit line is located on the upper surface of the etch stop layer of the first unit structure; and A first separate insulating pattern is located between the first additional bit line and the bit line of the first unit structure. The second unit structure further includes: A second additional bit line is located on the upper surface of the etch stop layer of the second unit structure; and The second separate insulating pattern is located between the second additional bit line and the bit line of the second unit structure. Wherein, the lower surface of the first separated insulating pattern is at the same level as the upper surface of the etch stop layer of the first unit structure in the third direction, and Wherein, the lower surface of the second separated insulating pattern is at the same level in the third direction as the upper surface of the etch stop layer of the second unit structure.

18. The semiconductor device according to claim 14, in, The etch stop layer of the first unit structure and the etch stop layer of the second unit structure extend in the first direction and the second direction, and include a planar shape.

19. The semiconductor device according to claim 14, in, The etch stop layer of the second unit structure includes connection pads, and The connecting pads connect the bit lines of the first unit structure and the bit lines of the second unit structure.

20. The semiconductor device of claim 14, further comprising: A via extending through the peripheral substrate and connecting the peripheral circuit wiring layer and the unit wiring structure of the second unit structure, and A substrate insulating pattern, which is located in the peripheral substrate and at least partially surrounds the via. The width of the via in the second direction and the width of the substrate insulating pattern in the second direction decrease towards the lower side of the via and the substrate insulating pattern in the third direction, respectively.

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