Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a substrate having a cell array region with cell active regions, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region; gate structures including gate electrodes extending on the cell array region in a first direction crossing the cell active regions and extending into the connection region, each of the gate structures being spaced apart from each other in a second direction substantially perpendicular to the first direction; bit line structures extending on the cell array region in the second direction and connected to the cell active regions; dummy bit line structures extending on the connection region in the second direction; and dummy structures provided on the connection region and penetrating the dummy bit line structures, wherein the dummy bit line structures have different widths measured in the first direction along the second direction.

Description

Cross-references to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0055951, filed with the Korean Intellectual Property Office on April 29, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The exemplary embodiments disclosed herein relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0003] With the development of the electronics industry and user demands, electronic devices have been designed to have reduced size and high performance. Therefore, semiconductor devices used in electronic devices also need to have high integration density. To manufacture highly miniaturized semiconductor devices, technologies are needed to create reduced environmental differences between regions. Summary of the Invention

[0004] The exemplary embodiments disclosed herein are intended to provide semiconductor devices with improved reliability and performance.

[0005] According to an exemplary embodiment of this disclosure, a semiconductor device includes: a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region; a device isolation region on the substrate including a cell device isolation region and a connection device isolation region, the cell device isolation region defining a cell active region on the cell array region, and the connection device isolation region defining an active region on the connection region; a gate structure including a gate electrode that intersects with the cell active region on the cell array region and extends into the connection device isolation region of the device isolation region on the connection region; and a bit line structure on the cell array region intersecting the gate structure on a first side. Extending upward and connected to the cell active region; a pseudo bit line structure extending in a first direction over the connection region and having at least a portion disposed at a level substantially the same as the level of the bit line structure; an insulating structure disposed on the pseudo bit line structure over the connection region; and a pseudo structure disposed on the connection region and penetrating at least a portion of the insulating structure, wherein the pseudo structure includes: a first pseudo structure disposed on the connection device isolation region; and a second pseudo structure spaced apart from the first pseudo structure in the first direction, vertically overlapping the gate structure, and having at least a portion disposed at a level substantially the same as the level of the bit line structure.

[0006] According to an example embodiment of this disclosure, a semiconductor device includes: a substrate including a cell array region having cell active regions, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region; a gate structure including a gate electrode extending on the cell array region in a first direction intersecting the cell active regions and extending into the connection region, the gate structures being spaced apart from each other in a second direction substantially perpendicular to the first direction; a bit line structure extending on the cell array region in a second direction intersecting the gate structures and connected to the cell active regions; a pseudo bit line structure extending on the connection region in the second direction; an insulating structure including an insulating pad and an interlayer insulating layer on the insulating pad, the insulating pad covering the upper and side portions of the pseudo bit line structure and extending along the upper surface of the gate structure; and a pseudo pattern on the connection region, wherein the pseudo pattern includes: at least one first pseudo pattern that penetrates the insulating structure and the pseudo bit line structure between the gate structures; and at least one second pseudo pattern that vertically overlaps the gate structure and penetrates the insulating structure and the pseudo bit line structure.

[0007] According to an example embodiment of this disclosure, a semiconductor device includes: a substrate having a cell array region having cell active regions, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region; a gate structure including a gate electrode extending on the cell array region in a first direction intersecting the cell active regions and extending into the connection region, each of the gate structures being spaced apart from each other in a second direction perpendicular to the first direction; a bit line structure extending on the cell array region in the second direction and connected to the cell active regions; a pseudo bit line structure extending on the connection region in the second direction; and a pseudo structure disposed on the connection region and penetrating the pseudo bit line structure, wherein the pseudo bit line structure has a different width measured in the first direction along the second direction. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 2A and Figure 2B This is an enlarged view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 3A , Figure 3B , Figure 3C and Figure 3D This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 4 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 5This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 6 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 7A and Figure 7B This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 8A and Figure 8B This is an enlarged view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 9 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 10A and Figure 10B This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 11 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 12A and Figure 12B This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 13 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 14A and Figure 14B This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 15 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A and Figure 17B as well as Figure 18A , Figure 18B , Figure 18C and Figure 18D This is a cross-sectional view illustrating a method for sequentially manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure; and Figure 19A and Figure 19B , Figure 20A and Figure 20B as well as Figure 21A and Figure 21B This is a cross-sectional view illustrating a process for sequentially manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0009] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0010] Unless otherwise indicated, terms such as “upper,” “upper part,” “upper surface,” “lower,” “lower part,” “lower surface,” “side surface,” “upper end,” and “lower end” may be referenced based on the accompanying drawings. Terms such as “upper part,” “middle part,” and “lower part” may be replaced by other terms such as “first,” “second,” and “third,” and may be used to describe elements in the embodiments. Terms such as “first,” “second,” and “third” may be used to describe various elements, but the elements are not limited to these terms, and “first component” may be referred to as “second component.”

[0011] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment.

[0012] Figure 2A and Figure 2B This is an enlarged view showing a portion of a semiconductor device according to an example embodiment. Figure 2A It is shown Figure 1 An enlarged view of region "A" in the image, and Figure 2B It is shown Figure 1 An enlarged view of region "B" in the image.

[0013] Figure 3A , Figure 3B , Figure 3C and Figure 3D This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 3A It is along Figure 2A The cross-sectional view taken from line I-I' in the diagram. Figure 3B It is along Figure 2A The cross-sectional view taken from line II-II' in the diagram. Figure 3C It is along Figure 2A The cross-sectional view taken from line III-III' in the diagram. Figure 3D It is along Figure 2B The cross-sectional view taken from line IV-IV' in the diagram.

[0014] Reference Figure 1 , Figure 2A and Figure 2BThe semiconductor device 100 may include a cell array region CAR, a peripheral circuit region PCR for driving the cell array region CAR, and a connection region IR between the cell array region CAR and the peripheral circuit region PCR. In an example embodiment, regions CAR, PCR, and IR may be defined on a substrate 101. Memory cells may be disposed in the cell array region CAR. The peripheral circuit region PCR may be disposed around the cell array region CAR. Word line drivers, sense amplifiers, row decoders, column decoders, and control circuitry may be disposed in the peripheral circuit region PCR. The connection region IR may be configured to electrically connect the cell array region CAR to the peripheral circuit region PCR. In an example, in the connection region IR, word lines WL may be connected to contact plugs 160cp1, and contact plugs 160cp1 may be connected to upper conductive patterns 160p1.

[0015] Reference Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C and Figure 3D The semiconductor device 100 may include: a substrate 101 including an active region ACT; a device isolation region 110 defining the active region ACT in the substrate 101; a word line structure WLS extending through the substrate 101 and including a word line WL; a bit line structure BLS extending across the word line structure WLS on the substrate 101 and including a bit line BL; and a pseudo bit line structure BL_D. The active region ACT, the word line structure WLS, and the bit line structure BLS may be disposed in a cell array region CAR. The pseudo bit line structure BL_D may be disposed in a connection region IR. The pseudo bit line structure BL_D may be referred to as a pseudo bit line.

[0016] The semiconductor device 100 may further include: a lower conductive pattern 150 on the active region ACT, a first upper conductive pattern 160c on the lower conductive pattern 150, a contact plug 160cp1 connected to the word line WL in the connection region IR, a second upper conductive pattern 160p1 on the contact plug 160cp1, a peripheral contact plug 160cp2 connected to the peripheral source / drain region 30 in the peripheral circuit region PCR, a third upper conductive pattern 160p2 on the peripheral contact plug 160cp2, and an insulating pattern 165 penetrating the upper conductive patterns 160c, 160p1, and 160p2.

[0017] The semiconductor device 100 may further include: a peripheral transistor disposed on a substrate 101 in the connection region IR and the peripheral circuit region PCR, an insulating pad 152, and interlayer insulating layers 156 and 158. In an example embodiment, the insulating pad 152 and the interlayer insulating layers 156 and 158 may be collectively referred to as an insulating structure. The peripheral transistor may include a peripheral gate dielectric layer 40, peripheral gate electrodes 41, 42 and 43, and a peripheral source / drain region 30.

[0018] Semiconductor device 100 may include a pseudo-structure DS on a connection region IR. The pseudo-structure DS may include: a first pseudo-structure DS1 disposed between adjacent word line structures WLS, and a second pseudo-structure DS2 vertically overlapping the word line structures WLS. In an example embodiment, the pseudo-structure DS may be referred to as a pseudo-pattern, the first pseudo-structure DS1 may be referred to as a first pseudo-pattern, and the second pseudo-structure DS2 may be referred to as a second pseudo-pattern.

[0019] Semiconductor device 100 may include, for example, a cell array of DRAM (Dynamic Random Access Memory). For example, bit line BL may be connected to a first impurity region 105a of active region ACT, and a second impurity region 105b of active region ACT may be electrically connected to a capacitor structure on the first upper conductive pattern 160c via a lower conductive pattern 150 and an upper conductive pattern 160c. Although not shown, the capacitor structure may include, for example, a lower electrode, a capacitor dielectric layer, and an upper electrode, and its structure is not limited thereto.

[0020] Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 101 may also include impurities. Substrate 101 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0021] The active region ACT may be defined in the substrate 101 by the device isolation region 110. The active region ACT may be strip-shaped and may have an island shape extending in the substrate 101 in a direction (e.g., along the W direction). The W direction may be a direction inclined relative to the extension directions of the word line WL and the bit line BL. The active regions ACT may be arranged parallel to each other, and the end of one active region ACT may be arranged adjacent to the center of another active region ACT adjacent to that active region.

[0022] The active region ACT may have a first impurity region 105a and a second impurity region 105b, the first impurity region 105a and the second impurity region 105b having a predetermined depth relative to the upper surface of the substrate 101. The first impurity region 105a and the second impurity region 105b may be spaced apart from each other. The first impurity region 105a and the second impurity region 105b may be provided as the source / drain regions of a transistor formed by word lines WL. For example, respectively, a drain region may be formed between two word lines WL intersecting an active region ACT, and a source region may be formed outside these two word lines WL. The source and drain regions may be formed by doping or ion implantation of substantially the same impurity from the first impurity region 105a and the second impurity region 105b, and may be interchangeably named according to the circuit configuration of the ultimately formed transistor. The impurity may include a dopant having a conductivity type opposite to that of the substrate 101. In an example embodiment, the depths of the first impurity region 105a and the second impurity region 105b in the source and drain regions may be different.

[0023] Device isolation region 110 can be formed using a shallow trench isolation (STI) process. Device isolation region 110 can surround the active region ACT and can electrically isolate the active regions ACT from each other. Device isolation region 110 can be formed of an insulating material (e.g., silicon oxide, silicon nitride, or a combination thereof). Device isolation region 110 can include multiple regions having different lower end depths depending on the width of the trench in which the substrate 101 is etched.

[0024] Device isolation region 110 may include: a cell device isolation region 110C defining a cell active region ACT on the cell array region CAR, a peripheral device isolation region 110B defining a peripheral active region ACT_P on the peripheral circuit region PCR, and a connection device isolation region 110I defining a pseudo active region ACT_D on the connection region IR. The pseudo active region ACT_D may protrude from the substrate 101, and the upper surface of the pseudo active region ACT_D may be disposed at a level substantially the same as the upper surface of the gate capping layer 125. A pseudo gate structure GS_D may be disposed on the pseudo active region ACT_D, but exemplary embodiments are not limited thereto.

[0025] The device isolation region 110 may include multiple layers on the connection region IR. For example, the connection device isolation region 110I may be as follows: Figure 3A and Figure 3BThe region adjacent to the end EP of the word line WL includes a first insulating pad 111, a second insulating pad 112, and a filling insulating layer 113. The second insulating pad 112 may be disposed on the first insulating pad 111, and the filling insulating layer 113 may be disposed on the second insulating pad 112. The first insulating pad 111 and the second insulating pad 112 may be conformally formed sequentially along the surface of an etched trench in which a connection device isolation region 110I is formed on the substrate 101. The filling insulating layer 113 may fill the spaces in the trench that are not filled by the first insulating pad 111 and the second insulating pad 112. The second insulating pad 112 may include an insulating material different from the insulating material of the first insulating pad 111, and the filling insulating layer 113 may include an insulating material different from the insulating material of the second insulating pad 112. For example, the first insulating pad 111 and the filling insulating layer 113 may include silicon oxide, and the second insulating pad 112 may include silicon nitride.

[0026] A word line structure (WLS) may be disposed in a gate trench 115 extending in the substrate 101. Each of the word line structures (WLS) may include a gate dielectric layer 120, a word line (WL), and a gate capping layer 125. In an example embodiment, "gate 120, WL" may be referred to as a structure including the gate dielectric layer 120 and the word line (WL), the word line (WL) may be referred to as a "gate electrode," and the word line structure (WLS) may be referred to as a "gate structure."

[0027] Word lines WL may intersect with the active region ACT and may extend in the first direction X. For example, a pair of adjacent word lines WL may be configured to intersect the active region ACT. Word lines WL may form the gate of a buried channel array transistor (BCAT), but exemplary embodiments thereof are not limited thereto. In exemplary embodiments, word lines WL may also be disposed in the upper portion of substrate 101. Word lines WL may be disposed in the lower portion of gate trench 115 with a predetermined thickness. The upper surface of word lines WL may be located at a level lower than the level of the upper surface of substrate 101. In exemplary embodiments, the term "level" is defined relative to the substantially flat upper surface of substrate 101.

[0028] The word line WL may include at least one of the following conductive materials: polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or aluminum (Al)). For example, the word line WL may include a lower pattern 121 and an upper pattern 122 formed from different materials.

[0029] For example, the lower pattern 121 may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). For example, the upper pattern 122 may be a semiconductor pattern comprising polycrystalline silicon doped with P-type or N-type impurities, and the lower pattern 121 may be a metal pattern comprising at least one of a metal and a metal nitride. The thickness of the lower pattern 121 may be greater than the thickness of the upper pattern 122. Each of the lower pattern 121 and the upper pattern 122 may extend in a first direction X.

[0030] A gate dielectric layer 120 may be disposed on the bottom surface and inner surface of the gate trench 115. The gate dielectric layer 120 may conformally cover the inner sidewall of the gate trench 115. The gate dielectric layer 120 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The gate dielectric layer 120 may be, for example, silicon oxide or an insulating film having a high κ. In an example embodiment, the gate dielectric layer 120 may be formed by oxidizing the active region ACT, or it may be formed by deposition.

[0031] The gate capping layer 125 may be configured to fill the gate trench 115 above the word line WL. The upper surface of the gate capping layer 125 may be located at substantially the same level as the upper surface of the substrate 101. The gate capping layer 125 may be formed of an insulating material such as silicon nitride.

[0032] The bit line structure (BLS) can extend in a direction substantially perpendicular to the word line (WL) (e.g., in the Y direction). The bit line structure (BLS) can include a bit line (BL) and a bit line capping pattern (BC) on the bit line (BL). The bit line structure (BLS) can be disposed on the cell array region (CAR).

[0033] The pseudo bitline structure BL_D can extend in a direction parallel to the direction in which the bitline structure BLS extends (e.g., in the Y direction). The pseudo bitline structure BL_D can be disposed on the connection region IR. Except that the pseudo bitline structure BL_D has a width in the X direction that is larger than the width of the bitline structure BLS, the pseudo bitline structure BL_D can have a structure similar to the bitline structure BLS.

[0034] Bit line BL may include a first conductive pattern 141, a second conductive pattern 142, and a third conductive pattern 143 stacked sequentially. A bit line capping pattern BC may be disposed on the third conductive pattern 143. A buffer insulating layer 128 may be disposed between the first conductive pattern 141 and the substrate 101, and a portion of the first conductive pattern 141 (hereinafter, the bit line contact pattern DC) may contact a first impurity region 105a of the active region ACT. Bit line BL may be electrically connected to the first impurity region 105a via the bit line contact pattern DC. The lower surface of the bit line contact pattern DC may be located at a level lower than the level of the upper surface of the substrate 101 and at a level higher than the level of the upper surface of the word line WL. In an example embodiment, the bit line contact pattern DC may be partially disposed in a bit line contact hole 135 formed in the substrate 101 and exposing the first impurity region 105a.

[0035] The first conductive pattern 141 may include a semiconductor material, such as polysilicon. The first conductive pattern 141 may be in direct contact with the first impurity region 105a. The second conductive pattern 142 may include a metal-semiconductor compound. The metal-semiconductor compound may be a layer formed, for example, by silicided a portion of the first conductive pattern 141. For example, the metal-semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. The third conductive pattern 143 may include a metallic material such as titanium (Ti), tantalum (Ta), tungsten (W), or aluminum (Al). In the example embodiment, the number of conductive patterns included in the bit line BL, the type of material, and / or their stacking order may be varied.

[0036] The bit line capping pattern BC may include a first capping pattern 146, a second capping pattern 147, and a third capping pattern 148 sequentially stacked on a third conductive pattern 143. Each of the first to third capping patterns 146, 147, and 148 may include an insulating material, such as a silicon nitride film. The first to third capping patterns 146, 147, and 148 may be formed of different materials, and even when the first to third capping patterns 146, 147, and 148 include the same material, their boundaries may be distinct due to differences in physical properties. The thickness of the second capping pattern 147 may be less than the thickness of each of the first capping pattern 146 and the third capping pattern 148. In the example embodiment, the number of capping patterns and / or the type of material forming the bit line capping pattern BC may be varied. The bit line structure BLS may extend perpendicular to the word line WL in one direction (e.g., the Y direction). The bit line structure BLS may include a bit line BL and the bit line capping pattern BC on the bit line BL. Bitline structure (BLS) can be set on the cell array region (CAR).

[0037] The pseudo bitline structure BL_D can extend in a direction parallel to the direction in which the bitline structure BLS extends (e.g., in the Y direction). The pseudo bitline structure BL_D can be disposed on the connection region IR. Except that the pseudo bitline structure BL_D has a larger width in the X direction than the bitline structure BLS, the pseudo bitline structure BL_D can have a structure similar to the bitline structure BLS.

[0038] Bit line BL may include a first conductive pattern 141, a second conductive pattern 142, and a third conductive pattern 143 stacked sequentially. A bit line capping pattern BC may be disposed on the third conductive pattern 143. A buffer insulating layer 128 may be disposed between the first conductive pattern 141 and the substrate 101, and a portion of the first conductive pattern 141 (hereinafter, the bit line contact pattern DC) may contact a first impurity region 105a of the active region ACT. Bit line BL may be electrically connected to the first impurity region 105a via the bit line contact pattern DC. The lower surface of the bit line contact pattern DC may be located at a level lower than the level of the upper surface of the substrate 101 and at a level higher than the level of the upper surface of the word line WL. In an example embodiment, the bit line contact pattern DC may be partially disposed in a bit line contact hole 135 formed in the substrate 101 and exposing the first impurity region 105a.

[0039] The first conductive pattern 141 may include a semiconductor material such as polycrystalline silicon. The first conductive pattern 141 may be in direct contact with the first impurity region 105a. The second conductive pattern 142 may include a metal-semiconductor compound. The metal-semiconductor compound may be a layer formed, for example, by silicided a portion of the first conductive pattern 141. For example, the metal-semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. The third conductive pattern 143 may include a metallic material such as titanium (Ti), tantalum (Ta), tungsten (W), or aluminum (Al). In the example embodiment, the number of conductive patterns included in the bit line BL, the type of material, and / or their stacking order may be varied.

[0040] The bit line capping pattern BC may include a first capping pattern 146, a second capping pattern 147, and a third capping pattern 148 sequentially stacked on a third conductive pattern 143. Each of the first to third capping patterns 146, 147, and 148 may include an insulating material, such as a silicon nitride film. The first to third capping patterns 146, 147, and 148 may be formed of different materials, and even when the first to third capping patterns 146, 147, and 148 comprise the same material, their boundaries may be clearly defined due to differences in physical properties. The thickness of the second capping pattern 147 may be less than the thickness of each of the first capping pattern 146 and the third capping pattern 148. In the example embodiment, the number of capping patterns and / or the type of material forming the bit line capping pattern BC may be varied.

[0041] Spacer structures SS may be disposed on two sidewalls of each of the bit line structures BLS and may extend in one direction (e.g., the Y direction). Spacer structures SS may be disposed between the bit line structures BLS and the lower conductive pattern 150. Spacer structures SS may be configured to extend along the sidewalls of the bit line BL and the bit line capping pattern BC. A pair of spacer structures SS disposed on opposite sides of the bit line structure BLS may have an asymmetrical shape relative to the bit line structure BLS. Each spacer structure SS may include multiple spacer layers, and in an example embodiment, each spacer structure SS may also include air spacers. The semiconductor device 100 may also include a gate insulating pattern 154 between the spacer structures SS. The gate insulating pattern 154 may include silicon nitride or silicon oxynitride.

[0042] The semiconductor device 100 may further include a pseudo spacer structure SS_D, which is disposed on one side of the pseudo bit line structure BL_D and on the side surface of the pseudo gate structure GS_D. Each pseudo spacer structure SS_D may include multiple spacer layers, and in an example embodiment, each pseudo spacer structure SS_D may further include an air spacer.

[0043] The lower conductive pattern 150 can be connected to a region of the active region ACT, such as the second impurity region 105b. The lower conductive pattern 150 can be disposed between the bit line BL and the word line WL. The lower conductive pattern 150 can penetrate the buffer insulating layer 128 and can be connected to the second impurity region 105b of the active region ACT. The lower conductive pattern 150 can be in direct contact with the second impurity region 105b. The lower surface of the lower conductive pattern 150 can be located at a level lower than the upper surface of the substrate 101 and at a level higher than the lower surface of the bit line contact pattern DC. The lower conductive pattern 150 can be insulated from the bit line contact pattern DC by a spacer structure SS. The lower conductive pattern 150 can be formed of a conductive material and can include at least one of, for example, polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In an example embodiment, the lower conductive pattern 150 may include multiple layers.

[0044] A metal-semiconductor compound layer 155 may be disposed between the lower conductive pattern 150 and the first upper conductive pattern 160c. When the lower conductive pattern 150 includes a semiconductor material, the metal-semiconductor compound layer 155 may be formed, for example, by silicided a portion of the lower conductive pattern 150. The metal-semiconductor compound layer 155 may include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. In an example embodiment, the metal-semiconductor compound layer 155 may not be disposed.

[0045] A first upper conductive pattern 160c may be disposed on the lower conductive pattern 150 in the cell array region CAR. The first upper conductive pattern 160c may extend between spacer structures SS and may cover the upper surface of the metal-semiconductor compound layer 155. A second upper conductive pattern 160p1 and a third upper conductive pattern 160p2 may be disposed on the connection region IR and the peripheral circuit region PCR. The upper surfaces of the first to third upper conductive patterns 160c, 160p1 and 160p2 may be disposed at substantially the same level. Each of the upper conductive patterns 160c, 160p1 and 160p2 may include a barrier layer 162 and a conductive layer 164. The barrier layer 162 may cover the lower surface and side surface of the conductive layer 164. The barrier layer 162 may include at least one of a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN)). The conductive layer 164 may include at least one of the following conductive materials: polycrystalline silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)).

[0046] Contact plug 160cp1 can be connected to the end EP of word line WL. Contact plug 160cp1 can be disposed in connection area IR. The end EP of word line WL can provide an end surface ES exposed in the extension direction of word line WL (i.e., the first direction X), and contact plug 160cp1 can be configured to overlap with the end EP of word line WL in the vertical direction Z.

[0047] The dummy structure DS can penetrate at least a portion of the insulating structures 152, 156, and 158 in the connection region IR. For example, the dummy structure DS can be formed in the open region penetrating the insulating structures 152, 156, and 158. Figure 16A "OR2a" and Figure 16B In “OR2b”, the pseudostructure DS may include a first pseudostructure DS1 disposed between adjacent word line structures WLS and a second pseudostructure DS2 that vertically overlaps with the word line structures WLS. Alternatively, the first pseudostructure DS1 may be defined as a pseudostructure that does not vertically overlap with the word line structures WLS. The pseudostructures DS may be spaced apart from each other in the Y direction, and each pseudostructure DS may be aligned in the Y direction.

[0048] The distance d1 between the first pseudostructure DS1 and the second pseudostructure DS2, which are closest to each other in the Y direction, can be greater than or approximately equal to the distance d2 between the bit line structures BL, which are adjacent to each other in the X direction.

[0049] The first pseudo-structure DS1 may penetrate the interlayer insulation layers 156 and 158 and the insulating pad 152 on one side of the pseudo-bit line structure BL_D. The upper surface of the first pseudo-structure DS1 may be at substantially the same level as the upper surface of the interlayer insulation layer 158. The upper surface of the first pseudo-structure DS1 may be at a higher level than the upper surface of the pseudo-bit line structure BL_D. The lower surface of the first pseudo-structure DS1 may be at a lower level than the lower surface of the pseudo-bit line structure BL_D. At least a portion of the first pseudo-structure DS1 may penetrate the buffer insulation layer 128 and the connection device isolation region 110I.

[0050] The first pseudostructure DS1 may also include structures set in the open region ( Figure 16AThe pseudo-spacer structure SS' on the sidewall of the "OR2a" in the diagram, and pseudo-conductive patterns 150', 155', and 164' filling other portions of the open region. Pseudo-conductive patterns 150', 155', and 164' may include a lower pseudo-conductive pattern 150', a pseudo-metal-semiconductor compound layer 155' on the lower pseudo-conductive pattern 150', and a pseudo-conductive layer 164' on the pseudo-metal-semiconductor compound layer 155'. At least a portion of the lower pseudo-conductive pattern 150' penetrates the connection device isolation region 110I, and other portions of the lower pseudo-conductive pattern 150' are surrounded by the first pseudo-spacer structure SS'. Alternatively, the first pseudo-spacer structure SS' may surround the sidewalls of the pseudo-conductive patterns 150', 155', and 164'. The lower surface of the lower pseudo-conductive pattern 150' may be at a lower level than the lower surface of the pseudo-bit line structure BL_D.

[0051] The first pseudo-structure DS1 may further include a barrier layer 162' disposed between the first pseudo-spacer structure SS' and the pseudo-conductive layer 164'. The barrier layer 162' may cover the upper surface of the pseudo-metal-semiconductor compound layer 155'.

[0052] At least one of the first pseudo-spacer structures SS' on the connecting region IR and the spacer structure SS on the cell array region CAR can be at substantially the same level. At least one of the first pseudo-spacer structures SS' and the spacer structure SS can comprise substantially the same material.

[0053] The lower pseudo-conductive pattern 150' on the connection region IR and the lower conductive pattern 150 on the cell array region CAR can be at substantially the same level. The lower pseudo-conductive pattern 150' and the lower conductive pattern 150 can comprise substantially the same material.

[0054] The pseudo-metal-semiconductor compound layer 155' on the connection region IR and the metal-semiconductor compound layer 155 on the cell array region CAR can be at substantially the same level. The pseudo-metal-semiconductor compound layer 155' and the metal-semiconductor compound layer 155 can comprise substantially the same material.

[0055] The pseudo-conductive layer 164' on the connection region IR and the conductive layer 164 on the cell array region CAR can be at substantially the same level. The pseudo-conductive layer 164' and the conductive layer 164 can comprise substantially the same material.

[0056] The semiconductor device 100 may also include an interlayer insulating layer 159 disposed on interlayer insulating layers 156 and 158 in the connection region IR and the peripheral circuit region PCR. The interlayer insulating layer 159 may be disposed on the upper part of the first pseudostructure DS1.

[0057] The second pseudo-structure DS2 can be aligned with the first pseudo-structure DS1 in the Y direction. The second pseudo-structure DS2 can penetrate the interlayer insulation layers 156 and 158 and the insulating gasket 152 between the pseudo-bit line structure BL_D and the contact plug 160cp1. The upper surface of the second pseudo-structure DS2 can be substantially at the same level as the upper surface of the interlayer insulation layer 158. The upper surface of the second pseudo-structure DS2 can be at a higher level than the upper surface of the pseudo-bit line structure BL_D. The lower surface of the second pseudo-structure DS2 can be substantially at the same level as the lower surface of the pseudo-bit line structure BL_D.

[0058] The second pseudostructure DS2 may also include structures set in the open area ( Figure 16B The second pseudo spacer structure SS” on the sidewall of “OR2b” and the pseudo insulating pattern 154’ filling the other part of the open area. On the other hand, the second pseudo spacer structure SS” may surround the sidewall of the pseudo insulating pattern 154’.

[0059] The second pseudo-spacer structure SS” on the connecting region IR may be at a higher level than the spacer structure SS on the cell array region CAR. For example, the upper surface of the second pseudo-spacer structure SS” may be at a higher level than the upper surface of the spacer structure SS. At least one of the spacer structures SS and the second pseudo-spacer structure SS” may comprise substantially the same material.

[0060] The dummy insulating pattern 154' on the connection region IR may be at a higher level than the fence insulating pattern 154 on the cell array region CAR. For example, the upper surface of the dummy insulating pattern 154' may be at a higher level than the upper surface of the fence insulating pattern 154. The lower surfaces of each of the dummy insulating pattern 154' and the fence insulating pattern 154 may be substantially at the same level. The dummy insulating pattern 154' and the fence insulating pattern 154 may comprise substantially the same material.

[0061] At least a portion of the first pseudostructure DS1 and at least a portion of the second pseudostructure DS2 may be substantially at the same level. For example, the upper surface of the first pseudostructure DS1 and the upper surface of the second pseudostructure DS2 may be substantially at the same level. The lower surface of the first pseudostructure DS1 and the lower surface of the second pseudostructure DS2 may be substantially at the same level.

[0062] In the planar diagram, the first pseudo-structure DS1 and the second pseudo-structure DS2 may have a quadrilateral shape, but the exemplary embodiments are not limited thereto. For example, in the planar diagram, at least one of the first pseudo-structures DS1 and / or at least one of the second pseudo-structures DS2 may have a polygonal shape including triangles, pentagons, etc.

[0063] The peripheral contact plug 160cp2 can penetrate the first interlayer insulating layer 156 and the second interlayer insulating layer 158 and the insulating pad 152 in the peripheral circuit region PCR, and can be connected to the peripheral source / drain region 30. A peripheral metal-semiconductor compound layer 35 can be disposed between the peripheral contact plug 160cp2 and the peripheral source / drain region 30. The peripheral contact plug 160cp2 can be connected to the third upper conductive pattern 160p2 and can be integrated with the third upper conductive pattern 160p2.

[0064] The insulating pattern 165 may be configured to penetrate the upper conductive patterns 160c, 160p1, and 160p2. The upper conductive patterns 160c, 160p1, and 160p2 may be divided into multiple portions by the insulating pattern 165. The insulating pattern 165 may include at least one of the insulating materials (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

[0065] A peripheral gate structure GS can be disposed on the peripheral active region ACT_P within the peripheral circuit region PCR. The peripheral gate structure GS may include a peripheral gate dielectric layer 40, peripheral gate electrodes 41, 42, and 43, and a peripheral gate capping layer 46, which are sequentially stacked. An insulating pad 152 may cover the peripheral gate structure GS. The peripheral active region ACT_P may be defined by a peripheral device isolation region 110B, which may include a first insulating pad 111 and a second insulating pad 112 comprising different materials, but exemplary embodiments are not limited thereto. The peripheral gate dielectric layer 40 may include silicon oxide, silicon nitride, or a high-κ material. A high-κ material may indicate a dielectric material with a dielectric constant higher than that of silicon oxide. The peripheral gate electrodes 41, 42, and 43 may have a structure similar to that of the bit line BL and may be formed of a material similar to that of the bit line BL, and may have a shape with a width greater than that of the bit line BL.

[0066] Figure 4 This is a plan view showing a semiconductor device 100A according to an example embodiment.

[0067] Reference Figure 4 In addition to including the construction of a first pseudo-structure DS1 and a second pseudo-structure DS2 having at least one circular shape in the plan view, the semiconductor device 100A can be configured to be consistent with the reference. Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C and Figure 3D The examples described are the same or similar.

[0068] As described above, the shapes of the first pseudo-structure DS1 and the second pseudo-structure DS2 in the planar diagram are not limited to quadrilateral shapes. For example, the shape may include polygonal shapes containing triangles, pentagons, etc., elliptical shapes, and circular shapes.

[0069] Figure 5 This is a plan view showing a semiconductor device 100B according to an example embodiment.

[0070] Reference Figure 5 Except for the pseudostructure DS, which restrictively includes references Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 4 Apart from the construction of the first pseudo-structure DS1 or the second pseudo-structure DS2 described, the semiconductor device 100B can be constructed as described in reference. Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 4 The examples described are the same or similar.

[0071] For example, the semiconductor device 100B may include, but is limited to, a pseudo-structure (e.g., DS2) that vertically overlaps with the word line structure WLS, or may include, but is limited to, a pseudo-structure (e.g., DS1) disposed between the word line structures WLS.

[0072] Figure 6 This is a plan view illustrating a semiconductor device 100C according to an example embodiment.

[0073] Figure 7A and Figure 7B This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 7A It is along Figure 6 The cross-sectional view taken from line I-I' in the diagram. Figure 7B It is along Figure 6 The cross-sectional view taken from line II-II' in the diagram.

[0074] Figure 8A and Figure 8B This is an enlarged view showing a portion of a semiconductor device according to an example embodiment. Figure 8A It is shown Figure 7A An enlarged view of region "C" in the image. Figure 8B It is shown Figure 7B An enlarged view of region "D" in the image.

[0075] Reference Figure 6 , Figure 7A , Figure 7B , Figure 8A and Figure 8B Apart from the construction where the pseudo-structure DS is formed on the pseudo-bitline structure BL_D, the example embodiment can be compared with the reference. Figures 1 to 5 The examples described are the same or similar.

[0076] The pseudo-structure DS can penetrate the pseudo-bit line structure BL_D on the connection region IR. For example, the pseudo-structure DS can be formed in the open region that penetrates the interlayer insulating layer 158, the insulating pad 152, and the pseudo-bit line structure BL_D. Figure 19A "OR2a" and Figure 19B In "OR2b").

[0077] The first pseudo-structure DS1 can penetrate the interlayer insulation layer 158, the insulating pad 152, the pseudo bit line structure BL_D, and the connection device isolation area 110I between adjacent word line structures WLS.

[0078] The upper region of the first pseudo-spacer structure SS' can be connected with the open region ( Figure 19A The insulating pad 152 and the side surface of the interlayer insulating layer 158, defined by "OR2a" in the text, are in contact. The lower region of the first pseudo spacer structure SS' can contact the open area ( Figure 19A The pseudo-bit line structure BL_D, defined by "OR2a" in the diagram, is in contact with the side surface. The lower region of the lower pseudo-conductive pattern 150' can contact the isolation region 110I of the connection device.

[0079] The second pseudo-structure DS2 can penetrate the interlayer insulation layer 158, the insulating pad 152, and the pseudo-bit line structure BL_D on the word line structure WLS. The upper region of the second pseudo-spacer structure SS” can be connected to the open area ( Figure 19B The interlayer insulation layer 158 and the insulating pad 152, defined by "OR2b" in the text, are in contact with each other, and the lower region of the second pseudo spacer structure "SS" can be connected to the open area ( Figure 19B The side surface contact of the pseudo bit line structure BL_D defined by "OR2b" in the text.

[0080] The pseudo bitline structure BL_D can have different widths in the first direction X through the pseudo structure DS. The pseudo bitline structure BL_D may include a first part p1 with a first width w1 and a second part p2 with a second width w2 that is smaller than the first width w1.

[0081] The first part p1 may include the portion of the pseudo bitline structure BL_D that is not penetrated by the pseudo structure DS in the first direction X.

[0082] The second part p2 may include the portion of the pseudo-bitline structure BL_D that is penetrated by the pseudo-structure DS in the first direction X. Alternatively, the second width w2 may be defined as the width of the pseudo-bitline structure BL_D on one side of the pseudo-structure DS in the first direction X.

[0083] For ease of description, a first part p1 and a second part p2 can be provided to describe a pseudo bitline structure BL_D with different widths. Therefore, the boundary between the first part p1 and the second part p2 may not be particularly clear, and the first part p1 and the second part p2 may be continuous.

[0084] Figure 9 This is a plan view illustrating a semiconductor device according to an example embodiment.

[0085] Figure 10A and Figure 10B This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 10A It is along Figure 9 The cross-sectional view taken from line I-I' in the diagram. Figure 10B It is along Figure 9 The cross-sectional view taken from line II-II' in the diagram.

[0086] Reference Figure 9 , Figure 10A and Figure 10B Apart from the construction of at least a portion of the pseudo-spacer structure SS_D on the sidewall of the pseudo-bit line structure BL_D through the pseudo-structure DS, the example embodiment can be compared with the reference Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8A and Figure 8B The examples described are the same or similar.

[0087] The first pseudo-structure DS1 can penetrate the interlayer insulation layer 158, the insulating pad 152, the pseudo spacer structure SS_D, and the pseudo bit line structure BL_D between adjacent word line structures WLS. In an example embodiment, the first pseudo-structure DS1 can be in contact with the pseudo spacer structure SS_D. For example, the first pseudo spacer structure SS' and the pseudo spacer structure SS_D can be in contact with each other.

[0088] The second pseudo-structure DS2 can penetrate the interlayer insulation layer 158, the insulating pad 152, the pseudo spacer structure SS_D, and the pseudo bit line structure BL_D on the word line structure WLS. In an example embodiment, the second pseudo-structure DS2 can contact the pseudo spacer structure SS_D. For example, the second pseudo spacer structure SS_D and the pseudo spacer structure SS_D can contact each other.

[0089] At least one of the insulating patterns 165 may penetrate at least a portion of the second pseudo-structure DS2. For example, at least one of the insulating patterns 165 may penetrate the upper region of the pseudo-insulating pattern 154' and the second pseudo-spacer structure SS".

[0090] Figure 11 This is a plan view showing a semiconductor device 100E according to an example embodiment.

[0091] Figure 12A and Figure 12B This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 12A It is along Figure 11 The cross-sectional view taken from line I-I' in the diagram. Figure 12B It is along Figure 11 The cross-sectional view taken from line II-II' in the diagram.

[0092] Reference Figure 11 , Figure 12A and Figure 12B The semiconductor device 100E may include a plurality of pseudo-structure groups DSG spaced apart from each other in a first direction X.

[0093] Multiple pseudo-structure groups DSG can include the first pseudo-structure group to the third pseudo-structure group DSG1, DSG2 and DSG3.

[0094] Each of the first to third pseudostructure groups DSG1, DSG2, and DSG3 may include a reference. Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9 , Figure 10A and Figure 10B The first pseudostructure DS1 and the second pseudostructure DS2 are described. The first pseudostructure group to the third pseudostructure group DSG1, DSG2 and DSG3 can be spaced apart from each other along the first direction X in the connection region IR.

[0095] At least a portion of the plurality of pseudo-structure groups DSGs may vertically overlap with the pseudo-bitline structure BL_D. Alternatively, a portion of the plurality of pseudo-structure groups DSGs may be spaced apart from the pseudo-bitline structure BL_D. In another embodiment, this portion of the plurality of pseudo-structure groups DSGs may not vertically overlap with the pseudo-bitline structure BL_D.

[0096] For example, the first pseudo-structure group DSG1 can be formed on the pseudo-bitline structure BL_D, similar to the reference. Figure 6 , Figure 7A , Figure 7B , Figure 8A and Figure 8B The pseudo-structure DS is described.

[0097] The second pseudo-structure group DSG2 can penetrate at least a portion of the pseudo-spacer structure SS_D on the sidewall of the pseudo-bit line structure BL_D, similar to the reference. Figure 9 , Figure 10A and Figure 10B The pseudo-structure DS is described.

[0098] At least a portion of the third pseudo-structure group DSG3 can penetrate the insulating structures 152, 156, and 158 and the connecting device isolation region 110I on one side of the pseudo-bit line structure BL_D, similar to the reference. Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C and 3D The first pseudostructure described is DS1.

[0099] A portion of the third pseudo-structure group DSG3 can penetrate insulating structures 152, 156, and 158 between the pseudo bit line structure BL_D and the contact plug 160cp1, similar to the reference. Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C and 3D The second pseudostructure DS2 is described.

[0100] Figure 13 This is a plan view illustrating a semiconductor device according to an example embodiment.

[0101] Figure 14A and Figure 14B This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 14A It is along Figure 13 The cross-sectional view taken from line I-I' in the diagram. Figure 14B It is along Figure 13 The cross-sectional view taken from line II-II' in the diagram.

[0102] Reference Figure 13 , Figure 14A and Figure 14B In addition to including a pseudostructure DS having a width greater than that of the pseudo bit line structure BL_D in the first direction X, the semiconductor device 100F can be configured to be similar to the reference. Figures 1 to 12B The examples described are the same or similar.

[0103] The first pseudo-structure DS1 can penetrate the interlayer insulation layers 156 and 158, the insulating pad 152, and the pseudo bit line structure BL_D between adjacent word line structures WLS.

[0104] In an example embodiment, the two side surfaces s1 and s2 of the first pseudo-structure DS1, which are opposite to each other in the first direction X, can be defined in different regions. The first side s1 may be defined on the pseudo bit line structure BL_D, and the second side s2 may be defined on the insulating structures 152, 156, and 158 beyond the pseudo bit line structure BL_D. The first side may point to the bit line structure BLS, and the second side s2 may point to the pseudo gate structure GS_D.

[0105] In the example embodiment, the widths of the pseudo conductive patterns 150', 155', and 164' on the connection region IR can be greater than the widths of the conductive patterns 150, 155, and 164 on the cell array region CAR, respectively.

[0106] The second pseudo-structure DS2 can penetrate the interlayer insulation layers 156 and 158, the insulating pad 152, and the pseudo bit line structure BL_D on the word line structure WLS.

[0107] In an example embodiment, a first side of the second pseudo-structure DS2 may be defined on the pseudo bit line structure BL_D, and a second side opposite to the first side may extend beyond the pseudo bit line structure BL_D and be defined on insulating structures 152, 156, and 158. The first side may be adjacent to the bit line structure BLS, and the second side may be adjacent to the contact plug 160cp1. The first side of the first pseudo-structure DS1 and the first side of the second pseudo-structure DS2 may be aligned, and the second side of the first pseudo-structure DS1 and the second side of the second pseudo-structure DS2 may be aligned.

[0108] In the example embodiment, the width of the pseudo-insulation pattern 154' on the connection region IR can be greater than the width of the fence insulation pattern 154 on the cell array region CAR.

[0109] Figure 15 This is a plan view illustrating a semiconductor device 100G according to an example embodiment.

[0110] Reference Figure 15 Apart from the construction including the pseudo-structure DS extending diagonally, the semiconductor device 100G can be constructed as a reference. Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9 , Figure 10A , Figure 10B , Figure 11 , Figure 12A , Figure 12B , Figure 13 , Figure 14A and Figure 14B The examples described are the same or similar.

[0111] and Figure 13 , Figure 14A and Figure 14B Compared to the pseudo-structure DS of the semiconductor device 100F, Figure 15 At least one of the pseudo-structures DS of the semiconductor device 100G can have a structure that extends in a diagonal direction.

[0112] Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A and 17B as well as Figure 18A , Figure 18B , Figure 18C and 18D This is a cross-sectional view illustrating the process of sequentially manufacturing a semiconductor device according to an example embodiment.

[0113] Reference Figure 1 , Figure 2A , Figure 2B , Figure 16A , Figure 16B , Figure 16C and Figure 16DBy forming a device isolation region 110 on substrate 101, a cell active region ACT can be defined in the cell array region CAR, a pseudo active region ACT_D can be defined in the connection region IR, and a peripheral active region ACT_P can be defined in the peripheral circuit region PCR. Device isolation trenches can be formed on substrate 101, and the device isolation region 110 can fill the device isolation trenches. In a plan view, the active region ACT may have a stripe extending in the W direction. The device isolation region 110 can be used as an ion implantation mask to perform an ion implantation process, thereby forming an impurity region on top of the active region ACT. Gate trenches 115 can be formed by patterning the active region ACT and the device isolation region 110. A pair of gate trenches 115 may intersect with the active region ACT, but exemplary embodiments are not limited thereto. Impurity regions can also be isolated by the gate trenches 115, and a first impurity region 105a and a second impurity region 105b can be formed.

[0114] A gate dielectric layer 120 can be formed on the inner surface of the gate trench 115 with a substantially conformal thickness. Subsequently, a lower pattern 121 and an upper pattern 122 can be formed to fill the gate trench 115, and a word line WL can be formed by partially etching the upper portion of the upper pattern 122. The upper surface of the word line WL can be recessed to a level lower than the upper surface of the active region ACT. The gate trench 115 can be filled by stacking an insulating layer on the substrate 101, and this layer can be etched to form a gate capping layer 125 on the word line WL.

[0115] Insulating and conductive layers can be sequentially formed on the entire surface of substrate 101, and the insulating and conductive layers can be patterned to form sequentially stacked buffer insulating layers 128 and first conductive patterns 141. Buffer insulating layers 128 can be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride. Multiple buffer insulating layers 128 can be spaced apart from each other. The first conductive pattern 141 can have a shape corresponding to the planar shape of the buffer insulating layers 128. Buffer insulating layers 128 can be formed to simultaneously cover the ends of two adjacent active regions ACT, i.e., the ends of adjacent second impurity regions 105b. The buffer insulating layers 128 and the first conductive pattern 141 can be used as an etching mask to etch the upper portion of the device isolation region 110, substrate 101, and gate capping layer 125, thereby forming bit line contact holes 135. Bit line contact holes 135 can expose the first impurity region 105a.

[0116] A bit line contact pattern DC can be formed to fill the bit line contact hole 135. Forming the bit line contact pattern DC may include forming a conductive layer to fill the bit line contact hole 135 and performing a planarization process. For example, the bit line contact pattern DC may be formed from polysilicon. A second conductive pattern 142, a third conductive pattern 143, and first capping patterns to third capping patterns 146, 147, and 148 may be sequentially formed on the first conductive pattern 141.

[0117] A peripheral transistor can be formed in the peripheral circuit region PCR. The peripheral transistor may include a peripheral gate structure GS and a peripheral source / drain region 30. A peripheral gate spacer structure SS_P may be formed on the side surface of the peripheral gate structure GS. The peripheral gate structure GS may be formed using the same process as forming the bit line BL, but exemplary embodiments thereof are not limited thereto. An insulating pad 152, a first interlayer insulating layer 156, and a second interlayer insulating layer 158 covering the peripheral transistor may be formed. Each of the insulating pad 152, the first interlayer insulating layer 156, and the second interlayer insulating layer 158 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0118] The first conductive pattern to the third conductive pattern 141, 142 and 143 can be sequentially etched using an etching process with the first to third capping patterns 146, 147 and 148 as etching masks. Thus, the first open area OR1 can be formed.

[0119] Each of the first open regions OR1 may extend along the second direction Y, and the first open regions OR1 may be spaced apart from each other in the first direction X.

[0120] The first open region OR1 may define the side surface of the bit line structure BLS. The bit line structure BLS may include a bit line BL and a bit line capping pattern BC. The bit line BL includes first conductive patterns to third conductive patterns 141, 142 and 143, and the bit line capping pattern BC includes first capping patterns to third capping patterns 146, 147 and 148.

[0121] The first open region OR1 may include the 1-1 open region OR1a between word line structures WL (see...). Figure 16A The first open region OR1 may include 1-2 open regions OR1b that vertically overlap with each word line structure WL (see...). Figure 16B ).

[0122] In the connection region IR, a pseudo bit line structure BL_D (or pseudo bit line) can be formed.

[0123] After the etching process, the upper surface levels of the third capping pattern 148 and the second interlayer insulating layer 158 may differ from each other. From different perspectives, the initial semiconductor device that has undergone the etching process may have a step difference Sd between the cell array region CAR and the connection region IR. The step difference Sd may be caused by multiple first open regions OR1 formed on the cell array region CAR. The step difference Sd may negatively affect the accuracy and flatness of subsequent processes, which may reduce the reliability of the final semiconductor device.

[0124] According to the example embodiment, the etching process may further include etching the first interlayer insulating layer 156 and the second interlayer insulating layer 158 to form a second open region OR2. Therefore, the process environment differences between the cell array region CAR and the connection region IR caused by the step difference Sd can be mitigated, and similar process conditions can be created between the two regions. In the example embodiment, the first open region OR1 and the second open region OR2 may be collectively referred to as multiple open regions. The first open region OR1 and the second open region OR2 can be formed by the same process (i.e., the same etching process).

[0125] The second open area OR2 can penetrate the insulating pad 152, the first interlayer insulation layer 156, and the second interlayer insulation layer 158. The second open area OR2 may include the 2-1 open area OR2a between the word line structures WL (see...). Figure 16A The second open area OR2 may include a 2-2 open area OR2b that vertically overlaps with the word line structure WL (see [link]). Figure 16B The second open area OR2 can be spaced apart and aligned in the second direction Y.

[0126] Reference Figure 1 , Figure 2A , Figure 2B , Figure 17A and Figure 17B The spacer structure SS and the fence insulation pattern 154 can be formed in the first open region OR1 and the second open region OR2. Therefore, the second pseudo-structure DS2 can be defined.

[0127] The spacer structure SS may be formed on the side surface of the bit line structure BLS defined by the first open region OR1. The spacer structures SS (i.e., SS' and SS) may also be formed in the second open region OR2. The spacer structure SS may include multiple layers.

[0128] The fence insulation pattern 154 may be formed between the spacer structures SS. The fence insulation pattern 154 may comprise silicon nitride or silicon oxynitride. The fence insulation pattern 154 may also be formed in the second open region OR2, and in this case, for ease of description, the fence insulation pattern 154 may be referred to as the pseudo insulation pattern 154'.

[0129] The spacer structure SS and pseudo-insulation pattern 154' formed in the 2-2 open region OR2b within the second open region OR2 can be defined as the second pseudo-structure DS2.

[0130] Subsequently, step difference removal can be optionally performed. Figure 16A and Figure 16B The planarization process of “Sd” in the text.

[0131] Reference Figure 1 , Figure 2A , Figure 2B , Figure 18A , Figure 18B , Figure 18C and Figure 18D An anisotropic etching process can be performed using a fence insulating pattern 154 and a third capping pattern 148 as etching masks to form a first opening OP1 that exposes the second impurity region 105b. The anisotropic etching process may include using a pseudo insulating pattern 154' as an etching mask to form a second opening OP2 that exposes the connection device isolation region 110I.

[0132] The first opening OP1 and the second opening OP2 can be formed between the word line structures WLS. On the other hand, the first opening OP1 can correspond to the 1-1 open area OR1a, and the second opening OP2 can correspond to the 2-1 open area OR2a.

[0133] Conductive material can be formed on the lower part of each of the first opening OP1 and the second opening OP2. A lower conductive pattern 150 can be formed on the lower part of the first opening OP1, and a lower pseudo-conductive pattern 150' can be formed on the lower part of the second opening OP2.

[0134] Metal-semiconductor compounds can be formed on conductive materials. A metal-semiconductor compound layer 155 can be formed on the lower conductive pattern 150, and a pseudo-metal-semiconductor compound layer 155' can be formed on the lower pseudo-conductive pattern 150'.

[0135] A first contact hole Ha can be formed that penetrates the first interlayer insulation layer 156 and the second interlayer insulation layer 158, the insulating pad 152 and the buffer insulation layer 128, and exposes the word line WL. The lower part of the first contact hole Ha can expose the word line WL.

[0136] A second contact hole Hb can be formed that penetrates the insulating pad 152, the first interlayer insulating layer 156, and the second interlayer insulating layer 158, exposing the peripheral source / drain region 30 on the peripheral transistor. The first contact hole Ha and the second contact hole Hb can be formed by the same process (i.e., the same etching process).

[0137] Refer to together Figure 3A and Figure 3B A barrier layer 162 and a conductive layer 164 can be sequentially deposited in the first opening OP1 and the second opening OP2, as well as in the first contact hole Ha and the second contact hole Hb. Therefore, a first upper conductive pattern 160c can be formed in the first opening OP1, and a first dummy structure DS1 can be formed in the second opening OP2. A contact plug 160cp1 can be formed in the first contact hole Ha, and a peripheral contact plug 160cp2 can be formed in the second contact hole Hb. The contact plug 160cp1 and the peripheral contact plug 160cp2 can be formed simultaneously.

[0138] The conductive layer formed on the interlayer insulating layer 158 and the first pseudostructure DS1 in the conductive layer 164 can be selectively removed, and an insulating material can be deposited to form the interlayer insulating layer 159.

[0139] Subsequently, a patterning process can be performed on the barrier layer 162 and the conductive layer 164 to form an insulating pattern 165 that penetrates these layers. Then, a capacitor structure including a lower electrode, a capacitor dielectric layer, and an upper electrode can be formed on the first upper conductive pattern 160c.

[0140] Figure 19A and Figure 19B , Figure 20A and Figure 20B as well as Figure 21A and Figure 21B This is a cross-sectional view illustrating the process of sequentially manufacturing a semiconductor device according to an example embodiment.

[0141] Reference Figure 6 , Figure 7A , Figure 7B , Figure 19A and Figure 19B The first open region OR1 can be formed by sequentially etching the first conductive pattern to the third conductive pattern 141, 142, and 143 using the first to third capping patterns 146, 147, and 148 as etching masks through an etching process. The second open region OR2 can be formed by sequentially etching the interlayer insulating layer 158, the insulating pad 152, and the pseudo bit line structure BL_D. The first open region OR1 and the second open region OR2 can be formed using the same process (i.e., the same etching process).

[0142] The first open zone OR1 can be compared with the reference. Figure 16A , Figure 16B , Figure 16C and Figure 16D The first open region OR1 is essentially the same or similar, so its detailed description is not required.

[0143] Through the second open region OR2, the pseudo bitline structure BL_D can have different widths. (See also...) Figure 6 The pseudo-bitline structure BL_D may have a first width w1. Through the second open region OR2, a portion of the pseudo-bitline structure BL_D may have a second width w2 that is smaller than the first width w1. The second width w2 may be the width of the pseudo-bitline structure BL_D on one side of the second open region OR2 in the first direction X.

[0144] The second open region OR2 may include the 2-1 open region OR2a between word line structures WL (see...). Figure 19A The second open area OR2 may include 2-2 open areas OR2b that vertically overlap with the word line structure WL (see...). Figure 19B The second open area OR2 can be spaced apart and aligned in the second direction Y.

[0145] Reference Figure 6 , Figure 7A , Figure 7B , Figure 20A and Figure 20B The spacer structure SS and the fence insulation pattern 154 can be formed in the first open region OR1 and the second open region OR2. Therefore, the second pseudo-structure DS2 can be defined.

[0146] The spacer structure SS may be formed on the side surface of the bit line structure BLS defined by the first open region OR1. The spacer structures SS (i.e., SS' and SS) may also be formed in the second open region OR2. The spacer structure SS may include multiple layers.

[0147] A fence insulation pattern 154 may be formed between the spacer structures SS. The fence insulation pattern 154 may include silicon nitride or silicon oxynitride. The fence insulation pattern 154 may also be formed in the second open area OR2, and in this case, for ease of description, the fence insulation pattern 154 may be referred to as the pseudo insulation pattern 154'.

[0148] The spacer structure SS and pseudo-insulation pattern 154' formed in the 2-2 open region OR2b within the second open region OR2 can be defined as the second pseudo-structure DS2.

[0149] Subsequently, optional steps can be performed to remove step differences ( Figure 19A and Figure 19B The planarization process of “Sd” in the text.

[0150] Reference Figure 6 , Figure 7A , Figure 7B , Figure 21A and Figure 21BAn anisotropic etching process can be performed using the fence insulating pattern 154 and the third capping pattern 148 as etching masks to form a first opening OP1 that exposes the second impurity region 105b. The anisotropic etching process can use the pseudo insulating pattern 154' as an etching mask to form a second opening OP2 that exposes the connection device isolation region 110I.

[0151] A first opening OP1 and a second opening OP2 may be formed between word line structures WLS. On the other hand, the first opening OP1 may correspond to a 1-1 open area OR1a, and the second opening OP2 may correspond to a 2-1 open area OR2a.

[0152] Conductive material can be formed on the lower part of each of the first opening OP1 and the second opening OP2. A lower conductive pattern 150 can be formed in the lower part of the first opening OP1, and a lower pseudo-conductive pattern 150' can be formed in the lower part of the second opening OP2.

[0153] Metal-semiconductor compounds can be formed on conductive materials. A metal-semiconductor compound layer 155 can be formed on the lower conductive pattern 150, and a pseudo-metal-semiconductor compound layer 155' can be formed on the lower pseudo-conductive pattern 150'.

[0154] A first contact hole Ha can be formed that penetrates the first interlayer insulation layer 156, the second interlayer insulation layer 158, the insulating pad 152, and the buffer insulation layer 128, exposing the word line WL. The lower part of the first contact hole Ha can expose the word line WL.

[0155] A second contact hole Hb can be formed on the peripheral transistor, penetrating the insulating pad 152, the first interlayer insulating layer 156, and the second interlayer insulating layer 158, and exposing the peripheral source / drain region 30. The first contact hole Ha and the second contact hole Hb can be formed by the same process (i.e., the same etching process).

[0156] Refer to together Figure 7A and Figure 7B A barrier layer 162 and a conductive layer 164 can be sequentially deposited in the first opening OP1, the second opening OP2, the first contact hole Ha, and the second contact hole Hb. Therefore, a first upper conductive pattern 160c can be formed in the first opening OP1, and a first dummy structure DS1 can be formed in the second opening OP2. A contact plug 160cp1 can be formed in the first contact hole Ha. (Similar to reference...) Figure 18D The example described can be found in the second contact hole ( Figure 18D The peripheral contact plug 160cp2 is formed in the "Hb" of the middle part. The contact plug 160cp1 and the peripheral contact plug 160cp2 can be formed simultaneously.

[0157] The conductive layer formed on the interlayer insulating layer 158 and the first pseudostructure DS1 in the conductive layer 164 can be selectively removed, and an insulating material can be deposited to form the interlayer insulating layer 159.

[0158] Subsequently, by performing a patterning process on the barrier layer 162 and the conductive layer 164, an insulating pattern 165 that penetrates these layers can be formed. Then, a capacitor structure including a lower electrode, a capacitor dielectric layer, and an upper electrode can be formed on the first upper conductive pattern 160c.

[0159] Based on the above example embodiments, a semiconductor device and a method for manufacturing the same can be provided that have improved reliability and performance.

[0160] In addition, semiconductor devices that include pseudostructures on the connection region can be provided.

[0161] According to an example embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region; forming a device isolation region on the substrate, the device isolation region including a cell device isolation region defining a cell active region on the cell array region and a connection device isolation region defining an active region on the connection region; forming a gate structure including a gate electrode extending in the cell array region in a first direction intersecting the cell active region and extending into the connection region, the gate structures being spaced apart from each other in a second direction substantially perpendicular to the first direction; forming a stacked structure on the substrate including a conductive material layer and an insulating material layer on the conductive material layer; patterning the stacked structure and forming a plurality of open regions, a bit line structure, and a pseudo bit line structure extending in the second direction intersecting the gate structure, the plurality of open regions including a first open region on the side surface of the upper limit bit line structure of the cell array region and a second open region penetrating the pseudo bit line structure in the connection region; and forming a pseudo structure in the second open region.

[0162] The second open region may include a 2-1 open region between the gate structures and a 2-2 open region that vertically overlaps with each gate structure.

[0163] The 2-1 open area and the 2-2 open area can be spaced apart from each other and aligned in the second direction.

[0164] Forming a pseudostructure may include: forming a first pseudostructure in the 2-1 open region; and forming a second pseudostructure in the 2-2 open region.

[0165] Forming the first pseudo-structure may include: forming a first pseudo-spacer structure on the sidewall of the open region 2-1; and forming a pseudo-insulating material layer covering the first pseudo-spacer structure in the open region 2-1.

[0166] The upper surface of the first pseudostructure can be at a higher level than the upper surface of the pseudo-position line structure.

[0167] Forming the second pseudo-structure may include: forming a second pseudo-spacer structure on the sidewall of the 2-2 open region; and forming at least one conductive material layer in the 2-2 open region.

[0168] The upper surface of the second pseudostructure can be at a higher level than the upper surface of the pseudo-position line structure.

[0169] In the plan view, the first open area and the second open area may have at least one of polygonal and circular shapes.

[0170] The method may also include forming a gate contact plug connected to the gate electrode and an upper conductive pattern on the gate contact plug in the connection region.

[0171] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region; A device isolation region includes a unit device isolation region and a connection device isolation region on the substrate, wherein the unit device isolation region defines a unit active region on the unit array region, and the connection device isolation region defines an active region on the connection region; A gate structure comprising a gate electrode that intersects with the cell active region on the cell array region and extends into the connection device isolation region on the connection region; Bit line structure, which extends on the cell array region in a first direction intersecting with the gate structure and is connected to the cell active region; A pseudo bitline structure that extends in the first direction over the connection region and has at least a portion disposed at a level substantially the same as the level of the bitline structure; An insulating structure is disposed on the pseudo-position line structure in the connection area; as well as A pseudo-structure, which is disposed on the connection area and extends through at least a portion of the insulation structure. The pseudo-structure includes: A first pseudo-structure is disposed on the isolation area of ​​the connecting device; and The second pseudo-structure is spaced apart from the first pseudo-structure in the first direction, vertically overlaps with the gate structure, and has at least a portion disposed at a level substantially the same as the level of the bit line structure.

2. The semiconductor device according to claim 1, in: The insulating structure covers the upper part of the pseudo-position line structure, and The upper surface of each of the first pseudo-structure and the second pseudo-structure is substantially at the same level as the upper surface of the insulating structure.

3. The semiconductor device according to claim 2, wherein, The upper surface of each of the first pseudo-structure and the second pseudo-structure is at a higher level than the upper surface of the pseudo-bitline structure.

4. The semiconductor device according to claim 1, in: The active region of the unit includes a first impurity region and a second impurity region. The bit line structure is connected to the first impurity region, and The semiconductor device further includes: The lower conductive pattern connected to the second impurity region; The first upper conductive pattern on the lower conductive pattern; and A capacitor structure on the first conductive pattern.

5. The semiconductor device according to claim 4, further comprising: A gate contact plug connected to the gate electrode over the connection region; as well as The second conductive pattern is on the gate contact plug. The upper surfaces of the first and second upper conductive patterns are substantially at the same level.

6. The semiconductor device according to claim 4, wherein, The first pseudo-structure includes: Pseudo-conductive patterns; and A first pseudo-spacer structure surrounds the side surface of the pseudo-conductive pattern.

7. The semiconductor device according to claim 6, wherein, The lower surface of the lower conductive pattern and the lower surface of the pseudo conductive pattern are substantially at the same level.

8. The semiconductor device according to claim 1, further comprising: The fence insulation pattern is located on one side of the bit line structure. The second pseudo-structure includes: A pseudo-insulating pattern that extends vertically; and The second pseudo-spacer structure surrounds the side surface of the pseudo-insulating pattern, and The lower surface of the fence insulation pattern and the lower surface of the pseudo insulation pattern are substantially at the same level.

9. The semiconductor device according to claim 1, wherein, The first pseudo-structure extends through the insulating structure and into at least a portion of the isolation region of the connecting device.

10. The semiconductor device according to claim 1, wherein, The first pseudo-structure and the second pseudo-structure extend through the insulating structure and the pseudo bit line structure.

11. The semiconductor device according to claim 1, wherein, In the plan view, the pseudo-structure has at least one of a polygonal shape and a circular shape.

12. A semiconductor device, comprising: The substrate includes a cell array region having a cell active region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region; A gate structure comprising a gate electrode extending in the cell array region in a first direction intersecting the cell active region and extending into the connection region, the gate structures being spaced apart from each other in a second direction substantially perpendicular to the first direction; Bit line structure, which extends on the cell array region in the second direction intersecting with the gate structure and is connected to the cell active region; A pseudo bitline structure that extends in the second direction over the connection region; An insulating structure comprising an insulating pad and an interlayer insulating layer on the insulating pad, the insulating pad covering the upper and side portions of the pseudo-bit line structure and extending along the upper surface of the gate structure; as well as Pseudo-patterns, which are on the connecting area, The pseudo-patterns include: At least one first dummy pattern extending between the gate structures and through the insulating structure and the dummy bit line structure; and At least one second pseudo-pattern, which vertically overlaps with the gate structure and extends through the insulating structure and the pseudo bit line structure.

13. The semiconductor device according to claim 12, wherein, The at least one first pseudo-pattern and the at least one second pseudo-pattern are aligned in the second direction.

14. The semiconductor device according to claim 12, wherein, The at least one first pseudo-pattern includes: A pseudo-conductive pattern, spaced apart from the pseudo-bit line structure; and A first pseudo spacer structure surrounds the side surface of the pseudo conductive pattern and contacts the pseudo bit line structure and the insulating structure.

15. The semiconductor device according to claim 14, wherein, The lower surface of the pseudo-conductive pattern is at a lower level than the lower surface of the first pseudo-spacer structure.

16. The semiconductor device according to claim 12, wherein, The at least one second pseudo-pattern includes: A pseudo-insulating pattern that extends vertically; and A second pseudo spacer structure surrounds the side surface of the pseudo insulation pattern and contacts the pseudo position line structure and the insulation structure.

17. The semiconductor device of claim 12, further comprising: An interlayer insulating layer on the at least one first dummy pattern; An upper conductive pattern is formed on the at least one second pseudo-pattern; as well as A gate contact plug extends downward from the upper conductive pattern over the connection region and is connected to the gate electrode. The upper surface of the upper conductive pattern and the upper surface of the interlayer insulating layer are substantially at the same level.

18. The semiconductor device according to claim 12, in, The at least one first pseudo-pattern includes a plurality of first pseudo-patterns spaced apart from each other in the first direction, and The at least one second pseudo-pattern includes a plurality of second pseudo-patterns spaced apart from each other in the first direction.

19. A semiconductor device, comprising: A substrate having a cell array region with cell active regions, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region; A gate structure comprising a gate electrode extending in a first direction intersecting the cell active region and extending into the connection region on the cell array region, each of the gate structures being spaced apart from each other in a second direction substantially perpendicular to the first direction; Bit line structure, which extends in the second direction over the cell array region and is connected to the cell active region; A pseudo bitline structure that extends in the second direction over the connection region; A pseudo-structure is disposed on the connection region and penetrates the pseudo bitline structure. The pseudo bit line structure has a different width measured in the first direction along the second direction.

20. The semiconductor device of claim 19, wherein, The pseudo bitline structure includes: The first portion has a first width that is larger than the width of the bit line structure in the first direction; and The second part has a second width that is smaller than the first width.

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