Method of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming a bonded structure including a first structure and a second structure bonded to each other, the first structure including a first semiconductor substrate, the second structure including a second semiconductor substrate including a first portion adjacent to the first structure and a second portion on the first portion, the first portion including a first impurity implantation region doped with a first impurity, and the second portion including a first semiconductor region on the first impurity implantation region; forming at least one semiconductor pattern by patterning the second semiconductor substrate, the at least one semiconductor pattern including a first semiconductor pattern including the first impurity implantation region and the first semiconductor region; and forming a first source / drain region and a second source / drain region spaced apart from each other in a first direction in the first semiconductor pattern.

Description

Technical Field

[0001] The exemplary embodiments of this disclosure relate to a method for forming a bonding structure, a method for manufacturing a semiconductor device using the method, and a semiconductor device thereby manufactured. Background Technology

[0002] Studies have been conducted to reduce the size of components included in semiconductor devices and improve their performance. For example, in dynamic random access memory (DRAM), studies have been conducted on the reliable and stable fabrication of components with reduced dimensions. However, as the size of components decreases, the dispersion properties of semiconductor devices may deteriorate. Summary of the Invention

[0003] One or more exemplary embodiments of this disclosure are intended to provide a semiconductor device with improved integration density.

[0004] One or more exemplary embodiments disclosed herein are intended to provide a method for manufacturing a semiconductor device.

[0005] According to one aspect of this disclosure, a method of manufacturing a semiconductor device includes: forming a bonding structure comprising a first structure and a second structure bonded together, the first structure comprising a first semiconductor substrate, the second structure comprising a second semiconductor substrate, the second semiconductor substrate comprising a first portion adjacent to the first structure and a second portion located on the first portion, the first portion comprising a first impurity implantation region doped with a first impurity, and the second portion comprising a first semiconductor region located on the first impurity implantation region; forming at least one semiconductor pattern by patterning the second semiconductor substrate, the at least one semiconductor pattern comprising the first semiconductor pattern, the first semiconductor pattern comprising the first impurity implantation region and the first semiconductor region; and forming a first source / drain region and a second source / drain region spaced apart from each other in a first direction in the first semiconductor pattern, wherein forming the first source / drain region further comprises performing a source / drain annealing for diffusing and activating the first impurity in the first impurity implantation region in the first semiconductor pattern, and wherein the first impurity implantation region is formed into the first source / drain region by the source / drain annealing.

[0006] According to one aspect of this disclosure, a method of manufacturing a semiconductor device includes: forming a first semiconductor structure; forming a second semiconductor structure including peripheral circuitry; and forming a bonded semiconductor structure by bonding the first semiconductor structure to the second semiconductor structure, wherein forming the first semiconductor structure further includes: forming a first semiconductor pattern including a first impurity implantation region and a first semiconductor region located on the first impurity implantation region; forming a first gate structure facing a side surface of the first semiconductor pattern; forming a first source / drain region and a second source / drain region spaced apart from each other in a first direction in the first semiconductor pattern; forming a data storage structure connected to the second source / drain region; and forming a bit line connected to the first source / drain region, wherein forming the first source / drain region further includes performing source / drain annealing for diffusing and activating a first impurity in the first impurity implantation region of the first semiconductor pattern, wherein the first impurity implantation region is formed into the first source / drain region by the source / drain annealing, and wherein the second source / drain region is located in the region of the first semiconductor region.

[0007] According to one aspect of this disclosure, a method of manufacturing a semiconductor device includes: forming a semiconductor substrate, the semiconductor substrate including a first portion and a second portion located on the first portion, the first portion including a first impurity implantation region doped with a first impurity and a second impurity implantation region doped with a second impurity different from the first impurity, and the second portion including a first semiconductor region located on the first impurity implantation region and a second semiconductor region located on the second impurity implantation region; forming a plurality of semiconductor patterns by patterning the semiconductor substrate, the plurality of semiconductor patterns including a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern including the first impurity implantation region and the first semiconductor region, and the second semiconductor pattern including a second semiconductor region located on the second impurity implantation region; forming a plurality of gate structures, the plurality of gate structures including a first gate structure facing a surface of the first semiconductor pattern and a second gate structure facing a surface of the second semiconductor pattern; and forming a plurality of sources. The plurality of source / drain regions include: a first source / drain region and a second source / drain region located in the first semiconductor pattern, the first source / drain region and the second source / drain region being spaced apart from each other in a first direction; and a third source / drain region and a fourth source / drain region located in the second semiconductor pattern, the third source / drain region and the fourth source / drain region being spaced apart from each other in the first direction, wherein forming the first source / drain region and the third source / drain region includes performing source / drain annealing for diffusing and activating a first impurity in the first impurity implantation region in the first semiconductor pattern and simultaneously diffusing and activating a second impurity in the second impurity implantation region in the second semiconductor pattern, wherein the first impurity implantation region is formed into the first source / drain region by the source / drain annealing, and wherein the second impurity implantation region is formed into the third source / drain region by the source / drain annealing. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A , Figure 1B , Figure 2A and Figure 2B This is a diagram illustrating a semiconductor device according to an example embodiment; Figure 3 This is a cross-sectional view showing a semiconductor device according to one or more example embodiments; Figure 4This is a cross-sectional view showing a semiconductor device according to one or more example embodiments; Figure 5 This is a cross-sectional view showing a semiconductor device according to one or more example embodiments; Figure 6 This is a cross-sectional view showing a semiconductor device according to one or more example embodiments; Figure 7 This is a cross-sectional view showing a semiconductor device according to one or more example embodiments; Figure 8 This is a cross-sectional view showing a semiconductor device according to one or more example embodiments; Figure 9 and Figure 10 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one or more example embodiments; Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 , Figure 33 , Figure 34 , Figure 35 , Figure 36 and Figure 37 This is a diagram illustrating a method of manufacturing a semiconductor device according to one or more example embodiments; Figure 38 , Figure 39 and Figure 40 This is a diagram illustrating a method of manufacturing a semiconductor device according to one or more example embodiments; Figure 41 and Figure 42 This is a diagram illustrating a method of manufacturing a semiconductor device according to one or more example embodiments; Figure 43 and Figure 44 This is a diagram illustrating a method of manufacturing a semiconductor device according to one or more example embodiments; Figure 45 and Figure 46This is a diagram illustrating a method of manufacturing a semiconductor device according to one or more example embodiments. Detailed Implementation

[0009] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0010] In the example embodiments, terms such as "upper," "lower," "first lower," "first upper," "second lower," and "second upper" can be replaced with other terms such as "first," "second," and "third," and can be used to describe the elements in the example embodiments. Terms such as "upper," "lower," "first lower," "first upper," "second lower," and "second upper" can be used to describe various elements, but the elements are not limited to the terms above, and "first element" can be represented as "second element." For example, "third semiconductor pattern" can be represented as "second semiconductor pattern."

[0011] In the example embodiments, the terms "upper" and "lower" may be described with reference to the accompanying drawings.

[0012] This specification uses degree terms including "substantially" or "approximately". In one or more examples, when the specified parameter X can be substantially the same as parameter Y, the term "substantially" can be understood as X being within 10% of Y. In one or more examples, when the specified parameter is approximately X, the term "approximately" can be understood as being within 10% of X.

[0013] In an example embodiment, an "impurity implantation region" can be defined as a region in which an impurity of a Group 15 or Group 13 element from the periodic table is doped into the semiconductor and source / drain annealing for forming the source / drain region has not yet been performed.

[0014] In the example embodiment, impurities injected through different impurity injection processes can be represented as different impurities. For example, a Group 15 element injected through a first impurity injection process can be represented as a first impurity, and a Group 15 element injected through a second impurity injection process can be represented as a second impurity.

[0015] In an example embodiment, the "source / drain region" can be defined as a region formed by diffusion and activation of impurities in the "impurity injection region" via source / drain annealing.

[0016] Reference Figure 1A , Figure 1B , Figure 2A and Figure 2B A semiconductor device is described according to one or more example embodiments. Figure 1A , Figure 1B , Figure 2A and Figure 2B middle, Figure 1A This is a perspective view illustrating a semiconductor device according to one or more example embodiments. Figure 1B This is a plan view illustrating the memory cell array region MCA, dummy region DA, PMOS region PA, and NMOS region NA of a first semiconductor structure of a semiconductor device according to one or more example embodiments. Figure 2A It shows along Figure 1B A cross-sectional view of the region intercepted by lines I-I' and II-II' in the diagram, and Figure 2B It shows along Figure 1B A cross-sectional view of the region intercepted by lines III-III' and IV-IV'.

[0017] refer to Figure 1A , Figure 1B , Figure 2A and Figure 2B According to one or more example embodiments, the semiconductor device 1 may include a first semiconductor structure STC1 and a second semiconductor structure STC2 that overlaps the first semiconductor structure STC1 perpendicularly. The second semiconductor structure STC2 may be disposed on the first semiconductor structure STC1. In example embodiments, the second semiconductor structure STC2 may be disposed below the first semiconductor structure STC1.

[0018] Semiconductor device 1 may include multiple memory banks BA and peripheral regions PERI.

[0019] The peripheral region PERI may include a first peripheral region PERI1 in the first semiconductor structure STC1 and a second peripheral region PERI2 in the second semiconductor structure STC2. Peripheral circuitry for inputting / outputting data or commands or inputting power / ground may be provided in the peripheral region PERI. As will be understood by those skilled in the art, the size, shape, and location of the peripheral regions PERI1 and PERI2 are not limited to... Figure 1A The configuration shown can be modified.

[0020] Each of the plurality of memory banks BA may include a first memory bank region BA1 in a first semiconductor structure STC1 and a second memory bank region BA2 in a second semiconductor structure STC2.

[0021] The first memory region BA1 of the first semiconductor structure STC1 may include a memory cell disposed therein. Figure 2AThe memory cell array region MCA in the MC (memory cell array) of the second semiconductor structure STC2. The second memory cell region BA2 in the second semiconductor structure STC2 may include a region in which circuitry for operating the memory cells MC is provided. For example, the second memory cell region BA2 may include: a sense amplifier region in which a sense amplifier for reading data from the memory cells MC is provided; a sub-word line driver region in which a sub-word line driver for activating or deactivating the memory cells MC is provided; and a peripheral circuitry region for controlling at least one of the circuitry in the sense amplifier region and the sub-word line driver region.

[0022] The first peripheral region PERI1 in the first semiconductor structure STC1 may include a dummy region DA.

[0023] In one or more examples, the first peripheral region PERI1 in the first semiconductor structure STC1 may also include a PMOS region PA and an NMOS region NA.

[0024] The first semiconductor structure STC1 may include a lower structure LC and an upper structure US located on the lower structure LC.

[0025] The lower structure LC may include a first semiconductor pattern 48a disposed in the memory cell array region MCA and a dummy semiconductor pattern 48d disposed in the dummy region DA. The width of the dummy semiconductor pattern 48d in the first direction X may be larger than the width of each first semiconductor pattern 48a in the first direction X. The width of the dummy semiconductor pattern 48d in the second direction Y, which is perpendicular to the first direction X, may be larger than the width of each first semiconductor pattern 48a in the second direction Y.

[0026] The lower structure LC may also include a second semiconductor pattern 48b disposed in the NMOS region NA and a third semiconductor pattern 48c disposed in the PMOS region PA.

[0027] Each first semiconductor pattern 48a may include a first upper source / drain region SD1a and a first lower source / drain region SD1b spaced apart from each other in the vertical direction Z, and a first channel region CH1 located between the first upper source / drain region SD1a and the first lower source / drain region SD1b. The first upper source / drain region SD1a may be disposed on the first lower source / drain region SD1b.

[0028] In one or more examples, the vertical thickness of the first upper source / drain region SD1a can be greater than the vertical thickness of the first lower source / drain region SD1b. In one or more examples, the vertical thickness can refer to... Figure 2A The Z direction in the equation.

[0029] In one or more examples, the first upper source / drain region SD1a and the first lower source / drain region SD1b can be formed by diffusion and activation of the same element. For example, the first upper source / drain region SD1a and the first lower source / drain region SD1b may include at least one of phosphorus (P) or arsenic (As). In one or more examples, diffusion and activation can be performed simultaneously or substantially simultaneously. In one or more examples, diffusion and activation can be performed separately, wherein the activation operation is performed after the diffusion operation.

[0030] In one or more modified examples, the first upper source / drain region SD1a and the first lower source / drain region SD1b may include different elements. The dominant impurity of the first upper source / drain region SD1a may be arsenic (As), and the dominant impurity of the first lower source / drain region SD1b may be phosphorus (P). For example, the first upper source / drain region SD1a can be formed by diffusion and activation of arsenic (As), and the first lower source / drain region SD1b can be formed by diffusion and activation of phosphorus (P).

[0031] Each second semiconductor pattern 48b may include a second lower source / drain region SD2b, a second upper source / drain region SD2a located on the second lower source / drain region SD2b, and a second channel region CH2 located between the second upper source / drain region SD2a and the second lower source / drain region SD2b.

[0032] In one or more examples, the vertical thickness of the second upper source / drain region SD2a can be greater than the vertical thickness of the second lower source / drain region SD2b.

[0033] Each third semiconductor pattern 48c may include a third lower source / drain region SD3b, a third upper source / drain region SD3a located on the third lower source / drain region SD3b, and a third channel region CH3 located between the third upper source / drain region SD3a and the third lower source / drain region SD3b.

[0034] In one or more examples, the vertical thickness of the third upper source / drain region SD3a can be greater than the vertical thickness of the third lower source / drain region SD3b.

[0035] In one or more examples, the dummy semiconductor pattern 48d may include a first dummy source / drain region SDd1 and a second dummy source / drain region SDd2 spaced apart from each other in the vertical direction Z, and a dummy semiconductor region CHd located between the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2. The dummy semiconductor region CHd may be an undoped semiconductor region. The first dummy source / drain region SDd1 may be disposed on the second dummy source / drain region SDd2. The first dummy source / drain region SDd1 may include a portion disposed at the same horizontal height as at least a portion of the first upper source / drain region SD1a. The second dummy source / drain region SDd2 may include a portion disposed at the same horizontal height as at least a portion of the first lower source / drain region SD1b or disposed at substantially the same horizontal height.

[0036] In one or more examples, the vertical thickness of the first dummy source / drain region SDd1 can be greater than the vertical thickness of the second dummy source / drain region SDd2.

[0037] In one or more examples, the first upper source / drain region SD1a, the first lower source / drain region SD1b, the second upper source / drain region SD2a, and the second lower source / drain region SD2b may have N-type conductivity, and the third upper source / drain region SD3a and the third lower source / drain region SD3b may have P-type conductivity.

[0038] In one or more examples, the first upper source / drain region SD1a and the first dummy source / drain region SDd1 can be formed by diffusion and activation of the same element. The first upper source / drain region SD1a and the first dummy source / drain region SDd1 can have the same conductivity type. The first upper source / drain region SD1a and the first dummy source / drain region SDd1 can have N-type conductivity.

[0039] In one or more examples, the impurity concentration of the first dummy source / drain region SDd1 may be different from the impurity concentration of the first upper source / drain region SD1a.

[0040] In one or more examples, the impurity concentration of the first dummy source / drain region SDd1 may be higher than the impurity concentration of the first upper source / drain region SD1a.

[0041] In one or more examples, the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2 may have the same conductivity type. For example, the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2 may have N-type conductivity or P-type conductivity.

[0042] In one or more modified examples, the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2 can have different conductivity types. For example, one of the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2 can have N-type conductivity, and the other can have P-type conductivity. For example, the first dummy source / drain region SDd1 can have N-type conductivity, and the second dummy source / drain region SDd2 can have P-type conductivity. In another example, the first dummy source / drain region SDd1 can have P-type conductivity, and the second dummy source / drain region SDd2 can have N-type conductivity.

[0043] The lower structure LC may also include gate structures 54a, 54b and 54c and a dummy insulating pattern 54d.

[0044] Gate structures 54a, 54b and 54c may include a first gate structure 54a in the memory cell array region MCA, a second gate structure 54b in the NMOS region NA and a third gate structure 54c in the PMOS region PA.

[0045] Each first gate structure 54a may include a first gate dielectric layer 56a and a first gate electrode 58a. Each first gate structure 54a may also include a first insulating pattern 60a and a first gate overlay pattern 62a. The first gate electrode 58a may extend in a first direction X.

[0046] Each second gate structure 54b may include a second gate dielectric layer 56b and a second gate electrode 58b. Each second gate structure 54b may also include a second insulating pattern 60b and a second gate overlay pattern 62b.

[0047] Each third gate structure 54c may include a third gate dielectric layer 56c and a third gate electrode 58c. Each third gate structure 54c may also include a third insulating pattern 60c and a third gate overlay pattern 62c.

[0048] In each first gate structure 54a, a first insulating pattern 60a may face the side surface of a corresponding first semiconductor pattern 48a in the first semiconductor pattern 48a; a first gate electrode 58a may face the side surface of a corresponding first semiconductor pattern 48a in the first semiconductor pattern 48a and may be disposed between the first insulating pattern 60a and the first semiconductor pattern 48a; a first gate cover pattern 62a may be disposed on the first gate electrode 58a; a first gate dielectric layer 56a may be disposed between the first gate electrode 58a and the first semiconductor pattern 48a, and between the first gate cover pattern 62a and the first semiconductor pattern 48a, and may extend between the first insulating pattern 60a and the buffer insulating pattern 51. In each first gate structure 54a, the first gate electrode 58a may face the first channel region CH1 of the first semiconductor pattern 48a.

[0049] In each second gate structure 54b, the second insulating pattern 60b may face the side surface of the corresponding second semiconductor pattern 48b, the second gate electrode 58b may face the side surface of the corresponding second semiconductor pattern 48b and may be disposed between the second insulating pattern 60b and the second semiconductor pattern 48b, the second gate cover pattern 62b may be disposed on the second gate electrode 58b, and the second gate dielectric layer 56b may be disposed between the second gate electrode 58b and the second semiconductor pattern 48b and between the second gate cover pattern 62b and the second semiconductor pattern 48b, and may extend between the second insulating pattern 60b and the buffer insulating pattern 51. In each second gate structure 54b, the second gate electrode 58b may face the second channel region CH2 of the second semiconductor pattern 48b.

[0050] In each third gate structure 54c, the third insulating pattern 60c may face the side surface of the corresponding third semiconductor pattern 48c in the third semiconductor pattern 48c, the third gate electrode 58c may face the side surface of the corresponding third semiconductor pattern 48c in the third semiconductor pattern 48c and may be disposed between the third insulating pattern 60c and the third semiconductor pattern 48c, the third gate cover pattern 62c may be disposed on the third gate electrode 58c, and the third gate dielectric layer 56c may be disposed between the third gate electrode 58c and the third semiconductor pattern 48c and between the third gate cover pattern 62c and the third semiconductor pattern 48c, and may extend between the third insulating pattern 60c and the buffer insulating pattern 51. In each third gate structure 54c, the third gate electrode 58c may face the third channel region CH3 of the third semiconductor pattern 48c.

[0051] The first gate cover pattern 62a, the second gate cover pattern 62b, and the third gate cover pattern 62c can be formed from an insulating material such as silicon oxide or silicon nitride.

[0052] The dummy insulating pattern 54d may include a fourth insulating pattern 60d on the side surface of the buffer insulating pattern 51 facing the dummy semiconductor pattern 48d, and a dummy dielectric layer 56d disposed between the dummy semiconductor pattern 48d and the fourth insulating pattern 60d and extending between the fourth insulating pattern 60d and the buffer insulating pattern 51.

[0053] The lower-structure LC can also include back gate structures 39aa, 39ba and 39ca.

[0054] The back gate structures 39aa, 39ba and 39ca may include a first back gate structure 39aa, a second back gate structure 39ba and a third back gate structure 39ca.

[0055] The first back gate structure 39aa can be arranged alternately with the gate structure 54a in the second direction Y. The first direction X and the second direction Y can be perpendicular to the vertical direction Z. The first semiconductor pattern 48a can be disposed between the first back gate structure 39aa and the gate structure 54a.

[0056] Each first back gate structure 39aa may include a first back gate electrode 43aa passing between adjacent first semiconductor patterns 48a along the second direction Y, a first lower back gate capping layer 45a disposed below the first back gate electrode 43aa, a first upper back gate capping layer 46a disposed on the first back gate electrode 43aa, and a first back gate dielectric layer 41a located on the side surface of the first back gate electrode 43aa. The first back gate electrode 43aa may extend in the first direction X.

[0057] The second back gate structure 39ba may include a second back gate electrode 43ba passing between second semiconductor patterns 48b that are adjacent to each other along the second direction Y, a second lower back gate capping layer 45b disposed below the second back gate electrode 43ba, a second upper back gate capping layer 46b disposed on the second back gate electrode 43ba, and a second back gate dielectric layer 41b located on the side surface of the second back gate electrode 43ba.

[0058] The third back gate structure 39ca may include a third back gate electrode 43ca passing between third semiconductor patterns 48c that are adjacent to each other along the second direction Y, a third lower back gate capping layer 45c disposed below the third back gate electrode 43ca, a third upper back gate capping layer 46c disposed on the third back gate electrode 43ca, and a third back gate dielectric layer 41c disposed on the side surface of the third back gate electrode 43ca.

[0059] The lower structure LC may also include a buffer insulating pattern 51. The buffer insulating pattern 51 may be disposed on the gate structures 54a, 54b, and 54c, the back gate structures 39aa, 39ba, and 39ca, and the dummy insulating pattern 54d. The buffer insulating pattern 51 may be disposed on the side surfaces of the semiconductor patterns 48a, 48b, 48c, and 48d at a higher horizontal height than the horizontal height of the gate structures 54a, 54b, and 54c, the back gate structures 39aa, 39ba, and 39ca, and the dummy insulating pattern 54d.

[0060] The lower structure LC may include cell transistors cTR disposed in the memory cell array region MCA. Each cell transistor cTR may include a first upper source / drain region SD1a, a first lower source / drain region SD1b, a first channel region CH1, a first gate dielectric layer 56a, and a first gate electrode 58a. The first gate electrode 58a may be a word line.

[0061] The lower structure LC may include a first peripheral transistor N_TR disposed in the NMOS region NA. Each first peripheral transistor N_TR may include a second upper source / drain region SD2a, a second lower source / drain region SD2b, a second channel region CH2, a second gate dielectric layer 56b, and a second gate electrode 58b. The first peripheral transistor N_TR may be an NMOS transistor.

[0062] The lower structure LC may include a second peripheral transistor P_TR disposed in the PMOS region PA. Each second peripheral transistor P_TR may include a third upper source / drain region SD3a, a third lower source / drain region SD3b, a third channel region CH3, a third gate dielectric layer 56c, and a third gate electrode 58c. The second peripheral transistor P_TR may be a PMOS transistor.

[0063] The lower structure LC may also include contact patterns 68a, 68b, 68c, and 68d. Contact patterns 68a, 68b, 68c, and 68d may be connected to semiconductor patterns 48a, 48b, 48c, and 48d.

[0064] In one or more examples, contact patterns 68a, 68b, 68c, and 68d may include a first contact pattern 68a connected to a first lower source / drain region SD1b of a first semiconductor pattern 48a, a second contact pattern 68b connected to a second lower source / drain region SD2b of a second semiconductor pattern 48b, a third contact pattern 68c connected to a third lower source / drain region SD3b of a third semiconductor pattern 48c, and a dummy contact pattern 68d connected to a second dummy source / drain region SD2d of a dummy semiconductor pattern 48d.

[0065] Each first contact pattern 68a may include a first doped polysilicon layer 64a and a first conductive layer 66a below the first doped polysilicon layer 64a. Each second contact pattern 68b may include a second doped polysilicon layer 64b and a second conductive layer 66b below the second doped polysilicon layer 64b. Each third contact pattern 68c may include a third doped polysilicon layer 64c and a third conductive layer 66c below the third doped polysilicon layer 64c. A dummy contact pattern 68d may include a dummy doped polysilicon layer 64d and a dummy conductive layer 66d below the dummy doped polysilicon layer 64d.

[0066] The lower structure LC may also include an interlayer insulating layer 71 disposed on the side surfaces of the contact patterns 68a, 68b, 68c and 68d.

[0067] The lower structure LC may also include lower peripheral interconnects 70a and 70b. For example, lower peripheral interconnects 70a and 70b may include a first lower peripheral interconnect 70a connected to at least one second contact pattern 68b and a second lower peripheral interconnect 70b connected to at least one third contact pattern 68c.

[0068] The lower structure LC may also include an insulating etch stop layer 72 disposed below the contact patterns 68a, 68b, 68c and 68d, the interlayer insulating layer 71, and the lower peripheral interconnects 70a and 70b.

[0069] The lower structure LC may also include a data storage structure 74. The data storage structure 74 may include: a first electrode 76a, penetrating the etch stop layer 72, connected to the first contact pattern 68a and extending downwards; a dielectric layer 76b, covering the first electrode 76a and the etch stop layer 72; and a second electrode 76c, covering the dielectric layer 76b. The data storage structure 74 may be a cell capacitor for storing data in a memory such as DRAM.

[0070] Data storage structure 74 and unit transistor cTR can be included in the storage cell MC of a memory such as DRAM.

[0071] The lower structure LC may further include: a first insulating layer 78 disposed below the data storage structure 74 and the etch stop layer 72; an interconnect 82 penetrating the first insulating layer 78 and connected to the second electrode 76c; and a lower insulating layer 84 disposed below the first insulating layer 78 and the interconnect 82.

[0072] The lower structure LC may also include a bit line 90a disposed in the memory cell array region MCA, a first upper peripheral interconnect 90b disposed in the NMOS region NA, and a second upper peripheral interconnect 90c disposed in the PMOS region PA.

[0073] Bit line 90a, first upper peripheral interconnect 90b, and second upper peripheral interconnect 90c may each comprise conductive material layers 91a, 91b, and 91c stacked sequentially. Each bit line 90a may extend in the second direction Y.

[0074] The conductive material layers 91a, 91b, and 91c may comprise a first material layer 91a, a second material layer 91b, and a third material layer 91c stacked sequentially. The first material layer 91a may comprise a doped polysilicon layer. The second material layer 91b may comprise at least one of a metal nitride and a metal semiconductor compound. The third material layer 91c may comprise a metal layer containing a metal. The thickness of the third material layer 91c, which may be a metal layer, may be greater than the thickness of the first material layer 91a, which may be a polysilicon layer.

[0075] Bit line 90a can be connected to the first upper source / drain region SD1a of the first semiconductor pattern 48a, the first upper peripheral interconnect 90b can be connected to the second upper source / drain region SD2a of the second semiconductor pattern 48b, and the second upper peripheral interconnect 90c can be connected to the third upper source / drain region SD3a of the third semiconductor pattern 48c.

[0076] The lower structure LC may also include a first insulating cover pattern 92a located on bit line 90a, a second insulating cover pattern 92b located on the first upper peripheral interconnect 90b, and a third insulating cover pattern 92c located on the second upper peripheral interconnect 90c.

[0077] The lower structure LC may also include a first intermediate insulating layer 93, which covers bit lines 90a, a first upper peripheral interconnect 90b and a second upper peripheral interconnect 90c, as well as a first insulating covering pattern 92a, a second insulating covering pattern 92b and a third insulating covering pattern 92c.

[0078] The upper structure US may include a routing interconnect 95 disposed on a first intermediate insulating layer 93, a second intermediate insulating layer 97 covering the routing interconnect 95 on the first intermediate insulating layer 93, and a first bonding dielectric layer 99 disposed on the second intermediate insulating layer 97.

[0079] In one or more examples, the first bonding dielectric layer 99 may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN. In one or more examples, the first bonding dielectric layer 99 may be formed from two or more of the aforementioned materials.

[0080] The second semiconductor structure STC2 may include peripheral transistors PTR. Each peripheral transistor PTR may include a peripheral source / drain region pSD, a peripheral channel region pCH located between the peripheral source / drain regions pSD, a peripheral gate electrode pGE located on the peripheral channel region pCH, and a peripheral gate dielectric layer pGO located between the peripheral channel region pCH and the peripheral gate electrode pGE.

[0081] In one or more examples, the second semiconductor structure STC2 may include an upper substrate 103, a peripheral device isolation region 106s defining a peripheral active region 106a on the upper substrate 103, a front insulating layer 112 covering a peripheral transistor PTR on the upper substrate 103, a back insulating layer 115 disposed below the upper substrate 103, and a second bonding dielectric layer 118 disposed below the back insulating layer 115.

[0082] In each peripheral transistor PTR, the peripheral source / drain region pSD and the peripheral channel region pCH can be disposed in the corresponding peripheral active region 106a in the peripheral active region 106a, and the peripheral gate dielectric layer pGO and the peripheral gate electrode pGE can be disposed on the peripheral channel region pCH in the peripheral active region 106a.

[0083] In one or more examples, the second bonding dielectric layer 118 may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN. In one or more examples, the second bonding dielectric layer 118 may be formed from two or more of the aforementioned materials.

[0084] The first bonding dielectric layer 99 and the second bonding dielectric layer 118 can be bonded to each other by a dielectric-to-dielectric bonding process. The first bonding dielectric layer 99 and the second bonding dielectric layer 118 can be bonded to each other by a dielectric-to-dielectric bonding process to form a bonding region JN.

[0085] The second semiconductor structure STC2 may also include a conductive path 120 and an insulating spacer 119. The conductive path 120 penetrates the front insulating layer 112 and the upper substrate 103, extends downward and is electrically connected to the routing interconnect 95. The insulating spacer 119 is disposed on the side surface of the conductive path 120.

[0086] The second semiconductor structure STC2 may also include a contact plug 121 that penetrates the front insulating layer 112 and is electrically connected to the peripheral transistor PTR.

[0087] The second semiconductor structure STC2 may also include an upper insulating layer 124 located on the front insulating layer 112, an upper interconnect structure 127 buried in the upper insulating layer 124, and input / output pads 130 electrically connected to the upper interconnect structure 127.

[0088] In the following, example embodiments of semiconductor device 1 will be described. The various example embodiments described below and those described above can be combined to form one or more example embodiments. In the following, elements described above may be directly referenced without detailed description, or may be omitted entirely. Additionally, elements described below that can be modified or replaced may be described with reference to the figures below; however, elements that can be modified, replaced, or added may be combined with each other or with elements described above to form semiconductor devices according to one or more example embodiments of this disclosure. Furthermore, in cases where the previously described components include multiple components, examples where the number of elements described above is one will be described.

[0089] Reference Figure 3 Describe one or more examples of the semiconductor device 1 described above. Figure 3 It shows along Figure 1B A cross-sectional view of the region intercepted by lines I-I' and II-II' in the diagram, to illustrate... Figure 2A Example of modification.

[0090] refer to Figure 3 It is not necessary to provide Figure 2A The dummy contact pattern in Figure 2A (68d in the example). Therefore, the lower surface of the dummy semiconductor pattern 48d can contact the interlayer insulating layer 71.

[0091] Reference Figure 4 Describe one or more examples of the semiconductor device 1 described above. Figure 4 It shows along Figure 1B A cross-sectional view of the region intercepted by lines I-I', II-II', III-III', and IV-IV', to illustrate... Figure 2A and Figure 2B Examples of modifications to the upper structure US and the second semiconductor structure STC2.

[0092] refer to Figure 4 , Figure 2A and Figure 2B The upper structure US may also include a first bonding pad 202, which has an upper surface coplanar with the first bonding dielectric layer 99 and is electrically connected to the routing interconnect 95. The first bonding pad 202 may include a metallic material, such as copper (Cu).

[0093] Figure 2A and Figure 2B The second semiconductor structure STC2 in the image can be replaced with, for example... Figure 4 The second semiconductor structure in it is STC2'.

[0094] The second semiconductor structure STC2' may include peripheral transistors PTR'. Each peripheral transistor PTR' may include a peripheral source / drain region pSD, a peripheral channel region pCH located between the peripheral source / drain regions pSD, a peripheral gate electrode pGE located on the peripheral channel region pCH, and a peripheral gate dielectric layer pGO located between the peripheral channel region pCH and the peripheral gate electrode pGE.

[0095] The second semiconductor structure STC2' may include an upper substrate 203', a peripheral device isolation region 206s defining a peripheral active region 206a below the upper substrate 203', an upper insulating layer 212 covering a peripheral transistor PTR' below the upper substrate 203', an upper interconnect structure 215 buried in the upper insulating layer 212 and electrically connected to the peripheral transistor PTR', a second bonding dielectric layer 218 disposed below the upper insulating layer 212, and a second bonding pad 221.

[0096] In each peripheral transistor PTR', the peripheral source / drain region pSD and the peripheral channel region pCH can be formed in the corresponding peripheral active region 206a, and the peripheral gate dielectric layer pGO and the peripheral gate electrode pGE can be formed below the peripheral channel region pCH in the peripheral active region 206a.

[0097] The second bonding pad 221 may include a metallic material, such as copper (Cu). The second bonding pad 221 may have an upper surface that is coplanar with the upper surface of the second bonding dielectric layer 218 and may be electrically connected to the upper interconnect structure 215.

[0098] In one or more examples, the second bonding dielectric layer 218 may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN. As will be understood by those skilled in the art, the dielectric layer 218 may be a composite material formed from two or more of the aforementioned materials.

[0099] The second semiconductor structure STC2' may also include a cover insulating layer 230 disposed on the upper substrate 203, a conductive path 239 penetrating the cover insulating layer 230 and the upper substrate 203 and electrically connected to the upper interconnect structure 215, an insulating spacer 236 located on the side surface of the conductive path 239, and an input / output pad 242 disposed on the conductive path 239.

[0100] The first semiconductor structure STC1 and the second semiconductor structure STC2' can be bonded to each other using a hybrid bonding process that includes metal-metal bonding and dielectric-dielectric bonding. For example, the first bonding pad 202 and the second bonding pad 221 can be bonded to each other using a hybrid bonding process, and the first bonding dielectric layer 99 and the second bonding dielectric layer 218 can be bonded to each other to form a bonding region JN.

[0101] Reference Figure 5 Describe one or more examples of the semiconductor device 1 described above. Figure 5 It shows along Figure 1B A cross-sectional view of the region intercepted by lines I-I', II-II', III-III', and IV-IV', to illustrate... Figure 2A and Figure 2B Example of modification of the substructure LC in the example.

[0102] refer to Figure 5 , Figure 2A The first lower source / drain region in ( Figure 2A SD1b in the first upper source / drain region SD1a can be replaced by a first lower source / drain region SD1ba having a vertical thickness that is the same as (or substantially the same as) or greater than that of the first upper source / drain region SD1a. Figure 2A The second dummy source / drain region in Figure 2A SDd2 in the first dummy source / drain region SDd1 can be replaced by a second dummy source / drain region SDd2a with a vertical thickness that is the same as (or substantially the same as) or greater than that of the first dummy source / drain region SDd1. Figure 2B The second lower source / drain region in ( Figure 2B SD2b in the second upper source / drain region SD2a can be replaced by a second lower source / drain region SD2ba with a vertical thickness that is the same as (or substantially the same as) or greater than that of the second upper source / drain region SD2a. Figure 2B The third lower source / drain region in Figure 2B SD3b in the third upper source / drain region SD3a can be replaced by a third lower source / drain region SD3ba with the same (or substantially the same) vertical thickness as or greater than that of the third upper source / drain region SD3a.

[0103] Reference Figure 6 Describe one or more examples of the semiconductor device 1 described above. Figure 6 It shows along Figure 1BA cross-sectional view of the region intercepted by lines I-I' and II-II' in the diagram, to illustrate... Figure 2A Example of modification.

[0104] refer to Figure 6 References are not required. Figure 2A The first dummy source / drain region described ( Figure 2A SDd1 in the example. In the dummy semiconductor pattern 48a, where the first dummy source / drain region is not provided ( Figure 2A The region SDd1 in the diagram can be replaced with a dummy semiconductor region CHd. Therefore, the dummy semiconductor pattern 48a can include a second dummy source / drain region SDd2 and a dummy semiconductor region CHd, and a portion of the dummy semiconductor region CHd can be positioned at the same or substantially the same horizontal level as the first upper source / drain region SD1a. The dummy semiconductor region CHd can be an undoped semiconductor region.

[0105] The dummy semiconductor pattern 48a may be at the same or substantially the same horizontal height as the first upper source / drain region SD1a, excluding the impurities in the first upper source / drain region SD1a.

[0106] Reference Figure 7 Describe one or more examples of the semiconductor device 1 described above. Figure 7 It shows along Figure 1B A cross-sectional view of the region intercepted by lines I-I' and II-II' in the diagram, to illustrate... Figure 2A Example of modification.

[0107] refer to Figure 7 It is not necessary to provide Figure 2A The second dummy source / drain region described in the text ( Figure 2A SDd2 in the example. In the dummy semiconductor pattern 48a, a second dummy source / drain region is not provided ( Figure 2A The region SDd2 in the diagram can be replaced with a dummy semiconductor region CHd. Therefore, the dummy semiconductor pattern 48a can include a first dummy source / drain region SDd1 and a dummy semiconductor region CHd, and a portion of the dummy semiconductor region CHd can be set at the same or substantially the same horizontal height as the first lower source / drain region SD1b.

[0108] The dummy semiconductor pattern 48a may be at the same or substantially the same horizontal height as the first lower source / drain region SD1b, excluding the impurities in the first lower source / drain region SD1b.

[0109] Reference Figure 8 Describe one or more examples of the semiconductor device 1 described above. Figure 8 It shows along Figure 1B A cross-sectional view of the region intercepted by lines I-I' and II-II' in the diagram, to illustrate... Figure 2A Example of modification.

[0110] refer to Figure 8 References are not required. Figure 2A The first dummy source / drain region described ( Figure 2A SDd1 in the middle) and the second dummy source / drain region ( Figure 2A (SDd2 in the example). The dummy semiconductor pattern 48a can be formed as an undoped semiconductor pattern. The dummy semiconductor pattern 48a can be at the same or substantially the same horizontal height as the first lower source / drain region SD1b and the first upper source / drain region SD1a, excluding the impurities in the first lower source / drain region SD1b and the first upper source / drain region SD1a.

[0111] In the following text, reference will be made to Figure 9 and Figure 10 Describe one or more examples of methods for manufacturing a semiconductor device according to one or more example embodiments. Figure 9 and Figure 10 middle, Figure 9 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one or more example embodiments, and Figure 10 This is a flowchart illustrating the formation of a first semiconductor structure in a method of manufacturing a semiconductor device according to one or more example embodiments. As will be understood by those skilled in the art, at least a portion of one operation may be performed simultaneously or in parallel with a portion of another operation. For example, a second operation may begin while a first operation is being performed, before the first operation is completed.

[0112] refer to Figure 9 and Figure 10 A method for manufacturing a semiconductor device according to one or more example embodiments may include: forming a first semiconductor structure (S10); forming a second semiconductor structure (S110); and forming a bonded semiconductor structure (S120).

[0113] Forming the first semiconductor structure (S10) may include: forming a bonding structure (S15); forming a semiconductor pattern (S60); forming a gate structure (S70); forming a source / drain region (S75); forming a data storage structure (S90); and forming a bit line (S95).

[0114] Reference Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 Description Reference Figure 10 One or more examples of the forming joint structure (S15) are described. Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 middle, Figure 11 This is a flowchart illustrating one or more examples of forming a joint structure (S15). Figure 12 It is a perspective view showing one or more examples of forming a joint structure (S15), and Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 This is a cross-sectional view showing one or more examples of forming the joint structure (S15), illustrating along... Figure 1B The regions intercepted by lines I-I', II-II', III-III', and IV-IV'.

[0115] refer to Figure 11 , Figure 12 and Figure 13 Forming the bonding structure (S15) may include preparing a first semiconductor substrate 3 (S20) and forming a bonding dielectric layer 6 on the first semiconductor substrate 3 (S25). The first semiconductor substrate 3 and the bonding dielectric layer 6 may be included in the first structure 9. The first semiconductor substrate 3 may be a single-crystal silicon substrate. The bonding dielectric layer 6 may be an oxide layer. For example, the bonding dielectric layer 6 may include a silicon oxide layer.

[0116] refer to Figure 11 , Figure 12 and Figure 14 The formation of the bonding structure (S15) may further include preparing a preliminary second semiconductor substrate 12a (S30). The preliminary second semiconductor substrate 12a may be a single-crystal silicon substrate. The formation of the bonding structure (S15) may also include forming a buffer dielectric layer 21 on the preliminary second semiconductor substrate 12a. The buffer dielectric layer 21 may include a silicon oxide layer. In one or more examples, a reference to a preliminary structure or component may refer to a component or structure that is developed in a first operation and modified or removed in a subsequent second operation.

[0117] refer to Figure 11 , Figure 12 , Figure 15 and Figure 16The formation of the bonding structure (S15) may further include forming at least one first-side impurity implantation region 14a, 14b and 14c in the preliminary second semiconductor substrate 12a (S35).

[0118] The preliminary second semiconductor substrate 12a may include a first portion 12_1 and a preliminary second portion 12_2a located below the first portion 12_1. The first portion 12_1 may be adjacent to or in contact with the buffer dielectric layer 21.

[0119] At least one first-side impurity implantation region 14a, 14b, and 14c may be formed in the first portion 12_1 of the preliminary second semiconductor substrate 12a. Therefore, the first portion 12_1 of the preliminary second semiconductor substrate 12a may include at least one first-side impurity implantation region 14a, 14b, and 14c.

[0120] In one or more examples, forming at least one first-side impurity implantation region 14a, 14b, and 14c (S35) may include: forming a first mask 24 that exposes the memory cell array region MCA and the peripheral NMOS region NA and covers the dummy region DA and the peripheral PMOS region PA; performing a first impurity implantation process (19N) using the first mask 24 as an impurity injection mask to form the first impurity implantation region 14a and the second impurity implantation region 14b; and removing the first mask 24. The first impurity implantation process (19N) may be an ion implantation process.

[0121] A first mask 24 can be formed on the buffer dielectric layer 21.

[0122] A first impurity implantation region 14a can be formed in a first portion 12_1 of the initial second semiconductor substrate 12a of the memory cell array region MCA. A second impurity implantation region 14b can be formed in a first portion 12_1 of the initial second semiconductor substrate 12b of the NMOS region NA.

[0123] The first impurity implantation process (19N) may include doping a first impurity into a first portion 12_1 of the preliminary second semiconductor substrate 12a of the memory cell array region MCA and into the first portion 12_1 of the preliminary second semiconductor substrate 12b of the NMOS region NA in the second impurity implantation region 14b. The first impurity may be a group 15 element in the periodic table.

[0124] In one or more examples, the first impurity may be phosphorus (P).

[0125] In one or more examples, the first impurity may be arsenic (As). In one or more examples, the first impurity may be a mixture of two or more elements.

[0126] In one or more examples, forming at least one first-side impurity implantation region 14a, 14b, and 14c (S35) may include: forming a second mask 27 that exposes the PMOS region PA and covers the dummy region DA, the memory cell array region MCA, and the NMOS region NA; performing a second impurity implantation process (19P) using the second mask 27 as an impurity injection mask to form a third impurity implantation region 14c in the preliminary second semiconductor substrate 12a of the PMOS region PA; and removing the second mask 27. The second impurity implantation process (19P) may be an ion implantation process.

[0127] A second mask 27 can be formed on the buffer dielectric layer 21.

[0128] A third impurity implantation region 14c can be formed in the first portion 12_1 of the initial second semiconductor substrate 12a of the PMOS region PA.

[0129] The second impurity implantation process (19P) may include doping a second impurity in the first portion 12_1 of the preliminary second semiconductor substrate 12a of the PMOS region PA. The second impurity may be a group 13 element in the periodic table.

[0130] In one or more examples, the second impurity may be boron (B).

[0131] In one or more examples, a first impurity implantation region 14a and a second impurity implantation region 14b doped with a first impurity may be formed before the formation of a third impurity implantation region 14c doped with a second impurity.

[0132] In one or more examples, after forming a third impurity implantation region 14c doped with a second impurity, a first impurity implantation region 14a and a second impurity implantation region 14b doped with a first impurity can be formed.

[0133] The buffer dielectric layer 21 can protect the surface of the preliminary second semiconductor substrate 12a from the effects of the first impurity implantation process (19N) and the second impurity implantation process (19P). For example, the buffer dielectric layer 21 can prevent the surface of the preliminary second semiconductor substrate 12a from being damaged by the first impurity implantation process (19N) and the second impurity implantation process (19P).

[0134] In an example embodiment, after performing the first impurity implantation process (19N) and the second impurity implantation process (19P), the first portion 12_1 of the preliminary second semiconductor substrate 12a may include a first impurity implantation region 14a, a second impurity implantation region 14b and a third impurity implantation region 14c.

[0135] After performing the first impurity implantation process (19N) and the second impurity implantation process (19P), the first portion 12_1 of the preliminary second semiconductor substrate 12a may include a first impurity implantation region 14a, a second impurity implantation region 14b and a third impurity implantation region 14c.

[0136] After performing the first impurity implantation process (19N) and the second impurity implantation process (19P), the preliminary second portion 12_2a of the preliminary second semiconductor substrate 12a may include a preliminary first semiconductor region 16a located below the first impurity implantation region 14a, a preliminary second semiconductor region 16b located below the second impurity implantation region 14b, and a preliminary third semiconductor region 16c located below the third impurity implantation region 14c.

[0137] In one or more examples, after performing the first impurity implantation process (19N) and the second impurity implantation process (19P), the first portion 12_1 of the preliminary second semiconductor substrate 12a of the dummy region DA may include a first dummy semiconductor region 14d undoped with the first and second impurities, and the preliminary second portion 12_2a of the preliminary second semiconductor substrate 12a of the dummy region DA may include a preliminary second dummy semiconductor region 16d undoped with the first and second impurities. The preliminary second dummy semiconductor region 16d may be formed below the first dummy semiconductor region 14d.

[0138] The preliminary second semiconductor substrate 12a and the buffer dielectric layer 21 can form the preliminary second structure 30a.

[0139] refer to Figure 11 , Figure 12 and Figure 17 Forming the bonding structure (S15) may also include forming a preliminary bonding structure 33a by performing a wafer bonding process (S40).

[0140] Forming the preliminary bonding structure 33a (S40) may include bonding the first structure 9 to the preliminary second structure 30a. For example, forming the preliminary bonding structure 33a (S40) may include bonding the bonding dielectric layer 6 of the first structure 9 to the buffer dielectric layer 21 of the preliminary second structure 30a. The wafer bonding process may be a dielectric-dielectric bonding process. For example, the silicon oxide layer of the bonding dielectric layer 6 of the first structure 9 and the silicon oxide layer of the buffer dielectric layer 21 of the preliminary second structure 30a may be bonded to each other through a wafer bonding process.

[0141] In one or more examples, the silicon oxide layer of the bonding dielectric layer 6 and the silicon oxide layer of the buffer dielectric layer 21 can be bonded to each other and can be formed as an integral silicon oxide layer.

[0142] A preliminary joined structure 33a can be formed by joining the first structure 9 to the preliminary second structure 30a.

[0143] refer to Figure 11 , Figure 12 and Figure 18 Forming the joint structure (S15) may also include reducing the initial joint structure ( Figure 17 The thickness of the initial second semiconductor substrate 12a in (33a) is used to form the second semiconductor substrate 12b (S45).

[0144] Forming the second semiconductor substrate 12b may include reducing the initial size of the second semiconductor substrate ( Figure 17 The preliminary second part of 12a) Figure 17 (12_2a in the text). As the thickness decreases, the initial second part ( Figure 17 12_2a) in the middle can be formed into the second part 12_2b.

[0145] As the thickness decreases, the initial first semiconductor region 16a can be formed as the first semiconductor region 16aa. As the thickness decreases, the initial second semiconductor region 16b can be formed as the second semiconductor region 16bb. As the thickness decreases, the initial third semiconductor region 16c can be formed as the third semiconductor region 16cc. As the thickness decreases, the initial second dummy semiconductor region 16d can be formed as the second dummy semiconductor region 16dd. As the thickness decreases, the initial second structure 30a can be formed as the second structure 30b. The second structure 30b may include the second semiconductor substrate 12b. As the thickness decreases, the initial bonding structure ( Figure 17 33a) can be formed as a bonding structure 33b. The bonding structure 33b may include a first structure 9 and a second structure 30b. In one or more examples, the thickness reduction of the component can be performed by mechanical and / or chemical polishing.

[0146] The second semiconductor substrate 12b may include a first portion 12_1 adjacent to the first semiconductor substrate 3 and a second portion 12_2b located on the first portion 12_1. The vertical thickness of the second portion 12_2b may be greater than the vertical thickness of the first portion 12_1.

[0147] The first portion 12_1 of the second semiconductor substrate 12b may include a first impurity implantation region 14a, a second impurity implantation region 14b, a third impurity implantation region 14c, and a first dummy semiconductor region 14d.

[0148] The second portion 12_2b of the second semiconductor substrate 12b may include a first semiconductor region 16aa located on the first impurity implantation region 14a, a second semiconductor region 16bb located on the second impurity implantation region 14b, a third semiconductor region 16cc located on the third impurity implantation region 14c, and a second dummy semiconductor region 16dd located on the first dummy semiconductor region 14d.

[0149] In the following description, reference will be made to Figure 19 and Figure 20 Describe one or more examples of methods for forming a dummy region DA. Figure 19 and Figure 20 It is a cross-sectional view showing one or more examples of methods for forming the dummy region DA, to show the region intercepted along lines I-I', II-II', III-III' and IV-IV' in Figure 2.

[0150] refer to Figure 19 , Figure 15 The first mask in the middle ( Figure 15 24) in the diagram can be replaced by a first mask 24a that exposes the memory cell array region MCA, the NMOS region NA, and the dummy region DA, and covers the PMOS region PA. Therefore, the first dummy impurity implantation region 14da, doped with the first impurity, can be... Figure 15 The first impurity implantation process (19N) is formed in the first portion 12_1 of the preliminary second semiconductor substrate 12a of the dummy region DA. For example, a first mask 24a can be formed on the buffer dielectric layer 21 to expose the memory cell array region MCA, the NMOS region NA and the dummy region DA and cover the PMOS region PA. The first impurity implantation region 14a, the second impurity implantation region 14b and the first dummy impurity implantation region 14da can be formed by performing the first impurity implantation process (19N) using the first mask 24a as an impurity injection mask, and the first mask 24a can be removed.

[0151] The second portion 12_2a of the preliminary second semiconductor substrate 12a may include a preliminary second dummy semiconductor region 16d formed below the first dummy impurity implantation region 14da and undoped with the first and second impurities.

[0152] The first impurity implantation region 14a, the second impurity implantation region 14b, and the first dummy impurity implantation region 14da may be doped with the first impurity described above. The first impurity implantation region 14a, the second impurity implantation region 14b, and the first dummy impurity implantation region 14da may be doped with the same impurity.

[0153] refer to Figure 20 In reference Figure 18In the second semiconductor substrate 12b of the described bonding structure 33b, the first dummy semiconductor region ( Figure 18 14d in the middle) can be formed as the first dummy impurity injection region ( Figure 19 14da in the middle). The second semiconductor substrate 12b may include a first dummy impurity implantation region ( Figure 19 (14da in the middle).

[0154] The first portion 12_1 of the second semiconductor substrate 12b may include a first impurity implantation region 14a, a second impurity implantation region 14b, and a first dummy impurity implantation region 14da.

[0155] The second portion 12_2b of the second semiconductor substrate 12b may include a first semiconductor region 16aa located on the first impurity implantation region 14a, a second semiconductor region 16bb located on the second impurity implantation region 14b, a third semiconductor region 16cc located on the third impurity implantation region 14c, and a second dummy semiconductor region 16dd located on the first dummy impurity implantation region 14da.

[0156] In the following description, reference will be made to Figure 21 and Figure 22 Description Reference Figure 10 One or more examples of forming a semiconductor pattern (S60) are described. Figure 21 and Figure 22 It is a reference. Figure 10 Cross-sectional views of one or more examples of the formed semiconductor pattern (S60) are described to illustrate the pattern along... Figure 1B The regions intercepted by lines I-I', II-II', III-III', and IV-IV' are described below. The use of references will be further explained in the following text. Figure 20 The described joint structure ( Figure 20 The method in 33b) will be based on the reference. Figure 18 The described joint structure ( Figure 18 33b) describes the parts that can be modified or replaced.

[0157] refer to Figure 10 and Figure 21 Forming the first semiconductor structure (S10) may include forming a second semiconductor substrate that penetrates the described bonding structure. Figure 18 or Figure 20 Grooves 36a, 36b and 36c in 12b).

[0158] Trench 36a, 36b, and 36c may include a first trench 36a penetrating the second semiconductor substrate 12c in the memory cell array region MCA, a second trench 36b penetrating the second semiconductor substrate 12c in the NMOS region NA, and a third trench 36c penetrating the second semiconductor substrate 12c in the PMOS region PA. Trench 36a, 36b, and 36c can penetrate the second semiconductor substrate 12c, can extend downwards, and can penetrate the buffer dielectric layer 21 and the bonding dielectric layer 6.

[0159] Forming the first semiconductor structure (S10) may also include forming preliminary back gate structures 39a, 39b and 39c in trenches 36a, 36b and 36c.

[0160] The preliminary back gate structures 39a, 39b and 39c may include a first preliminary back gate structure 39a in a first trench 36a, a second preliminary back gate structure 39b in a second trench 36b and a third preliminary back gate structure 39c in a third trench 36c.

[0161] Each first preliminary back gate structure 39a may include a first back gate dielectric layer 41a covering the inner wall of the first trench 36a, a preliminary first back gate electrode 43a partially filling the first trench 36a on the first back gate dielectric layer 41a, and a first lower back gate capping layer 45a located on the preliminary first back gate electrode 43a.

[0162] The second preliminary back gate structure 39b may include a second back gate dielectric layer 41b covering the inner wall of the second trench 36b, a preliminary second back gate electrode 43b partially filling the second trench 36b on the second back gate dielectric layer 41b, and a second lower back gate capping layer 45b located on the preliminary second back gate electrode 43b.

[0163] The third preliminary back gate structure 39c may include a third back gate dielectric layer 41c covering the inner wall of the third trench 36c, a preliminary third back gate electrode 43c partially filling the third trench 36c on the third back gate dielectric layer 41c, and a third lower back gate capping layer 45c located on the preliminary third back gate electrode 43c.

[0164] refer to Figure 10 and Figure 22 Forming semiconductor patterns 48a, 48b, 48c and 48d (S60) may also include forming a second semiconductor substrate ( Figure 21 Patterning can be performed on the second semiconductor substrate (12c) after trenches 36a, 36b, and 36c are formed. Figure 21 Patterning is performed on 12b).

[0165] Semiconductor patterns 48a, 48b, 48c and 48d may include a first semiconductor pattern 48a in the memory cell array region MCA, a second semiconductor pattern 48b in the NMOS region NA, a third semiconductor pattern 48c in the PMOS region PA and a dummy semiconductor pattern 48d in the dummy region DA.

[0166] Each first semiconductor pattern 48a may include a first impurity implantation region 14a and a first semiconductor region 16aa located on the first impurity implantation region 14a.

[0167] Each second semiconductor pattern 48b may include a second impurity implantation region 14b and a second semiconductor region 16bb located on the second impurity implantation region 14b.

[0168] Each third semiconductor pattern 48c may include a third impurity implantation region 14c and a third semiconductor region 16cc located on the third impurity implantation region 14c.

[0169] In one or more example embodiments, the dummy semiconductor pattern 48d may include a first dummy impurity implantation region 14da and a second dummy semiconductor region 16dd located on the first dummy impurity implantation region 14da.

[0170] In one or more example embodiments, the first dummy impurity injection region 14da may be replaced by a reference. Figure 18 The first dummy semiconductor region described ( Figure 18 (14d in the middle).

[0171] In the following description, reference will be made to Figure 23 and Figure 24 Description Reference Figure 10 One or more examples of forming a gate structure (S70) are described. Figure 23 and Figure 24 It is a reference. Figure 10 Cross-sectional views of one or more examples of the formed gate structure (S70) are described to illustrate the process along... Figure 1B The regions intercepted by lines I-I', II-II', III-III', and IV-IV'.

[0172] refer to Figure 10 and Figure 23Forming the first semiconductor structure (S10) may further include forming a buffer insulating pattern 51. Forming the buffer insulating pattern 51 may include: forming semiconductor patterns 48a, 48b, 48c, and 48d; forming an insulating material layer covering the semiconductor patterns 48a, 48b, 48c, and 48d and the preliminary back gate structures 39a, 39b, and 39c; and an etch-back insulating material layer. The buffer insulating pattern 51 may be formed on the buffer dielectric layer 21. The buffer insulating pattern 51 may be formed on the exposed side surfaces of the semiconductor patterns 48a, 48b, 48c, and 48d. The buffer insulating pattern 51 may have a vertical thickness greater than the vertical thickness of each of the first impurity implantation region 14a, the second impurity implantation region 14b, and the first dummy impurity implantation region 14da. The upper surface of the buffer insulating pattern 51 may be formed at a horizontal height higher than the horizontal height of the first impurity implantation region 14a, the second impurity implantation region 14b, and the first dummy impurity implantation region 14da.

[0173] refer to Figure 10 and Figure 24 Forming the first semiconductor structure (S10) may further include forming gate structures 54a, 54b, and 54c and a dummy insulating pattern 54d. The gate structures 54a, 54b, and 54c and the dummy insulating pattern 54d may be formed on the buffer insulating pattern 51.

[0174] Gate structures 54a, 54b and 54c may include a first gate structure 54a in the memory cell array region MCA, a second gate structure 54b in the NMOS region NA and a third gate structure 54c in the PMOS region PA.

[0175] Each first gate structure 54a may include a first gate dielectric layer 56a and a first gate electrode 58a. Each first gate structure 54a may also include a first insulating pattern 60a and a first gate overlay pattern 62a.

[0176] Each second gate structure 54b may include a second gate dielectric layer 56b and a second gate electrode 58b. Each second gate structure 54b may also include a second insulating pattern 60b and a second gate overlay pattern 62b.

[0177] Each third gate structure 54c may include a third gate dielectric layer 56c and a third gate electrode 58c. Each third gate structure 54c may also include a third insulating pattern 60c and a third gate overlay pattern 62c.

[0178] In each first gate structure 54a, the first insulating pattern 60a may face the side surface of the corresponding first semiconductor pattern 48a in the first semiconductor pattern 48a, the first gate electrode 58a may face the side surface of the corresponding first semiconductor pattern 48a in the first semiconductor pattern 48a and may be formed between the first insulating pattern 60a and the first semiconductor pattern 48a, the first gate cover pattern 62a may be formed on the first gate electrode 58a, and the first gate dielectric layer 56a may be disposed between the first gate electrode 58a and the first semiconductor pattern 48a and between the first gate cover pattern 62a and the first semiconductor pattern 48a, and may extend between the first insulating pattern 60a and the buffer insulating pattern 51.

[0179] In each second gate structure 54b, the second insulating pattern 60b may face the side surface of the corresponding second semiconductor pattern 48b in the second semiconductor pattern 48b, the second gate electrode 58b may face the side surface of the corresponding second semiconductor pattern 48b in the second semiconductor pattern 48b and may be formed between the second insulating pattern 60b and the second semiconductor pattern 48b, the second gate cover pattern 62b may be formed on the second gate electrode 58b, and the second gate dielectric layer 56b may be disposed between the second gate electrode 58b and the second semiconductor pattern 48b and between the second gate cover pattern 62b and the second semiconductor pattern 48b, and may extend between the second insulating pattern 60b and the buffer insulating pattern 51.

[0180] In each third gate structure 54c, the third insulating pattern 60c may face the side surface of the corresponding third semiconductor pattern 48c in the third semiconductor pattern 48c, the third gate electrode 58c may face the side surface of the corresponding third semiconductor pattern 48c in the third semiconductor pattern 48c and may be formed between the third insulating pattern 60c and the third semiconductor pattern 48c, the third gate cover pattern 62c may be formed on the third gate electrode 58c, and the third gate dielectric layer 56c may be disposed between the third gate electrode 58c and the third semiconductor pattern 48c and between the third gate cover pattern 62c and the third semiconductor pattern 48c, and may extend between the third insulating pattern 60c and the buffer insulating pattern 51.

[0181] The first gate cover pattern 62a, the second gate cover pattern 62b, and the third gate cover pattern 62c can be formed from an insulating material such as silicon oxide or silicon nitride.

[0182] The dummy insulating pattern 54d may include a fourth insulating pattern 60d on the side surface of the buffer insulating pattern 51 facing the dummy semiconductor pattern 48d, and a dummy dielectric layer 56d disposed between the dummy semiconductor pattern 48d and the fourth insulating pattern 60d and extending between the fourth insulating pattern 60d and the buffer insulating pattern 51.

[0183] A dummy insulating pattern 54d can be formed by forming gate structures 54a, 54b and 54c (S70).

[0184] In one or more examples, forming the gate structures 54a, 54b, and 54c and the dummy insulating pattern 54d may include: forming a buffer insulating pattern 51; conformally forming a dielectric layer; forming an electrode layer on the dielectric layer; anisotropically etching the electrode layer; removing the electrode layer from the dummy region DA; forming an insulating material layer covering the anisotropically etched electrode layer and the dielectric layer; and forming the first insulating pattern 60a, the second insulating pattern 60b, and the third insulating pattern 60c and the dummy insulating pattern 54d by planarizing the insulating material layer; forming the first gate electrode 58a, the second gate electrode 58b, and the third gate electrode 58c by etching back the anisotropically etched electrode layer; and forming the first gate cover pattern 62a, the second gate cover pattern 62b, and the third gate cover pattern 62c on the first gate electrode 58a, the second gate electrode 58b, and the third gate electrode 58c. As the portion of the dielectric layer located at a horizontal height higher than that of the semiconductor patterns 48a, 48b, 48c, and 48d is removed, the dielectric layer can be formed as a first gate dielectric layer 56a, a second gate dielectric layer 56b, a third gate dielectric layer 56c, and a dummy dielectric layer 56d.

[0185] In the following description, reference will be made to Figure 25 , Figure 26 and Figure 27 Description Reference Figure 10 One or more examples of the formation of the source / drain region (S75) are described. Figure 25 This is a flowchart illustrating one or more examples of forming source / drain regions (S75), and Figure 26 and Figure 27 This is a cross-sectional view showing one or more examples of the formation of the source / drain region (S75) to illustrate along... Figure 1B The regions intercepted by lines I-I', II-II', III-III', and IV-IV'.

[0186] refer to Figure 10 , Figure 25 and Figure 26The formation of the source / drain region 75 may include forming at least one doped polysilicon layer 64a, 64b, 64c and 64d (S80).

[0187] Forming at least one doped polysilicon layer 64a, 64b, 64c, and 64d (S80) may include forming a doped polysilicon layer doped with a Group 15 element of the periodic table and forming a polysilicon layer doped with a Group 13 element of the periodic table. The Group 15 element may be at least one of phosphorus (P) and arsenic (As). For example, the Group 15 element may be phosphorus (P). The Group 13 element may be boron (B).

[0188] In one or more examples, Group 13 and Group 15 elements may be referred to as impurities.

[0189] In one or more examples, after forming a doped polysilicon layer doped with a group 15 element, a polysilicon layer doped with a group 13 element can be formed.

[0190] In one or more modified examples, after forming a doped polysilicon layer doped with a Group 13 element, a doped polysilicon layer doped with a Group 15 element can be formed.

[0191] At least one doped polysilicon layer 64a, 64b, 64c and 64d may include a first doped polysilicon layer 64a in contact with the first semiconductor pattern 48a, a second doped polysilicon layer 64b in contact with the second semiconductor pattern 48b, a third doped polysilicon layer 64c in contact with the third semiconductor pattern 48c and a dummy doped polysilicon layer 65d in contact with the dummy semiconductor pattern 48d.

[0192] In one or more examples, the first doped polysilicon layer 64a and the second doped polysilicon layer 64b may be doped polysilicon layers doped with Group 15 elements.

[0193] In one or more examples, the third doped polysilicon layer 64c may be a doped polysilicon layer doped with a Group 13 element.

[0194] In one or more examples, the dummy doped polysilicon layer 65d can be a doped polysilicon layer doped with a Group 15 element.

[0195] In one or more modified examples, the dummy doped polysilicon layer 65d can be a doped polysilicon layer doped with a Group 13 element.

[0196] In one or more modified examples, the dummy doped polysilicon layer 65d may not be provided, so that the dummy semiconductor pattern 48d may not be in contact with the doped polysilicon layer.

[0197] refer to Figure 10, Figure 25 and Figure 27 The formation of the source / drain region 75 may also include performing source / drain annealing (S85).

[0198] Performing source / drain annealing (S85) may include: diffusing and activating impurities in at least one first-side impurity implantation region 14a, 14b, 14c and 14da, and simultaneously diffusing impurities in at least one doped polysilicon layer 64a, 64b, 64c and 64d into semiconductor patterns 48a, 48b, 48c and 48d in contact with at least one doped polysilicon layer and activating the impurities.

[0199] In one or more examples, source / drain annealing (S85) can be performed in the range of approximately 900°C to approximately 1050°C, but one or more example embodiments are not limited thereto. For example, depending on how the source / drain annealing is performed, it can be performed at a temperature of 900°C or lower, or at a temperature of 1050°C or higher.

[0200] In one or more examples, when performing source / drain annealing (S85), source / drain annealing can diffuse and activate impurities in semiconductor patterns 48a, 48b, 48c and 48d, and can simultaneously eliminate defects in semiconductor patterns 48a, 48b, 48c and 48d caused by the impurity implantation process.

[0201] By performing source / drain annealing (S85), impurities in at least one first-side impurity injection region 14a, 14b, 14c and 14da can be diffused and activated, thereby forming at least one first-side source / drain region SD1a, SD2a, SD3a and SDd1.

[0202] By performing source / drain annealing (S85), impurities in at least one doped polysilicon layer can diffuse into and be activated in semiconductor patterns 48a, 48b, 48c and 48d, forming at least one second-side source / drain region SD1b, SD2b, SD3b and SDd2.

[0203] Because impurities in at least one second-side impurity implantation region 14a, 14b, 14c and 14da can diffuse and be activated, at least one first-side source / drain region SD1a, SD2a, SD3a and SDd1 can be formed.

[0204] At least one first-side source / drain region SD1a, SD2a, SD3a and SDd1 may be spaced apart from at least one second-side source / drain region SD1b, SD2b, SD3b and SDd2 in the vertical direction Z.

[0205] Each first semiconductor pattern 48a may include a first upper source / drain region SD1a and a first lower source / drain region SD1b spaced apart from each other in the vertical direction Z, and a first channel region CH1 located between the first upper source / drain region SD1a and the first lower source / drain region SD1b.

[0206] The first impurity injection region can be diffused and activated by performing source / drain annealing (S85). Figure 26 The impurities in the first doped polysilicon layer 64a are used to form the first upper source / drain region SD1a. As the impurities in the first doped polysilicon layer 64a diffuse into the first semiconductor pattern 48a by performing source / drain annealing (S85), the first lower source / drain region SD1b can be formed, and the impurities diffused into the first semiconductor pattern 48a are activated.

[0207] In one or more examples, the vertical thickness of the first upper source / drain region SD1a can be greater than the vertical thickness of the first lower source / drain region SD1b.

[0208] In one or more examples, the first upper source / drain region SD1a and the first lower source / drain region SD1b can be formed by diffusion and activation of the same element. For example, the first upper source / drain region SD1a and the first lower source / drain region SD1b may include at least one of phosphorus (P) or arsenic (As).

[0209] In the modified example, to control the vertical thickness of the first upper source / drain region SD1a and the first lower source / drain region SD1b, the first upper source / drain region SD1a and the first lower source / drain region SD1b may include different elements. For example, the first upper source / drain region SD1a can be formed by diffusing and activating arsenic (As) which has a lower diffusion rate than phosphorus (P), and the first lower source / drain region SD1b can be formed by diffusing and activating phosphorus (P) which has a higher diffusion rate than arsenic (As).

[0210] Each second semiconductor pattern 48b may include a second upper source / drain region SD2a and a second lower source / drain region SD2b spaced apart from each other in the vertical direction Z, and a second channel region CH2 located between the second upper source / drain region SD2a and the second lower source / drain region SD2b.

[0211] With the second impurity injection region ( Figure 26Impurities in layer 14b) diffuse and are activated by performing source / drain annealing (S85), forming a second upper source / drain region SD2a. As impurities in the second doped polysilicon layer 64b diffuse into the second semiconductor pattern 48b by performing source / drain annealing (S85), a second lower source / drain region SD2b is formed, and impurities diffused into the second semiconductor pattern 48b are activated.

[0212] In one or more examples, the vertical thickness of the second upper source / drain region SD2a can be greater than the vertical thickness of the second lower source / drain region SD2b.

[0213] Each third semiconductor pattern 48c may include a third upper source / drain region SD3a and a third lower source / drain region SD3b spaced apart from each other in the vertical direction Z, and a third channel region CH3 located between the third upper source / drain region SD3a and the third lower source / drain region SD3b.

[0214] The third impurity injection region can be diffused and activated by performing source / drain annealing (S85). Figure 26 The third upper source / drain region SD3a is formed by impurities in 14c). The third lower source / drain region SD3b can be formed by diffusing impurities in the third doped polysilicon layer 64c into the third semiconductor pattern 48c and activating the impurities diffused into the third semiconductor pattern 48c via performing source / drain annealing (S85).

[0215] In one or more examples, the vertical thickness of the third upper source / drain region SD3a can be greater than the vertical thickness of the third lower source / drain region SD3b.

[0216] In one or more examples, the dummy semiconductor pattern 48d may include a first dummy source / drain region SDd1 and a second dummy source / drain region SDd2 spaced apart from each other in the vertical direction Z, and a dummy semiconductor region CHd located between the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2. The dummy semiconductor region CHd may be an undoped semiconductor region.

[0217] The first dummy impurity injection region can be diffused and activated by performing source / drain annealing (S85). Figure 26 The first dummy source / drain region SDd1 is formed by impurities in the dummy doped polysilicon layer 64d. As the impurities in the dummy doped polysilicon layer 64d diffuse into the dummy semiconductor pattern 48d by performing source / drain annealing (S85) and the impurities diffused into the dummy semiconductor pattern 48d are activated, the second dummy source / drain region SDd2 can be formed.

[0218] In one or more examples, the vertical thickness of the first dummy source / drain region SDd1 can be greater than the vertical thickness of the second dummy source / drain region SDd2.

[0219] At least one first-side source / drain region SD1a, SD2a, SD3a and SDd1 may include a first upper source / drain region SD1a, a second upper source / drain region SD2a, a third upper source / drain region SD3a and a first dummy source / drain region SDd1.

[0220] At least one second-side source / drain region SD1b, SD2b, SD3b and SDd2 may include a first lower source / drain region SD1b, a second lower source / drain region SD2b, a third lower source / drain region SD3b and a second dummy source / drain region SDd2.

[0221] The first upper source / drain region SD1a, the first lower source / drain region SD1b, the second upper source / drain region SD2a, and the second lower source / drain region SD2b can have N-type conductivity, and the third upper source / drain region SD3a and the third lower source / drain region SD3b can have P-type conductivity.

[0222] In one or more examples, the first upper source / drain region SD1a and the first dummy source / drain region SDd1 can be formed by diffusion and activation of the same element. The first upper source / drain region SD1a and the first dummy source / drain region SDd1 can have the same conductivity type. The first upper source / drain region SD1a and the first dummy source / drain region SDd1 can have N-type conductivity. The impurity concentration in the first dummy source / drain region SDd1 can be higher than the impurity concentration in the first upper source / drain region SD1a.

[0223] In one or more examples, the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2 may have the same conductivity type. For example, the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2 may have N-type conductivity or P-type conductivity.

[0224] In one or more modified examples, the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2 can have different conductivity types. For example, one of the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2 can have N-type conductivity, and the other can have P-type conductivity. For example, the first dummy source / drain region SDd1 can have N-type conductivity, and the second dummy source / drain region SDd2 can have P-type conductivity. In another example, the first dummy source / drain region SDd1 can have P-type conductivity, and the second dummy source / drain region SDd2 can have N-type conductivity.

[0225] In one or more modified examples, at least one of the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2 may not be provided, and the region where at least one of the first dummy source / drain region SDd1 and the second dummy source / drain region SDd2 is not provided may be formed as a dummy semiconductor region CHd. For example, when the dummy doped polysilicon layer 65d is not formed, the second dummy source / drain region SDd2 may not be formed.

[0226] A unit transistor cTR can be formed, comprising a first upper source / drain region SD1a, a first lower source / drain region SD1b, a first channel region CH1, a first gate dielectric layer 56a, and a first gate electrode 58a. The first gate electrode 58a can be a word line.

[0227] A first peripheral transistor N_TR can be formed, comprising a second upper source / drain region SD2a, a second lower source / drain region SD2b, a second channel region CH2, a second gate dielectric layer 56b, and a second gate electrode 58b. The first peripheral transistor N_TR can be an NMOS transistor.

[0228] A second peripheral transistor P_TR can be formed, comprising a third upper source / drain region SD3a, a third lower source / drain region SD3b, a third channel region CH3, a third gate dielectric layer 56c, and a third gate electrode 58c. The second peripheral transistor P_TR can be a PMOS transistor.

[0229] Reference Figure 28 , Figure 29 and Figure 30 Description Reference Figure 25 , Figure 26 and Figure 27 The description includes a modified example of forming the source / drain region (S75). Figure 28 This is a flowchart illustrating a modified example of forming the source / drain region (S75), and Figure 29 and Figure 30This is a cross-sectional view showing a modified example of forming the source / drain region (S75) to illustrate along... Figure 1B The regions intercepted by lines I-I', II-II', III-III', and IV-IV'.

[0230] refer to Figure 10 , Figure 28 and Figure 29 The source / drain region (S75) may not include a reference. Figure 25 and Figure 26 The formation of at least one doped polysilicon layer is described. Figure 26 (S80) and may include forming at least one second-side impurity injection region 63a, 63b, 63c and 63d (S82).

[0231] Forming at least one second-side impurity implantation region 63a, 63b, 63c, and 63d (S82) may include performing at least one impurity implantation process in Figure 24 The semiconductor patterns 48a, 48b, 48c and 48d are doped with impurities.

[0232] In one or more examples, forming at least one second-side impurity implantation region 63a, 63b, 63c, and 63d (S82) may include a first impurity implantation process for doping a Group 15 element in the periodic table and a second impurity implantation process for doping a Group 13 element in the periodic table. Here, the Group 15 element may be phosphorus (P) or arsenic (As), and the Group 13 element may be boron (B).

[0233] In one or more examples, a second impurity implantation process may be performed after the first impurity implantation process is executed.

[0234] In one or more modified examples, the first impurity implantation process may be performed after the second impurity implantation process is performed.

[0235] In one or more examples, at least one second-side impurity injection region 63a, 63b, 63c and 63d may be spaced apart from at least one first-side impurity injection region 14a, 14b, 14c and 14da in the vertical direction Z.

[0236] In one or more examples, at least one second-side impurity implantation region 63a, 63b, 63c, and 63d may include a fourth impurity implantation region 63a formed in the first semiconductor pattern 48a, a fifth impurity implantation region 63b formed in the second semiconductor pattern 48b, a sixth impurity implantation region 63c formed in the third semiconductor pattern 48c, and a second dummy impurity implantation region 63d formed in the dummy semiconductor pattern 48d.

[0237] In one or more examples, the fourth impurity implantation region 63a and the fifth impurity implantation region 63b can be formed by a first impurity implantation process using elements of group 15 in the periodic table, and the sixth impurity implantation region 63c can be formed by a second impurity implantation process using elements of group 13 in the periodic table.

[0238] In one or more examples, the second dummy impurity implantation region 63d can be formed by a first impurity implantation process doped with a group 15 element.

[0239] In one or more modified examples, the second dummy impurity implantation region 63d can be formed by a second impurity implantation process doped with group 13 elements.

[0240] In one or more modified examples, the formation of the second dummy impurity injection region 63d may be omitted.

[0241] Each first semiconductor pattern 48a may include a first impurity implantation region 14a, a fourth impurity implantation region 63a, and a first semiconductor region 16aa located between the first impurity implantation region 14a and the fourth impurity implantation region 63a.

[0242] Each second semiconductor pattern 48b may include a second impurity implantation region 14b, a fifth impurity implantation region 63b, and a second semiconductor region 16bb located between the second impurity implantation region 14b and the fifth impurity implantation region 63b.

[0243] Each third semiconductor pattern 48c may include a third impurity implantation region 14c, a sixth impurity implantation region 63c, and a third semiconductor region 16cc located between the third impurity implantation region 14c and the sixth impurity implantation region 63c.

[0244] In one or more examples, the dummy semiconductor pattern 48d may include a first dummy impurity implantation region 14d, a second dummy impurity implantation region 63d, and a dummy semiconductor region 16dd located between the first dummy impurity implantation region 14d and the second dummy impurity implantation region 63d.

[0245] In one or more modified examples, at least one of the first dummy impurity implantation region 14d and the second dummy impurity implantation region 63d may not be formed. In the dummy semiconductor pattern 48d, the region in which at least one of the first dummy impurity implantation region 14d and the second dummy impurity implantation region 63d is not formed may be formed as the dummy semiconductor region 16dd.

[0246] refer to Figure 10 , Figure 28 and Figure 30The formation of the source / drain region 75 may further include performing source / drain annealing (S85a). Performing source / drain annealing (S85a) may include diffusing and activating impurities in at least one first-side impurity implantation region 14a, 14b, 14c and 14da and impurities in at least one second-side impurity implantation region 63a, 63b, 63c and 63d.

[0247] By performing source / drain annealing (S85a), impurities in at least one first-side impurity implantation region 14a, 14b, 14c, and 14da can be diffused and activated, thereby forming a reference. Figure 27 At least one first-side source / drain region SD1a, SD2a, SD3a and SDd1 is described.

[0248] By performing source / drain annealing (S85a), impurities in at least one second-side impurity implantation region 63a, 63b, 63c and 63d can be diffused and activated, thereby forming at least one second-side source / drain region SD1ba, SD2ba, SD3ba and SDd2a.

[0249] The vertical thickness of at least one first-side impurity implantation region 14a, 14b, 14c, and 14da, and the vertical thickness of at least one second-side impurity implantation region 63a, 63b, 63c, and 63d, can be controlled by an impurity implantation process. Therefore, the vertical thickness of at least one second-side source / drain region SD1ba, SD2ba, SD3ba, and SDd2a, and the vertical thickness of at least one first-side source / drain region SD1a, SD2a, SD3a, and SDd1a, can be adjusted differently according to the desired characteristics of the semiconductor device.

[0250] In one or more examples, the vertical thickness of at least one second-side source / drain region SD1ba, SD2ba, SD3ba and SDd2a may be greater than the vertical thickness of at least one first-side source / drain region SD1a, SD2a, SD3a and SDd1.

[0251] In one or more modified examples, the vertical thickness of at least one second-side source / drain region SD1ba, SD2ba, SD3ba and SDd2a may be substantially the same as the vertical thickness of at least one first-side source / drain region SD1a, SD2a, SD3a and SDd1.

[0252] At least one second-side source / drain region SD1ba, SD2ba, SD3ba, and SDd2a can be formed having a larger size than at least one second-side source / drain region described above. Figure 27 The vertical thickness of SD1b, SD2b, SD3b, and SDd2 is the largest vertical thickness.

[0253] In addition to the vertical thickness, at least one second-side source / drain region SD1ba, SD2ba, SD3ba, and SDd2a can be associated with at least one second-side source / drain region described above. Figure 27 The SD1b, SD2b, SD3b, and SDd2a in the above description are substantially the same. For example, at least one second-side source / drain region SD1ba, SD2ba, SD3ba, and SDd2a may include the first lower source / drain region SD1ba, the second lower source / drain region SD2ba, the third lower source / drain region SD3b, and the second dummy source / drain region SD2da, respectively, corresponding to the first lower source / drain region SD1b, the second lower source / drain region SD2b, the third lower source / drain region SD3b, and the second dummy source / drain region SD2d described above.

[0254] In the following description, reference will be made to Figure 31 , Figure 32 , Figure 33 , Figure 34 and Figure 35 The description includes references Figure 10 The description includes one or more examples of forming a first semiconductor structure (S10) by forming a data storage structure (S90) and forming bit lines (S95). Figure 31 , Figure 32 , Figure 33 , Figure 34 and Figure 35 This is a cross-sectional view showing one or more examples of forming the first semiconductor structure (S10), illustrating along... Figure 1B The regions intercepted by lines I-I', II-II', III-III', and IV-IV'.

[0255] refer to Figure 10 and Figure 31 Forming the first semiconductor structure (S10) may also include forming contact patterns 68a, 68b, 68c and 68d.

[0256] Contact patterns 68a, 68b, 68c and 68d can be connected to semiconductor patterns 48a, 48b, 48c and 48d.

[0257] In one or more examples, contact patterns 68a, 68b, 68c, and 68d can be formed to connect to a reference. Figure 27 At least one second-side source / drain region SD1b, SD2b, SD3b, and SDd2 is described. For example, forming contact patterns 68a, 68b, 68c, and 68d may be included in the reference... Figure 27 At least one doped polysilicon layer described ( Figure 27At least one conductive layer 66a, 66b, 66c and 66d is formed on 64a, 64b, 64c and 64d, and the at least one conductive layer 66a, 66b, 66c and 66d and at least one doped polysilicon layer 64a, 64b, 64c and 64d are patterned.

[0258] In another example, contact patterns 68a, 68b, 68c, and 68d can be formed to connect to a reference. Figure 30 At least one second-side source / drain region SD1ba, SD2ba, SD3ba, and SDd2a is described. For example, forming contact patterns 68a, 68b, 68c, and 68d may include: forming a doped polysilicon layer in contact with the semiconductor patterns 48a, 48b, 48c, and 48d including at least one second-side source / drain region SD1ba, SD2ba, SD3ba, and SDd2a; forming a conductive layer on the doped polysilicon layer; and patterning the conductive layer and the doped polysilicon layer.

[0259] In the following text, the connection of contact patterns 68a, 68b, 68c and 68d to the reference will be described in detail. Figure 27 Examples of at least one of the second-side source / drain regions SD1b, SD2b, SD3b, and SDd2.

[0260] In one or more examples, contact patterns 68a, 68b, 68c, and 68d may include a first contact pattern 68a connected to a first lower source / drain region SD1b, a second contact pattern 68b connected to a second lower source / drain region SD2b, a third contact pattern 68c connected to a third lower source / drain region SD3b, and a dummy contact pattern 68d connected to a second dummy source / drain region SD2d.

[0261] Each first contact pattern 68a may include a first doped polysilicon layer 64a and a first conductive layer 66a stacked sequentially. Each second contact pattern 68b may include a second doped polysilicon layer 64b and a second conductive layer 66b stacked sequentially. Each third contact pattern 68c may include a third doped polysilicon layer 64c and a third conductive layer 66c stacked sequentially. A dummy contact pattern 68d may include a dummy doped polysilicon layer 64d and a dummy conductive layer 66d stacked sequentially.

[0262] In another example, the formation of the dummy contact pattern 68d can be omitted.

[0263] Forming the first semiconductor structure (S10) may also include forming an interlayer insulating layer 71 on the side surfaces of the contact patterns 68a, 68b, 68c and 68d.

[0264] refer to Figure 10and Figure 32 Forming the first semiconductor structure (S10) may further include forming lower peripheral interconnects 70a and 70b. For example, the lower peripheral interconnects 70a and 70b may include a first lower peripheral interconnect 70a connected to at least one second contact pattern 68b and a second lower peripheral interconnect 70b connected to at least one third contact pattern 68c.

[0265] Forming the first semiconductor structure (S10) may further include forming an insulating etch stop layer 72, which covers a structure including contact patterns 68a, 68b, 68c and 68d, an interlayer insulating layer 71, and lower peripheral interconnects 70a and 70b.

[0266] Forming the first semiconductor structure (S10) may also include forming a data storage structure 74 (S90).

[0267] The data storage structure 74 may include a first electrode 76a that penetrates the etch stop layer 72 and is connected to the first contact pattern 68a and extends upward therefrom, a dielectric layer 76b covering the first electrode 76a and the etch stop layer 72, and a second electrode 76c covering the dielectric layer 76b. The data storage structure 74 may be a cell capacitor for storing data in a memory such as DRAM. The data storage structure 74 and the cell transistor cTR may be included in a memory cell MC of a memory such as DRAM.

[0268] Forming the first semiconductor structure (S10) may further include: forming a first insulating layer 78 on the structure including the data storage structure 74 and the etch stop layer 72; forming an interconnect 82 that penetrates the first insulating layer 78 and is connected to the second electrode 76c; and forming a lower insulating layer 84 that covers the first insulating layer 78 and the interconnect 82.

[0269] Forming the first semiconductor structure (S10) may also include bonding the structure, including the lower insulating layer 84, to the disposal wafer 86 using a bonding layer 88.

[0270] refer to Figure 10 and Figure 33 Forming the first semiconductor structure (S10) may further include removing the first semiconductor substrate 3. When the first semiconductor substrate 3 is removed, the preliminary back gate structures 39a, 39b and 39c and the bonding dielectric layer 6 may be exposed.

[0271] refer to Figure 10 and Figure 34Forming the first semiconductor structure (S10) may further include forming preliminary back gate structures 39a, 39b, and 39c as back gate structures 39aa, 39ba, and 39ca. While forming the back gate structures 39aa, 39ba, and 39ca, the bonding dielectric layer 6 may be removed, and the semiconductor patterns 48a, 48b, 48c, and 48d may be exposed.

[0272] Forming the back gate structures 39aa, 39ba, and 39ca may include: exposing a preliminary first back gate electrode 43a, a preliminary second back gate electrode 43b, and a preliminary third back gate electrode 43c; forming the first back gate electrode 43aa, the second back gate electrode 43ba, and the third back gate electrode 43ca by etching portions of the preliminary first back gate electrode 43a, the preliminary second back gate electrode 43b, and the preliminary third back gate electrode 43c; and forming a fourth back gate capping layer 46a, a fifth back gate capping layer 46b, and a sixth back gate capping layer 46c. The first upper back gate capping layer 46a may be formed on the first back gate electrode 43aa, the second upper back gate capping layer 46b may be formed on the second back gate electrode 43ba, and the third upper back gate capping layer 46c may be formed on the third back gate electrode 43ca.

[0273] The back gate structures 39aa, 39ba and 39ca may include a first back gate structure 39aa, a second back gate structure 39ba and a third back gate structure 39ca.

[0274] Each first back gate structure 39aa may include a first back gate dielectric layer 41a, a first back gate electrode 43aa, a first lower back gate capping layer 45a, and a first upper back gate capping layer 46a. The second back gate structure 39ba may include a second back gate dielectric layer 41b, a second back gate electrode 43ba, a second lower back gate capping layer 45b, and a second upper back gate capping layer 46b. The third back gate structure 39ca may include a third back gate dielectric layer 41c, a third back gate electrode 43ca, a third lower back gate capping layer 45c, and a third upper back gate capping layer 46c.

[0275] refer to Figure 10 and Figure 35 Forming the first semiconductor structure (S10) may further include forming a bit line 90a (S95). Forming the first semiconductor structure (S10) may further include forming upper peripheral interconnects 90b and 90c simultaneously with the bit line 90a. The upper peripheral interconnects 90b and 90c may include a first upper peripheral interconnect 90b and a second upper peripheral interconnect 90c.

[0276] Forming bit line 90a and upper peripheral interconnects 90b and 90c may include: forming conductive material layers 91a, 91b and 91c stacked sequentially; forming insulating overlay patterns 92a, 92b and 92c on the conductive material layers 91a, 91b and 91c; and etching the conductive material layers 91a, 91b and 91c using an etching process that uses the insulating overlay patterns 92a, 92b and 92c as etching masks.

[0277] The conductive material layers 91a, 91b, and 91c may comprise a first material layer 91a, a second material layer 91b, and a third material layer 91c stacked sequentially. The first material layer 91a may comprise doped polysilicon. The second material layer 91b may comprise at least one of a metal nitride and a metal semiconductor compound. The third material layer 91c may comprise a metal.

[0278] Bit line 90a can be connected to the first upper source / drain region SD1a, the first upper peripheral interconnect 90b can be connected to the second upper source / drain region SD2a, and the second upper peripheral interconnect 90c can be connected to the third upper source / drain region SD3a.

[0279] Forming the first semiconductor structure (S10) may include forming a first intermediate insulating layer 93 covering bit lines 90a, upper peripheral interconnects 90b and 90c, and covering patterns 92a, 92b and 92c.

[0280] Forming the first semiconductor structure (S10) may further include: forming a routing interconnect 95 on the first intermediate insulating layer 93; forming a second intermediate insulating layer 97 covering the routing interconnect 95; and forming a first bonding dielectric layer 99 on the second intermediate insulating layer 97.

[0281] In one or more examples, the first bonding dielectric layer 99 may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN. In one or more examples, the first bonding dielectric layer 99 may be formed from two or more of the aforementioned materials.

[0282] In the following description, reference will be made to Figure 36 Description Reference Figure 9 One or more examples of forming a second semiconductor structure (S110) are described. Figure 36 This is a cross-sectional view showing one or more examples of forming a second semiconductor structure (S110) to illustrate along... Figure 1B The regions intercepted by lines I-I', II-II', III-III', and IV-IV'.

[0283] refer to Figure 9 and Figure 36Forming the second semiconductor structure (S110) may include forming a peripheral transistor PTR. Each peripheral transistor PTR may include a peripheral source / drain region pSD, a peripheral channel region pCH located between the peripheral source / drain regions pSD, a peripheral gate electrode pGE located on the peripheral channel region pCH, and a peripheral gate dielectric layer pGO located between the peripheral channel region pCH and the peripheral gate electrode pGE.

[0284] In one or more examples, forming the second semiconductor structure (S110) may include: forming a peripheral device isolation region 106s defining a peripheral active region 106a on the upper substrate 103; forming a peripheral transistor PTR; forming a front insulating layer 112 covering the peripheral transistor PTR; reducing the thickness of the upper substrate 103; forming a back insulating layer 115 covering the back side of the upper substrate 103; and forming a second bonding dielectric layer 118 covering the back insulating layer 115.

[0285] In each peripheral transistor PTR, the peripheral source / drain region pSD and the peripheral channel region pCH can be formed in the corresponding peripheral active region 106a, and the peripheral gate dielectric layer pGO and the peripheral gate electrode pGE can be formed on the peripheral channel region pCH in the peripheral active region 106a.

[0286] In one or more examples, the second bonding dielectric layer 118 may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN. In one or more examples, the second bonding dielectric layer 118 may be formed from two or more of the aforementioned materials.

[0287] In the following description, reference will be made to Figure 37 Description Reference Figure 9 One or more examples of semiconductor structures (S120) forming a junction are described. Figure 37 This is a cross-sectional view showing one or more examples of the semiconductor structure (S120) forming the junction, illustrating the relationship along... Figure 1B The regions intercepted by lines I-I', II-II', III-III', and IV-IV'.

[0288] refer to Figure 9 and Figure 37 The formation of the bonded semiconductor structure (S120) may include bonding the structure formed by forming the first semiconductor structure (S10) as described above to the structure formed by forming the second semiconductor structure (S110) as described above. For example, the formation of the bonded semiconductor structure (S120) may include performing a dielectric-dielectric bonding process to bond the structure formed by forming the first semiconductor structure (S10) as described above. Figure 35The first bonding dielectric layer 99 in the middle is bonded to Figure 36 The second bonding dielectric layer 118 is in the middle. Therefore, the first bonding dielectric layer 99 and the second bonding dielectric layer 118 can be bonded to each other to form a bonding region JN.

[0289] In one or more examples, forming the junction semiconductor structure (S120) may include: forming a via 114 that penetrates the front insulating layer 112 and the upper substrate 103, extends downward and exposes the routing interconnect 95; forming an insulating spacer 119 on the side surface of the via 114; and forming a conductive path 120 in the via 114. The conductive path 120 may be electrically connected to the routing interconnect 95.

[0290] In one or more examples, the semiconductor structure forming the junction (S120) may also include a contact plug 121 that forms a penetrating front insulating layer 112 and is electrically connected to the peripheral transistor PTR.

[0291] In one or more examples, the semiconductor structure forming the junction (S120) may further include: forming an upper interconnect structure 127 buried in the upper insulating layer 124; and forming input / output pads 130 electrically connected to the upper interconnect structure 127. The upper interconnect structure 127 may be formed on the front insulating layer 112 and may be electrically connected to the contact plug 121 and the conductive path 120.

[0292] In one or more examples, reference Figure 37 The structure from the lower insulating layer 84 to the first bonding dielectric layer 99 can be defined as a first semiconductor structure STC1, and the structure from the first bonding dielectric layer 99 to the input / output pads 130 can be defined as a second semiconductor structure STC2.

[0293] In one or more examples, reference Figure 37 In the first semiconductor structure STC1, the structure from the lower insulating layer 84 to the first intermediate insulating layer 93 can be defined as the lower structure LC, and the structure located on the lower structure LC can be defined as the upper structure US.

[0294] Return to reference Figure 1B , Figure 2A and Figure 2B The bonding layer 88 and the wafer 86 can be removed. Subsequently, a semiconductor device 1 can be formed by performing semiconductor processes, including packaging processes.

[0295] In the following description, reference will be made to Figure 38 , Figure 39 and Figure 40 One or more examples of methods for manufacturing a semiconductor device according to one or more example embodiments are described. Figure 38 , Figure 39 and Figure 40 It shows along Figure 1B Cross-sectional views of the regions intercepted by lines I-I', II-II', III-III', and IV-IV'. Figure 38 This is a cross-sectional view showing one or more examples of forming the first semiconductor structure (S10). Figure 39 It is a cross-sectional view showing one or more examples of forming a second semiconductor structure (S110), and Figure 40 It is a cross-sectional view showing one or more examples of semiconductor structures (S120) forming a junction.

[0296] refer to Figure 9 and Figure 38 Forming the first semiconductor structure (S10) may also include a reference Figure 35 A first bonding pad 202 is formed in the described structure. The first bonding pad 202 may include a metallic material, such as copper (Cu). The first bonding pad 202 may have an upper surface coplanar with the upper surface of the first bonding dielectric layer 99 and may be electrically connected to the routing interconnect 95.

[0297] refer to Figure 9 and Figure 39 To form a second semiconductor structure ( Figure 9 S110 in the process may include forming a peripheral transistor PTR'. Each peripheral transistor PTR' may include a peripheral source / drain region pSD, a peripheral channel region pCH located between the peripheral source / drain regions pSD, a peripheral gate electrode pGE located on the peripheral channel region pCH, and a peripheral gate dielectric layer pGO located between the peripheral channel region pCH and the peripheral gate electrode pGE.

[0298] In one or more examples, a second semiconductor structure is formed ( Figure 9 S110 may include: forming a peripheral device isolation region 106s defining a peripheral active region 206a on an upper substrate 203; forming a peripheral transistor PTR'; forming an upper interconnect structure 215 buried in an upper insulating layer 212 covering the peripheral transistor PTR' and electrically connected to the peripheral transistor PTR'; forming a second bonding dielectric layer 218 on the upper insulating layer 212; and forming a second bonding pad 221.

[0299] In each peripheral transistor PTR', the peripheral source / drain region pSD and the peripheral channel region pCH can be formed in the corresponding peripheral active region 206a, and the peripheral gate dielectric layer pGO and the peripheral gate electrode pGE can be formed on the peripheral channel region pCH in the peripheral active region 206a.

[0300] The second bonding pad 221 may include a metallic material, such as copper (Cu). The second bonding pad 221 may have an upper surface that is coplanar with the upper surface of the second bonding dielectric layer 218 and may be electrically connected to the upper interconnect structure 215.

[0301] In one or more examples, the second bonding dielectric layer 218 may include at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

[0302] refer to Figure 9 and Figure 40 To form a bonded semiconductor structure ( Figure 9 S120 in the process may include performing a hybrid bonding process including metal-metal bonding and dielectric-dielectric bonding. For example, forming a bonded semiconductor structure ( Figure 9 S120 may include bonding the first bonding pad 202 to the second bonding pad 221 and simultaneously bonding the first bonding dielectric layer 99 to the second bonding dielectric layer 218.

[0303] In one or more examples, a bonded semiconductor structure is formed ( Figure 9 S120 may include: performing a hybrid bonding process; reducing the thickness of the upper substrate 203; forming an upper substrate 203 with a reduced thickness; forming a cover insulating layer 230 on the upper substrate 203 with a reduced thickness; forming a via 233 that penetrates the cover insulating layer 230 and the upper substrate 203 with a reduced thickness and exposes the upper interconnect structure 215; forming an insulating spacer 236 on the side surface of the via 233; forming a conductive path 239 in the via 233; and forming input / output pads 242 on the conductive path 239. The conductive path 239 may be electrically connected to the upper interconnect structure 215.

[0304] Return to reference Figure 1B and Figure 4 The bonding layer 88 and the wafer 86 can be removed. Subsequently, a semiconductor device 1 can be formed by performing semiconductor processes, including packaging processes.

[0305] In the following description, reference will be made to Figure 41 and Figure 42 One or more examples of methods for manufacturing a semiconductor device according to one or more example embodiments are described. Figure 41 It is a reference. Figure 10 The flowchart describes a modified example of forming the joining structure (S15), and Figure 42 This is a perspective view showing a modified example of forming the joint structure (S15).

[0306] refer to Figure 41 and Figure 42 as well as Figure 10 Forming the bonding structure 313c (S15a) may include preparing a first semiconductor substrate 3 (S20) and forming a bonding dielectric layer 6 on the first semiconductor substrate 3 (S25). The first semiconductor substrate 3 and the bonding dielectric layer 6 may be included in the first structure 9. The first semiconductor substrate 3 may be a single-crystal silicon substrate. The bonding dielectric layer 6 may be an oxide layer.

[0307] Forming the bonding structure 313c (S15a) may further include preparing a preliminary second semiconductor substrate 12a (S30). The preliminary second semiconductor substrate 12a may be a single-crystal silicon substrate.

[0308] Forming the bonding structure 313c (S15a) may further include forming a preliminary bonding structure 333a (S210). Forming the preliminary bonding structure 333a (S210) may include bonding the first structure 9 and the preliminary second semiconductor substrate 12a. The bonding dielectric layer 6 may be bonded to the preliminary second semiconductor substrate 12a. The first structure 9 and the preliminary second semiconductor substrate 12a may be bonded to each other and may be formed as the preliminary bonding structure 333a.

[0309] Forming the bonding structure 313c (S15a) may also include forming a second semiconductor substrate 12b by reducing the thickness of the initial second semiconductor substrate 12a of the initial bonding structure 333a (S215).

[0310] Forming the bonding structure 313c (S15a) may further include forming at least one first-side impurity implantation region in the second semiconductor substrate 12b (S220).

[0311] In one or more examples, it can be derived from, as referenced Figure 18 At least one first-side impurity injection region described ( Figure 18 14a, 14b and 14c) form at least one first-side impurity injection region.

[0312] In one or more modified examples, at least one first-side impurity injection region can be formed as shown in the reference. Figure 20 At least one first-side impurity injection region described ( Figure 20 (14a, 14b, 14c and 14da).

[0313] The second semiconductor substrate 12b may include a first portion 12_1 and a second portion 12_2b' located on the first portion 12_1, the first portion 12_1 including at least one first-side impurity implantation region ( Figure 18 (14a, 14b and 14c in the text).

[0314] In one or more examples, at least one first-side impurity implantation region can be formed by performing an impurity implantation process 315 for implanting impurities. Figure 18 14a, 14b, and 14c (in the original text). At least one first-side impurity injection region ( Figure 18 14a, 14b and 14c in the first part 12_1 can be formed by impurities that penetrate the second part 12_2b' and are injected into the first part 12_1.

[0315] Forming the bonding structure 313c (S15a) may further include forming at least one oppositely doped region 12_2b'' in the second semiconductor substrate 12b (S225). At least one oppositely doped region 12_2b'' may be formed in the second portion 12_2b'. This can be achieved by implantation into at least one first-side impurity implantation region (…). Figure 18 At least one oppositely doped region 12_2b'' can be formed by using impurities different from those in 14a, 14b, and 14c. For example, when the first impurity implantation region 14a and the second impurity implantation region 14b are doped with elements of Group 15 in the periodic table, at least one oppositely doped region 12_2b'' located on the first impurity implantation region 14a and the second impurity implantation region 14b can be doped with elements of Group 13 in the periodic table, and when the third impurity implantation region 14c is doped with elements of Group 13 in the periodic table, at least one oppositely doped region 12_2b'' located on the third impurity implantation region 14c can be doped with elements of Group 15 in the periodic table.

[0316] In the following description, reference will be made to Figure 43 and Figure 44 One or more examples of methods for manufacturing a semiconductor device according to one or more example embodiments are described. Figure 43 It is a reference. Figure 10 The flowchart describes a modified example of forming the joining structure (S15), and Figure 44 This is a perspective view showing a modified example of forming the joint structure (S15).

[0317] refer to Figure 43 and Figure 44 as well as Figure 10 Forming the bonding structure 433b (S15b) may include preparing a first semiconductor substrate 3 (S20). The first semiconductor substrate 3 may be a single-crystal silicon substrate.

[0318] Forming the bonding structure 433b (S15b) may further include preparing a preliminary second semiconductor substrate 12a (S30) and forming at least one first-side impurity implantation region in the preliminary second semiconductor substrate 12a (S35).

[0319] The preliminary second semiconductor substrate 12a may include a first portion 12_1 and a preliminary second portion 12_2a located below the first portion 12_1.

[0320] At least one first-side impurity implantation region may be formed in the first portion 12_1 of the preliminary second semiconductor substrate 12a.

[0321] In one or more examples, at least one first-side impurity injection region can be formed as shown in the reference. Figure 18 At least one first-side impurity injection region described ( Figure 18 (14a, 14b, and 14c in the original text). The first portion 12_1 of the preliminary second semiconductor substrate 12a may include at least one first-side impurity implantation region 14a, 14b, and 14c.

[0322] In one or more modified examples, it can be obtained from, as referenced Figure 20 At least one first-side impurity injection region described ( Figure 20 14a, 14b, 14c and 14da) form at least one first-side impurity injection region.

[0323] Forming the bonding structure 433b (S15b) may also include forming the preliminary bonding structure 433a (S340) by performing a wafer bonding process in a humid atmosphere including H2O.

[0324] Forming the preliminary bonding structure 433a (S340) may include bonding the first portion 12_1 of the preliminary second semiconductor substrate 12a to the first semiconductor substrate 3 while oxidizing the surface of the first portion 12_1 of the preliminary second semiconductor substrate 12a and the surface of the first semiconductor substrate 3. As the first portion 12_1 of the preliminary second semiconductor substrate 12a and the first semiconductor substrate 3 are bonded together, an oxide layer 406 may be formed between the first portion 12_1 of the preliminary second semiconductor substrate 12a and the first semiconductor substrate 3. The oxide layer 406 may be a silicon oxide layer.

[0325] Forming the bonding structure 433b (S15b) may include forming the second semiconductor substrate 12b by reducing the thickness of the initial second semiconductor substrate 12a of the initial bonding structure 433a (S345). Forming the second semiconductor substrate 12b may include reducing the initial second portion 12_2a of the initial second semiconductor substrate 12a. As the thickness is reduced, the initial second portion 12_2a may be formed into the second portion 12_2b.

[0326] In the following description, reference will be made to Figure 45 and Figure 46 One or more examples of methods for manufacturing a semiconductor device according to one or more example embodiments are described. Figure 45It is a reference. Figure 10 The flowchart describes a modified example of forming the joining structure (S15), and Figure 46 This is a perspective view showing a modified example of forming the joint structure (S15).

[0327] refer to Figure 45 and Figure 46 as well as Figure 10 Forming the bonding structure 513c (S15c) may include preparing a first semiconductor substrate 3 (S20) and preparing a preliminary second semiconductor substrate 12a (S30). The first semiconductor substrate 3 may be a monocrystalline silicon substrate. The preliminary second semiconductor substrate 12a may be a monocrystalline silicon substrate.

[0328] Forming the bonding structure 513c (S15c) may also include forming the preliminary bonding structure 533a (S440) by performing a wafer bonding process in a humid atmosphere including H2O.

[0329] Forming the preliminary bonding structure 533a (S440) may include bonding the preliminary second semiconductor substrate 12a and the first semiconductor substrate 3 while oxidizing the surfaces of the preliminary second semiconductor substrate 12a and the first semiconductor substrate 3. When the preliminary second semiconductor substrate 12a and the first semiconductor substrate 3 are bonded to each other, an oxide layer 506 may be formed between the preliminary second semiconductor substrate 12a and the first semiconductor substrate 3. The oxide layer 506 may be a silicon oxide layer.

[0330] Forming the bonding structure 513c (S15c) may also include forming a second semiconductor substrate 12b by reducing the thickness of the initial second semiconductor substrate 12a of the initial bonding structure 533a (S445).

[0331] Forming the bonding structure 513c (S15c) may further include forming at least one first-side impurity implantation region in the second semiconductor substrate 12b (S450).

[0332] In one or more examples, it can be derived from, as referenced Figure 18 At least one first-side impurity injection region described ( Figure 18 14a, 14b and 14c) form at least one first-side impurity injection region.

[0333] In one or more modified examples, it can be obtained from, as referenced Figure 20 At least one first-side impurity injection region described ( Figure 18 14a, 14b, and 14c form at least one first-side impurity implantation region. A first-side impurity implantation region ( Figure 20 (14a, 14b, 14c, and 14da).

[0334] The second semiconductor substrate 12b may include a first portion 12_1 and a second portion 12_2b' located on the first portion 12_1, the first portion 12_1 including at least one first-side impurity implantation region ( Figure 18 (14a, 14b and 14c in the text).

[0335] Part 12_1 can be in contact with oxide layer 506.

[0336] In one or more examples, at least one first-side impurity implantation region can be formed by performing an impurity implantation process 315 for implanting impurities. Figure 18 14a, 14b, and 14c (in the original text). At least one first-side impurity injection region ( Figure 18 14a, 14b and 14c in the first part 12_1 can be formed by impurities that penetrate the second part 12_2b' and are injected into the first part 12_1.

[0337] Forming the bonding structure 513c (S15c) may further include forming at least one oppositely doped region 12_2b'' in the second semiconductor substrate 12b (S455). The at least one oppositely doped region 12_2b'' may be formed in the second portion 12_2b'. This may be achieved by implanting at least one first-side impurity implantation region (…). Figure 18 Impurities in 14a, 14b, and 14c that are different from the impurities in the first impurity implantation region 14a and the second impurity implantation region 14b are doped with elements of group 15 in the periodic table. At least one opposite doped region 12_2b'' located on the first impurity implantation region 14a and the second impurity implantation region 14b may be doped with elements of group 13 in the periodic table. And when the third impurity implantation region 14c is doped with elements of group 13 in the periodic table, at least one opposite doped region 12_2b'' located on the third impurity implantation region 14c may be doped with elements of group 15 in the periodic table.

[0338] In the example embodiment described above, multiple dummy semiconductor patterns 48d can be formed. For example, a semiconductor device ( Figure 1A 1) in the text may include, for example, Figure 2A The virtual semiconductor pattern 48a, such as Figure 5 The virtual semiconductor pattern 48a, such as Figure 6 The virtual semiconductor pattern 48a, such as Figure 7 The virtual semiconductor pattern 48a and such Figure 8 The dummy semiconductor pattern 48a in the example. For example, in a semiconductor device ( Figure 1AIn step 1), when the dummy semiconductor pattern 48a is adjacent to an NMOS region or a PMOS region, the dummy semiconductor pattern 48a may include at least one dummy source / drain region. Figure 2A SDd1 or Figure 2A In the SDd2 of the diagram), and when the interconnects for signal transmission are formed in a region adjacent to the dummy semiconductor pattern 48a, in order to minimize the impact (e.g., crosstalk) on the dummy semiconductor pattern 48a and the adjacent interconnects, the dummy semiconductor pattern 48a may not include at least one dummy source / drain region. Figure 2A SDd1 or Figure 2A SDd2 in (the text is incomplete and cannot be translated).

[0339] In the example embodiment described above, the dummy semiconductor pattern 48d can prevent the semiconductor patterns adjacent to the dummy semiconductor pattern 48d among the first semiconductor pattern 48a, the second semiconductor pattern 48b, and the third semiconductor pattern 48c from deforming or warping.

[0340] In the example embodiment described above, by forming a dummy semiconductor pattern 48d at the same or substantially the same horizontal height as the first semiconductor pattern 48a, the second semiconductor pattern 48b, and the third semiconductor pattern 48c, elements adjacent to the upper and lower surfaces of the first semiconductor pattern 48a, the second semiconductor pattern 48b, and the third semiconductor pattern 48c can be stably formed without defects.

[0341] According to an example embodiment, a semiconductor device may include: a first semiconductor pattern including a first lower source / drain region, a first upper source / drain region located on the first lower source / drain region, and a first channel region located between the first lower source / drain region and the first upper source / drain region; a dummy semiconductor pattern disposed at the same or substantially the same horizontal height as the first semiconductor pattern and electrically isolated from the first semiconductor pattern; a first gate electrode facing a side surface of the first semiconductor pattern; a first gate dielectric layer located between the first semiconductor pattern and the first gate electrode; a data storage structure connected to the first lower source / drain region; and a bit line connected to the first upper source / drain region. The width of the dummy semiconductor pattern in a first direction may be greater than the width of the first semiconductor pattern in the first direction. The dummy semiconductor pattern may include a first dummy source / drain region, which includes a portion disposed at the same or substantially the same horizontal height as at least a portion of the first upper source / drain region, and the impurity concentration of the first dummy source / drain region may be different from the impurity concentration of the first upper source / drain region.

[0342] The impurity concentration in the first dummy source / drain region can be higher than the impurity concentration in the first upper source / drain region.

[0343] In semiconductor devices, the dummy semiconductor pattern may further include a dummy semiconductor region located below the first dummy source / drain region. The dummy semiconductor region may be an undoped region.

[0344] A portion of the dummy semiconductor region may be positioned at the same horizontal height as the first lower source / drain region or at substantially the same horizontal height as the first lower source / drain region.

[0345] The dummy semiconductor pattern may further include a second dummy source / drain region located below the dummy semiconductor region. The second dummy source / drain region may include a portion disposed at the same horizontal height as at least a portion of the first lower source / drain region or at a horizontal height substantially the same as at least a portion of the first lower source / drain region.

[0346] The vertical thickness of the first upper source / drain region can be different from the vertical thickness of the first lower source / drain region.

[0347] The vertical thickness of the first upper source / drain region can be greater than the vertical thickness of the first lower source / drain region.

[0348] The semiconductor device may include: a second semiconductor pattern and a third semiconductor pattern disposed at the same or substantially the same horizontal height as the first semiconductor pattern; a second gate electrode facing a side surface of the second semiconductor pattern; and a third gate electrode facing a side surface of the third semiconductor pattern. The second semiconductor pattern may include a second lower source / drain region, a second upper source / drain region located on the second lower source / drain region, and a second channel region located between the second lower source / drain region and the second upper source / drain region. The third semiconductor pattern may include a third lower source / drain region, a third upper source / drain region located on the third lower source / drain region, and a third channel region located between the third lower source / drain region and the third upper source / drain region. The first lower source / drain region, the second lower source / drain region, the first upper source / drain region, and the second upper source / drain region may have N-type conductivity. The third lower source / drain region and the third upper source / drain region may have P-type conductivity.

[0349] The semiconductor device may further include: a first contact pattern located between the data storage structure and the first upper source / drain region; and a dummy contact pattern disposed at the same or substantially the same horizontal height as the first contact pattern and connected to the dummy semiconductor pattern.

[0350] Bit lines may include a polysilicon layer and a metal layer on the polysilicon layer, and the thickness of the metal layer may be greater than the thickness of the polysilicon layer.

[0351] The primary impurity in the first upper source / drain region can be arsenic (As), and the primary impurity in the first lower source / drain region can be phosphorus (P).

[0352] According to the foregoing example embodiments, by providing transistors that include source / drain regions spaced apart from each other in the vertical direction, the integration density of semiconductor devices can be improved.

[0353] In addition, in order to provide a semiconductor device with desired performance, a method can be provided to control the vertical thickness of the lower source / drain region and the upper source / drain region that are spaced apart from each other in the vertical direction.

[0354] Alternatively, a method can be provided for forming a bonding structure including a first semiconductor substrate and a second semiconductor substrate containing impurity regions. A method can also be provided for forming a semiconductor pattern including impurity regions by patterning the second semiconductor substrate including the impurity regions of the bonding structure.

[0355] Additionally, a method for performing source / drain annealing can be provided, which can reduce or eliminate defects in semiconductor patterns without damaging the capacitors of the data storage structure, and can simultaneously form a lower source / drain region and an upper source / drain region spaced apart from each other in the vertical direction.

[0356] Furthermore, by providing a dummy semiconductor pattern at the same or substantially the same horizontal height as the semiconductor pattern, transistors including source / drain regions formed in the dummy pattern can be stably formed without defects.

[0357] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A bonding structure is formed, comprising a first structure and a second structure bonded to each other. The first structure includes a first semiconductor substrate, and the second structure includes a second semiconductor substrate. The second semiconductor substrate includes a first portion adjacent to the first structure and a second portion located on the first portion. The first portion includes a first impurity implantation region doped with a first impurity, and the second portion includes a first semiconductor region located on the first impurity implantation region. At least one semiconductor pattern is formed by patterning the second semiconductor substrate, the at least one semiconductor pattern including a first semiconductor pattern, the first semiconductor pattern including the first impurity implantation region and the first semiconductor region; as well as A first source / drain region and a second source / drain region spaced apart from each other in a first direction are formed in the first semiconductor pattern. The formation of the first source / drain region further includes performing source / drain annealing for diffusion and activation of the first impurity in the first impurity implantation region of the first semiconductor pattern, and The first impurity injection region is formed into the first source / drain region by the source / drain annealing.

2. The method according to claim 1, further comprising: Before forming the first source / drain region and the second source / drain region, a gate structure is formed on the surface facing the first semiconductor pattern; Form a contact pattern connected to the second source / drain region; A data storage structure connected to the contact pattern is formed; After the data storage structure is formed, the first source / drain region is exposed by removing the first structure; as well as A bit line is formed that connects to the exposed first source / drain region.

3. The method according to claim 1, wherein, The formation of the first source / drain region and the second source / drain region further includes: A polycrystalline silicon layer doped with a second impurity is formed on the first semiconductor region of the first semiconductor pattern; and By performing the source / drain annealing, the first impurity in the first impurity implantation region is diffused and activated, and simultaneously the second impurity in the polysilicon layer is diffused into the first semiconductor region of the first semiconductor pattern and activated. Wherein, as the second impurity in the polysilicon layer diffuses into the first semiconductor region of the first semiconductor pattern and is activated in the first semiconductor region of the first semiconductor pattern, the second source / drain region is formed in the first semiconductor pattern.

4. The method according to claim 1, wherein, The formation of the first source / drain region and the second source / drain region further includes: An upper impurity implantation region is formed by doping a portion of the first semiconductor region of the first semiconductor pattern with a second impurity; and By performing the source / drain annealing, the first impurity in the first impurity implantation region and the second impurity in the upper impurity implantation region are simultaneously diffused and activated, and The impurity implantation region is formed into the second source / drain region by the source / drain annealing.

5. The method according to claim 1, wherein, The formation of the joining structure further includes: Forming the first structure including the first semiconductor substrate; Preparing the initial second semiconductor substrate; The first impurity implantation region doped with the first impurity and the preliminary first semiconductor region undoped with the first impurity are formed by doping a portion of the preliminary second semiconductor substrate with the first impurity. A preliminary bonded structure is formed by performing a wafer bonding process that bonds the first structure to the preliminary second semiconductor substrate doped with the first impurity; and The second semiconductor substrate is formed by reducing the thickness of the initial second semiconductor substrate of the initial bonding structure, and The first semiconductor region of the second semiconductor substrate is formed by reducing the thickness of the preliminary first semiconductor region of the preliminary second semiconductor substrate.

6. The method according to claim 5, wherein, Forming the bonding structure further includes forming a bonding dielectric layer on the first semiconductor substrate. The first structure further includes the bonding dielectric layer, and In the preliminary bonding structure, the bonding dielectric layer is located between the first semiconductor substrate and the preliminary second semiconductor substrate.

7. The method according to claim 5, wherein, Forming the bonding structure further includes forming a buffer dielectric layer on the initial second semiconductor substrate, and The buffer dielectric layer is bonded to the first structure via the wafer bonding process.

8. The method according to claim 5, wherein, The wafer bonding process is performed in a humid atmosphere including H2O, and The preliminary bonding structure is formed by bonding a first oxide layer to a second oxide layer via the wafer bonding process. The first oxide layer is formed by oxidation of the first semiconductor substrate, and the second oxide layer is formed by oxidation of the second semiconductor substrate.

9. The method according to claim 1, wherein, The formation of the joining structure further includes: Forming the first structure including the first semiconductor substrate; Preparing the initial second semiconductor substrate; A preliminary bonding structure is formed by performing a wafer bonding process that bonds the first structure to the preliminary second semiconductor substrate; The initial second semiconductor substrate with a reduced thickness is formed by reducing the thickness of the initial bonding structure; and By doping the first impurity in a region of the preliminary second semiconductor substrate having a reduced thickness, a second semiconductor substrate is formed adjacent to the first semiconductor substrate, comprising a first impurity implantation region doped with the first impurity and a first semiconductor region undoped with the first impurity.

10. The method of claim 9, wherein, Forming the bonding structure further includes doping the first semiconductor region of the second semiconductor substrate with an impurity that is opposite to the first impurity.

11. The method according to claim 1, wherein, In the bonding structure, the first portion of the second semiconductor substrate further includes a second impurity implantation region, and the second portion of the second semiconductor substrate further includes a second semiconductor region located on the second impurity implantation region. The at least one semiconductor pattern further includes a second semiconductor pattern, which includes the second impurity implantation region and the second semiconductor region.

12. The method according to claim 11, further comprising: A third source / drain region and a fourth source / drain region spaced apart from each other in the first direction are formed in the second semiconductor pattern; Forming the third source / drain region includes performing source / drain annealing to diffuse and activate one or more impurities in the second impurity implantation region of the second semiconductor pattern. The second impurity implantation region is formed into the third source / drain region through the source / drain annealing. Wherein, the first source / drain region and the second source / drain region have a first conductivity type, and The third source / drain region and the fourth source / drain region have a second conductivity type that is different from the first conductivity type.

13. The method of claim 12, wherein, The at least one semiconductor pattern also includes an electrically isolated dummy semiconductor pattern.

14. The method according to claim 13, wherein, The electrically isolated dummy semiconductor pattern includes a first dummy source / drain region, the first dummy source / drain region having at least a portion disposed at the same horizontal height as the first source / drain region, and The first dummy source / drain region has the same conductivity type as the first source / drain region, and has a first impurity concentration that is higher than the second impurity concentration of the first source / drain region.

15. The method of claim 1, further comprising removing the first structure after forming the first source / drain region and the second source / drain region.

16. A method for manufacturing a semiconductor device, the method comprising: Forming the first semiconductor structure; A second semiconductor structure including peripheral circuitry is formed; as well as A bonded semiconductor structure is formed by bonding the first semiconductor structure to the second semiconductor structure. The formation of the first semiconductor structure further includes: A first semiconductor pattern is formed, comprising a first impurity implantation region and a first semiconductor region located on the first impurity implantation region; A first gate structure is formed facing the side surface of the first semiconductor pattern; A first source / drain region and a second source / drain region spaced apart from each other in a first direction are formed in the first semiconductor pattern; Forming a data storage structure connected to the second source / drain region; and A bit line is formed connecting to the first source / drain region. The formation of the first source / drain region further includes performing source / drain annealing for diffusing and activating the first impurity in the first impurity implantation region of the first semiconductor pattern. The first impurity implantation region is formed into the first source / drain region through the source / drain annealing, and The second source / drain region is located in the region of the first semiconductor region.

17. The method according to claim 16, wherein, The first thickness of the first source / drain region in the first direction is greater than the second thickness of the second source / drain region in the first direction.

18. The method according to claim 16, wherein, The impurity in the first source / drain region is arsenic, and the impurity in the second source / drain region is phosphorus.

19. A method for manufacturing a semiconductor device, the method comprising: A semiconductor substrate is formed, the semiconductor substrate including a first portion and a second portion located on the first portion, the first portion including a first impurity implantation region doped with a first impurity and a second impurity implantation region doped with a second impurity different from the first impurity, and the second portion including a first semiconductor region located on the first impurity implantation region and a second semiconductor region located on the second impurity implantation region; Multiple semiconductor patterns are formed by patterning the semiconductor substrate. The multiple semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern includes a first impurity implantation region and a first semiconductor region. The second semiconductor pattern includes a second semiconductor region located on the second impurity implantation region. A plurality of gate structures are formed, the plurality of gate structures including a first gate structure facing the surface of the first semiconductor pattern and a second gate structure facing the surface of the second semiconductor pattern; as well as Multiple source / drain regions are formed; The plurality of source / drain regions include: A first source / drain region and a second source / drain region are located in the first semiconductor pattern, the first source / drain region and the second source / drain region being spaced apart from each other in a first direction; and The third source / drain region and the fourth source / drain region are located in the second semiconductor pattern, and the third source / drain region and the fourth source / drain region are spaced apart from each other in the first direction. The formation of the first source / drain region and the third source / drain region includes performing source / drain annealing for diffusing and activating the first impurity in the first impurity implantation region of the first semiconductor pattern and simultaneously diffusing and activating the second impurity in the second impurity implantation region of the second semiconductor pattern. The first impurity implantation region is formed into the first source / drain region through the source / drain annealing, and The second impurity implantation region is formed into the third source / drain region by the source / drain annealing.

20. The method according to claim 19, wherein, Forming the first source / drain region and the second source / drain region includes: A first polysilicon layer is formed on the first semiconductor region of the first semiconductor pattern, and the first polysilicon layer is doped with a third impurity. A second polysilicon layer is formed on the second semiconductor region of the second semiconductor pattern, the second polysilicon layer being doped with a fourth impurity; and By performing the source / drain annealing, the first impurity in the first impurity implantation region is diffused and activated, and the second impurity in the second impurity implantation region is diffused and activated. Simultaneously, the third impurity in the first polysilicon layer diffuses into the first semiconductor region of the first semiconductor pattern and activates the third impurity. Furthermore, the fourth impurity in the second polysilicon layer diffuses into the second semiconductor region and activates the fourth impurity. As the third impurity in the first polysilicon layer diffuses into the first semiconductor region of the first semiconductor pattern through the source / drain annealing and is activated in the first semiconductor region of the first semiconductor pattern, a second source / drain region is formed in the first semiconductor pattern, and Wherein, as the fourth impurity in the second polysilicon layer diffuses into the second semiconductor region of the second semiconductor pattern through the source / drain annealing and is activated in the second semiconductor region of the second semiconductor pattern, the fourth source / drain region is formed in the second semiconductor pattern.

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