Semiconductor device including word lines and back gate lines

Abstract

A semiconductor device including a word line and a back gate line includes: a first channel pattern extending in a first direction; a second channel pattern adjacent to the first channel pattern and extending in the first direction; a bit line connected to a first end of the first channel pattern and a first end of the second channel pattern and extending in a second direction orthogonal to the first direction; an information storage element connected to a second end of the second channel pattern opposite the first end of the second channel pattern in the first direction; a word line disposed between the first channel pattern and the second channel pattern and adjacent to the information storage element in the first direction; and a back gate line adjacent to at least one of the first channel pattern and the second channel pattern.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2025-0056747, filed with the Korean Intellectual Property Office on April 29, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including word lines and back gate lines. Background Technology

[0004] With the increasing demand for compact, multifunctional, and high-performance electronic products, the integration density of semiconductor devices is also constantly increasing. This necessitates semiconductor devices with improved integration density. Specifically, the trend towards higher integration density in semiconductor devices necessitates higher operational reliability. Summary of the Invention

[0005] One or more exemplary embodiments of this disclosure provide a semiconductor device that includes multiple memory cells and may have increased integration density and improved operational reliability.

[0006] According to one aspect of this disclosure, a semiconductor device includes: a first channel pattern extending in a first direction; a second channel pattern adjacent to the first channel pattern and extending in the first direction; a bit line connected to a first end of the first channel pattern and a first end of the second channel pattern and extending in a second direction orthogonal to the first direction; an information storage element connected to a second end of the second channel pattern, the second end of the second channel pattern being opposite to the first end of the second channel pattern in the first direction; a word line between the first channel pattern and the second channel pattern and adjacent to the information storage element in the first direction; and a back gate line adjacent to at least one of the first channel pattern and the second channel pattern.

[0007] According to one aspect of this disclosure, a semiconductor device includes: a substrate; a first channel pattern extending on the substrate along a first direction; a second channel pattern extending on the substrate along the first direction and spaced apart from the first channel pattern in a second direction orthogonal to the first direction; bit lines connected to a first end of the first channel pattern and a first end of the second channel pattern, and extending in the second direction; an information storage element connected to a second end of the second channel pattern, the second end of the second channel pattern being opposite to the first end of the second channel pattern in the first direction; word lines, each of which is adjacent to one of the first channel patterns and the second channel pattern in the second direction, each of which is adjacent to one of the information storage elements in the first direction, and each of which extends upward in a third direction orthogonal to the first and second directions; and a back gate line adjacent to the information storage element and extending upward in a third direction.

[0008] According to one aspect of this disclosure, a semiconductor device includes: a substrate; a first channel pattern extending on the substrate along a first horizontal direction; a second channel pattern extending on the substrate along the first horizontal direction and spaced apart from the first channel pattern in a vertical direction; bit lines connected to a first end of the first channel pattern and a first end of the second channel pattern, and extending in a vertical direction; information storage elements connected to a second end of the second channel pattern, the second end of the second channel pattern being opposite to the first end of the second channel pattern in the first horizontal direction; word lines, each of which is vertically adjacent to one of the first channel pattern and one of the second channel patterns, each word line being adjacent to one of the information storage elements in the first horizontal direction, and... Each word line extends in a second horizontal direction orthogonal to the first horizontal direction; a back gate line is adjacent to the second channel pattern and the information storage element and extends in the second horizontal direction; a first gate dielectric layer is between the first channel pattern and the information storage element; a second gate dielectric layer is between the second channel pattern and the back gate line; and a third gate dielectric layer is between the first channel pattern and the word line and between the second channel pattern and the word line, wherein each word line is spaced apart from an adjacent information storage element by a first separation distance in the first horizontal direction, and wherein each back gate line is spaced apart from an adjacent information storage element by a second separation distance in the vertical direction, and the second separation distance is less than the first separation distance.

[0009] According to one aspect of this disclosure, a method of manufacturing a semiconductor device includes: forming a stacked structure on a substrate, the stacked structure including a plurality of first channel layers, a plurality of first sacrificial layers, a plurality of second sacrificial layers, and a plurality of third sacrificial layers; forming a deep trench via through the stacked structure; forming a first isolation trench and a second isolation trench through the stacked structure, the first isolation trench and the second isolation trench dividing the plurality of first channel layers into a plurality of first channel patterns and communicating with the deep trench via; removing the plurality of first sacrificial layers and the plurality of second sacrificial layers through the second isolation trench to form a plurality of first removal spaces and a plurality of second removal spaces; forming a plurality of information storage elements; filling a plurality of third removal spaces corresponding to portions of the plurality of second sacrificial layers; removing the plurality of third sacrificial layers through the second isolation trench to form a plurality of fourth removal spaces; forming a plurality of second channel layers covering the inner surfaces of the plurality of fourth removal spaces; forming a plurality of back gate lines filling portions of the plurality of fourth removal spaces; and forming a plurality of gate lines filling portions of the plurality of second removal spaces.

[0010] The method may further include forming at least one plate electrode in the second isolation trench and forming multiple bit lines in the first isolation trench.

[0011] The method may also include removing portions of a plurality of second channel layers through a first isolation trench, thereby forming a plurality of second channel patterns.

[0012] Multiple first channel patterns may extend on the substrate along a first horizontal direction; multiple second channel patterns may be spaced apart from the multiple first channel patterns in a vertical direction and extend on the substrate along the first horizontal direction; multiple bit lines may be connected to the ends of the multiple first channel patterns and the ends of the multiple second channel patterns in the first horizontal direction and may extend in the vertical direction; and multiple information storage elements may be connected to the opposite ends of the multiple second channel patterns in the first horizontal direction.

[0013] At least one plate electrode may be spaced apart from multiple bit lines, multiple second channel patterns and multiple information storage elements, and may be connected to opposite ends of multiple first channel patterns in a first horizontal direction.

[0014] A stacked structure can be formed such that: multiple first channel patterns are spaced apart from each other in the vertical direction, multiple first sacrificial layers are spaced apart from each other in the vertical direction, multiple second sacrificial layers are spaced apart from each other in the vertical direction, and multiple third sacrificial layers are spaced apart from each other in the vertical direction.

[0015] A stacked structure can be formed such that: each of the plurality of first channel layers is located between the first and second sacrificial layers that are vertically adjacent to each other in the plurality of first sacrificial layers and the plurality of second sacrificial layers; each of the plurality of first sacrificial layers is located between the first channel layers that are vertically adjacent to each other in the plurality of first channel layers; each of the plurality of second sacrificial layers is located between the first and third sacrificial layers that are vertically adjacent to each other in the plurality of first channel layers and the plurality of third sacrificial layers; and each of the plurality of third sacrificial layers is located between the second sacrificial layers that are vertically adjacent to each other in the plurality of second sacrificial layers.

[0016] Each of the multiple word lines can be separated from an adjacent information storage element by a first separation distance, and each of the multiple back gate lines can be separated from an adjacent information storage element by a second separation distance, the second separation distance being less than the first separation distance.

[0017] Each of the multiple word lines can be separated from its adjacent bit line by a third separation distance, and each of the multiple back gate lines can be separated from its adjacent bit line by a fourth separation distance, the fourth separation distance being greater than the third separation distance.

[0018] Each of the multiple back grid lines overlaps at least partially in the vertical direction with one of the adjacent information storage elements. Attached Figure Description

[0019] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 It is a conceptual perspective view of a semiconductor device according to one or more example embodiments;

[0021] Figure 2 It is an equivalent circuit diagram of a memory cell of a semiconductor device according to one or more example embodiments;

[0022] Figure 3 A memory cell of a semiconductor device according to one or more example embodiments is shown;

[0023] Figure 4 A semiconductor device comprising a plurality of memory cells is illustrated according to one or more example embodiments;

[0024] Figure 5 This is a conceptual perspective view of a semiconductor device including multiple memory cells according to one or more example embodiments;

[0025] Figure 6A , Figure 6B、 Figure 6C 、 Figure 6D 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 17D 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 19D 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B , Figure 24C , Figure 24D , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 26A , Figure 26B , Figure 26C , Figure 26D , Figure 27A , Figure 27B , Figure 27C , Figure 27D , Figure 28A , Figure 28B , Figure 28C , Figure 28D , Figure 29A , Figure 29B , Figure 29C , Figure 29D , Figure 30A , Figure 30B , Figure 30C , Figure 30D , Figure 31A , Figure 31B , Figure 31C , Figure 31D , Figure 32A , Figure 32B , Figure 32C , Figure 32D , Figure 33A , Figure 33B , Figure 33C and Figure 33D This is a diagram illustrating a method of manufacturing a semiconductor device according to one or more example embodiments;

[0026] Figure 34A , Figure 34B , Figure 34C and Figure 34D This is a diagram illustrating a semiconductor device according to one or more example embodiments;

[0027] Figure 35 A memory cell of a semiconductor device according to one or more example embodiments is shown;

[0028] Figure 36A , Figure 36B and Figure 36C The memory cells of a semiconductor device according to one or more example embodiments are shown respectively;

[0029] Figure 37 A memory cell of a semiconductor device according to one or more example embodiments is shown;

[0030] Figure 38A , Figure 38B , Figure 38C and Figure 38DThis is a diagram illustrating a semiconductor device according to one or more example embodiments;

[0031] Figure 39 This is a diagram illustrating a semiconductor device according to one or more example embodiments;

[0032] Figure 40 This is a diagram illustrating a semiconductor device according to one or more example embodiments;

[0033] Figure 41A , Figure 41B and Figure 41C The memory cells of a semiconductor device according to one or more example embodiments are shown respectively;

[0034] Figure 42 This is a conceptual perspective view of a semiconductor device including multiple memory cells according to one or more example embodiments;

[0035] Figure 43A , Figure 43B , Figure 43C , Figure 43D and Figure 43E The memory cells of a semiconductor device according to one or more example embodiments are shown respectively;

[0036] Figure 44A and Figure 44B Word lines of semiconductor devices according to one or more example embodiments are shown respectively;

[0037] Figure 45A , Figure 45B and Figure 45C Information storage elements of semiconductor devices according to one or more example embodiments are shown respectively;

[0038] Figure 46 A semiconductor device comprising a plurality of memory cells is illustrated according to one or more example embodiments;

[0039] Figure 47 A semiconductor device comprising a plurality of memory cells is illustrated according to one or more example embodiments;

[0040] Figure 48 A memory cell of a semiconductor device according to one or more example embodiments is shown;

[0041] Figure 49A and Figure 49B These are conceptual perspective views of a semiconductor device including multiple memory cells according to one or more example embodiments; and

[0042] Figure 50A and Figure 50BSemiconductor devices comprising multiple memory cells according to one or more example embodiments are shown respectively. Detailed Implementation

[0043] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings. The same components in the drawings are denoted by the same reference numerals, and repeated descriptions thereof are omitted.

[0044] Figure 1 This is a conceptual perspective view of a semiconductor device according to one or more example embodiments.

[0045] refer to Figure 1 The semiconductor device 100 may include a first structure ST1 and a second structure ST2 stacked in a vertical direction. In one or more example embodiments, the second structure ST2 may be disposed below the first structure ST1, but one or more example embodiments are not limited thereto. For example, the second structure ST2 may be disposed above the first structure ST1. The first structure ST1 may include a memory cell array CA. The memory cell array CA may include, as referred to below... Figure 2 The described storage unit MC.

[0046] The second structure ST2 may include a Peripheral Circuit Region (PERI) on the peripheral substrate SUB. The PERI may include peripheral circuit elements, including peripheral transistors. For example, logic elements such as inverters, NAND gates, NOR gates, AND gates, OR gates, XOR gates, XNOR gates, NOT gates, and antifuse may be arranged in the PERI. The PERI may also include peripheral circuitry for the operation of the memory cell MC, such as sense amplifiers and sub-word line drivers; and peripheral circuitry for data or command input / output or power / ground input.

[0047] A first structure ST1 can be bonded to a second structure ST2. In one or more example embodiments, the first structure ST1 can be bonded to the second structure ST2 via a metal-oxide hybrid bonding process. For example, the first structure ST1 may include a first bonding pad on its bottom surface, and the second structure ST2 may include a second bonding pad on its top surface, the second bonding pad being bonded to the first bonding pad. When the first bonding pad and the second bonding pad are opposite each other, the first and second bonding pads can be expanded by heating to contact each other, thereby forming a diffusion bonding connection, and further forming a single body through the diffusion of the metal atoms included therein. The first and second bonding pads may each include a copper (Cu)-containing material. The first and second bonding pads can electrically connect the first structure ST1 to the second structure ST2. In one or more example embodiments, the first structure ST1 can be bonded to the second structure ST2 via a direct bonding process. For example, the semiconductor device 100 may include a connection via extending in a vertical direction (e.g., the Z direction) and passing through the bonding surface between the first structure ST1 and the second structure ST2. The connection via can electrically connect the first structure ST1 to the second structure ST2.

[0048] Figure 2 It is an equivalent circuit diagram of a memory cell of a semiconductor device according to one or more example embodiments.

[0049] refer to Figure 2 According to one or more example embodiments, the memory cell array CA may include a plurality of memory cells MC. The memory cells MC may be connected to the bit line BL and the word line WL. Each of the memory cells MC may include a write transistor Wtr, a read transistor Rtr, and a memory node SN. The memory node SN may be used as the gate (e.g., a floating gate) of the read transistor Rtr and may be electrically connected to the write transistor Wtr. For example, the memory node SN may be electrically connected to the channel of the write transistor Wtr.

[0050] Each of the memory cells MC can be selected by one bit line BL and one word line WL. Each of the memory cells MC can be used as dynamic random access memory (DRAM), to which write operations for storing information and read operations for reading information can be performed, and may not include capacitors. For example, each of the memory cells MC can store information in the memory node SN instead of in a capacitor, and may be called a two-transistor (2T) memory cell.

[0051] The write transistor Wtr stores charge in the memory node SN. The threshold voltage of the read transistor Rtr, whose gate is the memory node SN, can vary with the amount of charge stored in the memory node SN. Depending on the threshold voltage of the read transistor Rtr, the information stored in the memory cell MC can be read as "0" or "1".

[0052] One end of the channel of the write transistor Wtr can be connected to the bit line BL, and the other end of the channel of the write transistor Wtr can be connected to the memory node SN. The gate of the write transistor Wtr can be electrically connected to the word line WL.

[0053] One end of the channel of the read transistor Rtr can be connected to the bit line BL, and the other end of the channel of the read transistor Rtr can be grounded. The gate of the read transistor Rtr can be electrically connected to the word line WL. The word line WL can be used together with the memory node SN as the gate of the read transistor Rtr. For example, the memory node SN and the word line WL can be used to turn the read transistor Rtr on or off.

[0054] Bit line BL can be electrically connected to the memory cell MC. For example, bit line BL can be electrically connected to the channel of write transistor Wtr and the channel of read transistor Rtr.

[0055] The memory cell array CA may include back gate lines (BG). Each back gate line (BG) may be adjacent to, but spaced apart from, the memory node (SN) of the memory cell (MC). Each back gate line (BG) may increase the difference between the threshold voltage of the write transistor (Wtr) and the threshold voltage of the read transistor (Rtr).

[0056] Although Figure 2 The back gate lines (BGs) included in the memory cells MC shown are separated from each other, but one or more example embodiments are not limited thereto. Similar to word lines (WL), the back gate lines (BGs) can be formed to extend along adjacent memory cells MC.

[0057] In the memory cell array CA, the write transistor Wtr and read transistor Rtr of each memory cell MC can be connected to a word line WL, and due to the presence of the back gate line BG, the threshold voltage difference between the write transistor Wtr and the read transistor Rtr may increase. Accordingly, the integration density and operational reliability of the semiconductor device 100 including the memory cell array CA can be improved.

[0058] Figure 3 A memory cell MC of a semiconductor device 100 according to one or more example embodiments is shown.

[0059] refer to Figure 3The semiconductor device 100 may include a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180 disposed on a substrate 102. The first channel pattern 110, the second channel pattern 120, the information storage element 140, the word line 160, the back gate line 150, the bit line 170, and the plate electrode 180 may constitute a memory cell MC.

[0060] refer to Figure 2 The described read transistor Rtr may include a first channel pattern 110, and the write transistor Wtr may include a second channel pattern 120. The information storage element 140 may be electrically connected to the second channel pattern 120 and may include a reference. Figure 2 The storage node SN is described. Word line 160 can correspond to the reference. Figure 2 The described word line WL and back grid line 150 can correspond to the reference. Figure 2 The back gate line BG is described, and bit line 170 can correspond to the reference. Figure 2 The bit line BL is described.

[0061] For example, substrate 102 may include a semiconductor material, such as a group IV semiconductor material, a group III-V semiconductor material, a group II-VI semiconductor material, or a group II-VI oxide semiconductor material. For example, group IV semiconductor materials may include silicon (Si), germanium (Ge), or silicon-germanium (Si-Ge). For example, group III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide, or indium gallium arsenide (InGaAs). For example, group II-VI semiconductor materials may include zinc telluride (ZnTe) or cadmium sulfide (CdS). Substrate 102 may further include impurities. Substrate 102 may include a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer. Substrate 102 may correspond to... Figure 1 The substrate included in the first structure ST1, or the peripheral substrate SUB included in the second structure ST2.

[0062] The first channel pattern 110 may extend in a first horizontal direction (e.g., the X direction). The first channel pattern 110 may contact the bit line 170 and the plate electrode 180. In the first horizontal direction (X direction), one end of the first channel pattern 110 may contact and connect to the bit line 170, and the opposite end of the first channel pattern 110 may contact and connect to the plate electrode 180. The first channel pattern 110 may comprise a single-crystal semiconductor material, a polycrystalline semiconductor material, or an oxide semiconductor material. For example, the single-crystal semiconductor material may comprise a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. In one or more example embodiments, the first channel pattern 110 may comprise a single-crystal semiconductor material (e.g., silicon) or a polycrystalline semiconductor material (e.g., polycrystalline silicon).

[0063] In one or more example embodiments, the single-crystal or polycrystalline semiconductor material of the first channel pattern 110 may not be in contact with the bit line 170 or the plate electrode 180. For example, the first channel pattern 110 may include a first channel region 112, a first silicide layer 114, and a second silicide layer 116, wherein the first channel region 112 comprises a single-crystal or polycrystalline semiconductor material. The first channel region 112 may be disposed between the first silicide layer 114 and the second silicide layer 116. The first silicide layer 114 may be in contact with the bit line 170. The second silicide layer 116 may be spaced apart from the first silicide layer 114 in a first horizontal direction (X direction) and may be in contact with the plate electrode 180. The first channel region 112 may be spaced apart from the bit line 170, with the first silicide layer 114 between the first channel region 112 and the bit line 170; and may be spaced apart from the plate electrode 180, with the second silicide layer 116 between the first channel region 112 and the plate electrode 180.

[0064] The second channel pattern 120 may extend in the first horizontal direction (X direction). The second channel pattern 120 may be adjacent to and spaced apart from the first channel pattern 110 in the vertical direction (Z direction). The second channel pattern 120 may contact the bit line 170 and the information storage element 140. One end of the second channel pattern 120 in the first horizontal direction (X direction) may contact and be connected to the bit line 170. The opposite end of the second channel pattern 120 may contact and be connected to the information storage element 140.

[0065] The second channel pattern 120 may include a single-crystal semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor material, or a two-dimensional (2D) semiconductor material. For example, oxide semiconductor materials may include at least one selected from the group consisting of: indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO). The 2D semiconductor material may include at least one selected from the group consisting of: a transition metal dichalcogenide (TMD) material layer, a black phosphorus material layer, and a hexagonal boron nitride material layer that may have semiconductor properties. For example, the 2D semiconductor material may include at least one selected from the group consisting of: BiOSe, Cr1, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, black phosphorus, InSe, h-BN, GaSe, GaN, SrTiO, MXene, Janus 2D material, graphene, and carbon nanotubes. In one or more example embodiments, the second channel pattern 120 may include an oxide semiconductor material or a 2D semiconductor material. The oxide semiconductor material or 2D semiconductor material of the second channel pattern 120 may be in direct contact with the bit line 170. In one or more example embodiments, the second channel pattern 120 may include an oxide semiconductor material, such as IGZO.

[0066] In one or more example embodiments, the second channel pattern 120 may include channel contacts in its portion adjacent to bit line 170. The channel contacts may include doped polysilicon, metal, conductive metal nitride, metal-semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotubes, or combinations thereof. For example, the channel contacts may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes, or combinations thereof. The channel contacts may correspond to a portion of the second channel pattern 120 implanted with impurities (e.g., H or O).

[0067] Information storage element 140 may contact and be electrically connected to the second channel pattern 120. For example, at least a portion of information storage element 140 may overlap with the second channel pattern 120 in the vertical direction (Z direction) and may be spaced apart from the first channel pattern 110 in the vertical direction (Z direction). Information storage element 140 may be adjacent to the first channel pattern 110. For example, at least a portion of information storage element 140 may be adjacent to and overlap with the first channel pattern 110 in the vertical direction (Z direction). The thickness of information storage element 140 in the vertical direction (Z direction) may be equal to or greater than the thickness of the second channel pattern 120 in the vertical direction (Z direction). Information storage element 140 may be spaced apart from the substrate 102 in the vertical direction (Z direction) and spaced apart from the plate electrode 180 in the first horizontal direction (X direction).

[0068] Here, the vertical direction (Z direction) can be perpendicular to the top surface of the substrate 102, and the first horizontal direction (X direction) and the second horizontal direction (e.g., Y direction) can be parallel to the top surface of the substrate 102 and orthogonal to each other. The first horizontal direction (X direction), the vertical direction (Z direction), and the second horizontal direction (Y direction) can be referred to as the first direction, the second direction, and the third direction, respectively, and they are orthogonal to each other.

[0069] Information storage element 140 may include oxide semiconductor materials, 2D semiconductor materials, conductive materials, or combinations thereof. Conductive materials may include doped single-crystal silicon, doped polycrystalline silicon, metals, conductive metal nitrides, metal-semiconductor compounds, conductive metal oxides, conductive graphene, carbon nanotubes, or combinations thereof. For example, information storage element 140 may include oxide semiconductor materials. In one or more example embodiments, the second channel pattern 120 and information storage element 140 may include the same material. For example, the second channel pattern 120 and information storage element 140 may form a single body. In one or more example embodiments, the second channel pattern 120 and information storage element 140 may be formed into a single body using the same material, thereby avoiding the formation of an interface defining the boundary between the second channel pattern 120 and information storage element 140.

[0070] Word line 160 may be adjacent to both the first channel pattern 110 and the second channel pattern 120. Word line 160 may be arranged vertically (Z-direction) between the first channel pattern 110 and the second channel pattern 120 to be spaced apart from each of the first channel pattern 110 and the second channel pattern 120 included in the memory cell MC. For example, at least a portion of word line 160 may extend in a second horizontal direction (Y-direction) between the first channel pattern 110 and the second channel pattern 120. At least a portion of word line 160 may overlap with the first channel pattern 110 in the vertical direction (Z-direction), and at least a portion of word line 160 may overlap with the second channel pattern 120 in the vertical direction (Z-direction). Word line 160 can be used as... Figure 2 Write the gate of transistor Wtr into it, and it can be used as Figure 2 The word line 160 can be used as the gate of the read transistor Rtr. For example, at least a portion of the information storage element 140 and at least a portion of the word line 160 may be adjacent to the first channel pattern 110, such that the word line 160 can be used together with the information storage element 140 as the gate of the read transistor Rtr. For example, the word line 160 can serve as the gate of the read transistor Rtr when charge is stored in the information storage element 140. The word line 160 may be adjacent to both the first channel pattern 110 and the second channel pattern 120, and can be used as the gate of each of the write transistor Wtr and the read transistor Rtr, thereby increasing the integration density of the semiconductor device 100.

[0071] Word line 160 may include metals, conductive metal nitrides, metal compounds, conductive metal oxides, graphene, carbon nanotubes, or combinations thereof. For example, word line 160 may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes, or combinations thereof.

[0072] Back gate line 150 may be adjacent to information storage element 140. For example, back gate line 150 may be adjacent to and spaced apart from information storage element 140. Back gate line 150 may be adjacent to first channel pattern 110 and / or second channel pattern 120. For example, back gate line 150 may be adjacent to first channel pattern 110 and / or second channel pattern 120 and spaced apart from each of the first channel pattern 110 and second channel pattern 120. In one or more example embodiments, back gate line 150 may be closer to second channel pattern 120 than to first channel pattern 110. For example, back gate line 150 may be adjacent to second channel pattern 120 and spaced apart from second channel pattern 120 in the vertical direction (Z direction). For example, at least a portion of back gate line 150 may be adjacent to second channel pattern 120 and may extend in a second horizontal direction (Y direction). At least a portion of the back gate line 150 may overlap with the second channel pattern 120 in the vertical direction (Z direction). In one or more example embodiments, at least a portion of the back gate line 150 may overlap with the information storage element 140 in the vertical direction (Z direction), but one or more example embodiments are not limited thereto. For example, the back gate line 150 may be adjacent to the information storage element 140, but may not overlap with the information storage element 140 in the vertical direction (Z direction).

[0073] The back gate line 150 may include metals, conductive metal nitrides, metal compounds, conductive metal oxides, graphene, carbon nanotubes, or combinations thereof. For example, the back gate line 150 may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes, or combinations thereof.

[0074] Information storage element 140 may be spaced apart from word line 160 by a first separation distance D1 and from back gate line 150 by a second separation distance D2. The second separation distance D2 may be less than the first separation distance D1. In a first horizontal direction (X direction), word line 160 may have a first horizontal width W1, and back gate line 150 may have a second horizontal width W2. In one or more example embodiments, the second horizontal width W2 may be greater than the first horizontal width W1. The separation distance between information storage element 140 and back gate line 150, and the horizontal width of back gate line 150, may be determined by the horizontal width of each of the first separation insulating layer 152 and the second separation insulating layer 154 in the first horizontal direction (X direction), as will be referred to below. Figure 23A , Figure 23B , Figure 23C and Figure 23DThe separation distance between the information storage element 140 and the plate electrode 180 can be determined by the horizontal width of the third separation insulating layer 145 in the first horizontal direction (X direction), as described below. Figure 24A , Figure 24B , Figure 24C and Figure 24D It is described herein. The separation distance between the information storage element 140 and the word line 160, and the horizontal width of the word line 160, can be determined by the horizontal width of each of the fourth separation insulating layer 162 and the fifth separation insulating layer 164 in the first horizontal direction (X direction), as described below. Figure 32A , Figure 32B , Figure 32C and Figure 32D Describe it.

[0075] Bit line 170 may extend in the vertical direction (Z direction). Bit line 170 may contact and be electrically connected to the first channel pattern 110 and the second channel pattern 120. For example, bit line 170 may contact one end of the first channel pattern 110 and one end of the second channel pattern 120 in the first horizontal direction (X direction).

[0076] Bit line 170 may include doped polycrystalline silicon, metal, conductive metal nitride, metal-semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof. For example, bit line 170 may include doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotube, or a combination thereof.

[0077] In one or more example embodiments, bit line 170 may include a plurality of conductive layers stacked sequentially. For example, the conductive layers may include at least one selected from the group consisting of doped polysilicon, silicide materials, and metals. However, the number of layers and the type of material of bit line 170 may vary depending on one or more example embodiments.

[0078] Bit line 170 may be spaced apart from word line 160 by a third separation distance D3 and from back gate line 150 by a fourth separation distance D4. In one or more example embodiments, the fourth separation distance D4 may be greater than the third separation distance D3.

[0079] The plate electrode 180 may contact the first channel pattern 110. The plate electrode 180 may contact the opposite end of the first channel pattern 110 in a first horizontal direction (X direction). The plate electrode 180 may be spaced apart from the second channel pattern 120. For example, in one or more example embodiments, the plate electrode 180 may be electrically grounded.

[0080] The plate electrode 180 may include metals, conductive metal nitrides, metal compounds, conductive metal oxides, graphene, carbon nanotubes, or combinations thereof. For example, the plate electrode 180 may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes, or combinations thereof.

[0081] Figure 4 A semiconductor device comprising a plurality of memory cells is shown according to one or more example embodiments. Figure 5 This is a conceptual perspective view of a semiconductor device including multiple memory cells according to one or more example embodiments.

[0082] refer to Figure 4 and Figure 5 The semiconductor device 1000 may include a plurality of memory cells MC, each memory cell including a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170 and a plate electrode 180.

[0083] The first channel pattern 110 may extend in a first horizontal direction (X direction) and may be arranged in rows spaced apart from each other in a second horizontal direction (Y direction) and a vertical direction (Z direction). The second channel pattern 120 may extend in the first horizontal direction (X direction) and may be arranged in rows spaced apart from each other in the second horizontal direction (Y direction) and a vertical direction (Z direction). The second channel pattern 120 may be spaced apart from the first channel pattern 110 in the vertical direction (Z direction). The second channel pattern 120 may contact the bit line 170 and the information storage element 140. The information storage element 140 may contact and be electrically connected to the second channel pattern 120. The information storage element 140 may be adjacent to and spaced apart from the first channel pattern 110.

[0084] The word line 160 may be adjacent to both the first channel pattern 110 and the second channel pattern 120. The word line 160 may be arranged in the vertical direction (Z direction) between the first channel pattern 110 and the second channel pattern 120 of a memory cell MC, so as to be spaced apart from the first channel pattern 110 and the second channel pattern 120 of the memory cell MC.

[0085] The back gate line 150 may be adjacent to the information storage element 140. In one or more example embodiments, the back gate line 150 may be closer to the second channel pattern 120 than to the first channel pattern 110. For example, the back gate line 150 may be arranged to be adjacent to and spaced apart from the second channel pattern 120 in the vertical direction (Z direction). For example, at least a portion of the back gate line 150 may be adjacent to the second channel pattern 120 and may extend in the second horizontal direction (Y direction).

[0086] Bit lines 170 may extend in a vertical direction (Z direction) and may be arranged in rows spaced apart from each other in a second horizontal direction (Y direction). Bit lines 170 may contact and be electrically connected to the first channel pattern 110 and the second channel pattern 120. For example, bit lines 170 may contact the ends of the first channel pattern 110 and the ends of the second channel pattern 120 in the first horizontal direction (X direction).

[0087] The plate electrode 180 can contact the first channel pattern 110. For example, the plate electrode 180 can contact the opposite end of the first channel pattern 110 in a first horizontal direction (X direction). Although Figure 4 and Figure 5 The illustration shows a plate electrode 180 having a plate shape extending in a first horizontal direction (X direction) and a second horizontal direction (Y direction), and contacting a plurality of second channel patterns 120 arranged in rows in the first horizontal direction (X direction) and the second horizontal direction (Y direction), but one or more example embodiments are not limited thereto. According to one or more example embodiments, a plurality of plate electrodes 180 may be arranged, and each of the plurality of plate electrodes 180 may contact a plurality of first channel patterns 110. In one or more example embodiments, the plate electrodes 180 may be electrically grounded.

[0088] Multiple memory cells MC can be arranged in rows in a first horizontal direction (X direction), a second horizontal direction (Y direction), and a vertical direction (Z direction). In one or more example embodiments, two memory cells MC that are adjacent to each other in the first horizontal direction (X direction) can be mirror-symmetrical to each other in the first horizontal direction (X direction). In one or more example embodiments, two memory cells MC that are adjacent to each other in the vertical direction (Z direction) can be mirror-symmetrical to each other in the vertical direction (Z direction). Two second channel patterns 120 that are adjacent to each other in the vertical direction (Z direction) can be arranged between two first channel patterns 110 that are spaced apart in the vertical direction (Z direction), and two first channel patterns 110 that are adjacent to each other in the vertical direction (Z direction) can be arranged between two second channel patterns 120 that are spaced apart in the vertical direction (Z direction).

[0089] Each of the multiple word lines 160 can be arranged vertically (Z-direction) between the first channel pattern 110 and the second channel pattern 120 of a memory cell MC, spaced apart from the first channel pattern 110 and the second channel pattern 120 of the memory cell MC. Each of the multiple back gate lines 150 can be arranged vertically (Z-direction) between the two second channel patterns 120 respectively included in two memory cells MC, spaced apart from the two second channel patterns 120 of the two memory cells MC in the vertical direction (Z-direction). For example, two word lines 160 can be arranged vertically (Z-direction) on opposite sides of a back gate line 150, and in the vertical direction (Z-direction), a back gate line 150 can be provided on one side of a word line 160, while another word line 160 can be provided on the opposite side.

[0090] Multiple bit lines 170 and multiple plate electrodes 180 can be arranged alternately in the first horizontal direction (X direction). Although as Figure 4 and Figure 5 As shown, a plate electrode 180 extending in the second horizontal direction (Y direction) and vertical direction (Z direction) contacts a plurality of first channel patterns 110 arranged in rows in the second horizontal direction (Y direction) and vertical direction (Z direction), but one or more example embodiments are not limited thereto. According to one or more example embodiments, the plurality of plate electrodes 180 may be arranged in the second horizontal direction (Y direction), and each of the plate electrodes 180 may contact the plurality of first channel patterns 110 arranged in the vertical direction (Z direction).

[0091] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 17D 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 19D 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25A 、 Figure 25B 、 Figure 25C , Figure 25D , Figure 26A , Figure 26B , Figure 26C , Figure 26D , Figure 27A , Figure 27B , Figure 27C , Figure 27D , Figure 28A , Figure 28B , Figure 28C , Figure 28D , Figure 29A , Figure 29B , Figure 29C , Figure 29D , Figure 30A , Figure 30B , Figure 30C , Figure 30D , Figure 31A , Figure 31B , Figure 31C , Figure 31D , Figure 32A , Figure 32B , Figure 32C , Figure 32D , Figure 33A , Figure 33B , Figure 33C and Figure 33D This is a diagram illustrating a method of manufacturing a semiconductor device according to one or more example embodiments. Figure 34A , Figure 34B , Figure 34C and Figure 34D This is a diagram illustrating a semiconductor device according to one or more example embodiments. Specifically, Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B , Figure 32B , Figure 33B and Figure 34B They are along Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A , Figure 32A , Figure 33A and Figure 34A A cross-sectional view taken along the centerline B-B'. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 22C , Figure 23C , Figure 24C , Figure 25C , Figure 26C , Figure 27C , Figure 28C , Figure 29C , Figure 30C , Figure 31C , Figure 32C , Figure 33C and Figure 34C They are along Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A , Figure 32A , Figure 33A and Figure 34A A cross-sectional view taken along the centerline C-C'. Figure 6D , Figure 7D , Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D , Figure 16D , Figure 17D , Figure 18D , Figure 19D , Figure 20D , Figure 21D , Figure 22D , Figure 23D , Figure 24D , Figure 25D , Figure 26D , Figure 27D , Figure 28D , Figure 29D , Figure 30D , Figure 31D , Figure 32D , Figure 33D and Figure 34D They are along Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A , Figure 32A , Figure 33A and Figure 34A A cross-sectional view taken along the centerline D-D'.

[0092] refer to Figure 6A , Figure 6B , Figure 6C and Figure 6D Multiple first channel layers 110P, multiple first sacrificial layers SAC1, multiple second sacrificial layers SAC2, and multiple third sacrificial layers SAC3 can be formed on the substrate 102. The first channel layers 110P can be spaced apart from each other in the vertical direction (Z direction), the first sacrificial layers SAC1 can be spaced apart from each other in the vertical direction (Z direction), the second sacrificial layers SAC2 can be spaced apart from each other in the vertical direction (Z direction), and the third sacrificial layers SAC3 can be spaced apart from each other in the vertical direction (Z direction).

[0093] The first channel layer 110P can be located between adjacent first sacrificial layers SAC1 and SAC2 along the vertical direction (Z direction). The first sacrificial layer SAC1 can be located between adjacent first channel layers 110P along the vertical direction (Z direction). The second sacrificial layer SAC2 can be located between adjacent first channel layers 110P and a third sacrificial layer SAC3 along the vertical direction (Z direction). The third sacrificial layer SAC3 can be located between adjacent second sacrificial layers SAC2 along the vertical direction (Z direction). For example, Figure 4 and Figure 5 The first channel pattern 110 can be formed by the first channel layer 110P, the second channel pattern 120 can be formed in a portion of the second sacrificial layer SAC2 adjacent to the third sacrificial layer SAC3, the back gate line 150 can be formed in a portion of the third sacrificial layer SAC3, and the word line 160 can be formed in a portion of the second sacrificial layer SAC2.

[0094] Although Figure 6B , Figure 6C and Figure 6D The illustration shows a first sacrificial layer SAC1, a first channel layer 110P, a second sacrificial layer SAC2, a third sacrificial layer SAC3, and a first channel layer 110P arranged repeatedly in the vertical direction (Z direction), but one or more example embodiments are not limited thereto. For example, the arrangement of multiple first channel layers 110P, multiple first sacrificial layers SAC1, multiple second sacrificial layers SAC2, and multiple third sacrificial layers SAC3 on substrate 102 in the vertical direction (Z direction) can be varied depending on the arrangement of the first channel pattern 110, the second channel pattern 120, the back gate line 150, and the word line 160 on substrate 102 in the vertical direction (Z direction).

[0095] The first channel layer 110P may include a single-crystal semiconductor material, a polycrystalline semiconductor material, or an oxide semiconductor material. The first sacrificial layer SAC1 may include a material with etch selectivity relative to the first channel layer 110P and the third sacrificial layer SAC3. The second sacrificial layer SAC2 may include a material with etch selectivity relative to the first channel layer 110P and the third sacrificial layer SAC3. In one or more example embodiments, the first sacrificial layer SAC1 may include a material with the same or similar etch characteristics as the material of the second sacrificial layer SAC2. For example, the first sacrificial layer SAC1 and the second sacrificial layer SAC2 may each include SiGe. The third sacrificial layer SAC3 may include a material with etch selectivity relative to the first channel layer 110P, the first sacrificial layer SAC1, and the second sacrificial layer SAC2. For example, the third sacrificial layer SAC3 may include SiC. The first sacrificial layer SAC1 may be thicker than the first channel layer 110P. The second sacrificial layer SAC2 may be thicker than the first sacrificial layer SAC1. The third sacrificial layer SAC3 may be thicker than the first sacrificial layer SAC1. The thickness of the third sacrificial layer SAC3 can be less than or similar to the thickness of the second sacrificial layer SAC2.

[0096] refer to Figure 7A , Figure 7B , Figure 7C and Figure 7D Multiple deep trench vias (DTRHs) can be formed by a stacked structure comprising multiple first channel layers 110P, multiple first sacrificial layers SAC1, multiple second sacrificial layers SAC2, and multiple third sacrificial layers SAC3. A portion of the substrate 102 may expose the bottom of each DTRH. In one or more example embodiments, the DTRHs can extend into the substrate 102 by a stacked structure comprising first channel layers 110P, first sacrificial layers SAC1, second sacrificial layers SAC2, and third sacrificial layers SAC3. The DTRHs may be spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction). In one or more example embodiments, in a plan view, each DTRH may have a rectangular shape, longer in the first horizontal direction (X direction) and shorter in the second horizontal direction (Y direction).

[0097] The first pad insulating layer LDI1 can be formed to cover the inner sidewalls and bottom surface of each deep trench hole DTRH, and the first fill insulating layer FDI1 can be formed to cover the first pad insulating layer LDI1 and fill each deep trench hole DTRH. The first pad insulating layer LDI1 can be formed to conformally cover the inner sidewalls and bottom surface of each deep trench hole DTRH. For example, the first pad insulating layer LDI1 may include SiO2 or SiOC, and the first fill insulating layer FDI1 may include Si3N4 and SiOCN.

[0098] refer to Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C and Figure 8D The first isolation trench STR1 and the second isolation trench STR2 can be formed by a stacked structure including a first channel layer 110P, a first sacrificial layer SAC1, a second sacrificial layer SAC2, and a third sacrificial layer SAC3. A portion of the substrate 102 can be exposed at the bottom of each of the first isolation trench STR1 and the second isolation trench STR2. In one or more example embodiments, the first isolation trench STR1 and the second isolation trench STR2 can extend into the substrate 102 by a stacked structure including a first channel layer 110P, a first sacrificial layer SAC1, a second sacrificial layer SAC2, and a third sacrificial layer SAC3. The first isolation trench STR1 and the second isolation trench STR2 can be spaced apart from each other in a first horizontal direction (X direction). For example, the first isolation trench STR1 can be disposed between two second isolation trenches STR2 that are adjacent to each other in the first horizontal direction (X direction). Although Figure 8A and Figure 8B The illustration shows a first isolation trench STR1 and two second isolation trenches STR2, but one or more example embodiments are not limited thereto. For example, a plurality of first isolation trenches STR1 and a plurality of second isolation trenches STR2 may be arranged alternately in a first horizontal direction (X direction). The first channel layer 110P may be divided into a plurality of first channel patterns 110 by the first isolation trenches STR1 and the second isolation trenches STR2.

[0099] The first isolation trench STR1 and the second isolation trench STR2 can be formed to extend in a second horizontal direction (Y direction). The first liner insulating layer LDI1 filling each deep trench hole DTRH can be exposed in the first horizontal direction (X direction) at the inner sidewall of each of the first isolation trench STR1 and the second isolation trench STR2. For example, each of the first isolation trench STR1 and the second isolation trench STR2 can be formed to communicate with the deep trench holes DTRH arranged in a row in the second horizontal direction (Y direction).

[0100] refer to Figure 9A , Figure 9B , Figure 9C and Figure 9D A second padding insulating layer LDI2 can be formed to cover the inner sidewalls and bottom surface of the first isolation trench STR1, and a second filling insulating layer FDI2 can be formed to cover the second padding insulating layer LDI2 and fill the first isolation trench STR1. The second padding insulating layer LDI2 can be formed to conformally cover the inner sidewalls and bottom surface of the first isolation trench STR1. For example, the second padding insulating layer LDI2 may include SiO2 or SiOC, and the second filling insulating layer FDI2 may include Si3N4 and SiOCN.

[0101] A first cover mask layer CMK1 can be formed to cover a second pad insulating layer LDI2, a second fill insulating layer FDI2, and a stacked structure including a first channel layer 110P, a first sacrificial layer SAC1, a second sacrificial layer SAC2, and a third sacrificial layer SAC3. The first cover mask layer CMK1 can be formed so that it does not overlap with the second isolation trench STR2 in the vertical direction (Z direction).

[0102] refer to Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C and Figure 10D The first sacrificial layer SAC1 and the second sacrificial layer SAC2 can be removed through the second isolation trench STR2, thereby forming multiple first removal spaces RS1 and multiple second removal spaces RS2. The second isolation trench STR2 is exposed and not covered by the first cover mask layer CMK1. The first removal spaces RS1 can be formed by removing the first sacrificial layer SAC1, and the second removal spaces RS2 can be formed by removing the second sacrificial layer SAC2. The first channel pattern 110, the third sacrificial layer SAC3, the first pad insulation layer LDI1, and the second pad insulation layer LDI2 can be exposed through the first removal spaces RS1 and the second removal spaces RS2. The first removal spaces RS1 and the second removal spaces RS2 can be formed to communicate with the deep trench hole DTRH and the first isolation trench STR1.

[0103] refer to Figure 11A , Figure 11B , Figure 11C and Figure 11DA third pad insulating layer LDI3 can be formed to cover the exposed surfaces of the resulting structure having a first removal space RS1 and a second removal space RS2, and a third fill insulating layer FDI3 can be formed to cover the third pad insulating layer LDI3 and fill the space defined by the third pad insulating layer LDI3. For example, the third pad insulating layer LDI3 can be formed to conformally cover the inner surface of each of the first removal spaces RS1 and the second removal spaces RS2, the side surface of each of the first channel pattern 110, the side surface of each of the third sacrificial layers SAC3, and the surface of the substrate 102, which surfaces are exposed by the second isolation trench STR2. The third fill insulating layer FDI3 can fill the space defined by the third pad insulating layer LDI3. For example, the first removal space RS1 can be completely filled with the third pad insulating layer LDI3, and the second removal space RS2 can each be completely filled with the third pad insulating layer LDI3 and the third fill insulating layer FDI3. For example, the third pad insulating layer LDI3 may include SiO2 or SiOC, and the third fill insulating layer FDI3 may include Si3N4 and SiOCN.

[0104] refer to Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C and Figure 12D Multiple third removal spaces RS3 can be formed by removing portions of the third filler insulating layer FDI3 filling the second removal space RS2 through the second isolation trench STR2, and removing portions of the third pad insulating layer LDI3 exposed after removing portions of the third filler insulating layer FDI3. Each third removal space RS3 can correspond to a portion of the second removal space RS2. Portions of the third pad insulating layer LDI3 filling the first removal space RS1 can be retained without removal. During the process of removing portions of the third pad insulating layer LDI3, exposed portions of the first pad insulating layer LDI1 may also be removed. For example, the first filler insulating layer FDI1, the first channel pattern 110, the third sacrificial layer SAC3, the remaining portions of the third filler insulating layer FDI3, and the remaining portions of the third pad insulating layer LDI3 can be exposed through the third removal spaces RS3.

[0105] refer to Figure 13A , Figure 13B , Figure 13C and Figure 13DA first gate dielectric layer 132 may be formed to cover the inner surface of each of the third removal spaces RS3, and an information storage element 140 may be formed to cover the first gate dielectric layer 132 and fill each of the third removal spaces RS3. The first gate dielectric layer 132 may be formed to conformally cover the inner surface of each of the third removal spaces RS3.

[0106] For example, the first gate dielectric layer 132 may include at least one selected from the group consisting of silicon oxide, a high-k dielectric material with a dielectric constant higher than that of silicon oxide, and a ferroelectric material. In one or more example embodiments, the first gate dielectric layer 132 may have a stacked structure consisting of a first dielectric film including silicon oxide and a second dielectric film including at least one of a high-k dielectric material and a ferroelectric material. For example, high-k dielectric materials and ferroelectric materials may include at least one selected from the group consisting of: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxysilane (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). Information storage element 140 may include oxide semiconductor materials, 2D semiconductor materials, conductive materials, or combinations thereof. For example, information storage element 140 may include an oxide semiconductor material, such as IGZO.

[0107] refer to Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C and Figure 14D Multiple fourth removal spaces RS4 can be formed by removing the third removal space RS3. Each of the fourth removal spaces RS4 can expose a corresponding portion of the first pad insulating layer LDI1, the second pad insulating layer LDI2, the third pad insulating layer LDI3, and the first gate dielectric layer 132.

[0108] refer to Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C and Figure 15DEach of the fourth removal spaces RS4 can be enlarged by removing corresponding portions of the first pad insulating layer LDI1, the second pad insulating layer LDI2, the third pad insulating layer LDI3, and the first gate dielectric layer 132, thus exposing each of the first pad insulating layer LDI1, the second pad insulating layer LDI2, the third pad insulating layer LDI3, and the first gate dielectric layer 132 through each of the fourth removal spaces RS4. The corresponding portions of the information storage element 140, the first gate dielectric layer 132, the third fill insulating layer FDI3, the third pad insulating layer LDI3, the second pad insulating layer LDI2, the second fill insulating layer FDI2, and the first fill insulating layer FDI1 can be exposed through each of the enlarged fourth removal spaces RS4.

[0109] refer to Figure 16A , Figure 16B , Figure 16C and Figure 16D A second channel layer 120P can be formed to cover the inner surface of each of the fourth removal spaces RS4, and a fourth fill insulating layer FDI4 can be formed to cover the second channel layer 120P and fill each of the fourth removal spaces RS4. The second channel layer 120P can be formed to conformally cover the inner surface of each of the fourth removal spaces RS4. The fourth fill insulating layer FDI4 can be formed to fill the remaining space of each of the fourth removal spaces RS4. The second channel layer 120P may include a single-crystal semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor material, or a 2D semiconductor material. For example, the second channel layer 120P may include an oxide semiconductor material, such as IGZO. In one or more example embodiments, the second channel layer 120P may include the same material as the information storage element 140. For example, the fourth fill insulating layer FDI4 may include Si3N4 or SiOCN.

[0110] refer to Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C and Figure 17D The second cover mask layer CMK2 can be formed by removing a portion of the first cover mask layer CMK1. The second cover mask layer CMK2 can cover the second pad insulating layer LDI2 and the second fill insulating layer FDI2 that fill the first isolation trench STR1. For example, the second cover mask layer CMK2 can be formed by removing the portion of the first cover mask layer CMK1 that overlaps with the first channel pattern 110 in the vertical direction (Z direction).

[0111] refer to Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C and Figure 18D The fifth removal space RS5 can be formed by removing the first filler insulation layer FDI1 and a portion of the second channel layer 120P exposed by removing the first filler insulation layer FDI1. Corresponding portions of the first liner insulation layer LDI1, the second channel layer 120P, and the fourth filler insulation layer FDI4 can be exposed through the fifth removal space RS5.

[0112] refer to Figure 19A , Figure 19B , Figure 19C and Figure 19D A fifth fill insulating layer FDI5 can be formed to fill the fifth removal space RS5. For example, the fifth fill insulating layer FDI5 may include Si3N4 or SiOCN. In one or more example embodiments, before forming the fifth fill insulating layer FDI5, impurities may be implanted into the portion of the second channel layer 120P exposed by the fifth removal space RS5. For example, impurities such as H or O may be implanted into a portion of the second channel layer 120P.

[0113] refer to Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B , Figure 20C and Figure 20D By removing the fifth filler insulating layer FDI5 and the fourth filler insulating layer FDI4, a plurality of sixth removal spaces RS6 can be formed to communicate with the fifth removal space RS5 filled with the fifth filler insulating layer FDI5. In one or more example embodiments, the portion of the first pad insulating layer LDI1 exposed by the second isolation trench STR2 can be removed before removing the fifth filler insulating layer FDI5 and the fourth filler insulating layer FDI4. The sixth removal spaces RS6 may correspond to respectively Figure 15B , Figure 15C and Figure 15D The corresponding portion of the fourth removal space RS4. The second channel layer 120P may be exposed by each of the sixth removal spaces RS6. In one or more example embodiments, after the fifth removal space RS5 is formed, the fifth fill insulating layer FDI5 may not be formed, and each sixth removal space RS6 may be formed by removing the fourth fill insulating layer FDI4 through the fifth removal space RS5. The sixth removal space RS6 may correspond to the portion of each of the fourth removal spaces RS4 that is not filled by the second channel layer 120P.

[0114] refer to Figure 21A , Figure 21B , Figure 21C and Figure 21D A sixth filler insulating layer FDI6 can be formed to fill a portion of the fifth removal space RS5 and a portion of the sixth removal space RS6. For example, the sixth filler insulating layer FDI6 may include Si3N4 or SiOCN. The sixth filler insulating layer FDI6 may cover the second channel layer 120P and may not completely fill the sixth removal space RS6. The sixth filler insulating layer FDI6 may define a first finite space SP1 extending in the second horizontal direction (Y direction) within the fifth removal space RS5 and the sixth removal space RS6.

[0115] refer to Figure 22A , Figure 22B , Figure 22C and Figure 22D The second channel layer 120P can be exposed by removing a portion of the sixth fill insulating layer FDI6 through the first finite space SP1. In one or more example embodiments, a portion of the sixth fill insulating layer FDI6 that fills the fifth removal space RS5 and does not overlap with the fourth removal space RS4 can be retained without removal. The first finite space SP1 can be extended to be defined by the sixth fill insulating layer FDI6, the second channel layer 120P, the first gate dielectric layer 132, the first pad insulating layer LDI1, and the third pad insulating layer LDI3, and can extend in the second horizontal direction (Y direction) within the fifth removal space RS5 and the sixth removal space RS6.

[0116] refer to Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 23A , Figure 23B , Figure 23C and Figure 23DA second gate dielectric layer 158 may be formed to cover the exposed surface of the first confined space SP1. A first separating insulating layer 152, a back gate line 150, and a second separating insulating layer 154 may be formed to cover the second gate dielectric layer 158 and subsequently fill the first confined space SP1. The back gate line 150 may extend in a second horizontal direction (Y direction). The first separating insulating layer 152 and the second separating insulating layer 154 may be disposed on opposite side surfaces of the back gate line 150 in a first horizontal direction (X direction) and may extend in the second horizontal direction (Y direction). For example, the second gate dielectric layer 158 may include at least one selected from the group consisting of silicon oxide, a high-k dielectric material with a dielectric constant higher than silicon oxide, and a ferroelectric material. In one or more example embodiments, the first gate dielectric layer 132 and the second gate dielectric layer 158 may include the same material. For example, the first separating insulating layer 152 and the second separating insulating layer 154 may include Si3N4 or SiOCN.

[0117] The first separating insulating layer 152, the back gate line 150, and the second separating insulating layer 154 may each include upward and downward protruding portions to have increased thickness and correspond to the space between adjacent second channel layers 120P in the second horizontal direction (Y direction). Although Figure 23C Only the shape of the second separating insulating layer 154 is shown, but it will be apparent to those skilled in the art that the first separating insulating layer 152 may also include upward and downward protruding portions to have increased thickness and correspond to the space between the first channel patterns 110 that are adjacent to each other in the second horizontal direction (Y direction).

[0118] refer to Figure 24A , Figure 24B , Figure 24C and Figure 24D A portion of the information storage element 140 and a portion of the second channel layer 120P (exposed by the second isolation trench STR2) can be removed, thereby forming a third separation insulating layer 145 to fill the space where a portion of the information storage element 140 and a portion of the second channel layer 120P have been removed. For example, the third separation insulating layer 145 may comprise Si3N4 or SiOCN. In one or more example embodiments, Figure 35 The second impurity region 112D2 can be formed by injecting impurities into a portion of the first channel pattern 110 exposed by the second isolation trench STR2.

[0119] refer to Figure 25A , Figure 25B , Figure 25C and Figure 25DA plate electrode 180 can be formed to fill the second isolation trench STR2. The plate electrode 180 can be formed to contact the first channel pattern 110 and spaced apart from the second channel layer 120P and the information storage element 140. For example, a third separating insulating layer 145 can be disposed between the second channel layer 120P and the plate electrode 180, and between the information storage element 140 and the plate electrode 180. The plate electrode 180 can include a metal, a conductive metal nitride, a metal compound, a conductive metal oxide, graphene, carbon nanotubes, or a combination thereof. In one or more example embodiments, the plate electrode 180 can be formed in a portion of the first channel pattern 110 before its formation. Figure 3 The second silicide layer 116 in the middle.

[0120] refer to Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 26A , Figure 26B , Figure 26C and Figure 26D The second cover mask layer CMK2 can be removed, and the third isolation trench STR3 can be formed by removing the second filler insulating layer FDI2 and the second pad insulating layer LDI2, and then removing a portion of the third pad insulating layer LDI3. The third isolation trench STR3 may include a first isolation trench STR1, except for a portion of the first isolation trench STR1 in which the second channel layer 120P protrudes into the first isolation trench STR1, and may additionally include the space from which the third pad insulating layer LDI3 has been removed, and may be generally similar to the first isolation trench STR1. Accordingly, the third isolation trench STR3 may not be distinguished from the first isolation trench STR1 and may be referred to as the first isolation trench STR1. The third cover mask layer CMK3 can be formed to cover a plurality of first channel patterns 110 and a plurality of plate electrodes 180. A third overlay mask layer CMK3 can be formed to overlap with the plurality of first channel patterns 110 and plate electrodes 180 in the vertical direction (Z direction), but not to overlap with the exposed portion of the substrate 102 at the bottom of the third isolation trench STR3 in the vertical direction (Z direction). In one or more example embodiments, Figure 35 The first impurity region 112D1 can be formed by injecting impurities into a portion of each first channel pattern 110 exposed by the third isolation trench STR3.

[0121] refer to Figure 26A , Figure 26B , Figure 26C , Figure 26D , Figure 27A , Figure 27B , Figure 27C and Figure 27DMultiple seventh removal spaces RS7 can be formed by removing the third filling insulation layer FDI3 through the third isolation trench STR3. Each seventh removal space RS7 can correspond to... Figure 10B , Figure 10C and Figure 10D The second part of the space RS2 is removed.

[0122] refer to Figure 27A , Figure 27B , Figure 27C , Figure 27D , Figure 28A , Figure 28B , Figure 28C and Figure 28D Each of the seventh removal spaces RS7 can be enlarged by removing a portion of the third pad insulation layer LDI3 in each seventh removal space RS7. In one or more example embodiments, a portion of the third pad insulation layer LDI3 between two adjacent first channel patterns 110 in the vertical direction (Z direction) can be retained without being removed.

[0123] refer to Figure 28A , Figure 28B , Figure 28C , Figure 28D , Figure 29A , Figure 29B , Figure 29C and Figure 29D The eighth removal space RS8 can be formed by removing a portion of the sixth fill insulation layer FDI6 exposed by the seventh removal space RS7.

[0124] refer to Figure 30A , Figure 30B , Figure 30C and Figure 30D A seventh filling insulating layer FDI7 can be formed to fill a portion of the seventh removal space RS7 and a portion of the eighth removal space RS8. For example, the seventh filling insulating layer FDI7 may include Si3N4 or SiOCN. The seventh filling insulating layer FDI7 can be formed to completely fill the eighth removal space RS8, but may not completely fill the seventh removal space RS7. A second finite space SP2 extending along the second horizontal direction (Y direction) within the seventh removal space RS7 may be defined by the seventh filling insulating layer FDI7.

[0125] refer to Figure 30A , Figure 30B , Figure 30C , Figure 30D , Figure 31A , Figure 31B , Figure 31C and Figure 31D It is possible to remove part of the seventh filling insulating layer FDI7 that fills the seventh removal space RS7.

[0126] refer to Figure 32A , Figure 32B , Figure 32C and Figure 32D A third gate dielectric layer 168 may be formed to cover the exposed surface of the seventh removal space RS7. A fourth separating insulating layer 162, a word line 160, and a fifth separating insulating layer 164 may be formed to cover the third gate dielectric layer 168, and the seventh removal space RS7 may subsequently be filled. The word line 160 may extend in a second horizontal direction (Y direction). The fourth separating insulating layer 162 and the fifth separating insulating layer 164 may be formed on opposite sides of the word line 160, respectively, and may extend in the second horizontal direction (Y direction). For example, the third gate dielectric layer 168 may include at least one selected from the group consisting of silicon oxide, a high-k dielectric material with a dielectric constant higher than silicon oxide, and a ferroelectric material. In one or more example embodiments, the first gate dielectric layer 132, the second gate dielectric layer 158, and the third gate dielectric layer 168 may include the same material. The first gate dielectric layer 132, the second gate dielectric layer 158, and the third gate dielectric layer 168 may be collectively referred to as gate dielectric layers. For example, the fourth separating insulating layer 162 and the fifth separating insulating layer 164 may include Si3N4 or SiOCN.

[0127] refer to Figure 32A , Figure 32B , Figure 32C , Figure 32D , Figure 33A , Figure 33B , Figure 33C and Figure 33D The second channel pattern 120 can be formed by removing a portion of the second channel layer 120P exposed by the third isolation trench STR3. By removing a portion of the second channel layer 120P exposed by the third isolation trench STR3, the second channel layer 120P can be divided into the second channel pattern 120.

[0128] refer to Figure 34A , Figure 34B , Figure 34C and Figure 34D The semiconductor device 1000 can be formed by filling bit lines 170 in the third isolation trench STR3. Bit lines 170 can be formed to contact the first channel pattern 110 and the second channel pattern 120. A fifth separating insulating layer 164 can be formed between the bit lines 170 and the word lines 160. In one or more example embodiments, the bit lines 170 can be formed in a portion of the first channel pattern 110 before the bit lines 170 are formed. Figure 3 The first silicide layer 114 is in the middle. The bit line 170 may include a metal, a conductive metal nitride, a metal compound, a conductive metal oxide, graphene, carbon nanotubes, or a combination thereof.

[0129] Semiconductor device 1000 may include multiple memory cells MC, each memory cell including a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180. A first gate dielectric layer 132 may be located between the first channel pattern 110 and the information storage element 140. A second gate dielectric layer 158 may be located between the second channel pattern 120 and the back gate line 150. A third gate dielectric layer 168 may be located between the first channel pattern 110 and the word line 160. The third gate dielectric layer 168 may also be located between the second channel pattern 120 and the word line 160.

[0130] The first separating insulating layer 152, the back gate line 150, and the second separating insulating layer 154 may each include protrusions that project upwards and downwards to have increased thickness and correspond to the space between adjacent second channel patterns 120 in the second horizontal direction (Y direction). Although Figure 34C Only the shape of the second separating insulating layer 154 is shown, but it will be apparent to those skilled in the art that the first separating insulating layer 152 may include protrusions that project upwards and downwards to have increased thickness and correspond to the space between adjacent second channel patterns 120 in the second horizontal direction (Y direction). The protrusions of each of the first separating insulating layer 152, the back gate line 150, and the second separating insulating layer 154 may fill the space defined by the second gate dielectric layer 158. For example, a portion of the second gate dielectric layer 158 may be between adjacent second channel patterns 120 in the second horizontal direction (Y direction).

[0131] Figure 35 A memory cell of a semiconductor device according to one or more example embodiments is shown.

[0132] refer to Figure 35 The semiconductor device 100a may include a first channel pattern 110a, a second channel pattern 120a, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180 disposed on a substrate 102. The first channel pattern 110a, the second channel pattern 120a, the information storage element 140, the word line 160, the back gate line 150, the bit line 170, and the plate electrode 180 may form a memory cell MC.

[0133] The first channel pattern 110a may extend in a first horizontal direction (X direction). The first channel pattern 110a may contact the bit line 170 and the plate electrode 180. In the first horizontal direction (X direction), one end of the first channel pattern 110a may contact the bit line 170, and the opposite end of the first channel pattern 110a may contact the plate electrode 180. The first channel pattern 110a may comprise a single-crystal semiconductor material or a polycrystalline semiconductor material.

[0134] In one or more example embodiments, the first channel pattern 110a may include a first channel region 112a, a first silicide layer 114, and a second silicide layer 116. The first channel region 112a may be disposed between the first silicide layer 114 and the second silicide layer 116. The first channel region 112a may include a first channel portion 112C, a first impurity region 112D1, and a second impurity region 112D2. The first channel portion 112C may be disposed between the first impurity region 112D1 and the second impurity region 112D2. The first impurity region 112D1 and the second impurity region 112D2 may each include impurities. In one or more example embodiments, when Figure 2 When the read transistor Rtr is an N-channel metal-oxide-semiconductor (NMOS) transistor, the first impurity region 112D1 and the second impurity region 112D2 may each include N-type impurities, such as P or As. In one or more example embodiments, when Figure 2 When the read transistor Rtr is a P-channel metal-oxide-semiconductor (PMOS) transistor, the first impurity region 112D1 and the second impurity region 112D2 may each include P-type impurities, such as B or Al.

[0135] The second channel pattern 120a may extend in a first horizontal direction (X direction). The second channel pattern 120a may be spaced apart from the first channel pattern 110a in a vertical direction (Z direction). The second channel pattern 120a may contact the bit line 170 and the information storage element 140. In the first horizontal direction (X direction), one end of the second channel pattern 120a may contact the bit line 170, and the opposite end of the second channel pattern 120a may contact the information storage element 140. In one or more example embodiments, the second channel pattern 120a may include a second channel portion 122C and a channel contact 122D. The channel contact 122D may contact the bit line 170. The channel contact 122D may be disposed between the second channel portion 122C and the bit line 170. The channel contact 122D may include doped polysilicon, metal, conductive metal nitride, metal-semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof. The channel contact 122D may include an impurity region with injected impurities (e.g., H or O).

[0136] Figure 36A , Figure 36B and Figure 36C The memory cells of semiconductor devices according to one or more example embodiments are shown respectively.

[0137] refer to Figure 36A The semiconductor device 100b may include a first channel pattern 110, a second channel pattern 120b, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180 disposed on a substrate 102. The first channel pattern 110, the second channel pattern 120b, the information storage element 140, the word line 160, the back gate line 150, the bit line 170, and the plate electrode 180 may form a memory cell MC.

[0138] The second channel pattern 120b may include a single-crystal semiconductor material or a polycrystalline semiconductor material. In one or more example embodiments, the second channel pattern 120b may include a single-crystal semiconductor material (e.g., Si) or a polycrystalline semiconductor material (e.g., polycrystalline silicon). In one or more example embodiments, the single-crystal or polycrystalline semiconductor material of the second channel pattern 120b may not be in contact with the bit line 170 or the plate electrode 180. For example, the second channel pattern 120b may include a second channel region 122 and a third silicide layer 124, the second channel region 122 including a single-crystal or polycrystalline semiconductor material. The third silicide layer 124 may be disposed between the second channel region 122 and the bit line 170. The third silicide layer 124 may be in contact with the bit line 170. The second channel region 122 may be spaced apart from the bit line 170, and the third silicide layer 124 is located between the second channel region 122 and the bit line 170.

[0139] refer to Figure 36B The semiconductor device 100c may include a first channel pattern 110b, a second channel pattern 120b, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180 disposed on a substrate 102. The first channel pattern 110b, the second channel pattern 120b, the information storage element 140, the word line 160, the back gate line 150, the bit line 170, and the plate electrode 180 may form a memory cell MC.

[0140] The first channel pattern 110b may include an oxide semiconductor material or a 2D semiconductor material. The oxide semiconductor material or 2D semiconductor material of the first channel pattern 110b may be in direct contact with the bit line 170 and the plate electrode 180. For example, the first channel pattern 110b may not include the first silicide layer 114 and the second silicide layer 116, which are respectively in contact with... Figure 3 and Figure 36AThe bit line 170 and the plate electrode 180 included in the first channel pattern 110 are in direct contact. In one or more example embodiments, the first channel pattern 110b may include an oxide semiconductor material, such as IGZO. The second channel pattern 120b may include a single-crystal semiconductor material (e.g., Si) or a polycrystalline semiconductor material (e.g., polycrystalline silicon).

[0141] refer to Figure 36C The semiconductor device 100d may include a first channel pattern 110b, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180 disposed on a substrate 102. The first channel pattern 110b, the second channel pattern 120, the information storage element 140, the word line 160, the back gate line 150, the bit line 170, and the plate electrode 180 may form a memory cell MC.

[0142] The first channel pattern 110b and the second channel pattern 120 may each comprise an oxide semiconductor material or a 2D semiconductor material. The oxide semiconductor material or 2D semiconductor material of the first channel pattern 110b may be in direct contact with the bit line 170 and the plate electrode 180. The oxide semiconductor material or 2D semiconductor material of the second channel pattern 120 may be in direct contact with the bit line 170. In one or more example embodiments, the first channel pattern 110b and the second channel pattern 120 may each comprise an oxide semiconductor material, such as IGZO.

[0143] Figure 37 A memory cell of a semiconductor device according to one or more example embodiments is shown.

[0144] refer to Figure 37 The semiconductor device 100e may include a first channel pattern 110c, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170a, and a plate electrode 180a disposed on a substrate 102. The first channel pattern 110c may correspond to... Figure 3 and Figure 36A The first channel region 112 in the middle, or can correspond to Figure 35 The first channel region 112a. The first channel pattern 110c, the second channel pattern 120, the information storage element 140, the word line 160, the back gate line 150, the bit line 170a, and the plate electrode 180a can form a memory cell MC.

[0145] Bit line 170a may have a stacked structure of a first conductive semiconductor layer 172, a first silicide electrode layer 174, and a first metal electrode layer 176. Plate electrode 180a may have a stacked structure of a second conductive semiconductor layer 182, a second silicide electrode layer 184, and a second metal electrode layer 186. For example, the first conductive semiconductor layer 172 and the second conductive semiconductor layer 182 may each comprise doped polysilicon. For example, the first metal electrode layer 176 and the second metal electrode layer 186 may each comprise a metal or a conductive metal nitride. In one or more example embodiments, the first metal electrode layer 176 and the second metal electrode layer 186 may each have a stacked structure of a barrier layer, an electrode layer, and a capping layer. A first channel pattern 110c may contact the first conductive semiconductor layer 172 and the second conductive semiconductor layer 182, and a second channel pattern 120 may contact the first conductive semiconductor layer 172.

[0146] Figure 38A , Figure 38B , Figure 38C and Figure 38D This is a diagram illustrating a semiconductor device according to one or more example embodiments. Specifically, Figure 38B It is along Figure 38A A cross-sectional view taken along the centerline B-B'. Figure 38C It is along Figure 38A A cross-sectional view taken along the centerline C-C', and Figure 38D It is along Figure 38A A cross-sectional view taken along the centerline D-D'.

[0147] refer to Figure 38A , Figure 38B , Figure 38C and Figure 38D The semiconductor device 1000a may include a first separating insulating layer 152a, a back gate line 150a, and a second separating insulating layer 154a. The first separating insulating layer 152a, the back gate line 150a, and the second separating insulating layer 154a may extend in a second horizontal direction (Y direction) and have substantially the same thickness in the vertical direction (Z direction). For example, the first separating insulating layer 152a, the back gate line 150a, and the second separating insulating layer 154a may not include... Figure 34B , Figure 34C and Figure 34D The protrusions of each of the first separating insulating layer 152, the back gate line 150, and the second separating insulating layer 154. For example, a portion of the sixth filling insulating layer FDI6, instead of a portion of the second gate dielectric layer 158, may be arranged between second channel patterns 120 adjacent to each other in the second horizontal direction (Y direction). Although Figure 38AOnly the shape of the second separating insulating layer 154a is shown, but it will be apparent to those skilled in the art that the first separating insulating layer 152a may also extend in the second horizontal direction (Y direction) and have substantially the same thickness.

[0148] When referring to the above text Figure 22A , Figure 22B , Figure 22C and Figure 22D In the process of partially removing the sixth filler insulating layer FDI6 described above, a portion of the sixth filler insulating layer FDI6 is left between adjacent second channel layers 120P in the second horizontal direction (Y direction), and then the process described in the above reference is performed. Figure 23A , Figure 23B , Figure 23C and Figure 23D The process described for forming the first separation insulating layer 152, the back gate line 150, and the second separation insulating layer 154 can form the first separation insulating layer 152a, the back gate line 150a, and the second separation insulating layer 154a.

[0149] Figure 39 This is a diagram illustrating a semiconductor device according to one or more example embodiments.

[0150] refer to Figure 39 Semiconductor device 1000b may include a back gate line 150b. The back gate line 150b may include a main back gate line 150M and a work function control layer 150W. In one or more example embodiments, the work function control layer 150W may be disposed between the main back gate line 150M and a second separating insulating layer 154, but one or more example embodiments are not limited thereto. For example, the work function control layer 150W may be disposed between the main back gate line 150M and a first separating insulating layer 152.

[0151] Figure 40 This is a diagram illustrating a semiconductor device according to one or more example embodiments.

[0152] refer to Figure 40 The semiconductor device 1000c may include multiple memory cells MC, each memory cell MC including a first channel pattern 110, a second channel pattern 120S, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180.

[0153] Two adjacent memory cells MC in the vertical direction (Z direction) can share the second channel pattern 120S. For example, in the YZ plane formed by the second horizontal direction (Y direction) and the vertical direction (Z direction), the second channel pattern 120S can have a U-shape rotated 90 degrees. The second channel pattern 120S can be defined by omitting the reference above. Figure 32A , Figure 32B , Figure 32C , Figure 32D , Figure 33A , Figure 33B , Figure 33C and Figure 33D The process described involves removing the exposed portion of the second channel layer 120P in the third isolation trench STR3. For example, the second channel pattern 120S may correspond to... Figure 32A , Figure 32B , Figure 32C and Figure 32D The second channel layer 120P is included. The second channel pattern 120S may include a pair of channel portions extending in a second horizontal direction (Y direction) and a connecting portion extending in a vertical direction (Z direction) and connecting the channel portions to each other. The channel portions of the second channel pattern 120S may not overlap with the bit line 170 in the vertical direction (Z direction). For example, each of the channel portions of the second channel pattern 120S may correspond to Figure 34B , Figure 34C and Figure 34D The second channel pattern 120 is shown. The connecting portion of the second channel pattern 120S may overlap with the bit line 170 in the vertical direction (Z direction). For example, the connecting portion of the second channel pattern 120S may correspond to a removed portion of the second channel layer 120P, which has been referenced. Figure 32A , Figure 32B , Figure 32C , Figure 32D , Figure 33A , Figure 33B , Figure 33C and Figure 33D It has been described.

[0154] Figure 41A , Figure 41B and Figure 41C The memory cells of semiconductor devices according to one or more example embodiments are shown respectively.

[0155] refer to Figure 41A The semiconductor device 100f may include a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180 disposed on a substrate 102. The first channel pattern 110, the second channel pattern 120, the information storage element 140, the word line 160, the back gate line 150, the bit line 170, and the plate electrode 180 may form a memory cell MC.

[0156] The back grid line 150 may be adjacent to the information storage element 140, but may not overlap with the information storage element 140 in the vertical direction (Z direction). The information storage element 140 may be spaced apart from the word line 160 by a first separation distance D1a, and from the back grid line 150 by a second separation distance D2a. The second separation distance D2a may be less than the first separation distance D1a.

[0157] refer to Figure 41B The semiconductor device 100g may include a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180 disposed on a substrate 102. The first channel pattern 110, the second channel pattern 120, the information storage element 140, the word line 160, the back gate line 150, the bit line 170, and the plate electrode 180 may form a memory cell MC.

[0158] In the first horizontal direction (X direction), the word line 160 may have a first horizontal width W1a, and the back gate line 150 may have a second horizontal width W2a. In one or more example embodiments, the first horizontal width W1a may be substantially the same as the second horizontal width W2a. In one or more example embodiments, the back gate line 150 may overlap with the information storage element 140 in the vertical direction (Z direction), but one or more example embodiments are not limited thereto. In one or more example embodiments, the back gate line 150 may not overlap with the word line 160 in the vertical direction (Z direction), but one or more example embodiments are not limited thereto.

[0159] refer to Figure 41C The semiconductor device 100h may include a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180 disposed on a substrate 102. The first channel pattern 110, the second channel pattern 120, the information storage element 140, the word line 160, the back gate line 150, the bit line 170, and the plate electrode 180 may form a memory cell MC.

[0160] In the first horizontal direction (X direction), the word line 160 may have a first horizontal width W1b, and the back gate line 150 may have a second horizontal width W2b. In one or more example embodiments, the first horizontal width W1b may be greater than the second horizontal width W2b.

[0161] Figure 42 This is a conceptual perspective view of a semiconductor device including multiple memory cells according to one or more example embodiments.

[0162] refer to Figure 42The semiconductor device 1000d may include a plurality of plate electrodes 180S, each plate electrode 180S contacting a first channel pattern 110. The plate electrodes 180S may extend in a vertical direction (Z direction) and may be arranged in a row in a second horizontal direction (Y direction). In one or more example embodiments, the plate electrodes 180S may extend in the vertical direction (Z direction) and may be spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction). Each of the plate electrodes 180S may contact the first channel pattern 110 arranged in a row in the vertical direction (Z direction). In one or more example embodiments, the plate electrodes 180S may be electrically grounded.

[0163] Figure 43A , Figure 43B , Figure 43C , Figure 43D and Figure 43E The memory cells of semiconductor devices according to one or more example embodiments are shown respectively.

[0164] refer to Figure 43A The semiconductor device 100i may include a plate electrode 180b. In one or more example embodiments, the plate electrode 180b may include a plate body 181 and a protrusion 183 extending from the plate body 181 toward the information storage element 140. The plate body 181 may correspond to... Figure 5 Plate electrode 180 or Figure 42 The plate electrode 180S is located in the plate body 181. The protrusion 183 can extend from the plate body 181 in the first horizontal direction (X direction).

[0165] Since the plate electrode 180b includes a protrusion 183 extending toward the information storage element 140, the distance between the information storage element 140 and the plate electrode 180b can be reduced, and since the plate electrode 180b is electrically grounded, electrical coupling between the information storage element 140 and the word line 160 can be prevented.

[0166] refer to Figure 43B The plate electrode 180b of the semiconductor device 100j may include a protrusion 183 extending toward the information storage element 140a. In one or more example embodiments, the information storage element 140a may have multiple side surfaces facing the protrusion 183. For example, a portion of the information storage element 140a may overlap with the protrusion 183 in a first horizontal direction (X direction), while another portion of the information storage element 140a may overlap with the protrusion 183 in a vertical direction (Z direction).

[0167] refer to Figure 43CThe plate electrode 180b of the semiconductor device 100k may include a protrusion 183 extending toward the information storage element 140b. In one or more example embodiments, the information storage element 140b may have multiple side surfaces facing the protrusion 183. For example, the information storage element 140b may include a side surface overlapping the protrusion 183 in a first horizontal direction (X direction) and a side surface overlapping the protrusion 183 in a vertical direction (Z direction). At least three side surfaces of the information storage element 140b may overlap the protrusion 183. For example, the information storage element 140b may have a U-shape rotated 90 degrees in the YZ plane formed by the second horizontal direction (Y direction) and the vertical direction (Z direction). The information storage element 140b may include a pair of horizontal extensions extending in the second horizontal direction (Y direction) and a vertical extension extending in the vertical direction (Z direction) and connecting the pair of horizontal extensions to each other. One horizontal extension of the information storage element 140b may be adjacent to, spaced apart from, and at least partially overlap with the top surface of the protrusion 183 in the vertical direction (Z direction), while another horizontal extension of the information storage element 140b may be adjacent to, spaced apart from, and at least partially overlap with the bottom surface of the protrusion 183 in the vertical direction (Z direction). The vertical extension of the information storage element 140b may be adjacent to, spaced apart from, and at least partially overlap with the side surface of the protrusion 183 in a first horizontal direction (X direction).

[0168] refer to Figure 43D The plate electrode 180b of the semiconductor device 100l may include a protrusion 183 extending toward the information storage element 140b. At least three side surfaces of the information storage element 140b may overlap with the protrusion 183. In one or more example embodiments, the information storage element 140b may be U-shaped, and three side surfaces of the information storage element 140b may overlap with the protrusion 183. For example, the information storage element 140b may include: a portion that is adjacent to, spaced apart from, and at least partially overlaps with the top surface of the protrusion 183 in the vertical direction (Z direction); a portion that is adjacent to, spaced apart from, and at least partially overlaps with the bottom surface of the protrusion 183 in the vertical direction (Z direction); and a portion that is adjacent to, spaced apart from, and at least partially overlaps with the side surfaces of the protrusion 183 in a first horizontal direction (X direction).

[0169] refer to Figure 43EThe plate electrode 180b of the semiconductor device 100m may include a protrusion 183 extending toward the information storage element 140b. At least three side surfaces of the information storage element 140b may overlap with the protrusion 183. For example, the information storage element 140b may surround the protrusion 183. In one or more example embodiments, five side surfaces of the information storage element 140b may overlap with the protrusion 183. For example, the information storage element 140b may include: a portion that is adjacent to, spaced apart from, and at least partially overlaps with the top surface of the protrusion 183 in the vertical direction (Z direction); a portion that is adjacent to, spaced apart from, and at least partially overlaps with the bottom surface of the protrusion 183 in the vertical direction (Z direction); a portion that is adjacent to, spaced apart from, and at least partially overlaps with the side surface of the protrusion 183 in the first horizontal direction (X direction); a portion that is adjacent to, spaced apart from, and at least partially overlaps with the side surface of the protrusion 183 in the second horizontal direction (Y direction); and a portion that is adjacent to, spaced apart from, and at least partially overlaps with the opposite side surface of the protrusion 183 in the second horizontal direction (Y direction).

[0170] Figure 44A and Figure 44B Word lines of semiconductor devices according to one or more example embodiments are shown respectively.

[0171] refer to Figure 44A The semiconductor device 100n may include a bit line 170 in contact with a channel pattern CH and a word line 160 adjacent to the channel pattern CH. The channel pattern CH may correspond to a first channel pattern 110, 110a, 110b or 110c, or a second channel pattern 120, 120a or 120b, as already referenced above. Figures 3 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 17D 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 19D 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 25D 、 Figure 26A 、 Figure 26B 、 Figure 26C 、 Figure 26D 、 Figure 27A 、 Figure 27B 、 Figure 27C 、 Figure 27D 、 Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 28D 、 Figure 29A 、 Figure 29B 、 Figure 29C 、 Figure 29D 、 Figure 30A 、 Figure 30B 、 Figure 30C 、 Figure 30D , Figure 31A , Figure 31B , Figure 31C , Figure 31D , Figure 32A , Figure 32B , Figure 32C , Figure 32D , Figure 33A , Figure 33B , Figure 33C , Figure 33D , Figure 34A , Figure 34B , Figure 34C , Figure 34D , Figure 35 , Figure 36A , Figure 36B , Figure 36C , Figure 37 , Figure 38A , Figure 38B , Figure 38C , Figure 38D , Figure 39 , Figure 40 , Figure 41A , Figure 41B , Figure 41C , Figure 42 , Figure 43A , Figure 43B and Figure 43C The word line 160 may have a side surface facing the channel pattern CH. For example, the word line 160 may overlap with the side surface of the channel pattern CH.

[0172] refer to Figure 44B The semiconductor device 100o may include a bit line 170 in contact with a channel pattern CH and a word line 160 adjacent to the channel pattern CH. The channel pattern CH may correspond to a first channel pattern 110, 110a, 110b or 110c, or a second channel pattern 120, 120a or 120b, as already referenced above. Figures 3 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 17D 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 19D 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 25D 、 Figure 26A 、 Figure 26B 、 Figure 26C 、 Figure 26D 、 Figure 27A 、 Figure 27B 、 Figure 27C 、 Figure 27D 、 Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 28D 、 Figure 29A , Figure 29B , Figure 29C , Figure 29D , Figure 30A , Figure 30B , Figure 30C , Figure 30D , Figure 31A , Figure 31B , Figure 31C , Figure 31D , Figure 32A , Figure 32B , Figure 32C , Figure 32D , Figure 33A , Figure 33B , Figure 33C , Figure 33D , Figure 34A , Figure 34B , Figure 34C , Figure 34D , Figure 35 , Figure 36A , Figure 36B , Figure 36C , Figure 37 , Figure 38A , Figure 38B , Figure 38C , Figure 38D , Figure 39 , Figure 40 , Figure 41A , Figure 41B , Figure 41C , Figure 42 , Figure 43A , Figure 43B and Figure 43C The following description is provided. Word line 160 may have multiple side surfaces facing the channel pattern CH. For example, word line 160 may overlap with three side surfaces of the channel pattern CH. Word line 160 may be spaced apart from the channel pattern CH. Word line 160 may include a portion adjacent to the top surface of the channel pattern CH, portions adjacent to the side surfaces of the channel pattern CH, and portions adjacent to opposite side surfaces of the channel pattern CH. The thickness of the portion of word line 160 adjacent to the top surface of the channel pattern CH may be less than the thickness of each of the portions of word line 160 adjacent to the respective opposite side surfaces of the channel pattern CH.

[0173] Figure 45A , Figure 45B and Figure 45C Information storage elements of semiconductor devices according to one or more example embodiments are shown respectively.

[0174] refer to Figure 45AThe semiconductor device 100p may include a bit line 170 in contact with the channel pattern CH and an information storage element 140 adjacent to the channel pattern CH. The channel pattern CH may correspond to a first channel pattern 110, 110a, 110b or 110c, or a second channel pattern 120, 120a or 120b, as already referenced above. Figures 3 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 24A , Figure 24B , Figure 24C , Figure 24D , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 26A , Figure 26B , Figure 26C , Figure 26D , Figure 27A , Figure 27B , Figure 27C , Figure 27D , Figure 28A , Figure 28B , Figure 28C , Figure 28D , Figure 29A , Figure 29B , Figure 29C , Figure 29D , Figure 30A , Figure 30B , Figure 30C , Figure 30D , Figure 31A , Figure 31B , Figure 31C , Figure 31D , Figure 32A , Figure 32B , Figure 32C , Figure 32D , Figure 33A , Figure 33B , Figure 33C , Figure 33D , Figure 34A , Figure 34B , Figure 34C , Figure 34D , Figure 35 , Figure 36A , Figure 36B , Figure 36C , Figure 37 , Figure 38A , Figure 38B , Figure 38C , Figure 38D , Figure 39 , Figure 40 , Figure 41A , Figure 41B , Figure 41C , Figure 42 , Figure 43A , Figure 43B and Figure 43C The channel pattern CH can have a side facing the information storage element 140. For example, the channel pattern CH can overlap with one side of the information storage element 140.

[0175] refer to Figure 45B The semiconductor device 100q may include a bit line 170 in contact with the channel pattern CH and an information storage element 140c adjacent to the channel pattern CH. The channel pattern CH may correspond to a first channel pattern 110, 110a, 110b or 110c, or a second channel pattern 120, 120a or 120b, as already referenced above. Figures 3 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 19C 、 Figure 19D 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 25D 、 Figure 26A 、 Figure 26B 、 Figure 26C 、 Figure 26D 、 Figure 27A 、 Figure 27B 、 Figure 27C 、 Figure 27D 、 Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 28D 、 Figure 29A 、 Figure 29B 、 Figure 29C 、 Figure 29D 、 Figure 30A 、 Figure 30B 、 Figure 30C 、 Figure 30D 、 Figure 31A 、 Figure 31B 、 Figure 31C 、 Figure 31D 、 Figure 32A 、 Figure 32B 、 Figure 32C 、 Figure 32D 、 Figure 33A 、 Figure 33B 、 Figure 33C 、 Figure 33D 、 Figure 34A 、 Figure 34B 、 Figure 34C 、 Figure 34D 、 Figure 35 、 Figure 36A 、 Figure 36B 、 Figure 36C 、 Figure 37 、 Figure 38A 、 Figure 38B 、 Figure 38C 、 Figure 38D 、 Figure 39 , Figure 40 , Figure 41A , Figure 41B , Figure 41C , Figure 42 , Figure 43A , Figure 43B and Figure 43C The channel pattern CH has been described. It can have multiple sides facing the information storage element 140c. For example, the channel pattern CH can overlap with three sides of the information storage element 140c. When the channel pattern CH corresponds to the above reference... Figures 3 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 25D 、 Figure 26A 、 Figure 26B 、 Figure 26C 、 Figure 26D 、 Figure 27A 、 Figure 27B 、 Figure 27C 、 Figure 27D 、 Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 28D 、 Figure 29A 、 Figure 29B 、 Figure 29C 、 Figure 29D 、 Figure 30A 、 Figure 30B 、 Figure 30C 、 Figure 30D 、 Figure 31A 、 Figure 31B 、 Figure 31C 、 Figure 31D 、 Figure 32A 、 Figure 32B 、 Figure 32C 、 Figure 32D 、 Figure 33A 、 Figure 33B 、 Figure 33C 、 Figure 33D 、 Figure 34A 、 Figure 34B 、 Figure 34C 、 Figure 34D 、 Figure 35 、 Figure 36A 、 Figure 36B 、 Figure 36C 、 Figure 37 、 Figure 38A 、 Figure 38B 、 Figure 38C 、 Figure 38D 、 Figure 39 、 Figure 40 、 Figure 41A , Figure 41B , Figure 41C , Figure 42 , Figure 43A , Figure 43B and Figure 43C When the first channel pattern 110, 110a, 110b, or 110c is described, the information storage element 140c may be spaced apart from the channel pattern CH. When the channel pattern CH corresponds to the above reference... Figures 3 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B , Figure 20C , Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 25D 、 Figure 26A 、 Figure 26B 、 Figure 26C 、 Figure 26D 、 Figure 27A 、 Figure 27B 、 Figure 27C 、 Figure 27D 、 Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 28D 、 Figure 29A 、 Figure 29B 、 Figure 29C 、 Figure 29D 、 Figure 30A 、 Figure 30B 、 Figure 30C 、 Figure 30D 、 Figure 31A 、 Figure 31B 、 Figure 31C 、 Figure 31D 、 Figure 32A 、 Figure 32B 、 Figure 32C 、 Figure 32D 、 Figure 33A 、 Figure 33B 、 Figure 33C 、 Figure 33D 、 Figure 34A 、 Figure 34B 、 Figure 34C 、 Figure 34D 、 Figure 35 、 Figure 36A 、 Figure 36B 、 Figure 36C 、 Figure 37 、 Figure 38A 、 Figure 38B 、 Figure 38C 、 Figure 38D 、 Figure 39 、 Figure 40 、 Figure 41A 、 Figure 41B 、 Figure 41C 、 Figure 42 , Figure 43A , Figure 43B and Figure 43C When the second channel pattern 120, 120a, or 120b is described, the information storage element 140c may contact the channel pattern CH. The information storage element 140c may include a portion adjacent to the top surface of the channel pattern CH, a portion adjacent to the side surface of the channel pattern CH, and a portion adjacent to the opposite side surface of the channel pattern CH. The thickness of the portion of the information storage element 140c adjacent to the top surface of the channel pattern CH may be less than the thickness of each of the portions of the information storage element 140c adjacent to the respective opposite side surfaces of the channel pattern CH.

[0176] refer to Figure 45C The semiconductor device 100r may include a bit line 170 in contact with the channel pattern CH and an information storage element 140d adjacent to the channel pattern CH. The channel pattern CH may correspond to a first channel pattern 110, 110a, 110b or 110c, or a second channel pattern 120, 120a or 120b, as already referenced above. Figures 3 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B、 Figure 16C 、 Figure 16D 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 17D 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 19D 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 25D 、 Figure 26A 、 Figure 26B 、 Figure 26C 、 Figure 26D 、 Figure 27A 、 Figure 27B 、 Figure 27C 、 Figure 27D 、 Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 28D 、 Figure 29A 、 Figure 29B 、 Figure 29C 、 Figure 29D 、 Figure 30A 、 Figure 30B 、 Figure 30C 、 Figure 30D 、 Figure 31A 、 Figure 31B 、 Figure 31C 、 Figure 31D 、 Figure 32A 、 Figure 32B 、 Figure 32C 、 Figure 32D 、 Figure 33A 、 Figure 33B 、 Figure 33C 、 Figure 33D 、 Figure 34A 、 Figure 34B , Figure 34C , Figure 34D , Figure 35 , Figure 36A , Figure 36B , Figure 36C , Figure 37 , Figure 38A , Figure 38B , Figure 38C , Figure 38D , Figure 39 , Figure 40 , Figure 41A , Figure 41B , Figure 41C , Figure 42 , Figure 43A , Figure 43B and Figure 43C The channel pattern CH has been described. It can have multiple sides facing the information storage element 140d. For example, the channel pattern CH can surround the information storage element 140d and can overlap with four sides of the information storage element 140d. When the channel pattern CH corresponds to the above reference... Figures 3 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C、 Figure 16D 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 17D 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 19D 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 25D 、 Figure 26A 、 Figure 26B 、 Figure 26C 、 Figure 26D 、 Figure 27A 、 Figure 27B 、 Figure 27C 、 Figure 27D 、 Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 28D 、 Figure 29A 、 Figure 29B 、 Figure 29C 、 Figure 29D 、 Figure 30A 、 Figure 30B 、 Figure 30C 、 Figure 30D 、 Figure 31A 、 Figure 31B 、 Figure 31C 、 Figure 31D 、 Figure 32A 、 Figure 32B 、 Figure 32C 、 Figure 32D 、 Figure 33A 、 Figure 33B 、 Figure 33C 、 Figure 33D 、 Figure 34A 、 Figure 34B 、 Figure 34C , Figure 34D , Figure 35 , Figure 36A , Figure 36B , Figure 36C , Figure 37 , Figure 38A , Figure 38B , Figure 38C , Figure 38D , Figure 39 , Figure 40 , Figure 41A , Figure 41B , Figure 41C , Figure 42 , Figure 43A , Figure 43B and Figure 43C When the first channel pattern 110, 110a, 110b, or 110c is described, the information storage element 140d may be spaced apart from the channel pattern CH. When the channel pattern CH corresponds to the above reference... Figures 3 to 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C 、 Figure 17D 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 19D 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 25D 、 Figure 26A 、 Figure 26B 、 Figure 26C 、 Figure 26D 、 Figure 27A 、 Figure 27B 、 Figure 27C 、 Figure 27D 、 Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 28D 、 Figure 29A 、 Figure 29B 、 Figure 29C 、 Figure 29D 、 Figure 30A 、 Figure 30B 、 Figure 30C 、 Figure 30D 、 Figure 31A 、 Figure 31B 、 Figure 31C 、 Figure 31D 、 Figure 32A 、 Figure 32B 、 Figure 32C 、 Figure 32D 、 Figure 33A 、 Figure 33B 、 Figure 33C 、 Figure 33D 、 Figure 34A 、 Figure 34B 、 Figure 34C 、 Figure 34D 、 Figure 35 、 Figure 36A , Figure 36B , Figure 36C , Figure 37 , Figure 38A , Figure 38B , Figure 38C , Figure 38D , Figure 39 , Figure 40 , Figure 41A , Figure 41B , Figure 41C , Figure 42 , Figure 43A , Figure 43B and Figure 43C When the second channel pattern 120, 120a, or 120b is described, the information storage element 140d may contact the channel pattern CH. The information storage element 140d may include a portion adjacent to the top surface of the channel pattern CH, a portion adjacent to the bottom surface of the channel pattern CH, a portion adjacent to the side surface of the channel pattern CH, and a portion adjacent to the opposite side surface of the channel pattern CH. The thickness of each of the portions of the information storage element 140d adjacent to the top and bottom surfaces of the channel pattern CH may be less than the thickness of each of the portions of the information storage element 140d adjacent to the opposite side surface of the channel pattern CH.

[0177] Figure 46 A semiconductor device comprising a plurality of memory cells is shown according to one or more example embodiments.

[0178] refer to Figure 46 The semiconductor device 1000e may include multiple memory cells MC, each memory cell MC including a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180.

[0179] Word lines 160 may be adjacent to the first channel pattern 110 and the second channel pattern 120. Back gate lines 150 may be adjacent to the information storage element 140. In one or more example embodiments, back gate lines 150 may be closer to the first channel pattern 110 than to the second channel pattern 120. For example, back gate lines 150 may be arranged between two first channel patterns 110 included in two adjacent storage cells MC in the vertical direction (Z direction), spaced apart from the two first channel patterns 110. For example, two word lines 160 may be arranged on opposite sides of the back gate lines 150 in the vertical direction (Z direction), and the back gate line 150 and the other word line 160 may be arranged on opposite sides of one of the two word lines 160 in the vertical direction (Z direction).

[0180] Figure 47A semiconductor device comprising a plurality of memory cells is shown according to one or more example embodiments.

[0181] refer to Figure 47 The semiconductor device 1000f may include multiple memory cells MC, each memory cell MC including a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180.

[0182] Word lines 160 may be adjacent to first channel patterns 110 and second channel patterns 120. Back gate lines 150 may be adjacent to information storage elements 140. In one or more example embodiments, back gate lines 150 may be adjacent to either the first channel pattern 110 or the second channel pattern 120. For example, back gate lines 150 may be arranged between two first channel patterns 110 respectively included in two adjacent storage cells MC in the vertical direction (Z direction), spaced apart from the two first channel patterns 110; and arranged between two second channel patterns 120 respectively included in two adjacent storage cells MC in the vertical direction (Z direction), spaced apart from the two second channel patterns 120. For example, two word lines 160 may be arranged on opposite sides of back gate lines 150 in the vertical direction (Z direction), and back gate lines 150 may be arranged on opposite sides of one word line 160 in the vertical direction (Z direction).

[0183] Figure 48 A memory cell of a semiconductor device according to one or more example embodiments is shown.

[0184] refer to Figure 48 The semiconductor device 101 may include a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180 disposed on a substrate 102. The first channel pattern 110, the second channel pattern 120, the information storage element 140, the word line 160, the back gate line 150, the bit line 170, and the plate electrode 180 may form a memory cell MC. In one or more example embodiments, the plate electrode 180 may be disposed on the substrate 102, and the bit line 170 may be disposed above the plate electrode 180 to be spaced apart from the plate electrode 180 in the vertical direction (Z direction). The first channel pattern 110, the second channel pattern 120, the information storage element 140, the word line 160, and the back gate line 150 may be disposed between the bit line 170 and the plate electrode 180.

[0185] The first channel pattern 110 may extend in the vertical direction (Z direction). The first channel pattern 110 may contact the bit line 170 and the plate electrode 180. In the vertical direction (Z direction), one end of the first channel pattern 110 may contact the bit line 170, and the opposite end of the first channel pattern 110 may contact the plate electrode 180. In one or more example embodiments, the first channel pattern 110 may include a first channel region 112, a first silicide layer 114, and a second silicide layer 116. The first silicide layer 114 may contact the bit line 170, and the second silicide layer 116 may be spaced apart from the first silicide layer 114 in the vertical direction (Z direction) and may contact the plate electrode 180.

[0186] The second channel pattern 120 may extend in the vertical direction (Z direction). The second channel pattern 120 may be spaced apart from the first channel pattern 110 in the first horizontal direction (X direction). The second channel pattern 120 may contact the bit line 170 and the information storage element 140. In the vertical direction (Z direction), one end of the second channel pattern 120 may contact the bit line 170, and the opposite end of the second channel pattern 120 may contact the information storage element 140.

[0187] Information storage element 140 may contact and be electrically connected to the second channel pattern 120. For example, at least a portion of information storage element 140 may overlap with the second channel pattern 120 in a first horizontal direction (X direction). Information storage element 140 may be adjacent to the first channel pattern 110. For example, at least a portion of information storage element 140 may be adjacent to the first channel pattern 110 and may overlap with the first channel pattern 110 in the first horizontal direction (X direction). The width of information storage element 140 in the first horizontal direction (X direction) may be greater than the width of the second channel pattern 120 in the first horizontal direction (X direction). Information storage element 140 may be spaced apart from substrate 102 and plate electrode 180 in the vertical direction (Z direction).

[0188] The character line 160 may be adjacent to both the first channel pattern 110 and the second channel pattern 120. For example, at least a portion of the character line 160 may extend between the first channel pattern 110 and the second channel pattern 120 in a second horizontal direction (Y direction). At least a portion of the character line 160 may overlap with the first channel pattern 110 in a first horizontal direction (X direction), and at least a portion of the character line 160 may overlap with the second channel pattern 120 in the first horizontal direction (X direction).

[0189] Back gate line 150 may be adjacent to information storage element 140. Back gate line 150 may be adjacent to first channel pattern 110 and / or second channel pattern 120. In one or more example embodiments, back gate line 150 may be adjacent to second channel pattern 120. For example, back gate line 150 may be adjacent to and spaced apart from second channel pattern 120 in a first horizontal direction (X direction). For example, at least a portion of back gate line 150 may be adjacent to second channel pattern 120 and may extend in a second horizontal direction (Y direction). At least a portion of back gate line 150 may overlap with second channel pattern 120 in the first horizontal direction (X direction). In one or more example embodiments, at least a portion of back gate line 150 may overlap with information storage element 140 in the first horizontal direction (X direction), but one or more example embodiments are not limited thereto. For example, the back grid line 150 may be adjacent to the information storage element 140, but may not overlap with the information storage element 140 in the first horizontal direction (X direction).

[0190] Bit line 170 may extend in a first horizontal direction (X direction). Bit line 170 may contact and be electrically connected to the first channel pattern 110 and the second channel pattern 120. For example, bit line 170 may contact one end of the first channel pattern 110 and one end of the second channel pattern 120 in a vertical direction (Z direction).

[0191] The plate electrode 180 may contact the first channel pattern 110. The plate electrode 180 may contact the opposite end of the first channel pattern 110 in the vertical direction (Z direction). The plate electrode 180 may be spaced apart from the second channel pattern 120. For example, in one or more example embodiments, the plate electrode 180 may be electrically grounded.

[0192] The vertical direction (Z direction), the first horizontal direction (X direction), and the second horizontal direction (Y direction) can be referred to as the first direction, the second direction, and the third direction, respectively, and they are orthogonal to each other.

[0193] Figure 49A and Figure 49B These are conceptual perspective views of a semiconductor device comprising multiple memory cells according to one or more example embodiments.

[0194] refer to Figure 49A The semiconductor device 1010 may include a plurality of memory cells MC, each memory cell MC including a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180. The memory cells MC may be arranged in rows in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0195] Multiple first channel patterns 110 may extend in the vertical direction (Z direction) and may be spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction). Multiple second channel patterns 120 may extend in the vertical direction (Z direction) and may be spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction). Second channel patterns 120 may be spaced apart from first channel patterns 110 in the first horizontal direction (X direction). Second channel patterns 120 may contact bit lines 170 and information storage elements 140. Information storage elements 140 may contact and be electrically connected to second channel patterns 120. Information storage elements 140 may be adjacent to and spaced apart from first channel patterns 110.

[0196] The word line 160 may be adjacent to both the first channel pattern 110 and the second channel pattern 120. The word line 160 may be arranged in a first horizontal direction (X direction) between the first channel pattern 110 and the second channel pattern 120 included in a memory cell MC, so as to be spaced apart from the first channel pattern 110 and the second channel pattern 120 included in the memory cell MC.

[0197] The back gate line 150 may be adjacent to the information storage element 140. In one or more example embodiments, the back gate line 150 may be adjacent to the second channel pattern 120. For example, the back gate line 150 may be arranged adjacent to and spaced apart from the second channel pattern 120 in a first horizontal direction (X direction). For example, at least a portion of the back gate line 150 may be adjacent to the second channel pattern 120 and may extend in a second horizontal direction (Y direction).

[0198] Multiple bit lines 170 may extend in a first horizontal direction (X direction) and may be spaced apart from each other in a second horizontal direction (Y direction). Bit lines 170 may contact and be electrically connected to multiple first channel patterns 110 and multiple second channel patterns 120. For example, bit lines 170 may contact corresponding ends of first channel patterns 110 and second channel patterns 120 in a vertical direction (Z direction).

[0199] The plate electrode 180 may contact the first channel pattern 110. For example, the plate electrode 180 may contact a corresponding opposite end of the first channel pattern 110 in the vertical direction (Z direction). The plate electrode 180 may have a plate shape extending in a first horizontal direction (X direction) and a second horizontal direction (Y direction), and may contact the first channel patterns 110 arranged in rows in the first horizontal direction (X direction) and the second horizontal direction (Y direction). In one or more example embodiments, the plate electrode 180 may be electrically grounded.

[0200] refer to Figure 49BThe semiconductor device 1010a may include a plurality of plate electrodes 180S, each plate electrode 180S contacting a plurality of second channel patterns 120. The plate electrodes 180S may extend in a first horizontal direction (X direction) and may be arranged in a row in a second horizontal direction (Y direction). Each of the plate electrodes 180S may contact a plurality of first channel patterns 110 arranged in a row in the first horizontal direction (X direction). In one or more example embodiments, the plate electrodes 180S may be electrically grounded.

[0201] Figure 50A and Figure 50B Semiconductor devices comprising multiple memory cells according to one or more example embodiments are shown respectively.

[0202] refer to Figure 50A The semiconductor device 1010b may include memory cells MC stacked on a substrate 102 in a vertical direction (Z direction). Each memory cell MC may include a first channel pattern 110, a second channel pattern 120, an information storage element 140, a word line 160, a back gate line 150, a bit line 170, and a plate electrode 180. For example, a plurality of first channel patterns 110 may extend in the vertical direction (Z direction) and may be spaced apart from each other in the vertical direction (Z direction). A plurality of second channel patterns 120 may extend in the vertical direction (Z direction) and may be spaced apart from each other in the vertical direction (Z direction). A plurality of bit lines 170 and a plurality of plate electrodes 180 may extend in a first horizontal direction (X direction) and may be spaced apart from each other in the vertical direction (Z direction).

[0203] In one or more example embodiments, bit lines 170 and plate electrodes 180 may be arranged alternately in the vertical direction (Z direction). Each of the bit lines 170 may contact a plurality of first channel patterns 110 and a plurality of second channel patterns 120, and each of the plate electrodes 180 may contact a first channel pattern 110. The first channel pattern 110, the second channel pattern 120, the information storage element 140, the word line 160, and the back gate line 150 may be arranged between a plate electrode 180 and a bit line 170 above that plate electrode 180. The first channel pattern 110, the second channel pattern 120, the information storage element 140, the word line 160, and the back gate line 150 may not be arranged between a bit line 170 and a plate electrode 180 above that bit line 170.

[0204] refer to Figure 50BThe semiconductor device 1010c may include memory cells MC stacked on a substrate 102 in the vertical direction (Z direction). Bit lines 170 and plate electrodes 180 may be arranged alternately in the vertical direction (Z direction). Memory cells MC that are adjacent to each other in the vertical direction (Z direction) may share bit lines 170 and plate electrodes 180.

[0205] The first channel pattern 110, the second channel pattern 120, the information storage element 140, the word line 160, and the back gate line 150 can be arranged between a plate electrode 180 and a bit line 170 above the plate electrode 180. The first channel pattern 110, the second channel pattern 120, the information storage element 140, the word line 160, and the back gate line 150 can be arranged between a bit line 170 and a plate electrode 180 above the bit line 170.

[0206] Memory cells MC adjacent to each other in the vertical direction (Z direction) can be arranged in a mirror-symmetric manner with respect to bit line 170. Memory cells MC adjacent to each other in the vertical direction (Z direction) can be arranged in a mirror-symmetric manner with respect to plate electrode 180. The top and bottom surfaces of bit line 170 can contact the first channel pattern 110 and the second channel pattern 120. The top and bottom surfaces of plate electrode 180 can contact the first channel pattern 110.

[0207] While exemplary embodiments have been specifically shown and described, it will be apparent to those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor device, comprising: The first channel pattern extends in the first direction; The second channel pattern is adjacent to the first channel pattern and extends in the first direction; Bit lines connect the first end of the first channel pattern and the first end of the second channel pattern and extend in a second direction orthogonal to the first direction; An information storage element is connected to a second end of the second channel pattern, the second end of the second channel pattern being opposite to the first end of the second channel pattern in the first direction; The character line is located between the first channel pattern and the second channel pattern and is adjacent to the information storage element in the first direction; as well as The back gate line is adjacent to at least one of the first channel pattern and the second channel pattern.

2. The semiconductor device according to claim 1, wherein, The word lines and the information storage element are spaced apart by a first separation distance in the first direction, and The back gate line and the information storage element are spaced apart by a second separation distance in the second direction, and the second separation distance is less than the first separation distance.

3. The semiconductor device according to claim 1, wherein, The word line and the bit line are spaced apart by a third separation distance in the first direction, and Wherein, the back gate line and the bit line are spaced apart by a fourth separation distance in the first direction, and the fourth separation distance is greater than the third separation distance.

4. The semiconductor device according to claim 1, wherein, The first channel pattern and the second channel pattern are spaced apart in the second direction.

5. The semiconductor device according to claim 1, wherein, Each of the word lines and the back gate lines extends upward in a third direction orthogonal to the first direction and the second direction.

6. The semiconductor device according to claim 1, further comprising: A plate electrode, spaced apart from the bit line in the first direction, is connected to a second end of the first channel pattern, wherein the second end of the first channel pattern is opposite to the first end of the first channel pattern in the first direction.

7. The semiconductor device according to claim 6, wherein, The plate electrode is spaced apart from the second channel pattern in the first direction and from the information storage element in the first direction.

8. The semiconductor device according to claim 1, wherein, The back grid lines are closer to the second channel pattern than to the first channel pattern.

9. The semiconductor device according to claim 1, wherein, The back grid lines are closer to the first groove pattern than to the second groove pattern.

10. The semiconductor device according to claim 1, further comprising: A first gate dielectric layer is located between the first channel pattern and the information storage element; A second gate dielectric layer is located between the second channel pattern and the back gate line; as well as A third gate dielectric layer is disposed between the first channel pattern and the word line, and between the second channel pattern and the word line.

11. A semiconductor device, comprising: Substrate; A first channel pattern extends on the substrate along a first direction; The second channel pattern extends along the first direction on the substrate and is spaced apart from the first channel pattern in a second direction orthogonal to the first direction; Bit lines are connected to the first end of the first channel pattern and the first end of the second channel pattern, and extend in the second direction; An information storage element is connected to a second end of the second channel pattern, the second end of the second channel pattern being opposite to the first end of the second channel pattern in the first direction; Each of the word lines is between a first channel pattern and a second channel pattern that are adjacent to each other in the second direction, each of the word lines is adjacent to one of the information storage elements in the first direction, and each of the word lines extends upward in a third direction orthogonal to the first direction and the second direction; as well as The back grid line is adjacent to the information storage element and extends upward from the third party.

12. The semiconductor device according to claim 11, wherein, Each of the word lines is spaced apart from an adjacent information storage element by a first separation distance in the first direction, and Each of the back grid lines is spaced apart from an adjacent information storage element by a second separation distance in the second direction, and the second separation distance is less than the first separation distance.

13. The semiconductor device according to claim 12, wherein, Each of the back grid lines at least partially overlaps with an adjacent information storage element in the second direction and is spaced apart from each other by the second separation distance in the second direction.

14. The semiconductor device of claim 11, further comprising: At least one plate electrode is spaced apart from the bit line, spaced apart from the second channel pattern, spaced apart from the information storage element, and connected to a second end of the first channel pattern, wherein the second end of the first channel pattern is opposite to the first end of the first channel pattern in the first direction.

15. The semiconductor device according to claim 11, wherein, The first channel pattern is arranged in rows in the second direction and in rows in the third direction. Wherein, the second channel pattern is arranged in rows in the second direction and in rows in the third direction, and The bit lines are arranged in a row on the third direction.

16. The semiconductor device according to claim 15, wherein, Two second channel patterns adjacent to each other in the second direction are located between two first channel patterns adjacent to each other in the second direction, and Each of the back gate lines is located between two second channel patterns that are adjacent to each other in the second direction.

17. A semiconductor device, comprising: Substrate; The first channel pattern extends along a first horizontal direction on the substrate; The second channel pattern extends along the first horizontal direction on the substrate and is spaced apart from the first channel pattern in the vertical direction. The bit line connects to the first end of the first channel pattern and the first end of the second channel pattern, and extends in the vertical direction; An information storage element is connected to the second end of the second channel pattern, the second end of the second channel pattern being opposite to the first end of the second channel pattern in the first horizontal direction; Each of the word lines is between a first groove pattern and a second groove pattern that are adjacent to each other in the vertical direction, each of the word lines is adjacent to one of the information storage elements in the first horizontal direction, and each of the word lines extends in a second horizontal direction orthogonal to the first horizontal direction; The back gate line is adjacent to the second channel pattern and the information storage element, and extends in the second horizontal direction; A first gate dielectric layer is located between the first channel pattern and the information storage element; A second gate dielectric layer is located between the second channel pattern and the back gate line; as well as A third gate dielectric layer is located between the first channel pattern and the word line, and also between the second channel pattern and the word line. Wherein, each of the word lines is spaced apart from an adjacent information storage element by a first separation distance in the first horizontal direction, and Each of the back grid lines is separated from an adjacent information storage element by a second separation distance in the vertical direction, and the second separation distance is less than the first separation distance.

18. The semiconductor device according to claim 17, wherein, Each of the word lines is separated from its adjacent bit line by a third separation distance in the first horizontal direction, and Each of the back gate lines is separated from an adjacent bit line by a fourth separation distance in the first horizontal direction, and the fourth separation distance is greater than the third separation distance.

19. The semiconductor device according to claim 17, wherein, Each of the first channel patterns comprises a single-crystal semiconductor material. Each of the second channel patterns comprises an oxide semiconductor material, and Each of the information storage elements comprises an oxide semiconductor material.

20. The semiconductor device according to claim 17, wherein, The first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer comprise the same material.

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