Semiconductor structure and method of manufacturing the same
Patent Information
- Application Number
- CN202611255770.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-18
- Publication Date
- 2026-10-30
AI Technical Summary
[0004]基于此，有必要针对现有技术中的导电插塞与要电学引出的字线结构存在接触不良，从而影响半导体结构的电学性能问题提供一种半导体结构及其制备方法
[0018]提供衬底；
Smart Images
Figure CN123021653A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] In existing semiconductor structures, after the word line structure is formed, conductive plugs need to be formed to realize the electrical lead-out of the word line structure.
[0003] However, due to limitations of existing processes, insufficient etching may occur when forming conductive vias for conductive plugs using existing processes. This can lead to poor contact between the formed conductive plugs and the word lines that need to be electrically led out, thereby affecting the electrical performance of the semiconductor structure. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem of poor contact between the conductive plug and the word line structure to be electrically led out in the prior art, which affects the electrical performance of the semiconductor structure.
[0005] To achieve the above objectives, in a first aspect, this application provides a semiconductor structure, comprising:
[0006] Substrate;
[0007] The word line structure is located on the substrate and includes first word lines and second word lines arranged at intervals.
[0008] The connecting pad is located at the bottom of the letter line structure, spanning the first and second letter lines, and in contact with the bottom surfaces of the first and second letter lines.
[0009] In the semiconductor structure of this application, by providing a connecting pad that spans across the first word line and the second word line and contacts the bottom surfaces of the first word line and the second word line, the bottoms of adjacent first word lines and second word lines that need to be electrically led out together can be connected through the connecting pad. When forming the conductive plug, as long as the conductive plug is connected to at least one of the three—the connecting pad, the first word line, and the second word line—the electrical lead-out of adjacent first word lines and second word lines that need to be electrically led out together can be achieved. This can effectively improve the problem of poor contact between the conductive plug and the word line structure that needs to be electrically led out, thereby ensuring the electrical performance of the semiconductor structure.
[0010] In one embodiment, the semiconductor structure further includes a plurality of alternating active pillars and isolation pillars; the first word line and the second word line are located on opposite sides of the active pillars and isolation pillars.
[0011] In one embodiment, the semiconductor structure further includes a bit line structure located between the active pillar and the substrate.
[0012] In one embodiment, the semiconductor structure further includes a conductive plug located between the first word line and the second word line.
[0013] In one embodiment, the conductive plug is in direct contact with the adjacent first word line or second word line.
[0014] In one embodiment, the bottom surface of the conductive plug is higher than the bottom surface of the first letter.
[0015] In one embodiment, the bottom surface of the conductive plug is in direct contact with the top surface of the connecting pad.
[0016] In one embodiment, the word line structure further includes a gate dielectric layer located between the first word line and the active post, and between the second word line and the active post, isolating the active post from the first word line and the second word line.
[0017] Secondly, this application also provides a method for fabricating a semiconductor structure, the method comprising:
[0018] Provide substrate;
[0019] A bonding pad is formed on the substrate;
[0020] A word line structure is formed on a substrate, the word line structure including a first word line and a second word line arranged at intervals; a connecting pad is located at the bottom of the word line structure, spanning the first word line and the second word line, and in contact with the bottom surfaces of the first word line and the second word line.
[0021] In the semiconductor structure fabrication method of this application, by forming a connecting pad that spans the first word line and the second word line and contacts the bottom surfaces of the first word line and the second word line, the bottoms of adjacent first word lines and second word lines that need to be electrically led out together can be connected through the connecting pad. When forming the conductive plug, as long as the conductive plug is connected to at least one of the connecting pad, the first word line and the second word line, the electrical lead-out of adjacent first word lines and second word lines that need to be electrically led out together can be achieved. This can effectively improve the problem of poor contact between the conductive plug and the word line structure that needs to be electrically led out, thereby ensuring the electrical performance of the semiconductor structure.
[0022] In one embodiment, prior to forming the bonding pad on the substrate, the method further includes:
[0023] Multiple alternating active pillars and isolation pillars are formed on the substrate; the first word line and the second word line are located on opposite sides of the active pillars and isolation pillars.
[0024] In one embodiment, before forming a plurality of alternating active pillars and isolation pillars on the substrate, the method further includes: forming a bit line structure on the substrate; after forming the active pillars and isolation pillars, the bit line structure is located between the active pillars and the substrate.
[0025] In one embodiment, after forming the word line structure on the substrate, the method further includes forming a conductive plug on the substrate, the conductive plug being located between the first word line and the second word line.
[0026] In one embodiment, the word line structure formed on the substrate further includes a gate dielectric layer located between the first word line and the active pillar, and between the active pillar and the second word line, isolating the active pillar from the first word line and the second word line. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;
[0029] Figure 2 This is a top view schematic diagram of the structure obtained after forming the active region in the semiconductor structure fabrication method provided in one embodiment;
[0030] Figure 3 This is a schematic cross-sectional view of the structure obtained after forming the active region in a semiconductor structure fabrication method provided in one embodiment; wherein, Figure 3 (a) in the middle is along Figure 2 A schematic diagram of the cross-sectional structure in the X direction. Figure 3 Figure (b) shows the route along Figure 2 A schematic diagram of the cross-sectional structure in the Y direction;
[0031] Figure 4 This is a top view of the structure obtained after forming a contact hole in a semiconductor structure fabrication method provided in one embodiment.
[0032] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming a contact hole in a semiconductor structure fabrication method provided in one embodiment; wherein, Figure 5 (a) in the middle is along Figure 4 A schematic diagram of the cross-sectional structure in the X direction. Figure 5 Figure (b) shows the route along Figure 4 A schematic diagram of the cross-sectional structure in the Y direction;
[0033] Figure 6This is a top view schematic diagram of the structure obtained after forming a connection pad material layer in a semiconductor structure fabrication method provided in one embodiment;
[0034] Figure 7 This is a schematic cross-sectional view of the structure obtained after forming a bonding pad material layer in a semiconductor structure fabrication method provided in one embodiment; wherein, Figure 7 (a) in the middle is along Figure 6 A schematic diagram of the cross-sectional structure in the X direction. Figure 7 Figure (b) shows the route along Figure 6 A schematic diagram of the cross-sectional structure in the Y direction;
[0035] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming a filled dielectric layer in a semiconductor structure fabrication method provided in one embodiment; wherein, Figure 8 (a) in the middle is along Figure 6 A schematic diagram of the cross-sectional structure in the X direction. Figure 8 Figure (b) shows the route along Figure 6 A schematic diagram of the cross-sectional structure in the Y direction;
[0036] Figure 9 This is a top view schematic diagram of the structure obtained after forming a separation groove in a semiconductor structure fabrication method provided in one embodiment;
[0037] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming a separation trench in a semiconductor structure fabrication method provided in one embodiment; wherein, Figure 10 (a) in the middle is along Figure 9 A schematic diagram of the cross-sectional structure in the X direction. Figure 10 Figure (b) shows the route along Figure 9 A schematic diagram of the cross-sectional structure in the Y direction;
[0038] Figure 11 This is a top view of the structure obtained after forming a bottom filling layer in a semiconductor structure fabrication method provided in one embodiment.
[0039] Figure 12 This is a schematic cross-sectional view of the structure obtained after forming a bottom filling layer in a semiconductor structure fabrication method provided in one embodiment; wherein, Figure 12 (a) in the middle is along Figure 11 A schematic diagram of the cross-sectional structure in the X direction. Figure 12 Figure (b) shows the route along Figure 11 A schematic diagram of the cross-sectional structure in the Y direction;
[0040] Figure 13 This is a top view of the structure obtained after forming a word line structure in a semiconductor structure fabrication method provided in one embodiment.
[0041] Figure 14 This is a schematic cross-sectional view of the structure obtained after forming a word line structure in a semiconductor structure fabrication method provided in one embodiment; wherein, Figure 14 (a) in the middle is along Figure 13 A schematic diagram of the cross-sectional structure in the X direction. Figure 14 Figure (b) shows the route along Figure 13 A schematic diagram of the cross-sectional structure in the Y direction;
[0042] Figure 15 This is a top view schematic diagram of the structure obtained after forming a sidewall material layer in a semiconductor structure fabrication method provided in one embodiment;
[0043] Figure 16 This is a schematic cross-sectional view of the structure obtained after forming a sidewall material layer in a semiconductor structure fabrication method provided in one embodiment; wherein, Figure 16 (a) in the middle is along Figure 15 A schematic diagram of the cross-sectional structure in the X direction. Figure 16 Figure (b) shows the route along Figure 15 A schematic diagram of the cross-sectional structure in the Y direction;
[0044] Figure 17 This is a top view of the structure obtained after forming a partition layer in a semiconductor structure fabrication method provided in one embodiment.
[0045] Figure 18 This is a schematic cross-sectional view of the structure obtained after forming a barrier layer in a semiconductor structure fabrication method provided in one embodiment; wherein, Figure 18 (a) in the middle is along Figure 17 A schematic diagram of the cross-sectional structure in the X direction. Figure 18 Figure (b) shows the route along Figure 17 A schematic diagram of the cross-sectional structure in the Y direction;
[0046] Figure 19 This is a top view schematic diagram of the structure obtained after forming a conductive plug in a semiconductor structure fabrication method provided in one embodiment;
[0047] Figure 20 This is a schematic cross-sectional view of the structure obtained after forming a conductive plug in a semiconductor structure fabrication method provided in one embodiment; wherein... Figure 20 (a) in the middle is along Figure 19 A schematic diagram of the cross-sectional structure in the X direction. Figure 20 Figure (b) shows the route along Figure 19 A schematic diagram of the cross-sectional structure in the Z direction;
[0048] Figure 21This is a schematic cross-sectional view of a semiconductor structure forming different types of conductive plugs in a semiconductor structure fabrication method provided in one embodiment.
[0049] Explanation of reference numerals in the attached figures:
[0050] 10. Substrate; 11. First dielectric layer; 12. Second dielectric layer; 121. Isolation pillar; 13. Third dielectric layer; 14. Fourth dielectric layer; 15. Bit line structure; 151. First metal barrier layer; 152. Bit line conductive layer; 153. Second metal barrier layer; 16. Active region; 161. Active pillar; 17. Contact hole; 18. Connecting pad; 181. Connecting pad material layer; 19. Filling dielectric layer; 20. Patterned hard mask layer; 201. First patterned hard mask layer; 202. Second patterned hard mask layer; 21. Separation trench; 22. Bottom filling dielectric layer; 23. Word line structure; 231. First word line; 232. Second word line; 233. Gate dielectric layer; 24. Sidewall material layer; 25. Partition layer; 26. Conductive plug; 261. Third metal barrier layer; 262. Plug conductive layer. Detailed Implementation
[0051] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0053] Please see Figure 1 This application also provides a method for preparing a semiconductor structure, which may include the following steps: S10~S30.
[0054] S10: Provides a substrate.
[0055] S20: Forming a bonding pad on the substrate.
[0056] S30: A word line structure is formed on a substrate. The word line structure includes a first word line and a second word line arranged at intervals. A connecting pad is located at the bottom of the word line structure, spans the first word line and the second word line, and is in contact with the bottom surfaces of the first word line and the second word line.
[0057] In the semiconductor structure fabrication method of this application, by forming a connecting pad that spans the first word line and the second word line and contacts the bottom surfaces of the first word line and the second word line, the bottoms of adjacent first word lines and second word lines that need to be electrically led out together can be connected through the connecting pad. When forming the conductive plug, as long as the conductive plug is connected to at least one of the connecting pad, the first word line, and the second word line, the electrical lead-out of adjacent first word lines and second word lines that need to be electrically led out together can be achieved. This can effectively improve the problem of poor contact between the conductive plug and the word line structure that needs to be electrically led out, thereby ensuring the electrical performance of the semiconductor structure. At the same time, it can expand the fabrication process window of the conductive plug.
[0058] In step S10, please combine Figure 2 The provided substrate 10 can be a semiconductor substrate, and the material of the semiconductor substrate can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator.
[0059] As an example, the substrate 10 provided in step S10 can be a substrate doped with certain impurity ions. In one example, the substrate 10 can be a substrate doped with P-type impurity ions, which may include at least one of boron ions, gallium ions, and indium ions. In another example, the substrate 10 can be a substrate doped with N-type impurity ions, which may include at least one of phosphorus ions, arsenic ions, and antimony ions. Device structures or other electrical connection structures may be pre-formed in the substrate 10.
[0060] As an example, in step S10, multiple isolation trenches are first formed in the substrate 10, and then a second dielectric layer 12 is formed in the isolation trenches to isolate multiple spaced active regions 16. The multiple spaced active regions 16 can be arranged in an array. Figure 2 The example uses an active region 16 extending along the X direction and multiple active regions 16 arranged at intervals along the Y direction.
[0061] As an example, a first dielectric layer 11 may be formed on one side of the substrate 10. The first dielectric layer 11 and the second dielectric layer 12 may both include an oxide layer, a nitride layer, or a oxynitride layer, etc. The first dielectric layer 11 may be formed using, but is not limited to, physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes.
[0062] As an example, substrate 10 may include a device region (not shown, i.e., the region where active region 16 is located) and a peripheral region (not shown), the peripheral region being located outside the device region. Figure 3 As shown in Figure (b), in addition to the second dielectric layer 12, the peripheral region may also include a third dielectric layer 13 and a fourth dielectric layer 14 stacked sequentially from the second dielectric layer 12. The third dielectric layer 13 and the fourth dielectric layer 14 may both be oxide layers, nitride layers, or oxynitride layers, etc., and the material of the third dielectric layer 13 may be different from the material of the fourth dielectric layer 14.
[0063] As an example, in step S10, after forming the first dielectric layer 11, the step further includes forming a bit line structure 15 on the substrate 10, such as... Figure 3 In Figure (a), the bit line structure 15 can be located on the side of the first dielectric layer 11 away from the substrate 10. Specifically, the bit line structure 15 may include a first metal barrier layer 151, a bit line conductive layer 152, and a second metal barrier layer 153 stacked sequentially from bottom to top. Both the first metal barrier layer 151 and the second metal barrier layer 153 may include, but are not limited to, nitride layers, such as titanium nitride (TiN) layers or tantalum nitride (TaN) layers, to prevent the metal of the bit line conductive layer 152 from diffusing into the first dielectric layer 11, the second dielectric layer 12, or the active region 16.
[0064] As an example, step S20 may include the following steps: S201~S203.
[0065] S201: A contact hole 17 is formed in the peripheral area. The contact hole 17 can be located on opposite sides of the device area along the Y direction, such as... Figure 4 and Figure 5 As shown. Specifically, the contact hole 17 can be formed using, but is not limited to, photolithography etching processes. The contact hole 17 can penetrate the fourth dielectric layer 14 along the thickness direction and expose the third dielectric layer 13. Figure 5 As shown in Figure (b).
[0066] S202: A connecting pad material layer 181 is formed inside the contact hole 17, such as Figure 6 and Figure 7 As shown. Specifically, a connecting pad material layer 181 can be formed first inside the contact hole 17 and on the surface of the structure obtained in step S10. Then, the connecting pad material layer 181 on the surface of the structure obtained in step S10 is removed, leaving only the connecting pad material layer 181 inside the contact hole 17. Specifically, the connecting pad material layer 181 can be formed using, but is not limited to, deposition or electroplating processes. The connecting pad material layer 181 can include a metal layer, such as a copper layer, a tungsten layer, or an aluminum layer. The top surface of the connecting pad material layer 181 can be flush with the top surface of the contact hole 17.
[0067] S203: Part of the connector pad material layer 181 is removed by etching back, exposing the connector pad material layer 181 within the contact hole 17, which is the connector pad 18. Figure 8As shown. Specifically, a dry etching process or a wet etching process can be used to etch back and remove part of the bonding pad material layer 181.
[0068] As an example, after step S203, a step of forming a filling dielectric layer 19 within the contact hole 17 may also be included, such as... Figure 8 As shown in Figure (b). Specifically, a filling medium layer 19 can be formed using a deposition process, but not limited to, an oxide layer, a nitride layer, or a oxynitride layer, etc.
[0069] As an example, after forming the filling dielectric layer 19, the following may also be included: forming a plurality of alternating active pillars 161 and isolation pillars 121 on the substrate 10. Specifically, the following steps may be included: forming a patterned hard mask layer 20 on the surface of the structure obtained after forming the filling dielectric layer 19. The patterned hard mask layer 20 may include a first patterned hard mask layer 201 and a second patterned hard mask layer 202. Openings are formed in the patterned hard mask layer 20, and the openings define the shape and position of the separation groove 21 to be formed subsequently, such as... Figure 9 and Figure 10 As shown. Based on the patterned hard mask layer 20, the active region 16 and the second dielectric layer 12 are etched using, but not limited to, dry etching processes to form multiple regions along the... Figure 9 Separation grooves 21 extending in the Y direction and spaced apart along the X direction isolate the active region 16 into multiple active pillars 161 arranged in a multi-row, multi-column array, and isolate the second dielectric layer 12 into multiple isolation pillars 121 arranged in a multi-row, multi-column array. The isolation pillars 121 and the active pillars 161 can be arranged alternately along the Y direction, such as... Figure 9 and Figure 10 As shown.
[0070] It should be noted that the separation tank 21 is along the... Figure 9 The Y-direction of the connector penetrates the device region and extends to the peripheral region, extending to the side of the connection pad 18 away from the active post 161, as shown in the image. Figure 9 and Figure 10 As shown.
[0071] As an example, after forming a plurality of alternating active pillars 161 and isolation pillars 121 on the substrate 10, the following may also be included: forming a bottom-filled dielectric layer 22 at the bottom of the separation trench 21, such as... Figure 11 and Figure 12As shown. Specifically, a bottom filling medium material layer (not shown) can be formed first by a deposition process, but not limited to this one. Then, part of the bottom filling medium material layer is removed by etching back. The bottom filling medium material layer remaining at the bottom of the separation tank 21 is the bottom filling medium layer 22. The top surface of the bottom filling medium layer 22 is lower than the top surface of the separation tank 21 and can also be lower than the top surface of the connecting pad 18.
[0072] As an example, after the active pillar 161 and the isolation pillar 121 are formed, the bit line structure 15 is located between the active pillar 161 and the substrate 10.
[0073] As an example, the first word line 231 and the second word line 232 formed in step S30 are located on opposite sides of the active post 161 and the isolation post 121.
[0074] For example, please refer to Figure 13 and Figure 14 The word line structure 23 formed on the substrate 10 may also include a gate dielectric layer 233, which is located between the first word line 231 and the active pillar 161, and between the second word line 232 and the active pillar 161. The gate dielectric layer 233 is used to isolate the active pillar 161 from the first word line 231 and the second word line 232.
[0075] Specifically, a gate dielectric layer 233 can be formed first on the sidewall of the separation tank 21, and then a first word line 231 or a second word line 232 can be formed on the surface of the gate dielectric layer 233 away from the sidewall of the separation tank 21, such as... Figure 13 and Figure 14 As shown. The gate dielectric layer 233 may include, but is not limited to, an oxide layer, and the materials of the first word line 231 and the second word line 232 may include conductive materials, such as metallic materials or doped semiconductor materials, etc.
[0076] As an example, after forming the letter line structure 23, it may also include the following: forming a sidewall material layer 24 within the separation groove 21, such as... Figure 15 and Figure 16 As shown. Specifically, the sidewall material layer 24 can be formed using, but is not limited to, physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes. The sidewall material layer 24 fills the separation tank 21 and covers the upper surfaces of the first dielectric layer 11, the word line structure 23, the active pillar 161, and the isolation pillar 121. The sidewall material layer 24 covering the upper surfaces of the first dielectric layer 11, the word line structure 23, the active pillar 161, and the isolation pillar 121 is then removed, leaving only the sidewall material layer 24 located within the separation tank 21. The sidewall material layer 24 may include, but is not limited to, oxide layers, nitride layers, or oxynitride layers, etc.
[0077] As an example, such as Figure 13 and Figure 15As shown, since the first letter 231 and the second letter 232, which are formed in the same separation groove 21, are connected at the end sidewall of the separation groove 21, in order to disconnect the connection between the two, a step of forming a partition layer 25 at both ends of the separation groove 21 is also included, such as... Figure 17 and Figure 18 As shown. Specifically, a photolithography etching process can be used to form a partition trench (not shown). The partition trench is formed within the same separation trench 21, specifically the first word line 231 and the second word line 232. Then, a dielectric layer is filled into the partition trench as a partition layer 25. The dielectric layer can include, but is not limited to, oxide layers, nitride layers, or oxide oxynitride layers, etc.
[0078] As an example, after forming the word line structure 23 on the substrate 10, specifically after forming the partition layer 25, the method further includes: forming a conductive plug 26 on the substrate 10, the conductive plug 26 being located between the first word line 231 and the second word line 232, such as... Figure 19 and Figure 20 As shown.
[0079] As an example, conductive plug 26 is used to connect along Figure 19 The first word line 231 and the second word line 232 on opposite sides of the same column of active pillars 161 in the Y direction are electrically led out. The conductive plug 26 may include a plug conductive layer 262 and a third metal barrier layer 261 located on the sidewall and bottom of the plug conductive layer 262; the plug conductive layer 262 may include a metal layer, and the third metal barrier layer 261 may include, but is not limited to, a nitride layer, such as a titanium nitride layer or a tantalum nitride layer.
[0080] As an example, the conductive plug 26 can directly contact the first word line 231 or the second word line 232, such as Figure 21 As shown, Figure 21 The first, second, and fourth conductive plugs 26 from left to right are examples of direct contact with at least one of the first word line 231 and the second word line 232.
[0081] As an example, the bottom surface of the conductive plug 26 is higher than the bottom surface of the first letter line 231, such as... Figure 21 The leftmost conductive plug 26 is in contact with both the first word line 231 and the second word line 232, so it does not affect the electrical lead-out of the two together.
[0082] As an example, the bottom surface of the conductive plug 26 is in direct contact with the top surface of the connecting pad 18, such as Figure 21 The second to fourth connecting pads 18 from left to right. At this time, since the top surface of the connecting pad 18 is in contact with the bottom surface of the first letter 231 and the second letter 232, the conductive plug 26 can electrically lead out both of them regardless of whether it is in direct contact with the first letter 231 or the second letter 232.
[0083] In another embodiment, please refer to Figures 2 to 18 Continue reading Figures 19 to 21 This application also provides a semiconductor structure, which may include: a substrate 10; a word line structure 23 located on the substrate 10, including a first word line 231 and a second word line 232 arranged at intervals; and a connecting pad 18 located at the bottom of the word line structure 23, spanning the first word line 231 and the second word line 232, and in contact with the bottom surfaces of the first word line 231 and the second word line 232.
[0084] In the semiconductor structure of this application, by providing a connecting pad 18 that spans across the first word line 231 and the second word line 232 and contacts the bottom surfaces of the first word line 231 and the second word line 232, the bottom surfaces of adjacent first word lines 231 and the second word line 232 that need to be electrically led out together can be connected through the connecting pad 18. When forming the conductive plug, as long as the conductive plug is connected to at least one of the three—the connecting pad 18, the first word line 231, and the second word line 232—the electrical lead-out of adjacent first word lines 231 and the second word line 232 that need to be electrically led out together can be achieved. This can effectively improve the problem of poor contact between the conductive plug and the word line structure that needs to be electrically led out, thereby ensuring the electrical performance of the semiconductor structure.
[0085] As an example, substrate 10 may be a semiconductor substrate, and the material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), or other III / V or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate may be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator.
[0086] As an example, substrate 10 can be a substrate doped with certain impurity ions. In one example, substrate 10 can be a substrate doped with P-type impurity ions, which may include at least one of boron ions, gallium ions, and indium ions. In another example, substrate 10 can be a substrate doped with N-type impurity ions, which may include at least one of phosphorus ions, arsenic ions, and antimony ions. Device structures or other electrical connection structures may be pre-formed in substrate 10.
[0087] As an example, a first dielectric layer 11 may be formed on one side of the substrate 10, and both the first dielectric layer 11 and the second dielectric layer 12 may include an oxide layer, a nitride layer, or a oxynitride layer, etc.
[0088] As an example, substrate 10 may include a device region (not shown, i.e., the region where active region 16 is located) and a peripheral region (not shown), the peripheral region being located outside the device region. Figure 3 As shown in Figure (b), in addition to the second dielectric layer 12, the peripheral region may also include a third dielectric layer 13 and a fourth dielectric layer 14 stacked sequentially from the second dielectric layer 12. The third dielectric layer 13 and the fourth dielectric layer 14 may both be oxide layers, nitride layers, or oxynitride layers, etc., and the material of the third dielectric layer 13 may be different from the material of the fourth dielectric layer 14.
[0089] As an example, the semiconductor structure also includes a plurality of alternating active pillars 161 and isolation pillars 121; the first word line 231 and the second word line 232 are located on opposite sides of the active pillars 161 and the isolation pillars 121.
[0090] As an example, the semiconductor structure also includes a bit line structure 15, which is located between the active pillar 161 and the substrate 10. Specifically, the bit line structure 15 may include a first metal barrier layer 151, a bit line conductive layer 152, and a second metal barrier layer 153 stacked sequentially from bottom to top. Both the first metal barrier layer 151 and the second metal barrier layer 153 may include, but are not limited to, nitride layers (e.g., titanium nitride or tantalum nitride layers) to prevent the metal of the bit line conductive layer 152 from diffusing into the first dielectric layer 11, the second dielectric layer 12, or the active region 16.
[0091] As an example, the semiconductor structure may also include a sidewall material layer 24, which may be located at least between the first word line 231 and the second word line 232 between two adjacent columns of active pillars 161. The sidewall material layer 24 may include, but is not limited to, oxide layers, nitride layers, or oxynitride layers, etc.
[0092] As an example, the semiconductor structure may also include a partition layer 25 located at opposite ends of the first word line 231 and the second word line 232 along the Y direction and extending along the X direction. The partition layer 25 is used to isolate the first word line 231 and the second word line 232 from each other, preventing electrical connection. The partition layer 25 may include, but is not limited to, oxide layers, nitride layers, or oxynitride layers, etc.
[0093] As an example, the semiconductor structure also includes a conductive plug 26 located between the first word line 231 and the second word line 232. The conductive plug 26 may include a plug conductive layer 262 and a third metal barrier layer 261 located on the sidewalls and bottom of the plug conductive layer 262; the plug conductive layer 262 may include a metal layer, and the third metal barrier layer 261 may include, but is not limited to, a nitride layer, such as a titanium nitride layer or a tantalum nitride layer.
[0094] As an example, the conductive plug 26 can directly contact the first word line 231 or the second word line 232, such as Figure 21 As shown, Figure 21 The first, second, and fourth conductive plugs 26 from left to right are examples of direct contact with at least one of the first word line 231 and the second word line 232.
[0095] As an example, the bottom surface of the conductive plug 26 is higher than the bottom surface of the first letter line 231, such as... Figure 21 The leftmost conductive plug 26 is in contact with both the first word line 231 and the second word line 232, so it does not affect the electrical lead-out of the two together.
[0096] As an example, the bottom surface of the conductive plug 26 is in direct contact with the top surface of the connecting pad 18, such as Figure 21 The second to fourth connecting pads 18 from left to right. At this time, since the top surface of the connecting pad 18 is in contact with the bottom surface of the first letter 231 and the second letter 232, the conductive plug 26 can electrically lead out both of them regardless of whether it is in direct contact with the first letter 231 or the second letter 232.
[0097] As an example, the word line structure may also include a gate dielectric layer 233, which is located between the first word line 231 and the active post 161, and between the second word line 232 and the active post 161, isolating the active post 161 from the first word line 231 and the second word line 232.
[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0099] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; A word line structure, located on the substrate, includes a first word line and a second word line arranged at intervals; A connecting pad is located at the bottom of the word line structure, spanning the first word line and the second word line, and in contact with the bottom surfaces of the first word line and the second word line.
2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes a plurality of alternating active pillars and isolation pillars; the first word line and the second word line are located on opposite sides of the active pillars and the isolation pillars.
3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes a bit line structure located between the active pillar and the substrate.
4. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes a conductive plug located between the first word line and the second word line.
5. The semiconductor structure according to claim 4, characterized in that, The conductive plug is in direct contact with the adjacent first or second word line.
6. The semiconductor structure according to claim 5, characterized in that, The bottom surface of the conductive plug is higher than the bottom surface of the first letter.
7. The semiconductor structure according to claim 4, characterized in that, The bottom surface of the conductive plug is in direct contact with the top surface of the connecting pad.
8. The semiconductor structure according to claim 4, characterized in that, The word line structure further includes a gate dielectric layer, which is located between the first word line and the active post, and between the second word line and the active post, isolating the active post from the first word line and the second word line.
9. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A bonding pad is formed on the substrate; A word line structure is formed on the substrate, the word line structure including first word lines and second word lines arranged at intervals; The connecting pad is located at the bottom of the letter line structure, spans the first letter line and the second letter line, and contacts the bottom surfaces of the first letter line and the second letter line.
10. The method for preparing a semiconductor structure according to claim 9, characterized in that, Before forming the connection pad on the substrate, the method further includes: Multiple alternating active pillars and isolation pillars are formed on the substrate; the first word line and the second word line are located on opposite sides of the active pillars and the isolation pillars.
11. The method for preparing a semiconductor structure according to claim 10, characterized in that, Before forming a plurality of alternating active pillars and isolation pillars on the substrate, the method further includes: forming a bit line structure on the substrate; after forming the active pillars and isolation pillars, the bit line structure is located between the active pillars and the substrate.
12. The method for preparing a semiconductor structure according to claim 10, characterized in that, After forming the word line structure on the substrate, the method further includes: forming a conductive plug on the substrate, the conductive plug being located between the first word line and the second word line.
13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The word line structure formed on the substrate further includes a gate dielectric layer, which is located between the first word line and the active pillar, and between the second word line and the active pillar, isolating the active pillar from the first word line and the second word line.