Memory device and method of manufacturing the same

Abstract

A memory device and a method of fabricating the same are provided, which can be applied to 3D NAND flash memory with high capacity and / or high performance. The memory device includes a substrate, a source line layer, a stack structure, a plurality of separation walls, and a plurality of vertical channels. The source line layer is disposed above the substrate. The stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked above the source line layer. The separation walls penetrate through the stack structure and divide the stack structure into a plurality of blocks, wherein each separation wall includes a first portion proximate to the source line layer and a second portion on the first portion. A top of the first portion of the separation wall is larger than a bottom of the second portion thereof. The plurality of vertical channels penetrate through the stack structure and the source line layer in the plurality of blocks.

Description

Technical Field

[0001] This invention relates to a memory device and a method for manufacturing the same. Background Technology

[0002] Non-volatile memory elements are widely used in personal computers and other electronic devices because they have the advantage that stored data will not be lost after power is turned off.

[0003] To further improve the integration of memory elements, three-dimensional (3D) memory devices have been developed, such as NAND flash memory, NOR flash memory, and ROM flash memory. However, with the increase in storage layers in 3D memory devices, there are challenges related to process and construction. Summary of the Invention

[0004] The present invention provides a memory device and a method for manufacturing the same, which can produce a suitable partition wall structure as the thickness of the storage layer increases.

[0005] In one embodiment of the present invention, a memory device includes at least a substrate, a source line layer, a stacked structure, a plurality of partition walls, and a plurality of vertical channels. The source line layer is disposed above the substrate. The stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked above the source line layer. Partition walls penetrate the stacked structure and divide the stacked structure into a plurality of blocks, wherein each partition wall includes a first portion adjacent to the source line layer and a second portion located on the first portion. The top of the first portion of the partition wall is larger than the bottom of its second portion. Vertical channels penetrate the stacked structure and the source line layer in the plurality of blocks.

[0006] In another embodiment of the present invention, a method for manufacturing a memory device includes the following steps: forming a lower semiconductor layer over a substrate; forming a dielectric stack on the lower semiconductor layer; forming an upper semiconductor layer on the dielectric stack; forming a first stacked structure on the upper semiconductor layer, wherein the first stacked structure includes a plurality of alternately stacked insulating layers and a plurality of sacrificial layers; forming a first channel in the first stacked structure until the upper semiconductor layer is exposed; oxidizing the exposed surface of the upper semiconductor layer to form an oxide film; filling the first channel with a sacrificial material; forming a second stacked structure on the first stacked structure and the sacrificial material in the first channel; forming a plurality of vertical channels penetrating the second stacked structure, the first stacked structure, the upper semiconductor layer, the dielectric stack, and the lower semiconductor layer; forming a second channel in the second stacked structure on the first channel until the sacrificial material is exposed, wherein the width of the top of the first channel is greater than the width of the bottom of the second channel; and removing the sacrificial material.

[0007] Based on the above, the method for manufacturing the memory device according to embodiments of the present invention utilizes a segmented approach to form a stacked structure and openings. First, a larger trench is formed at the bottom of the stacked structure, and a sacrificial material is filled within it. After forming the remaining portion of the stacked structure, a deeper trench is formed on the aforementioned trench, using the sacrificial material as an etching stop layer. Therefore, this method ensures that the function and shape of the subsequently formed partition walls meet the requirements. Attached Figure Description

[0008] Figure 1 This is a top view of a memory device according to an embodiment of the present invention.

[0009] Figure 2 It is along Figure 1 A cross-sectional schematic diagram of the memory device of line II-II'.

[0010] Figures 3A to 3R This is a cross-sectional schematic diagram of the manufacturing process of a memory device according to another embodiment of the present invention.

[0011] Explanation of reference numerals in the attached figures:

[0012] 10: Memory devices

[0013] 100: Memory area

[0014] 102: Character Line Step Area

[0015] 104: Block

[0016] 200: Substrate

[0017] 202: Source Line Layer

[0018] 204: Stacked Structure

[0019] 204L: lower part

[0020] 204U: upper part

[0021] 206: Conductive layer

[0022] 208: Insulation layer

[0023] 210: Part One

[0024] 210b, 212b: Bottom

[0025] 210t: Top

[0026] 212: Part Two

[0027] 214: Conductive Channel Contact Window

[0028] 216: Insulating gap wall

[0029] 218: Gap

[0030] 220, 316: Insulating posts

[0031] 222, 314: Charge storage structures

[0032] 300: Dielectric stack

[0033] 302: First stacked structure

[0034] 304: Sacrificial Layer

[0035] 306: First Ditch

[0036] 308: Oxide film

[0037] 310: Sacrificial Materials

[0038] 312: Second stacked structure

[0039] 318: Second Ditch

[0040] 320: First protective layer

[0041] 322: Second protective layer

[0042] 324: Protective spacer wall

[0043] 326: Oxides

[0044] D, h1, h2, T: Height

[0045] f1, f2, f3: Dielectric film

[0046] HM: Hard Mask

[0047] LS: Lower semiconductor layer

[0048] P1: Conductive material

[0049] SB: Subblock

[0050] SL: Source Layer Space

[0051] SLT1, SLT2: Partition walls

[0052] US: Upper semiconductor layer

[0053] VC: Vertical Channel

[0054] w1, w2: Width

[0055] WLC: Wordline Contact Window Detailed Implementation

[0056] Figure 1 This is a top view of a memory device according to an embodiment of the present invention.

[0057] exist Figure 1 In this context, memory device 10 is a 3D memory device, and memory device 10 may include a memory region 100 and a word line ladder region 102. The memory region 100 has multiple vertical channels VC passing through a stacked structure (not shown), and the word line ladder region 102 has multiple word line contact windows WLC coupled to word lines within the stacked structure in the memory region 100. Memory device 10 also includes partition walls SLT2 that divide the stacked structure into blocks 104. Although... Figure 1 Only one block 104 is shown, but it should be understood that the memory device 10 may include multiple blocks 104. In some embodiments, in addition to the partition walls SLT2 formed by continuous lines extending along the first direction, the memory device 10 also includes partition walls SLT1 disposed between the partition walls SLT2. The partition walls SLT1 include multiple secondary partition walls extending along the first direction, for example... Figure 1 The partition wall SLT1 in the invention has four sub-partition walls, but the invention is not limited thereto.

[0058] The detailed construction of the partition wall SLT1 will be described below.

[0059] Figure 2 It is along Figure 1 A schematic cross-sectional view of line II-II', where line II-II' is... Figure 1 The second direction is parallel. Please refer to... Figure 2 The memory device includes at least a substrate 200, a source line layer 202, a stacked structure 204, a partition wall SLT1, and multiple vertical channels VC. In an embodiment of the present invention, Figure 1 The structure of partition wall SLT2 is the same as that of partition wall SLT1, and they can be manufactured together using the same process.

[0060] exist Figure 2In this structure, a source line layer 202 is disposed above a substrate 200, wherein the source line layer 202 may include a lower semiconductor layer LS, an upper semiconductor layer US, and a conductive material P1 therebetween. In some embodiments, the lower semiconductor layer LS, the upper semiconductor layer US, and the conductive material P1 may comprise doped or undoped semiconductor materials, such as doped or undoped polysilicon. The stacked structure 204 includes a plurality of conductive layers 206 and a plurality of insulating layers 208 alternately stacked above the source line layer 202. In some embodiments, the conductive layers 206 may comprise a conductive material, such as tungsten (W); the insulating layers 208 may comprise oxides, such as silicon oxide. A partition wall SLT1 extends through the entire stacked structure 204 and divides the stacked structure 204 into a plurality of sub-blocks SB, wherein the partition wall SLT1 includes a first portion 210 adjacent to the source line layer 202 and a second portion 212 located on the first portion 210. In some embodiments, the stacked structure 204 includes a lower portion 204L near the source line layer 202 and an upper portion 204U above the lower portion 204L. The interface between the upper portion 204U and the lower portion 204L is at the same level as the interface between the second portion 212 and the first portion 210 of the partition wall SLT1, wherein the number of layers in the lower portion 204L is less than the number of layers in the upper portion 204U. In the partition wall SLT1, the top 210t of the first portion 210 is greater than the bottom 212b of the second portion 212. In some embodiments, the ratio of the height h2 of the lower portion 204L of the stacked structure 204 to the height h1 of the first portion 210 of the partition wall SLT1 is 2:3 to 5:6. In some embodiments, the cross-sectional shape of the first portion 210 is an inverted trapezoid. In some embodiments, the bottom 210b of the first portion 210 is greater than the bottom 212b of the second portion 212.

[0061] In some embodiments, the partition wall SLT1 includes a conductive channel contact window 214 and an insulating spacer wall 216 disposed on the sidewall of the conductive channel contact window 214. In some embodiments, the conductive channel contact window 214 may include a conductive material, such as polycrystalline silicon or tungsten. In some embodiments, the insulating spacer wall 216 may include an oxide, such as low-temperature oxide (LTO). Due to the depth of the partition wall SLT1, there may be a gap 218 in the conductive channel contact window 214 within the first portion 210. The conductive channel contact window 214 is electrically connected to the source line layer 202, and the conductive material P1 of the conductive channel contact window 214 and the source line layer 202 may be the same material, so the interface between the two is not shown in the figure.

[0062] exist Figure 2In this configuration, the vertical channel VC extends through the stacked structure 204 and the source line layer 202. In some embodiments, the vertical channel VC is located on the surface of the insulating pillar 220, which may include doped or undoped semiconductor materials, such as doped or undoped polysilicon. The material of the insulating pillar 220 may include silicon oxide or other suitable insulating materials. In some embodiments, a charge storage structure 222 is further disposed between the vertical channel VC and the stacked structure 204, wherein the charge storage structure 222 may include known multilayer structures, such as ONO (oxide-nitride-oxide) structure, ONONO (oxide-nitride-oxide-nitride-oxide) structure, SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, BE-SONOS (bandgap engineered silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, etc.

[0063] Figures 3A to 3R This is a cross-sectional schematic diagram of the manufacturing process of a memory device according to another embodiment of the present invention, wherein the use of... Figure 2 The same element symbols are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the previous embodiment, which will not be repeated here.

[0064] Please refer to Figure 3A A lower semiconductor layer LS is formed above the substrate 200. A dielectric stack 300 is formed on the lower semiconductor layer LS, wherein the dielectric stack 300 may be a multilayer structure, such as dielectric film f1, dielectric film f2, and dielectric film f3, and the material of the intermediate dielectric film f2 may be different from the materials of dielectric film f1 and dielectric film f3 to facilitate subsequent processes. In some embodiments, the material of dielectric film f2 is, for example, silicon nitride; the materials of dielectric film f1 and dielectric film f3 are, for example, silicon oxide. Then, an upper semiconductor layer US is formed on the dielectric stack 300. In some embodiments, the above structural layers may be deposited sequentially using a method such as chemical vapor deposition (CVD). Then, a first stack structure 302 is formed on the upper semiconductor layer US, wherein the first stack structure 302 includes a plurality of alternately stacked insulating layers 208 and a plurality of sacrificial layers 304. In some embodiments, the sacrificial layer 304 is a material with etching selectivity to the insulating layer 208, such as nitride.

[0065] Please refer to Figure 3BA first channel 306 is formed in the first stacked structure 302 until the upper semiconductor layer US is exposed. The method for forming the first channel 306 includes, for example, using photolithography to remove a portion of the first channel 306 and slightly etch a portion of the upper semiconductor layer US. In the figure, the first channel 306 is recessed into the top of the upper semiconductor layer US, but the invention is not limited thereto; in some embodiments, because the height (or thickness) of the first stacked structure 302 is small, the first channel 306 can be easily controlled to stop above the upper semiconductor layer US, i.e., the bottom surface of the first channel 306 is coplanar with the top surface of the upper semiconductor layer US. Subsequently, the exposed surface of the upper semiconductor layer US is oxidized to form an oxide film 308. From the viewpoint of not easily etching through the semiconductor layer US, the thickness of the oxide film 308 can be from 10 angstroms to 300 angstroms, for example, 20 angstroms to 300 angstroms or 50 angstroms to 300 angstroms.

[0066] Please refer to Figure 3C The first channel 306 is filled with sacrificial material 310. In some embodiments, the sacrificial material 310 may be deposited in the first channel 306 and then chemically mechanically polished (CMP) so that the top surface of the sacrificial material 310 is coplanar with the top surface of the first stacked structure 302. In some embodiments, the sacrificial material 310 includes a metallic material (such as W, Ti, TiN, etc.), polycrystalline silicon, or carbon material. When the sacrificial material 310 is a metallic material, the ratio of the height T of the sacrificial material 310 to the height D of the upper semiconductor layer US is, for example, 1:1 to 2:1. When the sacrificial material 310 is polycrystalline silicon or carbon material, the ratio of the height T of the sacrificial material 310 to the height D of the upper semiconductor layer US may be 2:1 to 5:1. The aforementioned height ratio also applies when the first channel 306 is positioned above the upper semiconductor layer US.

[0067] Please refer to Figure 3D A second stack structure 312 is formed on the sacrificial material 310 in the first stack structure 302 and the first channel 306, wherein the second stack structure 312 includes a plurality of alternately stacked insulating layers 208 and a plurality of sacrificial layers 304. In some embodiments, the insulating layers 208 in the second stack structure 312 may be made of the same material as the insulating layers 208 in the first stack structure 302; the sacrificial layers 304 in the second stack structure 312 may be made of the same material as the sacrificial layers 304 in the first stack structure 302.

[0068] Please refer to Figure 3EThis forms multiple vertical channels VC that penetrate the second stacked structure 312, the first stacked structure 302, the upper semiconductor layer US, the dielectric stack 300, and the lower semiconductor layer LS. Furthermore, other steps can be performed before and after forming the vertical channels VC, such as, but not limited to, first forming multiple openings through the aforementioned structures, and then forming charge storage structures 314 within the openings. In some embodiments, the charge storage structure 314 can be conformally formed on the sidewalls and bottom surface of the openings, and the material of the charge storage structure 314 can refer to... Figure 2 The charge storage structure 222 is then formed. Next, the vertical channel VC is formed on the inner wall and bottom surface of the charge storage structure 314. Then, an insulating pillar 316 is formed on the inner surface of the vertical channel VC. The material of the insulating pillar 316 can be referred to... Figure 2 The insulating column 220 in the middle.

[0069] Please refer to Figure 3F A second channel 318 is formed in the second stacked structure 312 on the first channel 306 until the sacrificial material 310 is exposed. In some embodiments, the method of forming the second channel 318 is, for example, to first form a hard mask HM, and then use the hard mask HM as an etching mask to etch the second stacked structure 312, and the sacrificial material 310 may serve as an etching stop layer during the etching of the second stacked structure 312. In some embodiments, because the second channel 318 is deeper, its sidewalls are not vertical, but become narrower towards the bottom (first channel 306), so the width w1 at the top of the first channel 306 may be greater than the width w2 at the bottom of the second channel 318.

[0070] Please refer to Figure 3G Remove Figure 3F The sacrificial material 310 is used in the process. If the sacrificial material 310 is polysilicon, due to the etch selectivity between the insulating layer 208 and the sacrificial layer 304, the contours of the first channel 306 and the second channel 318 do not change much. Moreover, the presence of the oxide film 308 ensures that the underlying structure is not etched through during the removal of the sacrificial material 310.

[0071] Please refer to Figure 3H First, the oxide film 308 is removed, exposing a portion of the upper semiconductor layer US. Since the oxide film 308 and the insulating layer 208 may be made of the same material, a portion of the insulating layer 208 will be removed. However, because the oxide film 308 is very thin, it has little impact on the contours of the first channel 306 and the second channel 318. Next, the upper semiconductor layer US is etched until the dielectric film f3 is exposed. Because the upper semiconductor layer US is polysilicon, the etching process has little impact on the contours of the first channel 306 and the second channel 318.

[0072] Subsequent processes are intended to form a partition wall with circuit functionality, but the invention is not limited thereto. In some embodiments, the first channel 306 and the second channel 318 may be directly filled with insulating material.

[0073] Please refer to Figure 3I A first protective layer 320 and a second protective layer 322 are deposited sequentially to conformally form on the sidewalls and bottom surfaces of the first channel 306 and the second channel 318. In some embodiments, the first protective layer 320 and the second protective layer 322 are made of different materials, for example, the first protective layer 320 is a polycrystalline silicon layer and the second protective layer 322 is an oxide layer.

[0074] Please refer to Figure 3J The first protective layer 320 and the second protective layer 322 are etched back to form a protective spacer wall 324 on the inner sidewalls of the second channel 318 and the first channel 306. Then, using the protective spacer wall 324 as an etching mask, the exposed dielectric film f3 and the dielectric films f2 and f1 below it are removed, and the etching can stop at the lower semiconductor layer LS.

[0075] Please refer to Figure 3K First, the first protective layer 320 in the protective spacer wall 324 is oxidized so that the exposed part becomes oxide 326, in order to avoid damage to the first protective layer 320 in subsequent processes.

[0076] Please refer to Figure 3L ,Will Figure 3K The dielectric film f2 is removed. If the dielectric film f2 is a silicon nitride layer, since the second protective layer 322, oxide 326, dielectric film f3, and dielectric film f1 are not silicon nitride, they are unlikely to affect other structural layers during the etching process.

[0077] Please refer to Figure 3M Remove Figure 3L Dielectric films f1 and f3 are used to form the source layer space SL. Since dielectric films f1 and f3 are silicon oxide, Figure 3L The second protective layer 322 will also be removed. During the removal of dielectric films f1 and f3, the charge storage structure 314 will also be etched to expose the sidewalls of each vertical channel VC.

[0078] Please refer to Figure 3N The source layer space SL is filled with conductive material P1 to form source line layer 202. Conductive material P1 may cover the surface of the first protective layer 320.

[0079] Please refer to Figure 3O First, remove the topmost conductive material P1 and the conductive material P1 located in the second channel 318 and the first channel 306, then remove... Figure 3NThe first protective layer 320 is in the middle. At this time, there are no other structures in the first channel 306 and the second channel 318, and the second stacked structure 312 and the first stacked structure 302 are exposed.

[0080] Please refer to Figure 3P Completely remove Figure 3O The sacrificial layer 304 is used in this process. This process is also known as a metal gate replacement process. For example, etching steps can be performed through the second channel 318 and the first channel 306, and the etching steps can include wet etching, such as using hot phosphoric acid or other suitable chemicals.

[0081] Please refer to Figure 3Q The space between the insulating layers 208 is filled with a conductive layer 206 to complete the replacement of the metal gate. The conductive layer 206 is fabricated, for example, by filling the space between the insulating layers 208 with a conductive material, followed by back etching to remove the conductive material adjacent to the first channel 306 and the second channel 318. The conductive layer 206 in the figure is the metal gate, which can serve as a word line in a memory device.

[0082] Please refer to Figure 3R An insulating gap wall 216 is formed on the sidewalls of the second channel 318 and the first channel 306. The second channel 318 and the first channel 306 are then filled with conductive material. The conductive material outside the second channel 318 is removed by a planarization process such as CMP to form a conductive channel contact window 214. Figure 3R The structure is basically the same as Figure 2 They have similar structures.

[0083] In summary, the memory device of this embodiment has a specially constructed partition wall that ensures that the function and shape of the partition wall meet the requirements. Furthermore, the manufacturing method of the memory device of this embodiment can be applied to 3D memory devices, such as NAND flash memory, NOR flash memory, ROM flash memory, etc.

Claims

1. A memory device, comprising: Substrate; The source line layer is disposed above the substrate; The stacked structure includes multiple insulating layers and multiple conductive layers alternately stacked above the source line layer; Multiple partition walls penetrate the stacked structure and divide the stacked structure into multiple blocks, wherein each partition wall includes a first portion near the source line layer and a second portion located on the first portion; as well as Multiple vertical channels traverse the stacked structure and the source line layer within these multiple blocks, wherein The top of the first part is larger than the bottom of the second part.

2. The memory device of claim 1, wherein the stacked structure includes a lower portion near the source line layer and an upper portion above the lower portion, the interface between the upper portion and the lower portion being at the same level as the interface between the second portion and the first portion of each partition wall.

3. The memory device of claim 2, wherein the number of layers in the lower part is less than the number of layers in the upper part.

4. The memory device of claim 2, wherein the ratio of the height of the lower portion of the stacked structure to the height of the first portion of each partition wall is 2:3 to 5:

6.

5. The memory device of claim 1, wherein each of the partition walls includes a conductive channel contact window and an insulating gap wall disposed at a sidewall of the conductive channel contact window.

6. The memory device of claim 5, wherein the conductive channel contact window within the first portion has a gap.

7. The memory device of claim 5, wherein the conductive channel contact window is electrically connected to the source line layer.

8. The memory device of claim 1, wherein the cross-sectional shape of the first portion is an inverted trapezoid.

9. The memory device of claim 1, wherein the bottom of the first portion is larger than the bottom of the second portion.

10. The memory device of claim 1, wherein the plurality of partition walls comprises: Two first dividing walls, each of which is a continuous line extending along a first direction; as well as A second partition wall is disposed between the two first partition walls, wherein the second partition wall includes a plurality of secondary partition walls extending along the first direction.

11. A method for manufacturing a memory device, comprising: A lower semiconductor layer is formed above the substrate; A dielectric stack is formed on the lower semiconductor layer; An upper semiconductor layer is formed on the dielectric stack; A first stacked structure is formed on the semiconductor layer, wherein the first stacked structure includes a plurality of insulating layers and a plurality of sacrificial layers stacked alternately; A first channel is formed in the first stacked structure until the upper semiconductor layer is exposed; The exposed surface of the upper semiconductor layer is oxidized to form an oxide film; The first trench was filled with sacrificial material; A second stacked structure is formed on the sacrificial material in the first stacked structure and the first channel; Multiple vertical channels are formed that penetrate the second stacked structure, the first stacked structure, the upper semiconductor layer, the dielectric stack, and the lower semiconductor layer; A second channel is formed in the second stacking structure on the first channel until the sacrificial material is exposed, wherein the width of the top of the first channel is greater than the width of the bottom of the second channel; as well as Remove the sacrificial material.

12. The method of manufacturing a memory device according to claim 11, wherein the sacrificial material is a metallic material, and the ratio of the height of the sacrificial material to the height of the upper semiconductor layer is 1:1 to 2:

1.

13. The method of manufacturing a memory device according to claim 11, wherein the sacrificial material is polycrystalline silicon or carbon material, and the ratio of the height of the sacrificial material to the height of the upper semiconductor layer is 2:1 to 5:

1.

14. The method of manufacturing a memory device according to claim 11, wherein the second stacked structure comprises a plurality of insulating layers and a plurality of sacrificial layers stacked alternately.

15. The method of manufacturing a memory device according to claim 11, wherein the thickness of the oxide film is from 10 angstroms to 300 angstroms.

16. The method of manufacturing a memory device according to claim 11, wherein after removing the sacrificial material, it further comprises: Remove the oxide film to expose part of the upper semiconductor layer; Etch the upper semiconductor layer until the dielectric stack is exposed; Protective gap walls are formed on the inner walls of the second channel and the first channel; Remove the dielectric stack to form the source layer space; and The source layer space is filled with conductive material.

17. The method of manufacturing a memory device according to claim 16, wherein the sidewalls of each of the vertical channels are exposed during the removal of the dielectric stack.

18. The method of manufacturing a memory device according to claim 16, wherein after filling the source layer space with the conductive material, the method further comprises: Remove the protective gap wall; as well as In the metal gate replacement process, the multiple sacrificial layers are replaced with metal gates.

19. The method of manufacturing a memory device according to claim 18, wherein after the replacement metal gate process, it further comprises: An insulating gap wall is formed on the sidewalls of the second channel and the first channel; as well as Conductive channel contact windows are formed in the second channel and the first channel.

20. The method of manufacturing a memory device according to claim 19, wherein the material of the conductive channel contact window comprises the same material as the conductive material.

Images