Method of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device includes the steps of: forming a first stack including first insulating layers and first sacrificial layers alternately stacked, the first sacrificial layers each having a first etching rate; forming a second stack on the first stack, the second stack including second insulating layers and second sacrificial layers alternately stacked, and the second sacrificial layers each having a second etching rate lower than the first etching rate; forming a first opening extending through the first stack and the second stack; forming a second opening connected to the first opening by etching the first sacrificial layers; forming a first barrier pattern covering the second stack; forming a second barrier pattern covering the first sacrificial layers in the second opening; and etching the first insulating layers using the first barrier pattern and the second barrier pattern as etching barriers.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to an electronic device, and more specifically, to a semiconductor device and a method of manufacturing a semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices for forming memory cells on a single layer on a substrate has reached its limit, three-dimensional semiconductor devices for stacking memory cells on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0003] In embodiments of this disclosure, a method of manufacturing a semiconductor device may include the following steps: forming a first stack comprising alternating layers of a first insulating layer and a first sacrificial layer, each of the first sacrificial layers having a first etch rate; forming a second stack on the first stack, the second stack comprising alternating layers of a second insulating layer and a second sacrificial layer, each of the second sacrificial layers having a second etch rate lower than the first etch rate; forming a first opening extending through the first stack and the second stack; forming a second opening by etching the first sacrificial layer through the first opening, the second opening being connected to the first opening; forming a first barrier pattern in the first opening, the first barrier pattern covering the second stack; forming a second barrier pattern in the second opening, the second barrier pattern covering the first sacrificial layer; and using the first barrier pattern and the second barrier pattern as etch barriers to etch the first insulating layer.

[0004] In embodiments of this disclosure, a method of manufacturing a semiconductor device may include the following steps: forming a first stack comprising alternating layers of a first insulating layer and a first sacrificial layer; forming a second stack on the first stack, the second stack comprising alternating layers of a second insulating layer and a second sacrificial layer; forming a first opening extending through the first stack and the second stack; forming a second opening by etching the first sacrificial layer through the first opening, the second opening being connected to the first opening; forming a barrier layer along a surface of the first stack exposed through the first opening and the second opening and a surface of the second stack exposed through the first opening and the second opening, the barrier layer having a first thickness on the first insulating layer and a second thickness on the second insulating layer, wherein the second thickness is greater than the first thickness; forming a first barrier pattern by etching the barrier layer, the first barrier pattern covering the second stack; forming a second barrier pattern in the second opening by etching the barrier layer; and etching the first insulating layer using the first barrier pattern and the second barrier pattern as etching barriers. Attached Figure Description

[0005] Figure 1 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0006] Figure 2 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 3 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figures 5A to 5H This is a simplified schematic diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0010] Figures 6A to 6K This is a simplified schematic diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0011] Figure 7 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 8 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0013] Various embodiments relate to a semiconductor device having a stable structure and improved properties, as well as a method of manufacturing the semiconductor device.

[0014] By stacking memory cells in a three-dimensional manner, the integration density of semiconductor devices can be improved. This also provides semiconductor devices with a stable structure and enhanced reliability.

[0015] In the following description, embodiments according to the technical features and scope of this disclosure will be described with reference to the accompanying drawings.

[0016] Figure 1 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0017] Reference Figure 1 The semiconductor device may include a gate structure GST and a channel structure CH. The gate structure GST may include alternating layers of insulating layers 11 and conductive layers 12. The conductive layers 12 may be gate lines such as word lines, source select lines, or drain select lines. Each conductive layer 12 may each include a conductive material such as polycrystalline tungsten (W) silicon or molybdenum (Mo). For example, at least one conductive layer 12 at the bottom may be a source select line, at least one conductive layer 12 at the top may be a drain select line, and the remaining conductive layers 12 may be word lines. The insulating layers 11 may insulate the stacked conductive layers 12 from each other. Each insulating layer 11 may include an insulating material such as an oxide nitride or a gap.

[0018] The channel structure CH can extend through the gate structure GST. The channel structure CH may include a memory layer 13, a channel layer 14, and an insulating core 15. The memory layer 13 may surround the sidewalls of the channel layer 14, and the insulating core 15 may be located within the channel layer 14. The memory layer 13 may include at least one of a tunneling layer, a data storage layer, and a barrier layer. The tunneling layer may surround the sidewalls of the channel layer 14, the data storage layer may surround the tunneling layer, and the barrier layer may surround the data storage layer. For example, the data storage layer may include a floating gate, polysilicon, a nitride, a charge trapping material, a variable resistance material, etc. The barrier layer may include a high-k material and may be a single layer or multiple layers.

[0019] Source-select transistors, memory cells, or drain-select transistors can be located in the region where the channel structure CH and the conductive layer 12 intersect. For example, at least one source-select transistor, multiple memory cells, and at least one drain-select transistor can be stacked along the channel structure CH. At least one source-select transistor, multiple memory cells, and at least one drain-select transistor sharing the channel structure CH can form a memory string.

[0020] The channel structure CH may include a first part P1 and a second part P2. In a cross-sectional view, as shown... Figure 1 As shown, the first part P1 and the second part P2 can each have a uniform width or a width that gradually varies according to the height. The term "height" as used in this document refers to the position along the vertical direction (also known as the stacking direction). Figure 1 As shown in the example, each of the first part P1 and the second part P2 can have a conical or arcuate shape, and a step can be present at the junction of the first part P1 and the second part P2. At the junction of the first part P1 and the second part P2, the top width TW1 of the first part P1 can be greater than the bottom width BW2 of the second part P2. Furthermore, the bottom width BW1 of the first part P1 can be greater than the bottom width BW2 of the second part P2. The top width TW1 of the first part P1 can be the same as or substantially the same as the top width of the second part P2.

[0021] According to the above structure, the channel structure CH may include a first part P1 and a second part P2, and the bottom width BW1 of the first part P1 may be greater than the bottom width BW2 of the second part P2. Therefore, as the bottom width BW1 of the first part P1 increases, the channel width of the source selection transistor located corresponding to the first part P1 can be increased, and the cell current can be improved.

[0022] Figure 2 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0023] Reference Figure 2The semiconductor device may include a gate structure GST and a channel structure CH. The gate structure GST may include a first gate structure GST1 and a second gate structure GST2. The first gate structure GST1 may include alternating layers of a first insulating layer 21A and a first conductive layer 22A, and the second gate structure GST2 may include alternating layers of a second insulating layer 21B and a second conductive layer 22B. The first conductive layer 22A and the second conductive layer 22B may be gate lines such as word lines, source select lines, or drain select lines. The first conductive layer 22A and the second conductive layer 22B may each include a conductive material such as, for example, polycrystalline tungsten silicon (W) or molybdenum (Mo). For example, at least one first conductive layer 22A and at least one second conductive layer 22B located at the bottom may be a source select line, at least one first conductive layer 22A and at least one second conductive layer 22B located at the top may be a drain select line, and the remaining first conductive layers 22A and at least one second conductive layer 22B may be word lines. The first insulating layer 21A and the second insulating layer 21B are used to insulate the stacked first conductive layer 22A and the second conductive layer 22B from each other, and may each include an insulating material such as, for example, oxide nitride or air gap. For example, the thickness of the uppermost first insulating layer 21A of the first gate structure GST1 and the thickness of the lowermost second insulating layer 21B of the second gate structure GST2 may be different from the thickness of the remaining first insulating layer 21A and the thickness of the second insulating layer 21B. The thickness of the uppermost first insulating layer 21A of the first gate structure GST1 and the thickness of the lowermost second insulating layer 21B of the second gate structure GST2 may be less than or greater than the thickness of the remaining first insulating layer 21A and the thickness of the second insulating layer 21B.

[0024] The channel structure CH may include a first channel structure CH1 and a second channel structure CH2. The first channel structure CH1 may extend through the first gate structure GST1. The first channel structure CH1 may include a memory layer 23A, a channel layer 24A, and an insulating core 25A. The first channel structure CH1 may include a first portion P11 and a second portion P12. In cross-section, the first portion P11 and the second portion P12 may each have a uniform width or a width that varies according to the height. In this case, the height may be a height along the vertical direction or the stacking direction. For example, each of the first portion P11 and the second portion P12 may have a tapered shape or an arcuate shape, and a step may exist at the portion where the first portion P11 and the second portion P12 connect to each other. The bottom width BW1 of the first portion P11 may be greater than the bottom width BW2 of the second portion P12.

[0025] The second channel structure CH2 may extend through the second gate structure GST2. The second channel structure CH2 may include a memory layer 23B, a channel layer 24B, and an insulating core 25B. The second channel structure CH2 may include a first portion P21 and a second portion P22. In cross-section, the first portion P21 and the second portion P22 may each have a uniform width or a width that varies according to height. In this case, the height may be along the vertical direction or the stacking direction. For example, each of the first portion P21 and the second portion P22 may have a tapered or arcuate shape, and a step may be present at the junction of the first portion P21 and the second portion P22. The bottom width BW3 of the first portion P21 may be greater than the bottom width BW4 of the second portion P22.

[0026] According to the above structure, the first channel structure CH1 may include a first portion P11 and a second portion P12, and the bottom width BW1 of the first portion P11 may be greater than the bottom width BW2 of the second portion P12. Therefore, the channel width of the source selection transistor can be increased, and the cell current can be improved. Furthermore, the second channel structure CH2 may include a first portion P21 and a second portion P22, and the bottom width BW3 of the first portion P21 may be greater than the bottom width BW4 of the second portion P22. Therefore, the alignment margin between the first channel structure CH1 and the second channel structure CH2 can be increased.

[0027] Figure 3 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. In the following text, content overlapping with the previously described content may be omitted.

[0028] Reference Figure 3 The semiconductor device may include a substrate SUB, a transistor TR, a first interconnect structure IC1, a first interlayer insulating layer IL1, a source structure 30, a gate structure GST, a channel structure CH, a second interconnect structure IC2, and a second interlayer insulating layer IL2. Peripheral circuitry may be located below the memory cell array.

[0029] The transistor TR can be located on the substrate SUB. The transistor TR can be part of the peripheral circuitry. For example, the peripheral circuitry can include a line decoder, page buffer, input / output circuitry, logic circuitry, etc. The first interconnect structure IC1 can be located in the first interlayer insulating layer IL1 and can be electrically connected to the peripheral circuitry. The first interconnect structure IC1 can include vias, wiring, etc.

[0030] The source structure 30 may be located on the first interlayer insulating layer IL1, and the gate structure GST may be located on the source structure 30. The gate structure GST may include alternating layers of insulating layer 31 and conductive layer 32. The channel structure CH may extend through the gate structure GST and may be connected to the source structure 30.

[0031] The channel structure CH may include a memory layer 33, a channel layer 34, an insulating core 35, and a cover layer 36. The cover layer 36 may serve as a channel pad for connecting the channel layer 34 and bit lines to each other. For example, the cover layer 36 may include a conductive material such as polysilicon or metal. The channel structure CH may include a first portion P1 and a second portion P2, and the bottom width BW1 of the first portion P1 may be greater than (or wider than) the bottom width BW2 of the second portion P2.

[0032] The second interconnect structure IC2 can be located in the second interlayer insulating layer IL2 and can be connected to the channel structure CH, etc. The second interconnect structure IC2 can include vias, wiring, etc.

[0033] According to the above structure, by positioning the peripheral circuitry below the memory cell array, the integration density of the semiconductor device can be improved. Furthermore, as the bottom width BW1 of the first portion P1 increases, the channel width of the source selection transistor positioned corresponding to the first portion P1 can be increased, thereby improving the cell current.

[0034] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. In the following text, content overlapping with the previously described content may be omitted.

[0035] Reference Figure 4 The semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a bonding structure BS. The first semiconductor structure S1 may include peripheral circuitry, and the second semiconductor structure S2 may include a memory cell array.

[0036] The first semiconductor structure S1 may include a substrate SUB, a transistor TR, a first interlayer insulating layer IL1, and a first interconnect structure IC1. The transistor TR may be part of the peripheral circuitry. The first interconnect structure IC1 may be located within the first interlayer insulating layer IL1 and may include vias, wiring, etc. The first interconnect structure IC1 may be electrically connected to the peripheral circuitry.

[0037] The second semiconductor structure S2 may include a source structure 40, a gate structure GST, a channel structure CH, a second interlayer insulating layer IL2, and a second interconnect structure IC2. The gate structure GST may include alternating layers of insulating layer 41 and conductive layer 42. The source structure 40 may be located above or below the gate structure GST. The channel structure CH may extend through the gate structure GST and may be connected to the source structure 40. For example, the channel structure CH may extend into the source structure 40. The channel structure CH may include a memory layer 43, a channel layer 44, an insulating core 45, and a capping layer 46. The channel structure CH may include a first portion P1 and a second portion P2. The top width TW2 of the second portion P2 may be greater than the top width TW1 of the first portion P1.

[0038] The bonding structure BS can be located between the first semiconductor structure S1 and the second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 can be manufactured separately and can be electrically connected to each other through the bonding structure BS. The memory cell array and peripheral circuitry including transistors TR can be electrically connected to each other through the bonding structure BS.

[0039] The bonding structure BS may include a first bonding layer BR1, a second bonding layer BR2, a first bonding pad BD1, and a second bonding pad BD2. The first bonding layer BR1 and the second bonding layer BR2 may be in contact with each other. Furthermore, the first bonding pad BD1 and the second bonding pad BD2 may be in contact with each other. The first bonding layer BR1 and the second bonding layer BR2 may each include, for example, SiCN, tetraethyl orthosilicate (TEOS), etc. The first bonding pad BD1 may be electrically connected to the first interconnect structure IC1, and the second bonding pad BD2 may be electrically connected to the second interconnect structure IC2. The memory cell array and peripheral circuitry can be electrically connected to each other through the first bonding pad BD1 and the second bonding pad BD2.

[0040] According to the above structure, the first semiconductor structure S1 and the second semiconductor structure S2 can be joined together in the vertical direction, thus improving the integration density of the semiconductor device. Furthermore, as the top width TW2 of the second portion P2 increases, the channel width of the source selection transistor positioned corresponding to the second portion P2 can be increased, thereby increasing the cell current. In other words, as TW2 increases, the channel width of the source selection transistor also increases. Increasing the channel width means that more charge carriers can pass through simultaneously, thereby reducing resistance and improving conductivity.

[0041] Figures 5A to 5H This is a simplified schematic diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure. In the following description, content overlapping with the previously described material may be omitted.

[0042] Reference Figure 5AA first laminate ST1 can be formed comprising alternating layers of a first insulating layer 511 and a first sacrificial layer 512. The first sacrificial layer 512 can be used to form a gate line. Each of the first sacrificial layers 512 may comprise a material with high etch selectivity relative to the first insulating layer 511. The first insulating layer 511 located at the uppermost part of the first laminate ST1 may have a greater thickness than the other first insulating layers 511. For example, each of the first sacrificial layers 512 may comprise a nitride, and each of the first insulating layers 511 may comprise an oxide.

[0043] Subsequently, a second stack ST2 can be formed on the first stack ST1. The second stack ST2 may include alternating layers of a second insulating layer 521 and a second sacrificial layer 522. Each of the second sacrificial layers 522 may comprise a material with high etch selectivity relative to the second insulating layer 521. For example, each of the second sacrificial layers 522 may comprise a nitride, and each of the second insulating layers 521 may comprise an oxide.

[0044] The first sacrificial layer 512 may each have a first etch rate, and the second sacrificial layer 522 may each have a second etch rate different from the first etch rate. The second etch rate may be lower than the first etch rate. For example, the difference in etch rates between the first sacrificial layer 512 and the second sacrificial layer 522 may be due to a difference in density between the first sacrificial layer 512 and the second sacrificial layer 522. The first sacrificial layer 512 may each have a first density, and the second sacrificial layer 522 may each have a second density different from the first density. The first density may be lower than the second density.

[0045] The density of the first sacrificial layer 512 and the density of the second sacrificial layer 522 can be determined according to the process conditions. The first sacrificial layer 512 can be formed under a first pressure, and the second sacrificial layer 522 can be formed under a second pressure different from the first pressure. The first pressure can be higher than the second pressure, and the first density of the first sacrificial layer 512 can be lower than the second density of the second sacrificial layer 522. The flow rates of silane (SiH4) gas and ammonia (NH3) gas used during the formation of the first sacrificial layer 512 and the second sacrificial layer 522 can be different. Specifically, the flow rates of silane and ammonia gas used for the first sacrificial layer 512 can be higher than the corresponding flow rates used for the second sacrificial layer 522. The flow rates of silane gas and ammonia gas used in the formation of the first sacrificial layer 512 and the flow rates of silane gas and ammonia gas used in the formation of the second sacrificial layer 522 can be different from each other. The flow rates of SiH4 gas and NH3 gas used in forming the first sacrificial layer 512 can be greater than those used in forming the second sacrificial layer 522. In this case, the hydrogen content in the first sacrificial layer 512 can be higher than the hydrogen content in the second sacrificial layer 522, and the density of the first sacrificial layer 512 can be lower than the density of the second sacrificial layer 522.

[0046] Reference Figure 5B A first opening OP1 can be formed, extending through the first stack ST1 and the second stack ST2. The first opening OP1 can extend in the stacking direction or in the vertical direction. The first opening OP1 serves as a channel for forming the second opening OP2 and the third opening OP3, and can be a channel hole for forming a channel structure in subsequent processes. In a plan view, the first opening OP1 can have a circular shape, an elliptical shape, a polygonal shape, etc.

[0047] Reference Figure 5C The second opening OP2 can be formed by etching the first sacrificial layer 512 using the first opening OP1. More specifically, the second opening OP2 can be formed by etching the edge region of the first sacrificial layer 512 exposed to the first opening OP1. The second opening OP2 can be connected to and surround the first opening OP1. The third opening OP3 can also be formed by etching the second sacrificial layer 522 using the first opening OP1. The third opening OP3 can be connected to and surround the first opening OP1.

[0048] The first sacrificial layer 512 and the second sacrificial layer 522 can each have high etch selectivity relative to the first insulating layer 511 and the second insulating layer 521. Therefore, when the second opening OP2 is formed, the third opening OP3 can be formed. However, due to the difference in etch rate between the first sacrificial layer 512 and the second sacrificial layer 522, the shapes of the second opening OP2 and the third opening OP3 can be different from each other. The etch rate of the first sacrificial layer 512 can be higher than (or faster than) the etch rate of the second sacrificial layer 522, and the first width W1 of the second opening OP2 can be greater than the second width W2 of the third opening OP3.

[0049] Reference Figure 5D A barrier layer BL can be formed in the first opening OP1, the second opening OP2, and the third opening OP3. The barrier layer BL can be formed along the exposed surfaces of the first stack ST1 and the second stack ST2. The barrier layer BL can include a material with high etch selectivity relative to the first insulating layer 511 and the second insulating layer 521. For example, the barrier layer BL can include polysilicon.

[0050] The first thickness T51 of the barrier layer BL formed on the sidewall of the first insulating layer 511 may be different from the second thickness T52 of the barrier layer BL formed on the sidewall of the second insulating layer 521. The deposition environment above and below the first opening OP1 may be different from each other, and a thickness difference may occur depending on the difference in deposition environment. The deposition rate at the upper part may be faster than the deposition rate at the lower part, and the second thickness T52 may be greater than the first thickness T51.

[0051] Reference Figure 5E By etching the barrier layer BL, a first barrier pattern BP1 covering the second laminate ST2 can be formed in the first opening OP1. Furthermore, by etching the barrier layer BL, a second barrier pattern BP2 covering the first sacrificial layer 512 can be formed in the second opening OP2. The first barrier pattern BP1 and the second barrier pattern BP2 can be formed simultaneously by etching the barrier layer BL. Because the second thickness T52 is greater than the first thickness T51, the first barrier pattern BP1 can be formed as a spacer shape along the sidewall of the second laminate ST2. The second barrier pattern BP2 can be formed in the second opening OP2 and can be separated from each other. The sidewall of the second barrier pattern BP2 can be aligned with the sidewall of the first insulating layer 511. In this way, the first insulating layer 511 can be exposed in the first opening OP1.

[0052] Reference Figure 5FThe first barrier pattern BP1 and the second barrier pattern BP2 can be used as etching barriers to etch the first insulating layer 511 exposed in the first opening OP1. In this case, the first insulating layer 511 can be etched such that the sidewalls of the first insulating layer 511 are aligned with the sidewalls of the first sacrificial layer 512. Compared to the first insulating layer 511 and the first sacrificial layer 512, the second barrier pattern BP2 can protrude towards the first opening OP1. In other words, compared to the first insulating layer 511 and the first sacrificial layer 512, the second barrier pattern BP2 can extend further towards the first opening OP1.

[0053] Reference Figure 5G The first barrier pattern BP1 and the second barrier pattern BP2 can be removed through the first opening OP1. Specifically, the fourth opening OP4 can be formed by selectively etching the first barrier pattern BP1 and the second barrier pattern BP2 under the condition that the etching selectivity of the first barrier pattern BP1 and the second barrier pattern BP2 is relatively high relative to that of the first laminate ST1 and the second laminate ST2. Within the fourth opening OP4, the third width W3 corresponding to the lowermost part of the first laminate ST1 can be greater than the fourth width W4 corresponding to the lowermost part of the second laminate ST2.

[0054] Reference Figure 5H A channel structure CH can be formed in the fourth opening OP4. A memory layer 531, a channel layer 532, and an insulating core 533 can be formed in the fourth opening OP4. For example, a barrier layer can be formed in the fourth opening OP4, and a data storage layer and a tunneling layer can be formed on the barrier layer. The channel layer 532 can be formed on the tunneling layer, and the interior of the channel layer 532 can be filled with the insulating core 533.

[0055] Subsequently, the first sacrificial layer 512 and the second sacrificial layer 522 can be replaced with a conductive layer 54. For example, a slit extending through the first stack ST1 and the second stack ST2 can be formed, and the first sacrificial layer 512 and the second sacrificial layer 522 can be removed through the slit. The conductive layer 54 can then be formed in the region where the first sacrificial layer 512 and the second sacrificial layer 522 have been removed. In this way, a gate structure GST comprising alternating layers of conductive layer 54 and a first insulating layer 511, and alternating layers of conductive layer 54 and a second insulating layer 521, can be formed. For example, each of the conductive layers 54 may comprise a conductive material such as, for example, polycrystalline silicon tungsten (W) or molybdenum (Mo).

[0056] When the first sacrificial layer 512 and the second sacrificial layer 522 are removed through the slit, the first sacrificial layer 512 and the second sacrificial layer 522 can be etched, thereby exposing the sidewalls of the channel structure CH. Because the etching rate of the second sacrificial layer 522 is lower than (or slower than) the etching rate of the first sacrificial layer 512, etching conditions can be set so that the second sacrificial layer 522 can be fully etched.

[0057] According to the above method, a fourth opening OP4 with an enlarged bottom width can be formed using a first sacrificial layer 512 and a second sacrificial layer 522 with different etch rates, a first barrier pattern BP1, and a second barrier pattern BP2. Furthermore, a channel structure CH with an enlarged bottom width can be formed in the fourth opening OP4. Therefore, the channel width of the source-select transistor can be increased, and the cell current can be improved.

[0058] Figures 6A to 6K This is a simplified schematic diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure. In the following text, content overlapping with the previously described material may be omitted.

[0059] Reference Figure 6A A first laminate ST1 can be formed, comprising alternating layers of a first insulating layer 611 and a first sacrificial layer 612. Subsequently, a second laminate ST2 can be formed on the first laminate ST1. The second laminate ST2 may include alternating layers of a second insulating layer 621 and a second sacrificial layer 622.

[0060] The first sacrificial layer 612 may each have a first etch rate, and the second sacrificial layer 622 may each have a second etch rate different from the first etch rate. The second etch rate may be lower than the first etch rate. For example, the difference in etch rates between the first sacrificial layer 612 and the second sacrificial layer 622 may be due to a difference in density between the first sacrificial layer 612 and the second sacrificial layer 622. The first sacrificial layer 612 may each have a first density, and the second sacrificial layer 622 may each have a second density different from the first density. The first density may be lower than the second density.

[0061] Reference Figure 6B A first opening OP1 can be formed extending through the first stack ST1 and the second stack ST2. Subsequently, a second opening OP2 can be formed by etching the first sacrificial layer 612 using the first opening OP1. The second opening OP2 can be connected to and surround the first opening OP1. A third opening OP3 can be formed by etching the second sacrificial layer 622 using the first opening OP1. The third opening OP3 can be connected to and surround the first opening OP1.

[0062] When the second opening OP2 is formed, the third opening OP3 can be formed. However, due to the difference in etching rates between the first sacrificial layer 612 and the second sacrificial layer 622, the shapes of the second opening OP2 and the third opening OP3 can be different from each other. The etching rate of the first sacrificial layer 612 can be higher than (or faster than) the etching rate of the second sacrificial layer 622, and the first width W1 of the second opening OP2 can be greater than the second width W2 of the third opening OP3.

[0063] Reference Figure 6C The third sacrificial layer 631 can be formed on the first sacrificial layer 612 exposed through the second opening OP2. The fourth sacrificial layer 632 can be formed on the second sacrificial layer 622 exposed through the third opening OP3. Compared with the third sacrificial layer 631, the fourth sacrificial layer 632 can protrude into the first opening OP1. For example, the third sacrificial layer 631 and the fourth sacrificial layer 632 can each include SiOC.

[0064] The third sacrificial layer 631 and the fourth sacrificial layer 632 can be selectively deposited on the surfaces of the first sacrificial layer 612 and the second sacrificial layer 622, respectively. For example, the surfaces of the first insulating layer 611 and the second insulating layer 621 can each include hydroxyl groups, and the surfaces of the first sacrificial layer 612 and the second sacrificial layer 622 can include amino groups. Before depositing the third sacrificial layer 631 and the fourth sacrificial layer 632, an inhibitor can be formed on the first insulating layer 611 and the second insulating layer 621 using a precursor that is only adsorbed onto the hydroxyl groups. The inhibitor can inhibit the deposition of the third sacrificial layer 631 and the fourth sacrificial layer 632 on the surfaces of the first insulating layer 611 and the second insulating layer 621. Therefore, the third sacrificial layer 631 and the fourth sacrificial layer 632 can be selectively deposited on the surfaces of the first sacrificial layer 612 and the second sacrificial layer 622, respectively.

[0065] Reference Figure 6D A first barrier layer BL1 can be formed in the first opening OP1. The first barrier layer BL1 can be formed along the surfaces of the first insulating layer 611 and the second insulating layer 621, as well as the surfaces of the third sacrificial layer 631 and the fourth sacrificial layer 632. The first barrier layer BL1 can include a material with high etch selectivity relative to the third sacrificial layer 631 and the fourth sacrificial layer 632. For example, the first barrier layer BL1 can include polysilicon.

[0066] The first thickness T61 of the first barrier layer BL1 formed on the sidewall of the first insulating layer 611 may be different from the second thickness T62 of the first barrier layer BL1 formed on the sidewall of the second insulating layer 621. Because the fourth sacrificial layer 632 protrudes into the first opening OP1 compared to the third sacrificial layer 631, and the first barrier layer BL1 is formed on the fourth sacrificial layer 632, the second thickness T62 may be greater than (or thicker than) the first thickness T61.

[0067] Reference Figure 6E A third barrier pattern BP3 can be formed between the fourth sacrificial layers 632 by etching the first barrier layer BL1. The third barrier pattern BP3 can be formed on the sidewall of the second insulating layer 621 exposed between the fourth sacrificial layers 632.

[0068] Reference Figure 6F The third sacrificial layer 631 and the fourth sacrificial layer 632 can be removed in the first opening OP1. The third sacrificial layer 631 and the fourth sacrificial layer 632 can be selectively etched relative to the first insulating layer 611, the first sacrificial layer 612, and the second sacrificial layer 622. In this way, the first insulating layer 611, the first sacrificial layer 612, and the second sacrificial layer 622 can be exposed in the first opening OP1, and the second opening OP2 and the third opening OP3 can be reopened.

[0069] Reference Figure 6G A second barrier layer BL2 can be formed in the first opening OP1, the second opening OP2, and the third opening OP3. The second barrier layer BL2 can be formed along the surface of the third barrier pattern BP3, the surface of the first insulating layer 611, and the surfaces of the first sacrificial layer 612 and the second sacrificial layer 622. The second barrier layer BL2 can include a material with high etch selectivity relative to the first insulating layer 611 and the second insulating layer 621. For example, the second barrier layer BL2 can include the same material as the third barrier pattern BP3 and can include polysilicon.

[0070] The third thickness T63 of the second barrier layer BL2 formed on the sidewall of the first insulating layer 611 may be different from the fourth thickness T64 of the second barrier layer BL2 formed on the sidewall of the second insulating layer 621. Because the second barrier layer BL2 is formed on the third barrier pattern BP3, the fourth thickness T64 may be greater than (or thicker than) the third thickness T63.

[0071] Reference Figure 6HBy etching the second barrier layer BL2, a first barrier pattern BP1 covering the second laminate ST2 can be formed in the first opening OP1. The remaining second barrier layer BL2 and third barrier pattern BP3 after the etching process can be used as the first barrier pattern BP1. Because the fourth thickness T64 is greater than (or thicker than) the third thickness T63, the first barrier pattern BP1 can be formed as a spacer shape along the sidewall of the second laminate ST2. Furthermore, by etching the second barrier layer BL2, a second barrier pattern BP2 covering the first sacrificial layer 612 can be formed in the second opening OP2. The second barrier patterns BP2 can be formed in the second opening OP2 and can be separated from each other. The sidewall of the second barrier pattern BP2 can be aligned with the sidewall of the first insulating layer 611. By etching the second barrier layer BL2, the first barrier pattern BP1 and the second barrier pattern BP2 can be formed simultaneously. In this way, the first insulating layer 611 can be exposed in the first opening OP1.

[0072] Reference Figure 6I The first barrier pattern BP1 and the second barrier pattern BP2 can be used as etching barriers to etch the first insulating layer 611 exposed in the first opening OP1. In this case, the first insulating layer 611 can be etched such that the sidewalls of the first insulating layer 611 are aligned with the sidewalls of the first sacrificial layer 612. Compared to the first insulating layer 611 and the first sacrificial layer 612, the second barrier pattern BP2 can protrude toward the first opening OP1.

[0073] Reference Figure 6J The first barrier pattern BP1 and the second barrier pattern BP2 can be removed through the first opening OP1. The fourth opening OP4 can be formed by selectively etching the first barrier pattern BP1 and the second barrier pattern BP2 under the condition that the etching selectivity of the first barrier pattern BP1 and the second barrier pattern BP2 is higher than that of the first laminate ST1 and the second laminate ST2. Within the fourth opening OP4, the third width W3 corresponding to the lowermost part of the first laminate ST1 can be greater than the fourth width W4 corresponding to the lowermost part of the second laminate ST2.

[0074] Reference Figure 6K A channel structure CH can be formed in the fourth opening OP4. A memory layer 641, a channel layer 642, and an insulating core 643 can be formed in the fourth opening OP4. Subsequently, the first sacrificial layer 612 and the second sacrificial layer 622 can be replaced with conductive layers 65. In this way, a gate structure GST comprising alternating layers of conductive layers 65 and a first insulating layer 611, and alternating layers of conductive layers 65 and a second insulating layer 621, can be formed. For example, each of the conductive layers 65 can comprise a conductive material such as polycrystalline tungsten silicon (W) or molybdenum (Mo).

[0075] According to the above method, a third barrier pattern BP3 can be formed using a third sacrificial layer 631 and a fourth sacrificial layer 632. In this way, a second barrier layer BL2 with different thicknesses at its upper and lower parts can be formed, and the first barrier pattern BP1 and the second barrier pattern BP2 can be formed by etching the second barrier layer BL2. The first barrier pattern BP1 and the second barrier pattern BP2 can be used as etching barriers to form a fourth opening OP4 with an expanded bottom width. Furthermore, a channel structure CH with an expanded bottom width can be formed in the fourth opening OP4. Therefore, the channel width of the source selection transistor can be increased, and the cell current can be improved.

[0076] The structure and method described above can be applied to semiconductor devices with various structures. Figure 7 and Figure 8 A schematic configuration of a semiconductor device to which the above embodiments can be applied is shown.

[0077] Figure 7 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0078] Reference Figure 7 The semiconductor device may include a substrate SUB, peripheral circuitry PC, and memory cell array CA. Here, the peripheral circuitry PC and the memory cell array CA may be formed on the same substrate.

[0079] The substrate SUB may include a semiconductor material. For example, the semiconductor material may include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Here, group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors may include ZnS, ZnO, or CdS.

[0080] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. For example, the substrate SUB may include graphene.

[0081] The substrate SUB can be a bulk wafer or an epitaxial layer grown using the selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using the metal-induced lateral crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be monocrystalline, polycrystalline, or amorphous. The substrate SUB can include Group II, III, IV, V, or VI impurities. For example, the substrate SUB can include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0082] The peripheral circuitry PC can be located between the substrate SUB and the memory cell array CA. The peripheral circuitry PC can include row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. For example, the peripheral circuitry PC can include N-channel metal-oxide-semiconductor (NMOS) transistors, P-channel metal-oxide-semiconductor (PMOS) transistors, resistors, capacitors, etc. The peripheral circuitry PC can also include interconnect structures. These interconnect structures can serve as paths for transmitting operating voltages and can include contact plugs, wiring, etc.

[0083] A memory cell array (CA) may include memory cells. For example, the memory cell array (CA) may include memory strings connected between source lines and bit lines, and each memory string may include stacked memory cells. For example, the memory cell array (CA) may include memory cells connected between word lines and bit lines. The memory cell array (CA) may also include interconnect structures.

[0084] Figure 8 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0085] Reference Figure 8 The semiconductor device may include a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on separate substrates and then bonded together. The semiconductor device may also include a support substrate SP_B.

[0086] The substrate SUB can be used as a support during the formation of the peripheral circuit PC. The support substrate SP_B can be used as a support during the formation of the memory cell array CA. For example, a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC can be fabricated separately and then electrically connected to each other via a bonding structure BS. After the first and second wafers are bonded together, the support substrate SP_B of the first wafer can be at least partially removed. The support substrate SP_B can be completely removed or partially retained on the memory cell array CA.

[0087] The supporting substrate SP_B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The supporting substrate SP_B can be a bulk wafer, an epitaxial layer grown by selective epitaxial growth (SEG), or a layer formed by metal-induced lateral crystallization (MILC). The supporting substrate SP_B can be single-crystal, polycrystalline, or amorphous. The supporting substrate SP_B can include group II, III, IV, V, or VI impurities.

[0088] A bonding structure (BS) can be used to connect a memory cell array (CA) and peripheral circuitry (PC) to each other. For example, the bonding structure BS can bond the memory cell array (CA) and peripheral circuitry (PC) to each other using wafer-to-wafer bonding, chip-to-wafer bonding, chip-to-chip bonding, etc. The bonding structure BS may include bonding pads, bonding layers, bonding interfaces, etc. Bonding pads may include metals such as copper or aluminum and / or their alloys. Bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array (CA) and peripheral circuitry (PC) can be electrically connected to each other through the bonding structure BS.

[0089] For reference, the interconnect structures included in the memory cell array (CA) and / or peripheral circuitry (PC) can also be directly connected to each other without the need for bonding pads. For example, bonding layers included in the memory cell array (CA) and bonding layers included in the peripheral circuitry (PC) can be bonded to each other to form a bonding interface, and interconnect structures included in the memory cell array (CA) and interconnect structures included in the peripheral circuitry (PC) can be directly connected to each other. In this way, contacts, wiring, etc., formed on different wafers can be electrically connected to each other without the need for separate bonding pads.

[0090] Other configurations can be found in the above text. Figure 7 The configurations described are the same or similar.

[0091] Semiconductor devices can also have the above reference. Figure 7 and Figure 8 The described embodiments are structures that combine with each other, or structures with partial modifications. (Refer to...) Figure 7 and Figure 8 In the described implementation, the positions of the memory cell array CA and the peripheral circuitry PC can be changed. (Refer to...) Figure 7 and Figure 8 In the described embodiments, at least one memory cell array CA and / or at least one peripheral circuit PC may be additionally coupled. For example, a portion of the peripheral circuit PC may be located within the memory cell array CA. Furthermore, embodiments may be combined to form additional embodiments.

[0092] Cross-references to related applications

[0093] This application claims priority to Korean Patent Application No. 10-2025-0055564, filed on April 28, 2025, which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: A first stack is formed comprising alternating layers of first insulating layers and first sacrificial layers, each of the first sacrificial layers having a first etch rate; A second stack is formed on the first stack, the second stack comprising alternating layers of second insulating layers and second sacrificial layers, each of the second sacrificial layers having a second etch rate lower than the first etch rate; Forming a first opening that extends through the first and second laminates; A second opening is formed by etching the first sacrificial layer using the first opening; the second opening is connected to the first opening. A first barrier pattern is formed in the first opening, and the first barrier pattern covers the second laminate; A second barrier pattern is formed in the second opening, and the second barrier pattern covers the first sacrificial layer; as well as The first insulating layer is etched using the first barrier pattern and the second barrier pattern as etching barriers.

2. The method according to claim 1, further comprising the following steps: A third opening is formed by etching the second sacrificial layer using the first opening, and the third opening is connected to the first opening.

3. The method according to claim 2, wherein, When the second opening is formed, the third opening is formed.

4. The method according to claim 2, wherein, The width of each of the second openings is greater than the width of each of the third openings.

5. The method according to claim 2, further comprising the following steps: A third sacrificial layer is formed on the first sacrificial layer exposed through the second opening; as well as A fourth sacrificial layer is formed on the second sacrificial layer exposed through the third opening.

6. The method according to claim 5, wherein, The third and fourth sacrificial layers are formed by a selective deposition method.

7. The method according to claim 5, further comprising the following step: A third barrier pattern is formed on the second insulating layer exposed between the fourth sacrificial layers.

8. The method according to claim 7, wherein, The steps for forming the third barrier pattern include: A first barrier layer is formed along the surface of the third sacrificial layer, the surface of the fourth sacrificial layer, the surface of the first insulating layer, and the surface of the second insulating layer; and The third barrier pattern is formed by etching the first barrier layer.

9. The method according to claim 7, further comprising the following step: The third sacrificial layer and the fourth sacrificial layer are removed after the third barrier pattern is formed.

10. The method according to claim 7, further comprising the step of: A second barrier layer is formed in the first opening and the second opening along the surface of the first laminate, the surface of the second laminate, and the surface of the third barrier pattern.

11. The method according to claim 10, wherein, The first barrier pattern and the second barrier pattern are formed by etching the second barrier layer.

12. The method according to claim 1, further comprising the following steps: A fourth opening is formed by removing the first barrier pattern and the second barrier pattern, the fourth opening having a bottom width greater than the top width; as well as A channel structure is formed in the fourth opening.

13. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a first laminate comprising alternating layers of a first insulating layer and a first sacrificial layer; A second laminate is formed on the first laminate, the second laminate comprising alternating layers of a second insulating layer and a second sacrificial layer; Forming a first opening that extends through the first and second laminates; A second opening is formed by etching the first sacrificial layer using the first opening; the second opening is connected to the first opening. A barrier layer is formed along the surfaces of the first laminate exposed through the first opening and the second opening and the surfaces of the second laminate exposed through the first opening and the second opening, the barrier layer having a first thickness on the first insulating layer and a second thickness on the second insulating layer, wherein the second thickness is greater than the first thickness; A first barrier pattern is formed by etching the barrier layer, the first barrier pattern covering the second layer stack; A second barrier pattern is formed in the second opening by etching the barrier layer; and The first insulating layer is etched using the first barrier pattern and the second barrier pattern as etching barriers.

14. The method according to claim 13, wherein, When the second opening is formed, the etch rate of the first sacrificial layer is higher than that of the second sacrificial layer.

15. The method according to claim 13, wherein, The steps for forming the barrier layer include: A third barrier pattern is formed on the second insulating layer exposed through the first opening; and The barrier layer is formed to cover the third barrier pattern.

16. The method of claim 15, further comprising the step of: A third opening is formed by etching the second sacrificial layer using the first opening, and the third opening is connected to the first opening.

17. The method according to claim 16, wherein, The steps for forming the third barrier pattern include: A third sacrificial layer is formed on the first sacrificial layer exposed through the second opening; A fourth sacrificial layer is formed on the second sacrificial layer exposed through the third opening; A first barrier layer is formed in the first opening, the first barrier layer covering the third sacrificial layer, the fourth sacrificial layer, the first insulating layer, and the second insulating layer; and The third barrier pattern is formed by etching the first barrier layer on the sidewall of the second insulating layer exposed between the fourth sacrificial layer.

18. The method according to claim 17, wherein, The third and fourth sacrificial layers are formed by a selective deposition method.

19. The method of claim 17, further comprising the step of: The third sacrificial layer and the fourth sacrificial layer are removed after the third barrier pattern is formed.

20. The method of claim 13, further comprising the step of: A fourth opening is formed by removing the first barrier pattern and the second barrier pattern, the fourth opening having a bottom width greater than the top width; as well as A channel structure is formed in the fourth opening.

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