Memory device and memory package including the same

Abstract

Memory devices and memory packages including the same are provided. The memory device includes a gate electrode structure, a memory channel structure, a first contact plug, and a first electrical connection structure. The gate electrode structure includes gate electrodes. Each of the first gate electrodes includes sub-gate electrodes physically separated from each other. The memory channel structure extends through the gate electrode structure. The first contact plug extends partially through the gate electrode structure to contact an upper surface of a second gate electrode, and extends through a gate electrode disposed above the second gate electrode but electrically insulated from the gate electrode disposed above the second gate electrode. The first electrical connection structure electrically connects a first sub-gate electrode and a second sub-gate electrode via a third sub-gate electrode. The first sub-gate electrode and the second sub-gate electrode are disposed at a same level. The third sub-gate electrode is penetrated by the first contact plug and electrically insulated from the first contact plug and the memory channel structure.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0056611, filed on April 29, 2025, with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to the field of semiconductor memory devices, and more specifically, to memory devices and memory packages including memory devices. Background Technology

[0003] Semiconductor memory devices can be classified into two categories based on whether they retain stored data when disconnected from power. These categories include volatile memory devices and non-volatile memory devices. Volatile memory devices lose stored data when disconnected from power, while non-volatile memory devices retain stored data when disconnected from power. Although volatile memory devices can perform read and write operations at high speed, the content stored in them may be lost when power is off. Because non-volatile memory devices retain their stored content even when power is off, they can be used to store data that needs to be retained.

[0004] In electronic systems requiring data storage, high-capacity semiconductor memory devices capable of storing large amounts of data can be used. Therefore, several methods for increasing the data storage capacity of semiconductor memory devices have been investigated. Semiconductor memory devices comprising three-dimensionally stackable memory cells have been proposed.

[0005] Various methods have been studied to achieve miniaturization and high integration of semiconductor memory devices. Summary of the Invention

[0006] The example implementations generally relate to semiconductor integrated circuits, and more specifically, to memory devices and memory packages including memory devices. Semiconductor memory devices comprising three-dimensionally stackable memory cells are disclosed.

[0007] At least one exemplary embodiment of this disclosure provides a memory device capable of reducing size.

[0008] At least one exemplary embodiment of this disclosure provides a memory package including a memory device.

[0009] According to an example embodiment, a memory device includes: a gate electrode structure, a plurality of memory channel structures, a first contact plug, and a first electrical connection structure. The gate electrode structure is disposed on a first substrate and includes a plurality of gate electrodes, which are sequentially stacked and spaced apart from each other in a first direction perpendicular to the upper surface of the first substrate facing the gate electrode structure. Each of the plurality of gate electrodes extends in a second direction parallel to the upper surface of the first substrate. Each of the first gate electrodes, serving as the upper gate electrode among the plurality of gate electrodes, includes a plurality of sub-gate electrodes physically separated from each other. The plurality of memory channel structures extend through the gate electrode structure. The first contact plug partially extends through the gate electrode structure to contact the upper surface of a second gate electrode among the plurality of gate electrodes, and extends through a gate electrode disposed above the second gate electrode among the plurality of gate electrodes but is electrically insulated from the gate electrode disposed above the second gate electrode among the plurality of gate electrodes. The upper surface of the second gate electrode faces away from the upper surface of the first substrate. The first electrical connection structure electrically connects the first sub-gate electrode to the second sub-gate electrode via a third sub-gate electrode. The first and second sub-gate electrodes are disposed at the same level among the plurality of sub-gate electrodes. The third sub-gate electrode is penetrated by the first contact plug among the multiple sub-gate electrodes and is electrically insulated from the first contact plug and the multiple memory channel structures.

[0010] According to an example embodiment, a memory package includes: a base substrate and a plurality of memory chips stacked on the base substrate. Each of the plurality of memory chips includes a gate electrode structure, a plurality of memory channel structures, a first contact plug, and a first electrical connection structure. The gate electrode structure is disposed on the first substrate and includes a plurality of gate electrodes that are sequentially stacked and spaced apart from each other in a first direction perpendicular to the upper surface of the first substrate facing the gate electrode structure. Each of the plurality of gate electrodes extends in a second direction parallel to the upper surface of the first substrate. Each of the first gate electrodes, which is the upper gate electrode among the plurality of gate electrodes, includes a plurality of sub-gate electrodes that are physically separated from each other. The plurality of memory channel structures extend through the gate electrode structure. The first contact plug extends partially through the gate electrode structure to contact the upper surface of a second gate electrode among the plurality of gate electrodes, and extends through a gate electrode disposed above the second gate electrode among the plurality of gate electrodes but is electrically insulated from the gate electrode disposed above the second gate electrode among the plurality of gate electrodes. The upper surface of the second gate electrode faces away from the upper surface of the first substrate. The first electrical connection structure electrically connects the first sub-gate electrode to the second sub-gate electrode via a third sub-gate electrode. The first and second sub-gate electrodes are positioned at the same level among the multiple sub-gate electrodes. The third sub-gate electrode is penetrated by the first contact plug among the multiple sub-gate electrodes and is electrically insulated from the first contact plug and the multiple memory channel structures.

[0011] According to an example embodiment, a memory device includes: a first substrate, a gate electrode structure, a first memory channel structure, a second memory channel structure, a first contact plug, a first electrical connection structure, a first string of transmission transistors, a second string of transmission transistors, and a first string of ground transistors. The first substrate includes a first region, a second region, and a third region. The first and second regions are spaced apart from each other. The third region is disposed between the first and second regions. The gate electrode structure is disposed on the first, second, and third regions of the first substrate and includes a plurality of gate electrodes, which are sequentially stacked and spaced apart from each other in a first direction perpendicular to the upper surface of the first substrate facing the gate electrode structure. Each of the plurality of gate electrodes extends in a second direction parallel to the upper surface of the first substrate. Each of the first gate electrodes, serving as the upper gate electrode among the plurality of gate electrodes, includes a plurality of sub-gate electrodes physically separated from each other. The first memory channel structure is disposed on the first region of the first substrate and extends through the gate electrode structure. The second memory channel structure is disposed on the second region of the first substrate and extends through the gate electrode structure. A first contact plug is disposed on a third region of the first substrate, extending partially through the gate electrode structure to contact the upper surface of the second gate electrode among the plurality of gate electrodes, and extending through the gate electrode disposed above the second gate electrode among the plurality of gate electrodes but electrically insulated from the gate electrode disposed above the second gate electrode among the plurality of gate electrodes. The upper surface of the second gate electrode faces away from the upper surface of the first substrate. A first electrical connection structure electrically connects the first sub-gate electrode on the first region to the second sub-gate electrode on the second region via a third sub-gate electrode on the third region. The first and second sub-gate electrodes are spaced apart from each other and disposed at the same level among the plurality of sub-gate electrodes. The third sub-gate electrode is penetrated by the first contact plug among the plurality of sub-gate electrodes and is electrically insulated from the first contact plug, the first memory channel structure, and the second memory channel structure. The first and second sub-gate electrodes are electrically connected to each other and serve as a single string select line. A first string transmission transistor is connected to the string select line and is adjacent to the first sub-gate electrode. A second string transmission transistor is connected to the string select line and is adjacent to the second sub-gate electrode. A first string ground transistor is connected to the string select line and is adjacent to one of the first and second string transmission transistors.

[0012] In the memory device and memory package according to the example embodiments, the contact plug electrically connected to the gate electrode may be located at the center, except for the edge. Therefore, the gate electrode structure may not have a stepped or stepped shape, and the process for forming the gate electrode structure can be simplified.

[0013] Furthermore, in the memory device and memory package according to the example embodiments, the upper gate electrode can be physically separated into a plurality of sub-gate electrodes, and some of the sub-gate electrodes can be floating gate electrodes that are penetrated by contact plugs, electrically insulated from the contact plugs, and electrically insulated from the memory channel structure. Among the plurality of sub-gate electrodes, sub-gate electrodes disposed at the same level and spaced apart from each other can use one of the floating sub-gate electrodes and are electrically connected to each other using a first electrical connection structure. Therefore, the number of components used to drive the upper gate electrode can be reduced, and the size of the memory device can be reduced. Attached Figure Description

[0014] The illustrative, non-limiting exemplary embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0015] Figure 1 , Figure 2A , Figure 2B and Figure 3 This is a diagram illustrating a memory device according to an example embodiment.

[0016] Figure 4 This is a block diagram illustrating a memory device according to an example embodiment.

[0017] Figure 5 Is included Figure 4 A perspective view of an example memory block in a memory cell array of a memory device.

[0018] Figure 6 It shows a reference. Figure 5 The circuit diagram of the equivalent circuit of the described memory block.

[0019] Figure 7 It is shown that it includes Figure 4 A block diagram of an example address decoder in a memory device.

[0020] Figure 8 and Figure 9 It shows including Figure 7 An example diagram of a memory device with an address decoder.

[0021] Figure 10 , Figure 11 , Figure 12 and Figure 13 It is shown Figure 1 , Figure 2A , Figure 2B and Figure 3 An example illustration of a memory device.

[0022] Figure 14 It is shown that it includes Figure 4 A circuit diagram of an example memory block in a memory cell array of a memory device.

[0023] Figure 15 It is shown that it includes Figure 4 A block diagram of an example address decoder in a memory device.

[0024] Figure 16 It shows including Figure 15 An example diagram of a memory device with an address decoder.

[0025] Figure 17 and Figure 18 This is a diagram illustrating a memory device according to an example embodiment.

[0026] Figure 19 and Figure 20 This is a diagram illustrating a memory device according to an example embodiment.

[0027] Figure 21 and Figure 22 It is shown Figure 19 and Figure 20 An example illustration of a memory device.

[0028] Figure 23A and Figure 23B This is a diagram illustrating a memory package according to an example embodiment.

[0029] Figure 24 This is a block diagram illustrating a memory system according to an example implementation.

[0030] Figure 25 This is a cross-sectional view of a memory device according to an example embodiment. Detailed Implementation

[0031] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, similar reference numerals refer to similar elements.

[0032] In the following text, the vertical direction substantially perpendicular to the upper surface of the substrate may be referred to as the first direction DR1, and two intersecting directions among the horizontal directions substantially parallel to the upper surface of the substrate may be referred to as the second direction DR2 and the third direction DR3, respectively. For example, the second direction DR2 and the third direction DR3 may be substantially perpendicular to each other. In the accompanying drawings, each of the first direction DR1, the second direction DR2, and the third direction DR3 may include both the direction indicated by the arrow and the direction opposite to it. The first direction DR1, the second direction DR2, and the third direction DR3 may be referred to as the Z-axis direction, the X-axis direction, and the Y-axis direction, respectively.

[0033] Figure 1 , Figure 2A , Figure 2B and Figure 3 This is a diagram illustrating a memory device according to an example embodiment. For example, Figure 1 It is a plan view of the memory device, and Figure 2A , Figure 2B and Figure 3 They are along Figure 1 A sectional view taken from line I-I'.

[0034] Reference Figure 1 and Figure 2A The memory device includes a gate electrode structure disposed and / or formed on a first substrate 10, a plurality of memory channel structures MCS, a plurality of contact plugs CP, and a first electrical connection structure.

[0035] The first substrate 10 may include semiconductor materials, such as silicon, germanium, silicon-germanium, or III-V compound semiconductors, such as GaP, GaAs, GaSb, etc. In some example embodiments, the first substrate 10 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0036] The first substrate 10 may include a first region REG1, a second region REG2 spaced apart from the first region REG1, and a third region REG3 disposed between the first region REG1 and the second region REG2. For example, the first region REG1 and the second region REG2 may be cell regions in which memory cells and multiple memory channel structures MCS are disposed and / or formed, and the third region REG3 may be a region in which multiple contact plugs CP are disposed and / or formed to transmit electrical signals to word lines and ground select lines electrically connected to memory cells.

[0037] In some example embodiments, memory cells disposed on a first region REG1 and a second region REG2 may form a single memory block and / or a single block. Unlike conventional memory devices in which contact plugs surround or are disposed on both sides of a cell region, the memory device according to the example embodiments may have a plurality of contact plugs CP disposed between cell regions within a single memory block and / or a single block (e.g., between the first region REG1 and the second region REG2), or relatively closer to the center of the single memory block and / or the single block.

[0038] The gate electrode structure includes a plurality of gate electrodes 21a, 21b, 21c, 22a, 22b, 22c, 23, 24, 25 and 26 disposed on the first substrate 10.

[0039] Multiple gate electrodes 21a, 21b, 21c, 22a, 22b, 22c, 23, 24, 25 and 26 are stacked sequentially and spaced apart from each other in a first direction DR1. Each of the multiple gate electrodes 21a, 21b, 21c, 22a, 22b, 22c, 23, 24, 25 and 26 extends in a second direction DR2.

[0040] Multiple gate electrodes 21a, 21b, 21c, 22a, 22b, 22c, 23, 24, 25, and 26 may be disposed at multiple horizontal locations, which are spaced apart from each other in a first direction DR1. As mentioned herein, a horizontal location may refer to the height or vertical distance from a reference surface (e.g., the upper surface of the first substrate 10). A "lower horizontal location" is lower or smaller in height or distance from the same reference surface compared to a "higher horizontal location". For example, one gate electrode may be disposed at each horizontal location. For example, gate electrode 26 may be set at the lowest level, gate electrode 25 may be set at a level higher than the level of gate electrode 26, gate electrode 24 may be set at a level higher than the level of gate electrode 25, gate electrode 23 may be set at a level higher than the level of gate electrode 24, gate electrodes 22a, 22b and 22c may be set at the same level higher than the level of gate electrode 23, and gate electrodes 21a, 21b and 21c may be set at the same highest level higher than the levels of gate electrodes 22a, 22b and 22c.

[0041] Among the plurality of gate electrodes 21a, 21b, 21c, 22a, 22b, 22c, 23, 24, 25, and 26, each of the upper gate electrodes includes a plurality of sub-gate electrodes 21a, 21b, 21c, 22a, 22b, and 22c that are physically separated from each other. For example, the gate electrode at the highest level may include sub-gate electrodes 21a, 21b, and 21c that are physically separated from each other, and the gate electrode at a level below the sub-gate electrodes 21a, 21b, and 21c may include sub-gate electrodes 22a, 22b, and 22c that are physically separated from each other. For example, sub-gate electrodes 21a and 22a may be disposed on a first region REG1, sub-gate electrodes 21b and 22b may be disposed on a second region REG2, and sub-gate electrodes 21c and 22c may be disposed on a third region REG3.

[0042] In some example implementations, when the upper gate electrode is physically divided into a plurality of sub-gate electrodes 21a, 21b, 21c, 22a, 22b and 22c, the area of ​​each of the sub-gate electrodes 21a, 21b, 21c, 22a, 22b and 22c may be smaller than the area of ​​each of the gate electrodes 23, 24, 25 and 26 other than the upper gate electrode.

[0043] In some example implementations, the plurality of gate electrodes 21a, 21b, 21c, 22a, 22b, 22c, 23, 24, 25 and 26 may comprise metals with low resistance, such as tungsten, titanium, tantalum, platinum and the like.

[0044] In some example implementations, at least one gate electrode at a lower level (e.g., gate electrode 26) can be used as a ground select line for the memory device, at least one gate electrode at a higher level (e.g., a gate electrode including sub-gate electrodes 21a, 21b) can be used as a serial select line for the memory device, and gate electrodes at an intermediate level (e.g., gate electrodes 23 and 24) can be used as word lines for the memory device.

[0045] In some example implementations, when the multiple contact plugs CP are positioned relatively closer to the center of a single memory block and / or a single region as described above, the multiple gate electrodes 21a, 21b, 21c, 22a, 22b, 22c, 23, 24, 25, and 26 may extend in the second direction DR2 and may have a constant thickness in the first direction DR1. Furthermore, the gate electrodes 23, 24, 25, and 26, excluding the upper gate electrode which includes the sub-gate electrodes 21a, 21b, 21c, 22a, 22b, and 22c, may have substantially the same length in the second direction DR2. Therefore, the gate electrode structure may not have a stepped or stepped shape.

[0046] although Figure 2A An example is shown where six gate electrodes are stacked on a first direction DR1 and the two upper gate electrodes include physically separated sub-gate electrodes, but the example implementation is not limited thereto.

[0047] Multiple memory channel structures (MCS) extend into or through (or penetrate) the gate electrode structure. The multiple memory channel structures (MCS) may include a first memory channel structure 30a and a second memory channel structure 30b.

[0048] The first memory channel structure 30a may include: a first filling pattern 33a extending in a first direction DR1 and having a columnar shape; a first channel 32a covering the sidewalls and lower surface of the first filling pattern 33a and having a cup shape; and a first charge storage structure 31a on the outer sidewall of the first channel 32a. For example, the first memory channel structure 30a may be disposed on a first region REG1 and a first memory cell may be formed on the first region REG1 by the first memory channel structure 30a. The memory device may also include a first via 35a contacting the upper surface of the first memory channel structure 30a and a first wiring 37a contacting the upper surface of the first via 35a.

[0049] In some example implementations, although not shown in detail, the first charge storage structure 31a may include a first tunnel insulation pattern, a first charge storage pattern, and a first barrier pattern that are sequentially stacked in the horizontal direction from the outer sidewall of the first channel 32a.

[0050] Similarly, the second memory channel structure 30b may include: a second fill pattern 33b extending in the first direction DR1 and having a column shape; a second channel 32b covering the sidewalls and lower surface of the second fill pattern 33b and having a cup shape; and a second charge storage structure 31b on the outer sidewall of the second channel 32b. For example, the second memory channel structure 30b may be disposed on the second region REG2, and a second memory cell may be formed on the second region REG2 by the second memory channel structure 30b. The memory device may also include a second via 35b contacting the upper surface of the second memory channel structure 30b and a second wiring 37b contacting the upper surface of the second via 35b.

[0051] In some example implementations, each of the first channel 32a and the second channel 32b may include, for example, undoped polysilicon, each of the first fill pattern 33a and the second fill pattern 33b may include an oxide (e.g., silicon oxide), and each of the first charge storage structure 31a and the second charge storage structure 31b may include an oxide (e.g., silicon oxide) and a nitride (e.g., silicon nitride).

[0052] In some example embodiments, a plurality of first memory channel structures 30a may be spaced apart from each other on a first region REG1 of the first substrate 10 in a second direction DR2 and a third direction DR3, thereby forming a first memory channel structure array. Similarly, a plurality of second memory channel structures 30b may be spaced apart from each other on a second region REG2 of the first substrate 10 in a second direction DR2 and a third direction DR3, thereby forming a second memory channel structure array.

[0053] In some example implementations, a plurality of first wirings 37a may be spaced apart from each other on a first region REG1 of the first substrate 10 in a second direction DR2, and each of the plurality of first wirings 37a may extend on a third direction DR3. Similarly, a plurality of second wirings 37b may be spaced apart from each other on a second region REG2 of the first substrate 10 in a second direction DR2, and each of the plurality of second wirings 37b may extend on a third direction DR3.

[0054] In some example implementations, each of the first wiring 37a and the second wiring 37b can be used as a bit line of a memory device.

[0055] Multiple contact plugs CP extend partially through (or penetrate) the gate electrode structure. The multiple contact plugs CP may include contact plugs 42a, 42b, 42c, and 42d disposed on the third region REG3.

[0056] The contact plug 42a electrically contacts the upper surface of the gate electrode 23 and extends through the gate electrodes 21c and 22c on the gate electrode 23, but is electrically insulated from the gate electrodes 21c and 22c. For example, a spacer 41a may be formed on the sidewall of the contact plug 42a, and the contact plug 42a may be electrically insulated from the gate electrodes 21c and 22c by the spacer 41a. The memory device may also include a via 45a contacting the upper surface of the contact plug 42a and wiring 47a contacting the upper surface of the via 45a.

[0057] The contact plug 42b electrically contacts the upper surface of the gate electrode 24 and extends through the gate electrodes 21c, 22c, and 23 on the gate electrode 24, but is electrically insulated from the gate electrodes 21c, 22c, and 23. For example, a spacer 41b may be formed on the sidewall of the contact plug 42b, and the contact plug 42b may be electrically insulated from the gate electrodes 21c, 22c, and 23 by the spacer 41b. The memory device may also include a via 45b contacting the upper surface of the contact plug 42b and wiring 47b contacting the upper surface of the via 45b.

[0058] The contact plug 42c electrically contacts the upper surface of the gate electrode 25 and extends through the gate electrodes 21c, 22c, 23, and 24 on the gate electrode 25, but is electrically insulated from the gate electrodes 21c, 22c, 23, and 24. For example, a spacer 41c may be formed on the sidewall of the contact plug 42c, and the contact plug 42c may be electrically insulated from the gate electrodes 21c, 22c, 23, and 24 through the spacer 41c. The memory device may also include a via 45c contacting the upper surface of the contact plug 42c and wiring 47c contacting the upper surface of the via 45c.

[0059] The contact plug 42d electrically contacts the upper surface of the gate electrode 26 and extends through the gate electrodes 21c, 22c, 23, 24, and 25 on the gate electrode 26, but is electrically insulated from the gate electrodes 21c, 22c, 23, 24, and 25. For example, a spacer 41d may be formed on the sidewall of the contact plug 42d, and the contact plug 42d may be electrically insulated from the gate electrodes 21c, 22c, 23, 24, and 25 through the spacer 41d. The memory device may also include a via 45d contacting the upper surface of the contact plug 42d and wiring 47d contacting the upper surface of the via 45d.

[0060] In other words, each of the contact plugs 42a, 42b, 42c, and 42d is accessible to and electrically connected to the upper surface of the corresponding gate electrode included in the gate electrode structure. Each of the contact plugs 42a, 42b, 42c, and 42d may extend through other gate electrodes above the corresponding gate electrode, but may be electrically insulated from the other gate electrodes by corresponding spacers 41a, 41b, 41c, and 41d.

[0061] In some example embodiments, the lower surface of contact plug 42b may be lower than the lower surface of contact plug 42a, the lower surface of contact plug 42c may be lower than the lower surface of contact plug 42b, and the lower surface of contact plug 42d may be lower than the lower surface of contact plug 42c.

[0062] In some example embodiments, each of the contact plugs 42a, 42b, 42c and 42d, the vias 35a, 35b, 45a, 45b, 45c and 45d, and the wirings 37a, 37b, 47a, 47b, 47c and 47d may include a conductive material, such as a metal, a metal nitride, a metal silicide, etc. In some example embodiments, each of the spacers 41a, 41b, 41c and 41d may include an oxide, such as silicon oxide.

[0063] In some example implementations, the dimensions (e.g., diameter, radius, etc.) of each of the plurality of contact plugs CP in a plane or plan view may be larger than the dimensions of each of the plurality of memory channel structures MCS.

[0064] Among the multiple sub-gate electrodes 21a, 21b, 21c, 22a, 22b, and 22c that are included in the upper gate electrode and physically separated from each other, the sub-gate electrodes 21c and 22c disposed on the third region REG3 can be penetrated by and electrically insulated from the contact plugs 42a, 42b, 42c, and 42d, and are also electrically insulated from the memory channel structures 30a and 30b. In other words, the sub-gate electrodes 21c and 22c disposed on the third region REG3 can be floating gate electrodes that are electrically insulated from both the contact plugs 42a, 42b, 42c, and 42d and the memory channel structures 30a and 30b.

[0065] The first electrical connection structure electrically connects sub-gate electrodes 21a and 21b via sub-gate electrode 21c. Among the plurality of sub-gate electrodes 21a, 21b, 21c, 22a, 22b, and 22c, sub-gate electrodes 21a and 21b connected by the first electrical connection structure are positioned at the same horizontal level, spaced apart from each other, and respectively disposed on the first region REG1 and the second region REG2. Sub-gate electrode 21c is penetrated by contact plugs 42a, 42b, 42c, and 42d, and is electrically insulated from contact plugs 42a, 42b, 42c, and 42d and memory channel structures 30a and 30b.

[0066] The first electrical connection structure may include vias 51a, 51b, 53a and 53b and wiring 51c and 53c.

[0067] Via 51a can contact the upper surface of sub-gate electrode 21a, via 51b can contact the upper surface of sub-gate electrode 21c, and wiring 51c can contact the upper surfaces of vias 51a and 51b. Sub-gate electrodes 21a and 21c can be electrically connected to each other through vias 51a and 51b and wiring 51c. Vias 51a and 51b and wiring 51c can be referred to as a first-to-first electrical connection structure.

[0068] Via 53a can contact the upper surface of sub-gate electrode 21b, via 53b can contact the upper surface of sub-gate electrode 21c, and wiring 53c can contact the upper surfaces of vias 53a and 53b. Sub-gate electrodes 21b and 21c can be electrically connected to each other through vias 53a and 53b and wiring 53c. Vias 53a and 53b and wiring 53c can be referred to as a first-second electrical connection structure.

[0069] As described above, sub-gate electrodes 21a and 21c can be electrically connected to each other through a first-first electrical connection structure, sub-gate electrodes 21b and 21c can be electrically connected to each other through a first-second electrical connection structure, and finally sub-gate electrodes 21a and 21b can be electrically connected to each other via the first-first electrical connection structure, the first-second electrical connection structure, and sub-gate electrode 21c.

[0070] In some example implementations, each of the vias 51a, 51b, 53a and 53b and the wirings 51c and 53c may include a conductive material, such as a metal, a metal nitride, a metal silicide, etc.

[0071] In some example implementations, such as Figure 2A As shown, sub-gate electrodes 21a and 21b can be electrically connected to each other via sub-gate electrode 21c, which is disposed at the same level as them, and via a first electrical connection structure.

[0072] Although not in Figure 2AAs shown, however, sub-gate electrodes 22a and 22b may also be electrically connected to each other via sub-gate electrode 22c which is disposed at the same level as them, and the memory device may also include an electrical connection structure for their electrical connection.

[0073] In addition, although not in Figure 2A As shown, however, insulating material can be filled in the empty spaces between components.

[0074] In some example implementations, multiple gate electrode structures may be disposed on the third-direction DR3. For example, multiple dicing regions may be formed between the multiple gate electrode structures, multiple separation patterns may be formed through the multiple dicing regions, and the multiple gate electrode structures may be separated from and spaced apart from each other on the third-direction DR3 through the multiple separation patterns. The multiple dicing regions may be referred to as word line dicing regions.

[0075] Reference Figure 2B ,and Figure 2A Compared to the previous example, the construction of the first electrical connection structure can be partially modified. For brevity, the details are omitted. Figure 1 and Figure 2A The description is repetitive or overlapping.

[0076] The first electrical connection structure may further include vias 55a and 55b and wiring 55c. Via 55a may contact the upper surface of wiring 51c, via 55b may contact the upper surface of wiring 53c, and wiring 55c may contact the upper surfaces of vias 55a and 55b. The first-to-first electrical connection structure and the first-to-second electrical connection structure can be electrically connected vias 55a and 55b and wiring 55c. Vias 55a and 55b and wiring 55c may be referred to as the first-to-third electrical connection structure.

[0077] In some example implementations, such as Figure 2B As shown, the first-third electrical connection structure may be additionally configured and / or formed to electrically connect the first-first electrical connection structure and the first-second electrical connection structure to each other.

[0078] Reference Figure 3 ,and Figure 2A Compared to the previous example, the construction of the first electrical connection structure can be partially modified. For brevity, the details are omitted. Figure 1 and Figure 2A The description is repetitive or overlapping.

[0079] The first electrical connection structure electrically connects sub-gate electrode 21a and sub-gate electrode 21b via sub-gate electrode 22c, and may include vias 51a, 52b, 53a, and 54b, and wirings 51c and 53c. Via 52b may contact the upper surface of sub-gate electrode 22c, and wiring 51c may contact the upper surfaces of vias 51a and 52b. Via 54b may contact the upper surface of sub-gate electrode 22c, and wiring 53c may contact the upper surfaces of vias 53a and 54b.

[0080] In some example implementations, such as Figure 3 As shown, sub-gate electrodes 21a and 21b are electrically connected to each other via sub-gate electrode 22c disposed at a different level and via a first electrical connection structure. Although not shown in... Figure 3 As shown, however, sub-gate electrodes 22a and 22b can be electrically connected to each other via sub-gate electrodes 21c disposed at different levels from them.

[0081] In the memory device according to the example embodiment, contact plugs 42a, 42b, 42c, and 42d electrically connected to gate electrodes 23, 24, 25, and 26 may be provided at the center other than the edges. Therefore, the gate electrode structure may not have a stepped or stepped shape, and the process for forming the gate electrode structure can be simplified.

[0082] Furthermore, in the memory device according to the example embodiment, the upper gate electrode can be physically separated into a plurality of sub-gate electrodes 21a, 21b, 21c, 22a, 22b, and 22c, and some of the sub-gate electrodes 21c and 22c can be floating gate electrodes that are penetrated by contact plugs 42a, 42b, 42c, and 42d, electrically insulated from the contact plugs 42a, 42b, 42c, and 42d, and electrically insulated from the memory channel structures 30a and 30b. Among the plurality of sub-gate electrodes 21a, 21b, 21c, 22a, 22b, and 22c, sub-gate electrodes 21a and 21b disposed at the same level and spaced apart from each other can use one of the floating sub-gate electrodes 21c and 22c and are electrically connected to each other using a first electrical connection structure. Therefore, the number of components used to drive the upper gate electrode can be reduced, and the size of the memory device can be reduced.

[0083] Figure 4 This is a block diagram illustrating a memory device according to an example embodiment.

[0084] Reference Figure 4 The memory device 500 includes a memory cell array 510, an address decoder 520, a page buffer circuit 530, a data input / output (I / O) circuit 540, a voltage generator 550, and a control circuit 560. For example, the memory device 500 may be a non-volatile memory device, such as a NAND flash memory device.

[0085] The memory cell array 510 can be connected to the address decoder 520 via multiple serial select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). The memory cell array 510 can also be connected to the page buffer circuit 530 via multiple bit lines (BL). The memory cell array 510 may include multiple memory cells (e.g., multiple non-volatile memory cells) connected to the multiple word lines (WL) and multiple bit lines (BL). The memory cell array 510 can be divided into multiple memory blocks BLK1, BLK2, ..., BLKz (where z is any positive integer), each of which includes memory cells. Furthermore, each of the multiple memory blocks BLK1, BLK2, ..., BLKz can be divided into multiple pages.

[0086] In some example implementations, such as referring to Figure 5 and Figure 6 In more detail, the memory cell array 510 may be a three-dimensional memory cell array, which may be formed on a substrate in a three-dimensional structure (or a vertical structure). In this example, the memory cell array 510 may include multiple cell strings (e.g., multiple vertical NAND strings) that are vertically oriented such that at least one memory cell is located above another memory cell.

[0087] Control circuitry 560 may receive commands CMD and addresses ADDR from outside the memory device 500 (e.g., from a host device and / or a memory controller), and control circuitry 560 may be configured to control erase, programming, and read operations of the memory device 500 based on commands CMD and addresses ADDR. Erasing operations may include executing a series of erase cycles, and programming operations may include executing a series of programming cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. Read operations may include normal read operations and data recovery read operations.

[0088] In some example implementations, control circuitry 560 can generate a control signal CON that can be used to control voltage generator 550, and control circuitry 560 can generate a control signal PBC that can be used to control page buffer circuitry 530 based on command CMD. Control circuitry 560 can generate row address R_ADDR and column address C_ADDR based on address ADDR. Control circuitry 560 can provide row address R_ADDR to address decoder 520 and can provide column address C_ADDR to data I / O circuitry 540.

[0089] Address decoder 520 may be connected to memory cell array 510 via multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL. In some example embodiments, during data erase / write / read operations, address decoder 520 may determine at least one of the multiple word lines WL as the selected word line, at least one of the multiple serial select lines SSL as the selected serial select line, and at least one of the multiple ground select lines GSL as the selected ground select line based on row address R_ADDR. Address decoder 520 may include multiple transfer transistors (PT) 522 and driver circuitry (DRV) 524 for driving the multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL. (See also...) Figure 7 A more detailed configuration of the multiple transmission transistors 522 and driver circuitry 524 is described.

[0090] Voltage generator 550 can generate a voltage VD for operation of memory device 500 based on power PWR and control signal CON. Voltage VD can be applied via address decoder 520 to multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL. Additionally, voltage generator 550 can generate an erase voltage VERS for data erase operations based on power PWR and control signal CON.

[0091] Page buffer circuit 530 may be connected to memory cell array 510 via multiple bit lines BL. Page buffer circuit 530 may include multiple page buffers. Page buffer circuit 530 may store data DAT to be programmed into memory cell array 510, or may read data DAT sensed from memory cell array 510. In other words, page buffer circuit 530 may operate as a write driver and / or sense amplifier depending on the operating mode of memory device 500.

[0092] Data I / O circuit 540 can be connected to page buffer circuit 530 via data line DL. Data I / O circuit 540 can provide data DAT from outside the memory device 500 to memory cell array 510 via page buffer circuit 530 based on column address C_ADDR, or it can provide data DAT from memory cell array 510 to outside the memory device 500.

[0093] Figure 5 Is included Figure 4 A perspective view of an example memory block in a memory cell array of a memory device.

[0094] Reference Figure 5The memory block BLKi may include multiple cell strings (e.g., multiple vertical NAND strings) that can be formed on a substrate in a three-dimensional (or vertical) structure. The memory block BLKi may include a structure extending along a first direction DR1, a second direction DR2, and a third direction DR3. For example, the memory block BLKi may correspond to... Figure 1 It is a part of the first region REG1 or a part of the second region REG2.

[0095] Base 111 can be set (e.g., as shown in the image) Figure 19 As shown in the diagram, the upper substrate of the first semiconductor layer L1. In some example embodiments, the substrate 111 may have a well therein containing a first type of charge carrier impurity (e.g., a first conductivity type). In some example embodiments, the substrate 111 may have a p-well formed by implanting a group 3(III) element such as boron (B). However, the conductivity type of the substrate 111 is not limited to p-type.

[0096] A plurality of doped regions 311, 312, 313, and 314 arranged along the third direction DR3 are disposed in / on the substrate 111. These plurality of doped regions 311 to 314 may have a second type of charge carrier impurity (e.g., a second conductivity type) different from a first type of the substrate 111. In some example embodiments, the first doped regions 311 to the fourth doped regions 314 may be n-type. However, the conductivity type of the first doped regions 311 to the fourth doped regions 314 is not limited to n-type.

[0097] A plurality of insulating materials 112 extending along a second direction DR2 are sequentially disposed along a first direction DR1 in the region between a first doped region 311 and a second doped region 312 of a substrate 111. In some example embodiments, the plurality of insulating materials 112 are disposed on the first direction DR1 and spaced apart by a specific distance. In some example embodiments, the insulating materials 112 may include insulating materials such as oxide layers.

[0098] A plurality of pillars 113, penetrating or extending through the insulating material 112 along a first direction DR1, are sequentially arranged and spaced apart along a second direction DR2 in the region between the first doped region 311 and the second doped region 312 of the substrate 111. In some example embodiments, the plurality of pillars 113 may penetrate the insulating material 112 and may contact the substrate 111.

[0099] In some example embodiments, each pillar 113 may include multiple materials. In some example embodiments, each pillar 113 may include a channel layer 114 and an internal material 115. The channel layer 114 of each pillar 113 may include a silicon material having a first conductivity type. In some example embodiments, the channel layer 114 of each pillar 113 may include a silicon material having the same conductivity type as the substrate 111. In some example embodiments, the channel layer 114 of each pillar 113 includes p-type silicon. However, the channel layer 114 of each pillar 113 is not limited to p-type silicon. The internal material 115 of each pillar 113 includes an insulating material. In some example embodiments, the internal material 115 of each pillar 113 may include an insulating material such as silicon oxide. In some examples, the internal material 115 of each pillar 113 may include an air gap. As discussed herein, the term "air" may refer to air or other gases that may be present during the manufacturing process.

[0100] An insulating layer 116 may be disposed along the exposed surfaces of the insulating material 112, the pillar 113, and the substrate 111 in the region between the first doped region 311 and the second doped region 312. In some example embodiments, as shown, the insulating layer 116 disposed on the surface of the insulating material 112 may be positioned between the pillar 113 and a plurality of stacked first conductive materials 211, 221, 231, 241, 251, 261, 271, 281, and 291. In some examples, the insulating layer 116 may not be disposed and may not be present between the first conductive materials 211 and 291 corresponding to the ground select line GSL (e.g., 211) and the string select line SSL (e.g., 291) and the pillar 113. In this example, the ground select line GSL is the bottommost line in the stack of the first conductive materials 211 to 291, and the string select line SSL is the topmost line in the stack of the first conductive materials 211 to 291.

[0101] Multiple first conductive materials 211 to 291 may be disposed on the surface of the insulating layer 116 in the region between the first doped region 311 and the second doped region 312. In some example embodiments, the first conductive material 211 extending along the second direction DR2 may be disposed between the insulating material 112 adjacent to the substrate 111 and the substrate 111. More specifically, the first conductive material 211 extending along the second direction DR2 is disposed between the insulating layer 116 at the bottom of the insulating material 112 adjacent to the substrate 111 and the substrate 111.

[0102] A first conductive material extending along the second direction DR2 may be disposed between an insulating layer 116 at the top of a specific insulating material within the insulating material 112 and an insulating layer 116 at the bottom of a specific insulating material within the insulating material 112. In some example embodiments, a plurality of first conductive materials 221 to 281 extending along the second direction DR2 may be disposed between the insulating materials 112, and it is understood that the insulating layer 116 is disposed between the insulating materials 112 and the first conductive materials 221 to 281. The first conductive materials 211 to 291 may be formed of a conductive metal, but in other embodiments, the first conductive materials 211 to 291 may comprise a conductive material such as polycrystalline silicon.

[0103] A structure identical to the structure in the region between the first doped region 311 and the second doped region 312 can be provided in the region between the second doped region 312 and the third doped region 313. In the region between the second doped region 312 and the third doped region 313, a plurality of insulating materials 112 extending along the second direction DR2 are provided. Additionally, a plurality of pillars 113 arranged sequentially along the second direction DR2 and penetrating or extending through the plurality of insulating materials 112 along the first direction DR1 can be provided. An insulating layer 116 can be provided on the exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, and a plurality of first conductive materials 211 to 291 can extend along the second direction DR2. Similarly, a structure identical to the structure in the region between the first doped region 311 and the second doped region 312 can be provided in the region between the third doped region 313 and the fourth doped region 314.

[0104] Multiple drain regions may be disposed on multiple pillars 113. Drain regions 320 may comprise silicon material doped with a second type of charge carrier impurity. In some example embodiments, drain regions 320 may comprise silicon material doped with an n-type dopant. In some example embodiments, drain regions 320 comprise n-type silicon material. However, drain regions 320 are not limited to n-type silicon material.

[0105] On the drain region, a plurality of second conductive materials 331, 332, and 333 extending along a third direction DR3 are provided. The second conductive materials 331 to 333 may be arranged along a second direction DR2, spaced apart from each other by a specific distance. The second conductive materials 331 to 333 are respectively connected to the drain region 320 in their respective regions. The second conductive materials 333 extending along the third direction DR3 and the drain region 320 may be connected via each contact plug. In some example embodiments, each contact plug may be a conductive plug formed of a conductive material such as metal. The second conductive materials 331 to 333 may include metallic materials. The second conductive materials 331 to 333 may include conductive materials such as polysilicon.

[0106] exist Figure 5 In the examples, first conductive materials 211 to 291 can be used to form word lines WL, serial select lines SSL, and ground select lines GSL, respectively. In some example embodiments, first conductive materials 221 to 281 can be used to form word lines WL, wherein conductive materials belonging to the same layer can be interconnected. Second conductive materials 331 to 333 can be used to form bit lines BL. The number of layers of first conductive materials 211 to 291 can be varied depending on the process and control techniques.

[0107] Figure 6 It shows a reference. Figure 5 The circuit diagram of the equivalent circuit of the described memory block.

[0108] Figure 6 The memory block BLKi can be formed on the substrate in a three-dimensional (or vertical) structure. In some example implementations, multiple NAND strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate.

[0109] Reference Figure 6 The memory block BLKi may include multiple NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 connected between bit lines BL1, BL2, and BL3 and the common-source line CSL. Each of the NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a ground select transistor GST. In some example embodiments, bit lines BL1 to BL3 may correspond to Figure 5 The second conductive material 331 to 333 in the middle, and the common source electrode CSL can be used to... Figure 5 The first doped region 311 to the fourth doped region 314 are interconnected to form the structure.

[0110] Each string select transistor (SST) can be connected to a corresponding string select line (one of SSL1, SSL2, and SSL3). Multiple memory cells MC1 through MC8 can be connected to corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, respectively. Each ground select transistor (GST) can be connected to a corresponding ground select line (one of GSL1, GSL2, and GSL3). Each string select transistor (SST) can be connected to a corresponding bit line (e.g., one of BL1 through BL3), and each ground select transistor (GST) can be connected to the common-source line CSL. Figure 6In the example, some of the string select transistors SST are connected to the same bit line (e.g., one of BL1 to BL3) to connect the corresponding NAND strings to the same bit line under appropriate selection via select voltages applied to the appropriate string select lines SSL1 to SSL3 and ground select lines GSL1 to GSL3.

[0111] Strings of cells connected to a single bit line can form a column, and strings of cells connected to a single string select line can form a row. In some example implementations, strings of cells NS11, NS21, and NS31 connected to the first bit line BL1 can correspond to the first column, and strings of cells NS11, NS12, and NS13 connected to the first string select line SSL1 can form the first row.

[0112] Word lines of the same height (e.g., WL1) can be connected together, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separate. Memory cells located on the same semiconductor layer share word lines. Strings of cells in the same row share string select lines. All string of cells are connected together to the common source line CSL.

[0113] exist Figure 6 In the example, memory block BLKi is shown connected to eight word lines WL1 to WL8 and three bit lines BL1 to BL3, and each of the NAND strings NS11 to NS33 is shown to include eight memory cells MC1 to MC8. However, the example implementation is not limited to this. In some example implementations, each memory block may be connected to any number of word lines and bit lines, and each NAND string may include any number of memory cells.

[0114] A three-dimensional vertical array structure may include vertically oriented NAND strings such that at least one memory cell is situated above another memory cell. At least one memory cell may include a charge trapping layer. Suitable configurations for memory cell arrays comprising a 3D vertical array structure, in which the three-dimensional memory array is configured as a plurality of horizontals sharing word lines and / or bit lines, are described by reference in the following patent documents, which are incorporated herein by reference in their entirety: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0115] although Figure 6 An example is shown where each cell string includes a string selection transistor (SST), but the example implementation is not limited to this.

[0116] In some example implementations, each cell string may include two or more string select transistors (SSTs) and may be connected to two or more string select lines. In some example implementations, at least one of the two or more string select transistors (SSTs) adjacent to a bit line may be used as a GIDL string select transistor for erasing data using the gate-induced drain leakage (GIDL) phenomenon, and the string select line connected to the GIDL string select transistor may be used as a GIDL string select line.

[0117] Figure 7 It is shown that it includes Figure 4 A block diagram of an example address decoder in a memory device.

[0118] Reference Figure 7 The address decoder 600 can be connected to the memory cell array 510 via the serial select line SSL, word lines WL1, ..., WLn and the ground select line GSL, and may include a transmission switch circuit 610 and a driver circuit 620. The address decoder 600 may be referred to as a row decoder, word line decoder, etc.

[0119] The transmission switch circuit 610 may include a plurality of transmission transistors SPT, WPT1, ..., WPTn and GPT. For example, the plurality of transmission transistors SPT, WPT1 to WPTn and GPT may include a string transmission transistor SPT connected to the string select line SSL, word line transmission transistors WPT1 to WPTn connected to word lines WL1 to WLn and a ground transmission transistor GPT connected to the ground select line GSL.

[0120] The driver circuit 620 can control the switching operations of multiple transfer transistors SPT, WPT1 to WPTn and GPT, and can also control the supply of voltages VS, VW1, ..., VWn, VG to the memory cell array 510 through the multiple transfer transistors SPT, WPT1 to WPTn and GPT. For example, the switching operations of the multiple transfer transistors SPT, WPT1 to WPTn and GPT can be controlled by multiple switch control signals SCS, and the timing of the application of voltages VS, VW1 to VWn, VG to the memory cell array 510 can be controlled by the switching operations of the multiple transfer transistors SPT, WPT1 to WPTn and GPT.

[0121] The memory device may also include a series ground transistor SGT connected to the series select line SSL. For example, the switching operation of the series ground transistor SGT may be controlled by a ground control signal GCS provided from the driver circuit 620, and the series ground transistor SGT may be supplied with a ground voltage for discharging unselected strings in response to the ground control signal GCS.

[0122] Although memory cell arrays and memory devices according to some example embodiments have been described based on NAND flash memory devices, the memory devices according to some example embodiments can be any non-volatile memory device, such as phase-change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc.

[0123] Figure 8 and Figure 9 It shows including Figure 7 An example diagram of a memory device with an address decoder.

[0124] Reference Figure 8 and Figure 9 , showed Figure 2A An example of a memory device in which sub-gate electrodes 21a and 21b are electrically connected to each other via sub-gate electrode 21c and a first electrical connection structure and are used as a single string select line.

[0125] In some example implementations, such as Figure 8 As shown, the memory device may further include a first string of transmission transistors SPT1, a second string of transmission transistors SPT2, and a first string of ground transistors SGT1.

[0126] The first string of transmission transistors, SPT1, can be connected to the string select line and can be configured and connected to be adjacent to the sub-gate electrode 21a. "Adjacent to sub-gate electrode 21a" means closer to the sub-gate electrode 21a than "adjacent to sub-gate electrode 21b". The second string of transmission transistors, SPT2, can be connected to the string select line and can be configured and connected to be adjacent to the sub-gate electrode 21b. "Adjacent to sub-gate electrode 21b" means closer to the sub-gate electrode 21b than "adjacent to sub-gate electrode 21a". The first string of ground transistors, SGT1, can be connected to the string select line and can be configured and connected to be adjacent to the first string of transmission transistors, SPT1. "Adjacent to the first string of transmission transistors, SPT1" means closer to the first string of transmission transistors, SPT1, than "adjacent to the second string of transmission transistors, SPT2".

[0127] Although not shown in detail, it includes two string transmission transistors and one string ground transistor. Figure 8 In the example, the first string of ground transistors SGT1 can be configured and connected to be adjacent to the second string of transmission transistors SPT2. Adjacent to the second string of transmission transistors SPT2 can mean being closer to the second string of transmission transistors SPT2 than being closer to the first string of transmission transistors SPT1.

[0128] In some example implementations, such as Figure 9As shown, the memory device may further include a first string of transmission transistors SPT1 and a first string of ground transistors SGT1. The first string of transmission transistors SPT1 and the first string of ground transistors SGT1 may be connected to a reference... Figure 8 The first string of transmission transistors SPT1 and the first string of ground transistors SGT1 are essentially the same.

[0129] Although not shown in detail, it includes a string transmission transistor and a string ground transistor. Figure 9 In the example, the first string of transmission transistors SPT1 and the first string of ground transistors SGT1 may be configured and connected to be adjacent to the sub-gate electrode 21b. "Adjacent to the sub-gate electrode 21b" can mean closer to the sub-gate electrode 21b than to the sub-gate electrode 21a. In some embodiments, the first string of transmission transistors SPT1 may be configured and connected to be adjacent to one of the sub-gate electrodes 21a and 21b, and the first string of ground transistors SGT1 may be configured and connected to be adjacent to the other of the sub-gate electrodes 21a and 21b. "Adjacent to one of the sub-gate electrodes 21a and 21b" means closer to the first sub-gate electrode than to the second sub-gate electrode.

[0130] When the sub-gate electrodes 21a and 21b are not electrically connected to each other, for example, when the memory device does not include the first electrical connection structure according to the exemplary embodiment, each of the sub-gate electrodes 21a and 21b can operate as a separate string select line, and a string pass transistor and a string ground transistor may be required to drive each string select line. In other words, two string pass transistors and two string ground transistors should be required.

[0131] Conversely, according to the example embodiment, when sub-gate electrodes 21a and 21b are electrically connected to each other via sub-gate electrode 21c and the first electrical connection structure, sub-gate electrodes 21a and 21b can operate as a single string select line. Therefore, in the above-described two string transmission transistors and two string ground transistors, as follows... Figure 8 The diagram omits a series-grounded transistor and can be interpreted as follows: Figure 9 The diagram omits one string pass transistor and one string ground transistor. Therefore, the number of components used to drive the string select line can be reduced, and the size of the memory device can be decreased.

[0132] Figure 10 , Figure 11 , Figure 12 and Figure 13 It is shown Figure 1 , Figure 2A , Figure 2B and Figure 3 An example illustration of a memory device. For example, Figure 10 yes Figure 1 A floor plan of the first region REG1 in the example. Figure 11 yes Figure 10 A perspective view of the gate electrode structure on the first region REG1 in the image. Figure 12 yes Figure 1 A floor plan of the third region REG3 in the example, and Figure 13 yes Figure 12 A perspective view of the gate electrode structure on the third region REG3.

[0133] Reference Figure 10 and Figure 11 In the first region REG1, sub-gate electrodes 21a and 22a can be separated into multiple parts by multiple cutting regions C1a, C1b, C1c, C1d, C1e, and C1f. For example, multiple separation patterns can be formed by multiple cutting regions C1a, C1b, C1c, C1d, C1e, and C1f, and sub-gate electrodes 21a and 22a can be separated from each other and spaced apart from each other on the third-direction DR3 by multiple separation patterns.

[0134] Therefore, unlike the gate electrodes GE3, GE4, GE5, and GE6, which correspond to gate electrodes 23, 24, 25, and 26 and are formed as a single portion at a single level, sub-gate electrode 21a can be divided into multiple portions, such as seven portions GE11, GE12, GE13, GE14, GE15, GE16, and GE17, and sub-gate electrode 22a can be divided into multiple portions, such as seven portions GE21, GE22, GE23, GE24, GE25, GE26, and GE27. For example, the area of ​​each of the multiple portions GE11, GE12, GE13, GE14, GE15, GE16, GE17, GE21, GE22, GE23, GE24, GE25, GE26, and GE27 can be smaller than the area of ​​each of the sub-gate electrodes 21a and 22a.

[0135] In some example implementations, gate electrodes GE3, GE4, GE5, and GE6 can be used as word lines and ground select lines, and multiple portions of sub-gate electrodes 21a and 22a, GE11, GE12, GE13, GE14, GE15, GE16, GE17, GE21, GE22, GE23, GE24, GE25, GE26, and GE27, can be used as string select lines. In this example, multiple cut regions C1a, C1b, C1c, C1d, C1e, and C1f can be referred to as string select line cut regions.

[0136] In some example implementations, at least some portions of the memory channel structure MCS may also be cut by multiple cut regions C1a, C1b, C1c, C1d, C1e, and C1f.

[0137] Although not in Figure 10 and Figure 11As shown, however, similar to the first region REG1, in the second region REG2, each of the sub-gate electrodes 21b and 22b can be divided into multiple parts, such as seven parts.

[0138] In some example implementations, a portion (e.g., portion GE11) of the sub-gate electrodes 21a and 22a on the first region REG1 and a portion of their corresponding (e.g., located at the same level and in the same position) of the sub-gate electrodes 21b and 22b on the second region REG2 can be electrically connected to each other via the sub-gate electrode 21c and the first electrical connection structure, and can be used as a single string select line.

[0139] Reference Figure 12 and Figure 13 In the third region REG3, sub-gate electrodes 21c and 22c can be separated into multiple parts by multiple cutting regions C2a and C2b. For example, multiple separation patterns can be formed by multiple cutting regions C2a and C2b, and sub-gate electrodes 21c and 22c can be separated from each other and spaced apart by multiple separation patterns on the third direction DR3.

[0140] Therefore, sub-gate electrode 21c can be separated into multiple parts, such as three parts GE1a, GE1b, and GE1c, and sub-gate electrode 22c can be separated into multiple parts, such as three parts GE2a, GE2b, and GE2c. For example, the area of ​​each of the multiple parts GE1a, GE1b, GE1c, GE2a, GE2b, and GE2c can be smaller than the area of ​​each of sub-gate electrodes 21c and 22c.

[0141] In some example implementations, multiple cut regions C2a and C2b may be formed without cutting multiple contact plugs CP.

[0142] In some example implementations, sub-gate electrodes 21a and 21b at the same level may be electrically connected to each other via a portion of sub-gate electrodes 21c and 22c (e.g., a portion of GE1a) and a first electrical connection structure, and may be used as a single string select line.

[0143] In some example implementations, it can be achieved through combination Figure 10 and Figure 11 Examples and Figure 12 and Figure 13 Examples are provided to implement the memory device according to the example implementation. For example, portions GE11 on the first region REG1 and corresponding portions on the second region REG2, which are located at the same level and at the same position, can be electrically connected to each other via portions GE1a, and portions GE12 on the first region REG1 and corresponding portions on the second region REG2, which are located at the same level and at the same position, can be electrically connected to each other via portions GE1b.

[0144] although Figure 10 , Figure 11 , Figure 12 and Figure 13 A specific number of cutting regions C1a, C1b, C1c, C1d, C1e, C1f, C2a, and C2b are shown, as well as a specific number of portions GE11, GE12, GE13, GE14, GE15, GE16, GE17, GE21, GE22, GE23, GE24, GE25, GE26, GE27, GE1a, GE1b, GE1c, GE2a, GE2b, and GE2c separated by the cutting regions C1a, C1b, C1c, C1d, C1e, C1f, C2a, and C2b, but the example implementation is not limited thereto.

[0145] Figure 14 It is shown that it includes Figure 4 A circuit diagram of an example memory block in a memory cell array of a memory device.

[0146] For ease of explanation, Figure 14 A two-dimensional version of a memory block comprising multiple cell strings NS11, NS12, ..., NS1m connected to a bit line BL and a common-source line CSL is shown. However, it will be understood that the memory block may have the following characteristics as shown in the reference diagram. Figure 5 and Figure 6 The three-dimensional structure of multiple bit lines is described.

[0147] Reference Figure 14 The memory block may include multiple cell strings NS11 to NS1m connected together between the bit line BL and the common source line CSL, where m is a positive integer. Cell strings NS11 to NS1m may respectively include GIDL string select transistors controlled by GIDL string select lines GDSSL11, GDSSL12, ..., GDSSL1m, string select transistors controlled by string select lines SSL11, SSL12, ..., SSL1m, memory cells controlled by word lines WL1, WL2, ..., WLn-1, WLn, and ground select transistors controlled by ground select lines GSL11, GSL12, ..., GSL1m.

[0148] The GIDL string select lines GDSSL11 to GDSSL1m and the GIDL string select transistors connected to the GIDL string select lines GDSSL1 to GDSSL1m can be used to erase data stored in the memory block during an erase operation using the GIDL phenomenon.

[0149] Figure 15 It is shown that it includes Figure 4 A block diagram illustrating an example address decoder in a memory device. For brevity, the symbols and symbols are omitted. Figure 7 The description is repetitive or overlapping.

[0150] Reference Figure 15 The address decoder 602 can be connected to the memory cell array 510 via the GIDL serial select line GDSSL, the serial select line SSL, the word line WL1, ..., WLn and the ground select line GSL, and may include a transmission switch circuit 612 and a driver circuit 622.

[0151] The transmission switch circuit 612 may also include a GIDL string transmission transistor GSPT connected to the GIDL string select line GDSSL.

[0152] The driver circuit 622 can control the switching operation of the GIDL string transmission transistor GSPT through multiple switch control signals SCS, and can control the timing of applying voltage VGD to the memory cell array 510 through the switching operation of the GIDL string transmission transistor GSPT.

[0153] Figure 16 It shows including Figure 15 An example diagram of a memory device with an address decoder. For simplicity, the symbols and symbols are omitted. Figure 2A The description is repetitive or overlapping.

[0154] Reference Figure 16 , showing Figure 2A An example of a memory device in which sub-gate electrodes 21a and 21b are electrically connected to each other via sub-gate electrode 21c and a first electrical connection structure and are used as a single GIDL string select line.

[0155] In some example embodiments, the memory device may further include a first GIDL string transfer transistor GSPT1. The first GIDL string transfer transistor GSPT1 may be connected to the GIDL string select line and may be configured and connected to be adjacent to the sub-gate electrode 21a. "Adjacent to the sub-gate electrode 21a" means closer to the sub-gate electrode 21a than to the sub-gate electrode 21b.

[0156] Although not shown in detail, the first GIDL string transmission transistor GSPT1 may be configured and connected to be adjacent to the sub-gate electrode 21b. Adjacent to the sub-gate electrode 21b may mean being closer to the sub-gate electrode 21b than being closer to the sub-gate electrode 21a.

[0157] When the sub-gate electrodes 21a and 21b are not electrically connected to each other, each of the sub-gate electrodes 21a and 21b operates as a separate GIDL string select line, and two GIDL string transfer transistors may be required to drive each GIDL string select line.

[0158] Conversely, according to the example embodiment, when sub-gate electrodes 21a and 21b are electrically connected to each other via sub-gate electrode 21c and the first electrical connection structure, sub-gate electrodes 21a and 21b can operate as a single GIDL string select line. Therefore, one of the two GIDL string transmission transistors can be omitted, thereby reducing the number of components used to drive the GIDL string select line and reducing the size of the memory device.

[0159] Figure 17 and Figure 18 This is a diagram illustrating a memory device according to an example embodiment. For example, Figure 17 It is a plan view of the memory device, and Figure 18 It is along Figure 17 The sectional view taken from line II-II'. For the sake of brevity, the section view is omitted. Figure 1 and Figure 2A The description is repetitive or overlapping.

[0160] Reference Figure 17 and Figure 18 The memory device includes a gate electrode structure disposed and / or formed on a first substrate 10, a plurality of memory channel structures MCS, a plurality of contact plugs CP, and a first electrical connection structure and a second electrical connection structure.

[0161] The first substrate 10 may include a first region EG1, a second region REG2, and a third region REG3, and may also include a fourth region REG4 spaced apart from the second region REG2 and a fifth region REG5 disposed between the second region REG2 and the fourth region REG4. Similar to the first region REG1 and the second region REG2, the fourth region REG4 may be a cell region in which a plurality of memory channel structures (MCS) are disposed and / or formed. Similar to the third region REG3, the fifth region REG5 may be a region in which a plurality of contact plugs (CP) are disposed and / or formed.

[0162] The gate electrode structure includes multiple gate electrodes 21a, 21b, 21c, 21d, 21e, 22a, 22b, 22c, 22d, 22e, 23, 24, 25, and 26. For example, the gate electrode at the highest level may include sub-gate electrodes 21a, 21b, 21c, 21d, and 21e that are physically separated from each other, and the gate electrode at a level below the sub-gate electrodes 21a, 21b, 21c, 21d, and 21e may include sub-gate electrodes 22a, 22b, 22c, 22d, and 22e that are physically separated from each other. For example, sub-gate electrodes 21d and 22d may be disposed on a fourth region REG4, and sub-gate electrodes 21e and 22e may be disposed on a fifth region REG5.

[0163] The multiple memory channel structure (MCS) may further include a third memory channel structure 30d. The third memory channel structure 30d may include: a third fill pattern 33d extending in the first direction DR1 and having a column shape; a third channel 32d covering the sidewalls and lower surface of the third fill pattern 33d and having a cup shape; and a third charge storage structure 31d on the outer sidewall of the third channel 32d. The memory device may also include a third via 35d contacting the upper surface of the third memory channel structure 30d and a third wiring 37d contacting the upper surface of the third via 35d.

[0164] The plurality of contact plugs CP may further include contact plugs 62a, 62b, 62c, and 62d disposed on the fifth region REG5. Contact plugs 62a, 62b, 62c, and 62d may have a similar structure to contact plugs 42a, 42b, 42c, and 42d. Spacers 61a, 61b, 61c, and 61d, vias 65a, 65b, 65c, and 65d, and wiring 67a, 67b, 67c, and 67d may be formed relative to contact plugs 62a, 62b, 62c, and 62d.

[0165] The second electrical connection structure can electrically connect the sub-gate electrode 21b and the sub-gate electrode 21d via the sub-gate electrode 21e, and may include vias 71a, 71b, 73a and 73b, and wiring 71c and 73c. ​​The second electrical connection structure may have a structure similar to that of the first electrical connection structure.

[0166] Sub-gate electrodes 21a, 21b, and 21d at the same level can be electrically connected to each other via a first electrical connection structure, a second electrical connection structure, and floating sub-gate electrodes 21c and 21e, and can be used as a single string select line and / or a single GIDL string select line. In some example embodiments, although not in Figure 18 As shown, however, sub-gate electrodes 21b and 21d can be electrically connected to each other via a second electrical connection structure and sub-gate electrode 22e.

[0167] Although an example implementation is shown in which a single memory block and / or a single region is divided into two or three cell regions and contact plugs are disposed between them, the example implementation is not limited thereto.

[0168] Figure 19 and Figure 20 This is a diagram illustrating a memory device according to an example embodiment.

[0169] Reference Figure 19 and Figure 20 The memory device 10 includes a first semiconductor layer L1 and a second semiconductor layer L2.

[0170] A first semiconductor layer L1 and a second semiconductor layer L2 are disposed or stacked on a first direction DR1. For example, the second semiconductor layer L2 may be stacked on the first semiconductor layer L1 on the first direction DR1, and the first semiconductor layer L1 may be disposed below the second semiconductor layer L2 on the first direction DR1 (e.g., directly or indirectly below the second semiconductor layer L2). However, the exemplary embodiments are not limited to this. For example, the memory device 10 may be flipped during the manufacturing process, so the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 on the first direction DR1.

[0171] The first semiconductor layer L1 may include a first substrate SUB1, a memory cell array MCA, multiple word lines WL, and multiple bit lines BL. The first semiconductor layer L1 may also include a first pad PD_L1, a first contact CT_L1, and a first insulating layer IL1. Therefore, the first semiconductor layer L1 may be referred to as a memory cell region (MCR) and / or a cell wafer.

[0172] The first substrate SUB1 may be a support layer for components (or elements) supporting the first semiconductor layer L1. For example, the first substrate SUB1 may be a silicon substrate and may be referred to as a base substrate. The first insulating layer IL1 may cover the components of the first semiconductor layer L1. For example, the first insulating layer IL1 may include multiple insulating layers.

[0173] A memory cell array MCA, multiple word lines WL, and multiple bit lines BL may be disposed and / or formed on a first substrate SUB1. For example, each of the multiple word lines WL may extend in a second direction DR2, and the multiple word lines WL may be arranged along a first direction DR1 and a third direction DR3. For example, each of the multiple bit lines BL may extend in a third direction DR3, and the multiple bit lines BL may be arranged along the second direction DR2. For example, the memory cell array MCA may include multiple memory cells MC arranged along the first direction DR1, the second direction DR2, and the third direction DR3, and each of the multiple memory cells MC may be electrically connected to one of the multiple word lines WL and one of the multiple bit lines BL.

[0174] The first semiconductor layer L1 can be referenced. Figures 1 to 18 The structure described is implemented in a manner that, for example, allows a contact plug to be positioned at the center, the gate electrode structure to be without a stepped or stepped shape, and allows sub-gate electrodes in the upper gate electrode that are positioned at the same level and spaced apart from each other to be electrically connected to each other using at least one floating sub-gate electrode and at least one electrical connection structure.

[0175] The second semiconductor layer L2 may include a second substrate SUB2 and peripheral circuitry PCKT. The second semiconductor layer L2 may also include a second pad PD_L2, a second contact CT_L2, and a second insulating layer IL2. Therefore, the second semiconductor layer L2 may be referred to as the peripheral circuitry region (PCR) and / or the peripheral wafer (or core wafer).

[0176] Similar to the first substrate SUB1 and the first insulating layer IL1, the second substrate SUB2 can be a support layer for components supporting the second semiconductor layer L2, and the second insulating layer IL2 can cover components of the second semiconductor layer L2.

[0177] The peripheral circuitry PCKT may be disposed on and / or formed on the second substrate SUB2. For example, the peripheral circuitry PCKT may include multiple transistors TR, and various circuits may be formed using these multiple transistors TR. For example, the peripheral circuitry PCKT may include reference... Figure 7 and Figure 15 The description includes address decoders, etc.

[0178] In some example embodiments, the first semiconductor layer L1 and the second semiconductor layer L2 can be fabricated separately, and then connected to each other by a bonding scheme (or method). For example, a bonding scheme may refer to a method of electrically or physically connecting a bonding metal pattern (e.g., a first pad PD_L1) formed in the first semiconductor layer L1 to a bonding metal pattern (e.g., a second pad PD_L2) formed in the second semiconductor layer L2. For example, pads PD_L1 and PD_L2 may be formed of copper (Cu), and the bonding scheme may be a Cu-Cu bonding scheme. Alternatively, pads PD_L1 and PD_L2 may be formed of aluminum (Al) or tungsten (W).

[0179] For example, the memory cell array MCA (e.g., word lines WL and bit lines BL) of the first semiconductor layer L1 and the peripheral circuitry PCKT of the second semiconductor layer L2 can be electrically connected to each other via the first pad PD_L1 and the second pad PD_L2. In other words, the memory cell MC and the transistor TR can be electrically connected to each other via the first contact CT_L1 and the second contact CT_L2, as well as the first pad PD_L1 and the second pad PD_L2. For example, the memory cell MC can be electrically connected to the first contact CT_L1 and the first pad PD_L1, the transistor TR can be electrically connected to the second contact CT_L2 and the second pad PD_L2, and the memory cell MC and the transistor TR can be electrically connected to each other by electrically connecting the first pad PD_L1 and the second pad PD_L2. Although not shown in detail, at least one wire and / or contact can also be formed to connect the memory cell MC to the first pad PD_L1, and at least one wire and / or contact can also be formed to connect the transistor TR to the second pad PD_L2.

[0180] However, the example implementation is not limited to this, and various bonding schemes such as hybrid bonding schemes and dielectric bonding schemes can be used to electrically or physically connect the first semiconductor layer L1 to the second semiconductor layer L2.

[0181] The memory device 10 according to the example embodiment may have or employ a structure in which peripheral circuitry PCKT and memory cell array MCA are stacked. Therefore, the memory device 10 can have a relatively small size. For example, the first semiconductor layer L1 can be fabricated by forming the memory cell array MCA on a first substrate SUB1, and the second semiconductor layer L2 can be fabricated by forming the peripheral circuitry PCKT on a second substrate SUB2. The second semiconductor layer L2 can be flipped, and bonding schemes can be used to connect pads PD_L1 and PD_L2. As a result, the first semiconductor layer L1 and the second semiconductor layer L2 can be electrically connected in a first direction DR1.

[0182] Figure 21 and Figure 22 It is shown Figure 19 and Figure 20 An example diagram of a memory device. For the sake of brevity, [the symbols] will be omitted. Figure 2A and Figure 8 The description is repetitive or overlapping.

[0183] Reference Figure 21 and Figure 22 , showing Figure 19 and Figure 20 An example of a memory device in which sub-gate electrodes 21a and 21b are electrically connected to each other via sub-gate electrode 21c and a first electrical connection structure and are used as a single string select line.

[0184] In some example implementations, such as Figure 21 As shown, a first portion of the first electrical connection structure may be included in the first semiconductor layer L1, and a second portion of the first electrical connection structure may be included in the second semiconductor layer L2. For example, among the components included in the first electrical connection structure, portions of wirings 51c and 53c and vias 51a, 51b, 53a and 53b may be included in the second semiconductor layer L2.

[0185] In some example implementations, such as Figure 22 As shown, the entire portion of the first electrical connection structure may be included in the first semiconductor layer L1.

[0186] exist Figure 21 and Figure 22In the example, the gate electrode structure, memory channel structures 30a and 30b, and contact plugs 42a, 42b, 42c and 42d may be included in the first semiconductor layer L1, and the first string transmission transistor SPT1, the second string transmission transistor SPT2 and the first string ground transistor SGT1 may be included in the second semiconductor layer L2.

[0187] In some exemplary embodiments, the memory device according to the exemplary embodiments can be combined with reference to Figures 1 to 22 Implement two or more of the examples described.

[0188] Figure 23A and Figure 23B This is a diagram illustrating a memory package according to an example embodiment.

[0189] Reference Figure 23A The memory package 700 may include a base substrate 710 and a plurality of memory chips CHP1, CHP2 and CHP3 stacked on the base substrate 710.

[0190] Each of the memory chips CHP1 through CHP3 may include an I / O pad (IOPAD). Each of the memory chips CHP1 through CHP3 may be, according to reference... Figures 1 to 22 The memory device described in the example embodiment may have a connection structure with a floating electrode (CSFE) according to the example embodiment, wherein a contact plug may be disposed at the center, the gate electrode structure may not have a stepped or stepped shape, and the sub-gate electrodes disposed at the same level and spaced apart from each other in the upper gate electrode may be electrically connected to each other using at least one floating sub-gate electrode and at least one electrical connection structure.

[0191] In some example embodiments, memory chips CHP1 to CHP3 may be stacked on a base substrate 710 with the surface of the I / O pads (IOPADs) formed thereon facing upwards. In some example embodiments, the I / O pads (IOPADs) may be arranged near one side of the semiconductor substrate relative to each of the memory chips CHP1 to CHP3. Thus, the memory chips CHP1 to CHP3 may be stacked in a stepped manner, i.e., in a stepped shape, such that the I / O pads (IOPADs) of each memory chip are exposed. In this stacked configuration, the memory chips CHP1 to CHP3 may be electrically connected to the base substrate 710 via multiple bonding wires (BWs).

[0192] The stacked memory chips CHP1 to CHP3 and multiple bonding wires BW can be secured by a sealing member 740, and an adhesive member 730 can be located between the base substrate 710 and the memory chips CHP1 to CHP3. Conductive bumps 720 can be formed on the bottom surface of the base substrate 710 for electrical connection to external devices.

[0193] Reference Figure 23B The memory package 800 may include a base substrate 810 and multiple memory chips CHP1, CHP2, and CHP3 stacked on the base substrate 810. For brevity, the details will be omitted. Figure 23A The description is repetitive or overlapping.

[0194] Each of the memory chips CHP1 to CHP3 may further include multiple through-silicon vias (TSVs, or vias) 830. Conductive bumps 820 and sealing members 850 may be respectively connected to… Figure 23A The conductive bump 720 and the sealing member 740 are basically the same.

[0195] In some example implementations, a plurality of TSVs 830 may be arranged at the same location in each of the memory chips CHP1 to CHP3. Thus, the memory chips CHP1 to CHP3 can be stacked such that the TSVs 830 of each memory chip can be completely stacked (e.g., the arrangement of the TSVs 830 can perfectly match within the memory chips CHP1 to CHP3). In this stacked state, the memory chips CHP1 to CHP3 are electrically connected to each other and to the base substrate 810 via the plurality of TSVs 830 and the conductive material 840.

[0196] Figure 24 This is a block diagram illustrating a memory system according to an example implementation.

[0197] Reference Figure 24 The memory system 2000 may include a memory controller 2200 and a memory device 2400. The memory system 2000 may also include multiple signal lines 2300 that electrically connect the memory controller 2200 and the memory device 2400.

[0198] The memory device 2400 may be controlled by the memory controller 2200. For example, based on a request from a host device (not shown), the memory controller 2200 may store data (e.g., write or program) into the memory device 2400, or may retrieve (e.g., read or sense) data from the memory device 2400.

[0199] The memory device 2400 may be based on a reference Figures 1 to 22 The memory device described is an example embodiment and may have a connection structure 1410 with floating electrodes according to the example embodiment.

[0200] The multiple signal lines 2300 may include control lines, command lines, address lines, data I / O lines, and power lines. The memory controller 2200 can send the command CMD, address ADDR, and control signal CTRL to the memory device 2400 via the command lines, address lines, and control lines; it can exchange data signals DS with the memory device 2400 via the data I / O lines; and it can send the power supply voltage PWR to the memory device 2400 via the power lines. Although not explicitly stated... Figure 24 As shown, however, the multiple signal lines 2300 may also include a data strobe (DQS) line for transmitting DQS signals.

[0201] Figure 25 This is a cross-sectional view of a memory device according to an example embodiment.

[0202] Reference Figure 25 The memory device (or non-volatile memory device) 5000 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell region and a lower chip including a peripheral circuit region PREG can be manufactured separately. The at least one upper chip and the lower chip can then be connected to each other by a bonding method to realize the C2C structure. For example, the bonding method may refer to a method of electrically and / or physically connecting a bonding metal pattern formed in the highest metal layer of the upper chip to a bonding metal pattern formed in the highest metal layer of the lower chip. As another example, if the bonding metal pattern is formed of copper (Cu), the bonding method may be referred to as a Cu-Cu bonding method. Optionally or additionally, the bonding metal pattern may be formed of other materials such as, but not limited to, aluminum (Al) or tungsten (W).

[0203] The memory device 5000 may include at least one on-chip containing cell regions. For example, such as Figure 25 As shown, the memory device 5000 may include two upper chips. However, the number of upper chips is not limited to this. In the case where the memory device 5000 includes two upper chips, a first upper chip including a first cell region CREG1, a second upper chip including a second cell region CREG2, and a lower chip including a peripheral circuit region PREG can be manufactured separately. Then, the first upper chip, the second upper chip, and the lower chip can be connected to each other by a bonding method to manufacture the memory device 5000. The first upper chip can be flipped and then connected to the lower chip by a bonding method; the second upper chip can also be flipped and then connected to the first upper chip by a bonding method. In the following, the upper and lower portions of each of the first and second upper chips can be referenced based on their respective orientations before being flipped. For example, in Figure 25In this embodiment, the upper portion of the lower chip may refer to the upper portion defined based on the +Z axis direction, and the upper portion of each of the first and second upper chips may refer to the upper portion defined based on the -Z axis direction. However, the example implementation is not limited to this. In some example implementations, one of the first and second upper chips may be flipped and then connected to the corresponding chip by a bonding method.

[0204] Each of the peripheral circuit region PREG and the first cell region CREG1 and the second cell region CREG2 of the memory device 5000 may include an external pad bonding region PA, a word line bonding region WLBA and a bit line bonding region BLBA.

[0205] The peripheral circuit region PREG may include a first substrate 5210 and a plurality of circuit elements (e.g., first circuit element 5220a, second circuit element 5220b, and third circuit element 5220c) formed on the first substrate 5210. An interlayer insulating layer 5215 including one or more insulating layers may be disposed on the plurality of circuit elements 5220a to 5220c, and a plurality of metal wires electrically connected (e.g., bonded) to the plurality of circuit elements 5220a to 5220c may be disposed in the interlayer insulating layer 5215. For example, the plurality of metal wires may include first metal wires (e.g., 5230a, 5230b, and 5230c) connected to the plurality of circuit elements 5220a to 5220c and second metal wires (e.g., 5240a, 5240b, and 5240c) formed on the first metal wires 5230a to 5230c. The plurality of metal wires may be formed of at least one of a variety of conductive materials. For example, the first metal lines 5230a to 5230c may be formed of tungsten (W) with relatively high resistivity, and the second metal lines 5240a to 5240c may be formed of copper (Cu) with relatively low resistivity.

[0206] In some exemplary embodiments, first metal lines 5230a to 5230c and second metal lines 5240a to 5240c are shown and described. However, the exemplary embodiments are not limited thereto. In some exemplary embodiments, at least one or more additional metal lines may also be formed on the second metal lines 5240a to 5240c. In such embodiments, the second metal lines 5240a to 5240c may be formed of aluminum (Al), and at least some of the additional metal lines formed on the second metal lines 5240a to 5240c may be formed of copper (Cu) having a lower resistivity than that of the aluminum (Al) of the second metal lines 5240a to 5240c.

[0207] The interlayer insulating layer 5215 may be disposed on the first substrate 5210 and may include insulating materials such as, but not limited to, silicon oxide (SiO) and / or silicon nitride (SiN).

[0208] Each of the first cell region CREG1 and the second cell region CREG2 may include at least one memory block. The first cell region CREG1 may include a second substrate 5310 and a common source line 5320. Multiple word lines 5330 (e.g., first word line 5331, second word line 5332, third word line 5333, fourth word line 5334, fifth word line 5335, sixth word line 5336, seventh word line 5337, and eighth word line 5338) may be stacked on the second substrate 5310 in a direction perpendicular to the top surface of the second substrate 5310 (e.g., the Z-axis direction). Serial select lines and ground select lines may be disposed above and below the multiple word lines 5330, and the multiple word lines 5330 may be disposed between the serial select lines and the ground select lines. Similarly, the second unit region CREG2 may include a third substrate 5410 and a common source line 5420, and multiple word lines 5430 (e.g., first word line 5431, second word line 5432, third word line 5433, fourth word line 5434, fifth word line 5435, sixth word line 5436, seventh word line 5437, and eighth word line 5438) may be stacked on the third substrate 5410 in a direction perpendicular to the top surface of the third substrate 5410 (e.g., the Z-axis direction). Each of the second substrate 5310 and the third substrate 5410 may be formed of at least one of a variety of materials and may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystal epitaxial layer grown on a single-crystal silicon substrate. Multiple channel structures CH may be formed in each of the first unit region CREG1 and the second unit region CREG2.

[0209] In some example embodiments, such as region "A1" which is an alternative embodiment of region "A", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 5310 to at least partially penetrate the word line 5330, the serial select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected (e.g., bonded) to a first metal line 5350c and a second metal line 5360c in the bit line bonding region BLBA. For example, the second metal line 5360c may be a bit line and may be connected to the channel structure CH via the first metal line 5350c. The bit line 5360c may extend in a first direction (e.g., the Y-axis direction) parallel to the top surface of the second substrate 5310.

[0210] In some example embodiments, such as region "A2" which is another alternative embodiment of region "A", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process for forming the lower channel LCH and a process for forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 5310 to at least partially penetrate the common source line 5320 and the lower word lines 5331 and 5332. The lower channel LCH may include a data storage layer, a channel layer, and a filler insulating layer and may be connected to the upper channel UCH. The upper channel UCH may at least partially penetrate the upper word lines 5333 to 5338. The upper channel UCH may include a data storage layer, a channel layer, and a filler insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 5350c and the second metal line 5360c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. According to some example implementations, the memory device 5000 may include a channel that has improved width uniformity due to a lower channel LCH and an upper channel UCH formed by a sequentially performed process.

[0211] In cases where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in region "A2", word lines located near the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. For example, word lines 5332 and 5333 adjacent to the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. In such an example, data may not be stored in memory cells connected to the dummy word lines. Optionally or additionally, the number of pages corresponding to memory cells connected to dummy word lines may be less than the number of pages corresponding to memory cells connected to ordinary word lines. The voltage level applied to the dummy word lines may differ from the voltage level applied to the ordinary word lines, thus reducing the impact of the non-uniform channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device.

[0212] In some example embodiments, in region "A2", the number of lower word lines 5331 and 5332 that are at least partially penetrated by the lower channel LCH may be less than the number of upper word lines 5333 to 5338 that are at least partially penetrated by the upper channel UCH. However, the example embodiments are not limited thereto. In some example embodiments, the number of lower word lines that are at least partially penetrated by the lower channel LCH may be greater than or equal to the number of upper word lines that are at least partially penetrated by the upper channel UCH. Optionally or additionally, the structural features and connection relationships of the channel structure CH disposed in the second unit region CREG2 may be substantially the same as those of the channel structure CH disposed in the first unit region CREG1. In some example embodiments, the channel layer of the channel structure CH in the second unit region CREG2 may be electrically connected (e.g., bonded) to the first metal line 5450c and the second metal line 5460c.

[0213] In the bit line bonding region BLBA, a first through electrode THV1 may be disposed in the first cell region CREG1, and a second through electrode THV2 may be disposed in the second cell region CREG2. For example... Figure 25 As shown, the first through electrode THV1 can at least partially penetrate the common source line 5320 and the multiple word lines 5330. In some example embodiments, the first through electrode THV1 can also penetrate the second substrate 5310. The first through electrode THV1 may include a conductive material. Optionally or additionally, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same and / or substantially similar shape and structure as the first through electrode THV1.

[0214] In some example embodiments, the first through electrode THV1 and the second through electrode THV2 can be electrically connected (e.g., bonded) to each other via a first through metal pattern 5372d and a second through metal pattern 5472d. The first through metal pattern 5372d can be formed at the bottom of a first upper chip including a first cell region CREG1, and the second through metal pattern 5472d can be formed at the top of a second upper chip including a second cell region CREG2. The first through electrode THV1 can be electrically connected (e.g., bonded) to a first metal line 5350c and a second metal line 5360c. A lower via 5371d can be formed between the first through electrode THV1 and the first through metal pattern 5372d, and an upper via 5471d can be formed between the second through electrode THV2 and the second through metal pattern 5472d. The first through metal pattern 5372d and the second through metal pattern 5472d can be connected (e.g., bonded) to each other via a bonding method.

[0215] In the bit line bonding region BLBA, an upper metal pattern 5252 may be formed in the uppermost metal layer of the peripheral circuit region PREG, and an upper metal pattern 5392 having the same and / or substantially similar shape as the upper metal pattern 5252 may be formed in the uppermost metal layer of the first cell region CREG1. The upper metal pattern 5392 of the first cell region CREG1 and the upper metal pattern 5252 of the peripheral circuit region PREG may be electrically connected to each other (e.g., bonded) by a bonding method. In the bit line bonding region BLBA, bit lines 5360c may be electrically connected (e.g., bonded) to page buffers included in the peripheral circuit region PREG. For example, some of the circuit elements 5220c of the peripheral circuit region PREG may constitute page buffers, and bit lines 5360c may be electrically connected (e.g., bonded) to the circuit elements 5220c constituting page buffers via the upper bonding metal pattern 5370c of the first cell region CREG1 and the upper bonding metal pattern 5270c of the peripheral circuit region PREG.

[0216] Continue to refer to Figure 25 In the word line bonding area WLBA, the word lines 5330 of the first unit region CREG1 can extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 5310 and can be connected to a plurality of unit contact plugs 5340 (e.g., first unit contact plug 5341, second unit contact plug 5342, third unit contact plug 5343, fourth unit contact plug 5344, fifth unit contact plug 5345, sixth unit contact plug 5346, and seventh unit contact plug 5347). A first metal line 5350b and a second metal line 5360b can be sequentially connected (e.g., bonded) to the unit contact plugs 5340 connected to the plurality of word lines 5330. In the word line bonding area WLBA, the unit contact plugs 5340 can be connected (e.g., bonded) to the peripheral circuit region PREG via the upper bonding metal pattern 5370b of the first unit region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG.

[0217] Cell contact plug 5340 may be electrically connected (e.g., coupled) to a line decoder included in a peripheral circuit region PREG. For example, some of the circuit elements 5220b in the peripheral circuit region PREG may constitute a line decoder, and cell contact plug 5340 may be electrically connected (e.g., coupled) to the circuit elements 5220b constituting the line decoder via the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG. In some example embodiments, the operating voltage of the circuit elements 5220b constituting the line decoder may be different from the operating voltage of the circuit elements 5220c constituting the page buffer. For example, the operating voltage of the circuit elements 5220c constituting the page buffer may be greater than the operating voltage of the circuit elements 5220b constituting the line decoder.

[0218] Similarly, in the word line bonding area WLBA, the word line 5430 of the second unit region CREG2 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 5410, and may be connected to a plurality of unit contact plugs 5440 (e.g., first unit contact plug 5441, second unit contact plug 5442, third unit contact plug 5443, fourth unit contact plug 5444, fifth unit contact plug 5445, sixth unit contact plug 5446, and seventh unit contact plug 5447). The plurality of unit contact plugs 5440 may be connected (e.g., bonded) to the peripheral circuit region PREG via the upper metal pattern of the second unit region CREG2, the lower and upper metal patterns of the first unit region CREG1, and the eighth unit contact plug 5348.

[0219] In the word line bonding region WLBA, an upper bonding metal pattern 5370b may be formed in the first unit region CREG1, and an upper bonding metal pattern 5270b may be formed in the peripheral circuit region PREG. The upper bonding metal pattern 5370b of the first unit region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG may be electrically connected to each other by a bonding method (e.g., bonding). The upper bonding metal patterns 5370b and 5270b may be formed of aluminum (Al), copper (Cu), or tungsten (W).

[0220] In the external pad bonding region PA, a lower metal pattern 5371e may be formed in the lower part of the first unit region CREG1, and an upper metal pattern 5472a may be formed in the upper part of the second unit region CREG2. The lower metal pattern 5371e of the first unit region CREG1 and the upper metal pattern 5472a of the second unit region CREG2 may be connected to each other in the external pad bonding region PA by a bonding method. Similarly, the upper metal pattern 5372a may be formed in the upper part of the first unit region CREG1, and the upper metal pattern 5272a may be formed in the upper part of the peripheral circuit region PREG. The upper metal pattern 5372a of the first unit region CREG1 and the upper metal pattern 5272a of the peripheral circuit region PREG may be connected to each other by a bonding method.

[0221] Common source electrode contact plugs 5380 and 5480 may be disposed in the external pad bonding region PA. Common source electrode contact plugs 5380 and 5480 may be formed of a conductive material such as, but not limited to, metals, metal compounds, and / or doped polysilicon. Common source electrode contact plug 5380 of the first unit region CREG1 may be electrically connected (e.g., bonded) to common source electrode 5320, and common source electrode contact plug 5480 of the second unit region CREG2 may be electrically connected (e.g., bonded) to common source electrode 5420. First metal wire 5350a and second metal wire 5360a may be sequentially stacked on common source electrode contact plug 5380 of the first unit region CREG1, and first metal wire 5450a and second metal wire 5460a may be sequentially stacked on common source electrode contact plug 5480 of the second unit region CREG2.

[0222] Input / output (I / O) pads (e.g., first I / O pad 5205, second I / O pad 5405, and third I / O pad 5406) ​​may be disposed in the external pad mating area PA. See reference. Figure 25 The lower insulating layer 5201 may cover the bottom surface of the first substrate 5210, and the first I / O pad 5205 may be formed on the lower insulating layer 5201. The first I / O pad 5205 may be connected to at least one of a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG via the first I / O contact plug 5203, and may be separated from the first substrate 5210 via the lower insulating layer 5201. In addition, a side insulating layer may be disposed between the first I / O contact plug 5203 and the first substrate 5210 to electrically isolate the first I / O contact plug 5203 from the first substrate 5210.

[0223] An upper insulating layer 5401 covering the top surface of the third substrate 5410 may be formed on the third substrate 5410. A second I / O pad 5405 and / or a third I / O pad 5406 may be disposed on the upper insulating layer 5401. The second I / O pad 5405 may be connected to at least one of a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG via second I / O contact plugs 5403 and 5303, and the third I / O pad 5406 may be connected to at least one of a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG via third I / O contact plugs 5404 and 5304.

[0224] In some example embodiments, the third substrate 5410 may not be disposed in the region where the I / O contact plug is disposed. For example, as shown in region "B", the third I / O contact plug 5404 may be separated from the third substrate 5410 in a direction parallel to the top surface of the third substrate 5410 and may at least partially penetrate the interlayer insulation layer 5415 of the second unit region CREG2, thereby being connected to the third I / O pad 5406. In such an example, the third I / O contact plug 5404 may be formed by at least one of various processes.

[0225] In some exemplary embodiments, such as region "B1" which is an alternative embodiment of region "B", the third I / O contact plug 5404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third I / O contact plug 5404 may gradually increase toward the upper insulating layer 5401. That is, the diameter of the channel structure CH described in region "A1" may gradually decrease toward the upper insulating layer 5401, but the diameter of the third I / O contact plug 5404 may gradually increase toward the upper insulating layer 5401. For example, the third I / O contact plug 5404 may be formed after the second unit region CREG2 and the first unit region CREG1 are joined together by a joining method.

[0226] In some example embodiments, such as region "B2" which is another alternative embodiment of region "B", the third I / O contact plug 5404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third I / O contact plug 5404 may gradually decrease towards the upper insulating layer 5401. That is, similar to the channel structure CH, the diameter of the third I / O contact plug 5404 may gradually decrease towards the upper insulating layer 5401. For example, the third I / O contact plug 5404 may be formed together with the unit contact plug 5440 before the second unit region CREG2 and the first unit region CREG1 are engaged with each other.

[0227] In some example implementations, the I / O contact plug may overlap with the third substrate 5410. For example, as shown in region “C”, the second I / O contact plug 5403 may at least partially penetrate the interlayer insulation layer 5415 of the second unit region CREG2 in a third direction (e.g., the Z-axis direction) and may be electrically connected (e.g., bonded) to the second I / O pad 5405 through the third substrate 5410. In such examples, the connection structure of the second I / O contact plug 5403 and the second I / O pad 5405 may be implemented by various methods.

[0228] In some example embodiments, such as region "C1" which is an alternative embodiment of region "C", the opening 5408 may be formed to at least partially penetrate the third substrate 5410, and the second I / O contact plug 5403 may be directly connected (e.g., bonded) to the second I / O pad 5405 through the opening 5408 formed in the third substrate 5410. In such an example, as shown in region "C1", the diameter of the second I / O contact plug 5403 may gradually increase toward the second I / O pad 5405. However, the example embodiments are not limited thereto, and in some example embodiments, the diameter of the second I / O contact plug 5403 may gradually decrease toward the second I / O pad 5405.

[0229] In some example implementations, such as region "C2" which is an alternative implementation of region "C", an opening 5408 penetrating the third substrate 5410 may be formed, and a contact 5407 may be formed in the opening 5408. One end of the contact 5407 may be connected to the second I / O pad 5405, and the other end of the contact 5407 may be connected to the second I / O contact plug 5403. Thus, the second I / O contact plug 5403 can be electrically connected (e.g., bonded) to the second I / O pad 5405 through the contact 5407 in the opening 5408. In such an example, as shown in region "C2", the diameter of the contact 5407 may gradually increase toward the second I / O pad 5405, and the diameter of the second I / O contact plug 5403 may gradually decrease toward the second I / O pad 5405. For example, a second I / O contact plug 5403 may be formed together with the unit contact plug 5440 before the second unit region CREG2 and the first unit region CREG1 are engaged with each other, and a contact 5407 may be formed after the second unit region CREG2 and the first unit region CREG1 are engaged with each other.

[0230] In some example embodiments shown in region "C3," which is yet another alternative implementation of region "C," the stop member 5409 may also be formed on the bottom end of the opening 5408 of the third substrate 5410, compared to the implementation in region "C2." The stop member 5409 may be a metal wire formed in the same layer as the common source line 5420. Optionally or additionally, the stop member 5409 may be a metal wire formed in the same layer as at least one word line in the word lines 5430. The second I / O contact plug 5403 may be electrically connected (e.g., bonded) to the second I / O pad 5405 via the contact member 5407 and the stop member 5409.

[0231] Similar to the second I / O contact plug 5403 and the third I / O contact plug 5404 of the second unit region CREG2, the diameter of each of the second I / O contact plug 5303 and the third I / O contact plug 5304 of the first unit region CREG1 may gradually decrease and / or gradually increase towards the lower metal pattern 5371e.

[0232] In some example embodiments, slit 5411 may be formed in the third substrate 5410. For example, slit 5411 may be formed at a location in the outer pad engagement region PA. As another example, as shown in region “D”, when viewed in a plan view, slit 5411 may be located between the second I / O pad 5405 and the cell contact plug 5440. Optionally or additionally, when viewed in a plan view, the second I / O pad 5405 may be located between slit 5411 and the cell contact plug 5440.

[0233] In some example embodiments, such as region "D1" which is an alternative embodiment of region "D", the slit 5411 may be formed to at least partially penetrate the third substrate 5410. For example, the slit 5411 may be used to prevent minor cracking of the third substrate 5410 when the opening 5408 is formed. However, the example embodiments are not limited thereto, and in some example embodiments, the slit 5411 may be formed to a depth in the range of about 60% to about 70% of the thickness of the third substrate 5410.

[0234] In some example implementations, such as region "D2" which is an alternative implementation of region "D", conductive material 5412 may be formed in slit 5411. For example, conductive material 5412 may be used to discharge leakage current that occurs when driving circuit elements in the external pad bonding region PA to the outside. In such an example, conductive material 5412 may be connected to an external ground wire.

[0235] In some example embodiments, such as region "D3" which is another alternative embodiment of region "D", an insulating material 5413 may be formed in the slit 5411. For example, the insulating material 5413 may be used to electrically isolate the second I / O pad 5405 and the second I / O contact plug 5403 disposed in the outer pad bonding region PA from the word line bonding region WLBA. Because the insulating material 5413 is formed in the slit 5411, the voltage supplied through the second I / O pad 5405 can be prevented from affecting the metal layer disposed on the third substrate 5410 in the word line bonding region WLBA.

[0236] In some example embodiments, the first I / O pad 5205 to the third I / O pad 5406 may be selectively formed. For example, the memory device 5000 may be implemented to include only the first I / O pad 5205 disposed on the first substrate 5210, only the second I / O pad 5405 disposed on the third substrate 5410, or only the third I / O pad 5406 disposed on the upper insulating layer 5401.

[0237] In some example embodiments, at least one of the second substrate 5310 of the first cell region CREG1 and the third substrate 5410 of the second cell region CREG2 can be used as a sacrificial substrate and can be completely or partially removed before and / or after the bonding process. Additional layers can be stacked after substrate removal. For example, the second substrate 5310 of the first cell region CREG1 can be removed before or after the bonding process of the peripheral circuit region PREG and the first cell region CREG1, and then an insulating layer or a conductive layer for connection can be formed covering the top surface of the common source line 5320. Similarly, the third substrate 5410 of the second cell region CREG2 can be removed before or after the bonding process of the first cell region CREG1 and the second cell region CREG2, and then an upper insulating layer 5401 or a conductive layer for connection can be formed covering the top surface of the common source line 5420.

[0238] The memory device 5000 may be a non-volatile memory device according to an example embodiment, and may have a connection structure using floating electrodes according to an example embodiment.

[0239] The example implementations can be applied to a variety of electronic devices and systems that include memory devices. For example, the example implementations can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, automobiles, and the like.

[0240] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments defined in the claims. It should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

[0241] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to particular embodiments of the invention. Certain features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may function in certain combinations as described above, in some cases one or more features may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

Claims

1. A memory device, comprising: A gate electrode structure, on a first substrate, includes a plurality of gate electrodes stacked and spaced apart from each other on an upper surface of the first substrate, wherein each of the plurality of gate electrodes extends parallel to the upper surface of the first substrate, wherein the plurality of gate electrodes includes an upper gate electrode, wherein each of the upper gate electrodes includes a plurality of sub-gate electrodes spaced apart from each other. Multiple memory channel structures extend through the gate electrode structure; A first contact plug extends partially through the gate electrode structure and contacts the upper surface of a first gate electrode among the plurality of gate electrodes, wherein the first contact plug extends through a second gate electrode on the first gate electrode among the plurality of gate electrodes and is electrically insulated from the second gate electrode, wherein the upper surface of the first gate electrode faces away from the upper surface of the first substrate; and A first electrical connection structure electrically connects a first sub-gate electrode to a second sub-gate electrode via a third sub-gate electrode, wherein the first and second sub-gate electrodes are at the same level, wherein a first contact plug extends through the third sub-gate electrode, and wherein the third sub-gate electrode is electrically insulated from the first contact plug and from the plurality of memory channel structures.

2. The memory device according to claim 1, further comprising: A series select line, wherein the series select line includes a first sub-gate electrode and a second sub-gate electrode electrically connected to the first sub-gate electrode.

3. The memory device according to claim 2, further comprising: The first string of transmission transistors is connected to the string select line, wherein the first string of transmission transistors is adjacent to the first sub-gate electrode; A second string of transmission transistors is connected to the string select line, wherein the second string of transmission transistors is adjacent to the second sub-gate electrode; and The first string of ground transistors is connected to the string select line, wherein the first string of ground transistors is adjacent to one of the first string of transmission transistors and the second string of transmission transistors.

4. The memory device according to claim 2, further comprising: A first string of transmission transistors is connected to a string select line, wherein the first string of transmission transistors is adjacent to one of a first sub-gate electrode and a second sub-gate electrode; and The first string of ground transistors is connected to the string select line, wherein the first string of ground transistors is adjacent to the first string of transmit transistors.

5. The memory device according to claim 1, further comprising: The gate-drain leakage string select line includes a first sub-gate electrode and a second sub-gate electrode electrically connected to the first sub-gate electrode.

6. The memory device according to claim 1, wherein, The third sub-gate electrode is at the same level as the first and second sub-gate electrodes.

7. The memory device according to claim 1, wherein, The third sub-gate electrode is at a different level than the first and second sub-gate electrodes.

8. The memory device according to claim 1, in, The plurality of memory channel structures include a first memory channel structure and a second memory channel structure. The first memory channel structure is located on a first region of the first substrate. The second memory channel structure is located on a second region of the first substrate, the second region being spaced apart from the first region, and... The first contact plug is located on the third region of the first substrate, and the third region is located between the first region and the second region.

9. The memory device according to claim 8, in, The first sub-gate electrode is located in the first region, and wherein the first memory channel structure extends into the first sub-gate electrode. The second sub-gate electrode is located in the second region, and the second memory channel structure extends into the second sub-gate electrode. The third sub-gate electrode is located in the third region.

10. The memory device of claim 8, further comprising: The second contact plug extends partially through the gate electrode structure and contacts the upper surface of the third gate electrode among the plurality of gate electrodes. The second contact plug is insulated from the gate electrode of the plurality of gate electrodes that is above the third gate electrode, and The upper surface of the third gate electrode faces away from the upper surface of the first substrate.

11. The memory device according to claim 10, in, The plurality of memory channel structures includes a third memory channel structure. The third memory channel structure is located on a fourth region of the first substrate, the fourth region being spaced apart from the second region of the first substrate, and... The second contact plug is located on the fifth region of the first substrate, and the fifth region is located between the second region and the fourth region.

12. The memory device according to claim 1, in, The first substrate, the gate electrode structure, the plurality of memory channel structures, and the first contact plug define a first semiconductor layer comprising a memory cell array. The memory device further includes a second semiconductor layer on top of the first semiconductor layer, and The second semiconductor layer includes peripheral circuitry, which is located on the second substrate and configured to control the memory cell array.

13. The memory device according to claim 12, in, The first semiconductor layer includes a first portion of a first electrical connection structure, and The second semiconductor layer includes a second portion of the first electrical connection structure.

14. The memory device according to claim 12, wherein, The first semiconductor layer includes the entire portion of the first electrical connection structure.

15. The memory device according to claim 12, in, The first semiconductor layer also includes a first pad. The second semiconductor layer further includes a second pad, and The first semiconductor layer and the second semiconductor layer are electrically connected through a first pad and a second pad.

16. The memory device according to claim 15, wherein, The first and second pads are connected to each other by a bonding scheme.

17. A memory package, comprising: Basic base; as well as Multiple memory chips are stacked on a base substrate, each of the multiple memory chips comprising: A gate electrode structure, on a first substrate, includes a plurality of gate electrodes stacked and spaced apart from each other on an upper surface of the first substrate, wherein each of the plurality of gate electrodes extends parallel to the upper surface of the first substrate, wherein the plurality of gate electrodes includes an upper gate electrode, wherein each of the upper gate electrodes includes a plurality of sub-gate electrodes spaced apart from each other. Multiple memory channel structures extend through the gate electrode structure; A first contact plug extends partially through the gate electrode structure and contacts the upper surface of a first gate electrode among the plurality of gate electrodes, wherein the first contact plug extends through a second gate electrode above the first gate electrode among the plurality of gate electrodes and is electrically insulated from the second gate electrode, wherein the upper surface of the first gate electrode faces away from the upper surface of the first substrate; and A first electrical connection structure electrically connects a first sub-gate electrode to a second sub-gate electrode via a third sub-gate electrode, wherein the first and second sub-gate electrodes are at the same level, wherein a first contact plug extends through the third sub-gate electrode, and wherein the third sub-gate electrode is electrically insulated from the first contact plug and from the plurality of memory channel structures.

18. The memory package of claim 17, further comprising: Multiple bonding lines electrically connect the base substrate to the multiple memory chips; or Multiple through-silicon vias electrically connect the base substrate to the multiple memory chips.

19. A memory device, comprising: The first base includes a first region, a second region, and a third region, wherein the first region and the second region are spaced apart from each other, and wherein the third region is located between the first region and the second region. A gate electrode structure, on a first region, a second region, and a third region of a first substrate, includes a plurality of gate electrodes stacked and spaced apart from each other in a first direction perpendicular to the upper surface of the first substrate, wherein each of the plurality of gate electrodes extends in a second direction parallel to the upper surface of the first substrate, wherein the plurality of gate electrodes includes an upper gate electrode, wherein each of the upper gate electrodes includes a plurality of sub-gate electrodes spaced apart from each other. A first memory channel structure is located on a first region of a first substrate, wherein the first memory channel structure extends through a gate electrode structure. A second memory channel structure is provided on a second region of a first substrate, wherein the second memory channel structure extends through a gate electrode structure. A first contact plug is located in a third region of the first substrate, wherein the first contact plug extends partially through the gate electrode structure and contacts the upper surface of the first gate electrode among the plurality of gate electrodes, wherein the first contact plug extends through a second gate electrode above the first gate electrode among the plurality of gate electrodes and is electrically insulated from the second gate electrode, wherein the upper surface of the first gate electrode faces away from the upper surface of the first substrate; and A first electrical connection structure electrically connects a first sub-gate electrode in a first region to a second sub-gate electrode in a second region via a third sub-gate electrode in a third region, wherein the first sub-gate electrode and the second sub-gate electrode are spaced apart from each other and at the same level, wherein a first contact plug extends through the third sub-gate electrode, and wherein the third sub-gate electrode is electrically insulated from the first contact plug, the first memory channel structure, and the second memory channel structure.

20. The memory device of claim 19, further comprising: A series select line, wherein the series select line includes a first sub-gate electrode and a second sub-gate electrode electrically connected to the first sub-gate electrode; The first string of transmission transistors is connected to the string select line, wherein the first string of transmission transistors is adjacent to the first sub-gate electrode; A second string of transmission transistors is connected to the string select line, wherein the second string of transmission transistors is adjacent to the second sub-gate electrode; and The first string of ground transistors is connected to the string select line, wherein the first string of ground transistors is adjacent to one of the first string of transmission transistors and the second string of transmission transistors.

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