Semiconductor device with common gate structure

Abstract

A semiconductor device includes a substrate including a plurality of active regions defined by a device isolation layer. Each of the plurality of active regions includes a central region and first and second main active regions extending from the central region and spaced apart from each other in a first horizontal direction. The plurality of active regions includes a first active region and a second active region adjacent to each other in the first horizontal direction, a first gate structure on the first main active region of the first active region, and a second gate structure on the second main active region of the first active region and the first main active region of the second active region. The second gate structure is spaced apart from the first gate structure.

Description

Cross-reference of related applications

[0001] This application claims the benefit of the earlier filing date and priority of Korean Patent Application No. 10-2025-0057764, filed on April 30, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure provides a semiconductor device with improved operating characteristics and improved integration. Background Technology

[0003] In electronic systems that require data storage, there is a need for semiconductor devices capable of storing high-capacity data. As a method to increase the data storage capacity of semiconductor devices, semiconductor devices comprising three-dimensional memory cells instead of two-dimensional memory cells have been introduced. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate including a plurality of active regions defined by a device isolation layer, wherein each of the plurality of active regions includes a central region, a first main active region and a second main active region, and a third main active region and a fourth main active region, wherein the first main active region and the second main active region extend from the central region and are spaced apart from each other in a first horizontal direction, the third main active region and the fourth main active region extend from the central region, are spaced apart from each other in the first horizontal direction and are spaced apart from the first main active region and the second main active region in a second horizontal direction, and the plurality of active regions include the first active region and the second active region adjacent to each other in the first horizontal direction, a first gate structure on the first main active region of the first active region, and a second gate structure on the second main active region of the first active region and spaced apart from the first gate structure.

[0005] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a substrate including a plurality of active regions defined by a device isolation layer, wherein each of the plurality of active regions includes a central region, a first main active region and a second main active region extending from the central region and spaced apart from each other in a first horizontal direction, and a third main active region and a fourth main active region extending from the central region and spaced apart from the first main active region and the second main active region in a second horizontal direction; and a plurality of gate structures partially overlapping with two adjacent active regions among the plurality of active regions and extending in the first horizontal direction, the plurality of gate structures including a first gate structure on the first main active region of the first active region, a second gate structure on the second main active region of the first active region and the first main active region of the second active region, a third gate structure on the third main active region of the first active region, and a fourth gate structure on the fourth main active region of the first active region and the third main active region of the second active region.

[0006] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate including a plurality of active regions, wherein each of the plurality of active regions includes a central region, a first main active region and a second main active region extending from the central region and spaced apart from each other in a first horizontal direction, and a third main active region and a fourth main active region extending from the central region and spaced apart from the first main active region and the second main active region in a second horizontal direction; a device isolation layer on the substrate and defining the plurality of active regions, wherein the device isolation layer includes a first portion between two adjacent active regions among the plurality of active regions, and a portion between the first main active region and the second main active region of each of the plurality of active regions and in each of the plurality of active regions. A second portion between a third main active region and a fourth main active region; a plurality of gate structures that partially overlap with two adjacent active regions among the plurality of active regions and extend in a first horizontal direction, wherein the plurality of gate structures include a first gate structure on the first main active region of the first active region, a second gate structure on the second main active region of the first active region and the first main active region of the second active region, a third gate structure on the third main active region of the first active region, and a fourth gate structure on the fourth main active region of the first active region and the third main active region of the second active region; and a drain contact that is in the central region in the plan view and is surrounded by the first to fourth gate structures.

[0007] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a substrate including a plurality of active regions, wherein each of the plurality of active regions includes a central region, a first main active region and a second main active region extending from the central region and spaced apart from each other in a first horizontal direction, and a third main active region and a fourth main active region extending from the central region and spaced apart from the first main active region and the second main active region in a second horizontal direction; a device isolation layer on the substrate and defining the plurality of active regions, wherein the device isolation layer includes a first portion between two adjacent active regions among the plurality of active regions, and a portion in the plurality of active regions... The first active region and the second active region of each of the plurality of active regions are located between the first active region and the second active region, and between the third active region and the fourth active region of each of the plurality of active regions; and the third part is integrally connected to the second part in the plan view and is at least partially surrounded by the central region; the first gate structure is located on the first active region; and the field plate electrode is electrically connected to the first gate structure and includes a first conductive layer portion and a second conductive layer portion, the first conductive layer portion being vertically overlapped with the first gate structure, and the second conductive layer portion being integrally connected to the first conductive layer portion and vertically overlapped with the third part of the device isolation layer.

[0008] According to an embodiment, the second portion of the device isolation layer may have a first width in a first horizontal direction, and the third portion of the device isolation layer may have a second width in the first horizontal direction that is greater than the first width.

[0009] According to the implementation method, the second conductive layer portion may not vertically overlap with the central region or the first main active region.

[0010] According to an embodiment, the semiconductor device may further include a second gate structure on a second main active region, a third gate structure on a third main active region, and a fourth gate structure on a fourth main active region.

[0011] According to an embodiment, the semiconductor device may further include an insulating layer on a substrate and covering the first gate structure to the fourth gate structure, and a first gate contact passing through the insulating layer and between the first gate structure and the field plate electrode.

[0012] According to an embodiment, the semiconductor device may further include a drain contact that passes through an insulating layer and is located on a central region, and in a plan view, the drain contact may be surrounded by a first gate structure to a fourth gate structure.

[0013] According to an embodiment, the substrate may further include a first source region, a second source region, a third source region, and a fourth source region, wherein the first source region is in the first main active region and is located on one side of the first gate structure in the plan view, the second source region is in the second main active region and is located on one side of the second gate structure in the plan view, the third source region is in the third main active region and is located on one side of the third gate structure in the plan view, and the fourth source region is in the fourth main active region and is located on one side of the fourth gate structure in the plan view.

[0014] According to the implementation method, each of the plurality of active regions may have an H-shape in the plan view.

[0015] According to an embodiment, the semiconductor device may further include a cell array region on a substrate, wherein the cell array region may include a plurality of word lines spaced apart from each other in a vertical direction, a plurality of channels passing through the plurality of word lines and extending in a vertical direction, and a cell contact connected to any one of the plurality of word lines, and the cell contact may be electrically connected to any one of the plurality of active regions.

[0016] According to an implementation, the cell array region may include multiple memory blocks. A first main active region of the first active region may be electrically connected to a first word line in a first memory block included among the multiple memory blocks. A second main active region of the first active region may be electrically connected to a first word line in a second memory block included among the multiple memory blocks. A third main active region may be electrically connected to a first word line in a third memory block included among the multiple memory blocks. A fourth main active region may be electrically connected to a first word line in a fourth memory block included among the multiple memory blocks. Attached Figure Description

[0017] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0018] Figure 1 This is a block diagram of a semiconductor device according to an embodiment.

[0019] Figure 2 This is a schematic perspective view of a semiconductor device according to an embodiment.

[0020] Figure 3 This is a schematic diagram of a transistor circuit according to an implementation method.

[0021] Figure 4 This is a circuit diagram of a memory block according to an implementation method.

[0022] Figure 5 It is a layout diagram of transistors included in a semiconductor device according to an embodiment.

[0023] Figure 6 yes Figure 5An enlarged layout diagram of area EN1.

[0024] Figure 7 It is along Figure 6 A cross-sectional view of a semiconductor device taken by line A-A'.

[0025] Figure 8 It is along Figure 6 A cross-sectional view of a semiconductor device taken by line B-B'.

[0026] Figure 9 It is along Figure 6 A cross-sectional view of a semiconductor device taken by line C-C'.

[0027] Figure 10 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0028] Figure 11 It is a layout diagram of transistors included in a semiconductor device according to an embodiment.

[0029] Figure 12 yes Figure 11 An enlarged layout diagram of area EN1.

[0030] Figure 13 yes Figure 12 An enlarged layout diagram of region EN2.

[0031] Figure 14 It is along Figure 12 A cross-sectional view of a semiconductor device taken by line A-A'.

[0032] Figure 15 It is along Figure 12 A cross-sectional view of a semiconductor device taken by line B-B'.

[0033] Figure 16 This is a layout diagram of a semiconductor device according to an embodiment.

[0034] Figure 17 This is a layout diagram of a semiconductor device according to an embodiment.

[0035] Figure 18 This is a layout diagram of a semiconductor device according to an embodiment.

[0036] Figure 19 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0037] Figure 20 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0038] Figure 21 This is a schematic diagram of a data storage system including a semiconductor device according to an embodiment.

[0039] Figure 22 This is a schematic perspective view of a data storage system including a semiconductor device according to an embodiment.

[0040] Figure 23 This is a schematic cross-sectional view of a semiconductor package according to an embodiment. Detailed Implementation

[0041] In the following text, embodiments will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 This is a block diagram of a semiconductor device 10 according to an embodiment.

[0043] Reference Figure 1 The semiconductor device 10 may include a memory cell array 20 and peripheral circuitry 30.

[0044] The peripheral circuitry 30 may include transistor (TR) circuitry 32, row decoder 34, page buffer 36, and control logic circuitry 38. The peripheral circuitry 30 may also include one or more of the following: data input and output circuitry, input and output interfaces, column logic, voltage generator, pre-decoder, temperature sensor, command decoder, address decoder, amplifier circuitry, etc.

[0045] The memory cell array 20 can be connected to the transistor circuit 32 via the word line WL, the serial select line SSL, and the ground select line GSL, and can be connected to the page buffer 36 via the bit line BL. The memory cell array 20 may include a plurality of memory cells, which may include, for example, flash memory cells. In the following description, embodiments are described in detail based on an example in which the plurality of memory cells are NAND flash memory cells. However, this disclosure is not limited thereto. According to some embodiments, the plurality of memory cells may include resistive memory cells, such as resistive random access memory (ReRAM), phase-change random access memory (PRAM), and magnetic random access memory (MRAM).

[0046] According to some embodiments, the memory cell array 20 may include a three-dimensional (3D) memory cell array. The 3D memory cell array may include multiple NAND strings, each of which may include memory cells respectively connected to word lines vertically stacked on a substrate. For this aspect, reference will be made to… Figure 3 Provide a detailed description.

[0047] The control logic circuit 38 can generate various control signals based on the command CMD, address ADDR, and control signal CTRL for programming data on the memory cell array 20, reading data from the memory cell array 20, or erasing data stored on the memory cell array 20. For example, the control logic circuit 38 can output row address X-ADDR and column address Y-ADDR. In doing so, the control logic circuit 38 can generally control various operations in the semiconductor device 10.

[0048] In response to row address X-ADDR, row decoder 34 can output a block select signal to block select signal line BS for selecting one of a plurality of memory blocks. Furthermore, in response to row address X-ADDR, row decoder 34 can output a word line drive signal to word line drive signal line SI for selecting one of the word lines WL of the selected memory block, a serial select line drive signal to serial select line drive signal line SS for selecting one of the serial select lines SSL of the selected memory block, and a ground select line drive signal to ground select line drive signal line GS for selecting one of the ground select lines GSL of the selected memory block. Page buffer 36 can select one or more of the bit lines BL in response to column address Y-ADDR. Specifically, page buffer 36 can operate as a write driver or a sense amplifier depending on the operating mode.

[0049] Transistor circuit 32 can be connected to line decoder 34 via block select signal line BS, serial select line drive signal line SS, word line drive signal line SI, and ground select line drive signal line GS. The serial select line drive signal line SS, word line drive signal line SI, and ground select line drive signal line GS can be referred to as "drive signal lines". Transistor circuit 32 may include multiple transistors (e.g., ... Figure 3 (32_11 to 32_16 and 32_21 to 32_26), multiple transistors can be controlled by block select signals received through multiple select signal lines BS, and serial select line drive signals, word line drive signals and ground select line drive signals can be provided to serial select line SSL, word line WL and ground select line GSL respectively.

[0050] According to one embodiment, the plurality of through transistors may have a structure in which adjacent through transistors can share a common gate, and the plurality of through transistors may have a symmetrical arrangement or structure, wherein the through transistors sharing a common gate may be configured to provide an operating voltage to the same memory block. According to one embodiment, the plurality of through transistors may further include field plate electrodes connected to the gate structure. The through transistors may be configured to apply an additional electric field to the active region, thus the through transistors may have increased operating current and / or increased breakdown voltage.

[0051] Figure 2 This is a schematic perspective view of the semiconductor device 10 according to an embodiment.

[0052] Reference Figure 2 The semiconductor device 10 may include a cell array structure CS and a peripheral circuit structure PS that overlap each other in the vertical direction.

[0053] The cell array structure CS may include references Figure 1 The memory cell array 20 is described. The peripheral circuitry PS may include references. Figure 1 The peripheral circuit 30 is described.

[0054] The cell array structure CS may include multiple memory blocks, namely, the first memory block to the nth memory block BLK1, BLK2, ... and BLKn. Each of the multiple memory cell blocks (i.e., the first memory block to the nth memory block BLK1, BLK2, ... and BLKn) may include memory cells arranged in three dimensions.

[0055] Figure 3 This is a schematic diagram of the transistor circuit 32 according to the embodiment.

[0056] Reference Figure 3 The semiconductor device 10 may include transistor circuitry 32, and transistor circuitry 32 may include multiple transistor circuits corresponding to multiple memory blocks respectively. The first memory block BLK1 and the second memory block BLK2 may be arranged adjacent to each other, and each of the first memory block BLK1 and the second memory block BLK2 may include a ground select line GSL, multiple word lines WL1 to WLm, and a serial select line SSL, where m is a positive integer.

[0057] The line decoder 34 may include a block decoder 34a and a drive signal line decoder 34b. The transistor circuit 32 may include a transistor circuit 32_1 corresponding to the first memory block BLK1 and a transistor circuit 32_2 corresponding to the second memory block BLK2. The transistor circuit 32_1 may include a plurality of transistors 32_11 to 32_16, and the transistor circuit 32_2 may include a plurality of transistors 32_21 to 32_26.

[0058] The block decoder 34a can be connected to the transistor circuit 32_1 via a first block select signal line BS1, and to the transistor circuit 32_2 via a second block select signal line BS2. The first block select signal line BS1 can be connected to the gates of multiple transistors 32_11 to 32_16. For example, when the first block select signal provided via the first block select signal line BS1 is activated, multiple transistors 32_11 to 32_16 are turned on, thus the first memory block BLK1 can be selected. Furthermore, the second block select signal line BS2 can be connected to the gates of multiple transistors 32_21 to 32_26. For example, when the second block select signal provided via the second block select signal line BS2 is activated, multiple transistors 32_21 to 32_26 are turned on, thus the second memory block BLK2 can be selected.

[0059] The drive signal line decoder 34b can be connected to transistor circuits 32_1 and 32_2 via serial select drive signal lines SS, word line drive signal lines SI1 to SIm, and ground select drive signal line GS. Specifically, each of the serial select drive signal lines SS, word line drive signal lines SI1 to SIm, and ground select drive signal line GS can be connected to the sources of multiple transistors 32_11 to 32_16 and 32_21 to 32_26.

[0060] Transistor circuit 32_1 can be connected to the first memory block BLK1 via ground select line GSL, multiple word lines WL1 to WLm, and serial select line SSL. Transistor 32_11 can be connected between ground select line drive signal line GS and ground select line GSL. Transistors 32_12 to 32_15 can be connected between word line drive signal lines SI1 to SIm and multiple word lines WL1 to WLm, respectively. Transistor 32_16 can be connected between serial select line drive signal line SS and serial select line SSL. For example, when the first block select signal is activated, transistors 32_11 to 32_16 can provide drive signals provided by ground select line drive signal line GS, word line drive signal lines SI1 to SIm, and serial select line drive signal line SS to ground select line GSL, multiple word lines WL1 to WLm, and serial select line SSL, respectively. The description of transistor circuit 32_1 can be applied to transistor circuit 32_2; therefore, the same description is excluded.

[0061] Figure 4 This is a circuit diagram of the memory block BLK according to the implementation method.

[0062] Reference Figure 4A memory block BLK may include multiple memory cell strings MS arranged vertically. The memory block BLK may include multiple bit lines BL (e.g., BL1, BL2, ..., BLm), multiple word lines WL (e.g., first word lines to nth word lines WL1, WL2, ..., WLn-1, and WLn), at least one string select line SSL, at least one ground select line GSL, and a common-source line CSL. Multiple memory cell strings MS may be formed between the multiple bit lines BL (e.g., BL1, BL2, ..., BLm) and the common-source line CSL. Figure 4 An example is shown in which each of a plurality of memory cell strings (MS) includes two string select lines (SSL). However, this disclosure is not limited thereto. For example, each of the plurality of memory cell strings (MS) may include one string select line (SSL).

[0063] Each of the multiple memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn. The drain region of the string select transistor SST may be connected to bit lines BL (e.g., BL1, BL2, ..., and BLm), and the source region of the ground select transistor GST may be connected to the common-source line CSL. The common-source line CSL may be the region to which the source regions of multiple ground select transistors GST are commonly connected.

[0064] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. Multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn can be connected to multiple word lines WL (e.g., the first word line to the nth word line WL1, WL2, ..., WLn-1 and WLn).

[0065] Figure 5 It is a layout diagram of transistors included in the semiconductor device 100 according to the embodiment. Figure 6 yes Figure 5 An enlarged layout diagram of area EN1. Figure 7 It is along Figure 6 A cross-sectional view of semiconductor device 100 taken by line A-A'. Figure 8 It is along Figure 6 A cross-sectional view of semiconductor device 100 taken by line B-B'. Figure 9 It is along Figure 6 A cross-sectional view of the semiconductor device 100 taken by line C-C'.

[0066] Reference Figures 5 to 9The semiconductor device 100 may include a plurality of active regions 112 defined on a substrate 110 and a plurality of gate structures 130 disposed on the plurality of active regions 112. The plurality of active regions 112 may be defined in the substrate 110 via a device isolation layer 120, and the gate structures 130 may be disposed on the active regions 112. The active regions 112 and the gate structures 130 disposed on the active regions 112 may form a transistor PTR. The semiconductor device 100 may be disposed on a reference... Figure 2 The external circuit structure PS is described.

[0067] According to the implementation method, such as Figure 5 As shown, each of the plurality of active regions 112 may have an H-shape in a plan view and may be arranged to be separated from each other in a first horizontal direction X. Each of the active regions 112 may be included in each of the through transistor groups (i.e., the first through transistor group to the nth through transistor group GR_WL1, GR_WL2, GR_WL3, GR_WL4, ..., GR_WLn-1 and GR_WLn). According to an embodiment, each active region 112 may be shared by four through transistors. According to an embodiment, each of the through transistor groups (i.e., the first through transistor group to the nth through transistor group GR_WL1, GR_WL2, GR_WL3, GR_WL4, ..., GR_WLn-1 and GR_WLn) may include a first through transistor PTR1, a second through transistor PTR2, a third through transistor PTR3 and a fourth through transistor PTR4 sharing an active region 112.

[0068] According to an implementation, each of the transistor groups (i.e., the first through transistor group to the nth through transistor group GR_WL1, GR_WL2, GR_WL3, GR_WL4, ..., GR_WLn-1 and GR_WLn) can be configured to send an operating voltage to the same word line included in each of the four memory blocks. For example, the first through transistor group GR_WL1 can be configured to send an operating voltage to a first word line included in the four memory blocks, and the second through transistor group GR_WL2 can be configured to send an operating voltage to a second word line included in the four memory blocks.

[0069] According to the implementation, in the first pass transistor group GR_WL1, the first pass transistor PTR1 can be configured to send an operating voltage to the first word line included in the first memory block BLK1, the second pass transistor PTR2 can be configured to send an operating voltage to the first word line included in the second memory block BLK2, the third pass transistor PTR3 can be configured to send an operating voltage to the first word line included in the third memory block BLK3, and the fourth pass transistor PTR4 can be configured to send an operating voltage to the first word line included in the fourth memory block BLK4.

[0070] According to the implementation, two adjacent transistor groups may have a symmetrical structure. For example, the first transistor group GR_WL1 and the second transistor group GR_WL2 may have a symmetrical structure. In this specification, the phrase "having a symmetrical structure" or "having a symmetrical arrangement" for the first transistor group GR_WL1 and the second transistor group GR_WL2 may indicate that the second transistor PTR2 in the first transistor group GR_WL1 and the first transistor PTR1 in the second transistor group GR_WL2 are electrically connected to the same memory block, and that the fourth transistor PTR4 in the first transistor group GR_WL1 and the third transistor PTR3 in the second transistor group GR_WL2 are electrically connected to the same memory block.

[0071] According to an embodiment, in the second pass transistor group GR_WL2, the first pass transistor PTR1 can be configured to send an operating voltage to a second word line included in the second memory block BLK2, the second pass transistor PTR2 can be configured to send an operating voltage to a second word line included in the first memory block BLK1, the third pass transistor PTR3 can be configured to send an operating voltage to a second word line included in the fourth memory block BLK4, and the fourth pass transistor PTR4 can be configured to send an operating voltage to a second word line included in the third memory block BLK3.

[0072] According to an embodiment, each of the plurality of active regions 112 may include a central region AC and first main active regions to fourth main active regions AM1, AM2, AM3 and AM4. Each of the plurality of active regions 112 may have an H-shaped planar shape and may be arranged to be separated from each other in one direction (e.g., a first horizontal direction X).

[0073] According to the implementation method, in the plan view, the central region AC can be arranged at the center of each active region 112. The first main active region AM1 to the fourth main active region AM4 can be connected to the central region AC.

[0074] According to one embodiment, the drain region D may be located above the central region AC. The drain region D may be doped with a first impurity. A drain contact 142 may be disposed on the drain region D. The drain contact 142 may be disposed within the peripheral circuit 30 (see...). Figure 1 The voltage generation circuit in the memory receives the operating voltage and can send the operating voltage to the word line WL of the selected memory block (see...). Figure 1 ), Serial select line SSL (see Figure 1 The operating voltage can be, for example, the programming voltage. The programming voltage can be a relatively high voltage, and for example, in the range of 10V to 30V.

[0075] According to the implementation method, such as Figure 6 As shown, the first main active region AM1 to the fourth main active region AM4 can be arranged to extend from the central region AC along the second horizontal direction Y. According to an embodiment, the first main active region AM1 and the second main active region AM2 can be arranged to be separated from each other in the first horizontal direction X. The third main active region AM3 and the fourth main active region AM4 can be arranged to be separated from each other in the first horizontal direction X. The central region AC can be arranged between the first main active region AM1 and the third main active region AM3 in the second horizontal direction Y, and the central region AC can also be arranged between the second main active region AM2 and the fourth main active region AM4 in the second horizontal direction Y.

[0076] According to one embodiment, substrate 110 may include a semiconductor substrate. For example, substrate 110 may include a semiconductor material, such as a group IV-based semiconductor, a group III-V-based compound semiconductor, or a group II-IV-based oxide semiconductor. For example, group IV-based semiconductors may include Si, Ge, or Si-Ge. Substrate 110 may be provided as a bulk wafer or an epitaxial layer. According to another embodiment, substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0077] According to an embodiment, in a plan view, the device isolation layer 120 may include a first portion 121 disposed at the edge of each active region 112 and a second portion 122 extending from the first portion 121 toward the inside of each active region 112.

[0078] According to one embodiment, the first portion 121 may include a portion of the device isolation layer 120 disposed between two adjacent active regions 112. According to one embodiment, the second portion 122 may include a portion of the device isolation layer 120 disposed between the first main active region AM1 and the second main active region AM2, and a portion of the device isolation layer 120 disposed between the third main active region AM3 and the fourth main active region AM4.

[0079] According to some implementations, the first main active region AM1 and the second main active region AM2 may be axially symmetrical about each other about a virtual center line extending across the central portion of the central region AC in the second horizontal direction Y, and the third main active region AM3 and the fourth main active region AM4 may be axially symmetrical about each other about the virtual center line.

[0080] The first source region S1, the second source region S2, the third source region S3, and the fourth source region S4 may be located above the first main active region AM1, the second main active region AM2, the third main active region AM3, and the fourth main active region AM4, respectively. Specifically, the first source region S1 may be located above the first main active region AM1, the second source region S2 may be located above the second main active region AM2, the third source region S3 may be located above the third main active region AM3, and the fourth source region S4 may be located above the fourth main active region AM4. The first main active region AM1 to the fourth main active region AM4 may be doped with a second impurity. The second impurity may include, for example, an n-type impurity, such as P.

[0081] Source contacts 144 may be disposed on each of the first source regions S1 to the fourth source regions S4. Source contacts 144 may include a first source contact 144_1, a second source contact 144_2, a third source contact 144_3, and a fourth source contact 144_4, respectively, which can be connected to the first source regions S1 to the fourth source regions S4. The first source contacts 144_1 to the fourth source contacts 144_4 may receive an operating voltage from the drain contact 142 and send the operating voltage to the word line WL of the selected memory block (see...). Figure 1 ), Serial select line SSL (see Figure 1 And ground selection line GSL. For example, when a memory block (e.g., first memory block BLK1) connected to the first source contact 144_1 is selected, the first source contact 144_1 can receive an operating voltage from the drain contact 142 and send the operating voltage to the word line of the first memory block BLK1.

[0082] According to an embodiment, the gate structure 130 may be arranged to extend across portions of two adjacent active regions 112 in a first horizontal direction X. The gate structure 130 may include a first gate structure 130_1, a second gate structure 130_2, a third gate structure 130_3, and a fourth gate structure 130_4. The first gate structure 130_1 to the fourth gate structure 130_4 may be arranged separately on the substrate 110.

[0083] Figure 6Two active regions 112 are shown arranged sequentially along a first horizontal direction X. Here, multiple active regions 112 may include a first active region 112_1 and a second active region 112_2 arranged separately from each other in the first horizontal direction X. For example, the first active region 112_1 may be configured to send an operating voltage to a first word line WL1 (see [reference needed]) included in each of the first memory blocks BLK1 to the fourth memory blocks BLK4. Figure 3 The second active region 112_2 can be configured to send an operating voltage to the second word line WL2 included in each of the first memory blocks BLK1 to the fourth memory blocks BLK4 (see...). Figure 3 ).

[0084] Specifically, the first gate structure 130_1 may be disposed on the first main active region AM1 of the substrate 110, the second gate structure 130_2 may be disposed on the second main active region AM2 of the substrate 110, the third gate structure 130_3 may be disposed on the third main active region AM3 of the substrate 110, and the fourth gate structure 130_4 may be disposed on the fourth main active region AM4 of the substrate 110, so as to be separate from each other. The first gate structure 130_1 to the fourth gate structure 130_4 disposed on the first active region 112_1 may be arranged diagonally relative to the drain contact 142 disposed on the center region AC of the first active region 112_1.

[0085] The first channel region, second channel region, third channel region, and fourth channel region can be respectively arranged above the first main active region AM1 to the fourth main active region AM4. The first main active region AM1 to the fourth main active region AM4 overlap with the first gate structure 130_1 to the fourth gate structure 130_4 respectively in the vertical direction Z, which is perpendicular to the first horizontal direction X and the second horizontal direction Y. For example, the first channel region can be located above the first main active region AM1, which overlaps with the first gate structure 130_1 in the vertical direction Z.

[0086] The first gate structure 130_1, together with the first source region S1 and the drain region D, can form a first pass transistor PTR1. The second gate structure 130_2, together with the second source region S2 and the drain region D, can form a second pass transistor PTR2. The third gate structure 130_3, together with the third source region S3 and the drain region D, can form a third pass transistor PTR3. The fourth gate structure 130_4, together with the fourth source region S4 and the drain region D, can form a fourth pass transistor PTR4. That is, as described above, the first pass transistor PTR1 to the fourth pass transistor PTR4 can share a single drain region D.

[0087] According to an embodiment, as described above, the gate structure 130 may be arranged to extend across portions of two adjacent active regions 112 in a first horizontal direction X. According to an embodiment, the second gate structure 130_2 may be arranged on the second main active region AM2 of the first active region 112_1 and the first main active region AM1 of the second active region 112_2, and the fourth gate structure 130_4 may be arranged on the fourth main active region AM4 of the first active region 112_1 and the third main active region AM3 of the second active region 112_2.

[0088] According to the implementation method, such as Figure 7 As shown, the second gate structure 130_2 may include a first electrode region Ga that vertically overlaps with the second main active region AM2 of the first active region 112_1, a second electrode region Gb that vertically overlaps with the first main active region AM1 of the second active region 112_2, and an electrode connection portion Ge that is disposed between the second main active region AM2 of the first active region 112_1 and the first main active region AM1 of the second active region 112_2 and vertically overlaps with the first portion 121 of the device isolation layer 120. Figure 7 The second gate structure 130_2 may include a first electrode region Ga, a second electrode region Gb, and an electrode connection portion Ge. However, the first gate structure 130_1, the third gate structure 130_3, and the fourth gate structure 130_4 may all be arranged across portions of two adjacent active regions 112, and therefore may have a structure substantially the same as the second gate structure 130_2 (i.e., a structure including the first electrode region Ga, the second electrode region Gb, and the electrode connection portion Ge).

[0089] According to the implementation, as described above, an active region 112 may be electrically connected to the same memory block as another active region 112 adjacent to the active region 112. A transistor PTR including an active region 112 may be electrically connected to the same memory block as another transistor PTR including another active region 112 adjacent to the active region 112.

[0090] According to an embodiment, the second main active region AM2 of the first active region 112_1 can be configured to apply an operating voltage to the first word line WL1 included in the second memory block BLK2, and the first main active region AM1 of the second active region 112_2 can be configured to apply an operating voltage to the second word line WL2 included in the second memory block BLK2. Therefore, the second main active region AM2 of the first active region 112_1 can be electrically connected, for example, to the first word line WL1 included in the second memory block BLK2 via the second source contact 144_2. The first main active region AM1 of the second active region 112_2 can be electrically connected, for example, to the second word line WL2 included in the second memory block BLK2 via the first source contact 144_1.

[0091] Similarly, the fourth main active region AM4 of the first active region 112_1 can be electrically connected, for example, to the first word line WL1 included in the fourth memory block BLK4 via the fourth source contact 144_4. The third main active region AM3 of the second active region 112_2 can be electrically connected, for example, to the second word line WL2 included in the fourth memory block BLK4 via the third source contact 144_3.

[0092] As described above, the second gate structure 130_2 can be arranged across the second main active region AM2 of the first active region 112_1 and the first main active region AM1 of the second active region 112_2, so as to vertically overlap with the second main active region AM2 of the first active region 112_1 and the first main active region AM1 of the second active region 112_2. Therefore, when a voltage is applied to the second gate structure 130_2, the electrode connection portion Ge of the second gate structure 130_2 can apply an electric field to the second main active region AM2 of the first active region 112_1 or the first main active region AM1 of the second active region 112_2. Therefore, the operating current of the transistor included in the first main active region AM1 or the second main active region AM2 can be increased.

[0093] According to an embodiment, a first gate structure 130_1 disposed on a first main active region AM1 of the first active region 112_1 and a second gate structure 130_2 disposed on a second main active region AM2 of the first active region 112_1 can be arranged to be separated from each other in a first horizontal direction X. The first gate structure 130_1 and the second gate structure 130_2 can be disposed on a second portion 122 of the device isolation layer 120 to be separated from each other. Furthermore, a third gate structure 130_3 disposed on a third main active region AM3 of the first active region 112_1 and a fourth gate structure 130_4 disposed on a fourth main active region AM4 of the first active region 112_1 can be arranged to be separated from each other in the first horizontal direction X. The third gate structure 130_3 and the fourth gate structure 130_4 can be disposed on a second portion 122 of the device isolation layer 120 to be separated from each other.

[0094] like Figure 7 As shown, the gate structure 130 may include a gate electrode 132 and a gate insulating layer 134. The gate electrode 132 may include a metal (such as tungsten, nickel, cobalt, and tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, and tantalum silicide), doped polysilicon, or a combination thereof. The gate insulating layer 134 may include at least one of silicon oxide, silicon nitride, and a high dielectric constant material.

[0095] According to the implementation method, such as Figure 7As shown, the upper surface of the device isolation layer 120 may be coplanar with the upper surface of the substrate 110, and the bottom surface of the electrode connection portion Ge may be coplanar with the bottom surface of the first electrode region Ga and / or the bottom surface of the second electrode region Gb.

[0096] According to an embodiment, each of the plurality of active regions 112 may include a central region AC and a first main active region AM1 to a fourth main active region AM4, and may have an H-shaped horizontal cross-section, thus forming a structure in which four through transistors PTR share a single drain region D. Therefore, compared to a semiconductor device according to the prior art in which two through transistors have a single drain forming a shared active region, the area of ​​each through transistor can be reduced.

[0097] According to one embodiment, the gate structure 130 can be used as a portion arranged across two adjacent active regions 112 and configured to apply an operating voltage to a common gate of the same memory block. Furthermore, the electrode connection portion Ge of the gate structure 130 can be configured to apply an additional electric field to portions of the active regions 112 arranged adjacent to each other. Therefore, electrons can be allowed to accumulate rapidly in the active regions 112 adjacent to the electrode connection portion Ge, thereby reducing the resistance of the active regions 112.

[0098] Simulation tests determined that the semiconductor device 100 according to the embodiment can have further improved electrical performance compared to the semiconductor device without a common gate according to the comparative embodiment. For example, the on-current was measured by applying a high programming voltage of approximately 30V to the gate structure 130 of the transistor PTR, and the off-current and breakdown voltage were measured by applying a 0V off-voltage to the gate structure 130 of the transistor PTR. Compared to the transistor according to the comparative embodiment, the on-current indication when the programming voltage is applied increases by 15% or more.

[0099] According to the above embodiment, the semiconductor device 100 can have reduced resistance in the active region 112 by having a common gate and a symmetrical arrangement of memory blocks, and therefore, the semiconductor device 100 can have increased operating current. Therefore, even when the area through the transistor PTR is reduced, the semiconductor device 100 can still have improved electrical performance.

[0100] Figure 10 This is a cross-sectional view of the semiconductor device 100A according to an embodiment.

[0101] Reference Figure 10The upper surface of the device isolation layer 120 may be recessed or recessed in a direction toward the bottom side (e.g., toward the substrate 110). According to an embodiment, the upper surface of the device isolation layer 120 (i.e., the upper surface of the first portion 121 and the upper surface of the second portion 122) may be vertically lower than the upper surface of the substrate 110. In the manufacturing method according to an embodiment, after the device isolation layer 120 is formed, the upper surface of the device isolation layer 120 may be lowered by performing a recessing process.

[0102] According to an embodiment, the electrode connection portion Ge of the gate structure 130 may be arranged on the upper surface of the first portion 121 of the device isolation layer 120, and the bottom surface of the electrode connection portion Ge may be arranged vertically below the bottom surface of the first electrode region Ga and / or the bottom surface of the second electrode region Gb.

[0103] According to the embodiment, the distance between the electrode connection portion Ge and the first main active region AM1 or the distance between the electrode connection portion Ge and the second main active region AM2 can be relatively reduced, thereby increasing the operating current of the semiconductor device 100A.

[0104] Figure 11 It is a layout diagram of transistors included in the semiconductor device 200 according to the embodiment. Figure 12 yes Figure 11 An enlarged layout diagram of area EN1. Figure 13 yes Figure 12 An enlarged layout diagram of region EN2. Figure 14 It is along Figure 12 A cross-sectional view of semiconductor device 200 taken by line A-A'. Figure 15 It is along Figure 12 A cross-sectional view of semiconductor device 200 taken by line B-B'.

[0105] Reference Figures 11 to 15 The semiconductor device 200 may include a plurality of active regions 112 defined on a substrate 110 and a plurality of gate structures 130 disposed on the plurality of active regions 112. The plurality of active regions 112 may be defined on the substrate 110 by a device isolation layer 120, and the gate structures 130 may be disposed on the active regions 112. The active regions 112 and the gate structures 130 disposed on the active regions 112 may form a transistor PTR.

[0106] According to some implementation methods, Figure 11In some embodiments shown, adjacent transistor groups may not have a symmetrical structure. For example, in the first transistor group GR_WL1, the first transistor PTR1 may be configured to send an operating voltage to a first word line included in the first memory block BLK1, and the second transistor PTR2 may be configured to send an operating voltage to a first word line included in the second memory block BLK2. Furthermore, in the second transistor group GR_WL2, the first transistor PTR1 may be configured to send an operating voltage to a second word line included in the first memory block BLK1, and the second transistor PTR2 may be configured to send an operating voltage to a second word line included in the second memory block BLK2.

[0107] However, this disclosure is not limited thereto. According to other embodiments, two adjacent transistor groups may have a structure that is symmetrical to each other.

[0108] According to an embodiment, four gate structures 130 can be arranged separately on each active region 112, and a gate structure 130 arranged on one active region 112 can be arranged separately from gate structures 130 arranged on active regions 112 adjacent to that active region 112. For example, as Figure 12 As shown, the second gate structure 130_2 arranged on the second main active region AM2 of the first active region 112_1 can be arranged to be separate from the first gate structure 130_1 arranged on the first main active region AM1 of the second active region 112_2 in the first horizontal direction X, and the second gate structure 130_2 arranged on the second main active region AM2 of the first active region 112_1 can be arranged to be separate from the first gate structure 130_1 arranged on the first main active region AM1 of the first active region 112_1 in the first horizontal direction X.

[0109] like Figure 12 As shown in the plan view, the device isolation layer 120 may include a first portion 121 disposed at the edge of each active region 112, a second portion 122 extending from the first portion 121 into the interior of each active region 112, and a third portion 123 integrally connected to the second portion 122 and at least partially surrounded by the central region AC.

[0110] According to an embodiment, the second portion 122 may have a first width w1 in the first horizontal direction X, and the third portion 123 may have a second width w2 in the first horizontal direction X that is greater than the first width w1. The second portion 122 and the third portion 123 may together have a hammer-shaped horizontal cross-section.

[0111] According to an embodiment, the third portion 123 of the device isolation layer 120 may be formed to have a wider width than the second portion 122. Therefore, in a plan view, the active region 112 may have a curved portion BP. The curved portion BP may refer to the portion in the central region AC of each active region 112 adjacent to the corner of the third portion 123 of the device isolation layer 120. In other words, the curved portion BP may refer to the portion of the central region AC adjacent to the third portion 123 of the device isolation layer 120 and having an L-shape in a plan view.

[0112] like Figure 13 As shown, a curved portion BP, arranged adjacent to the first gate structure 130_1 and adjacent to the first corner (or the left corner in the figure) of the third portion 123 of the device isolation layer 120, may have a shape symmetrical to another curved portion BP, arranged adjacent to the second gate structure 130_2 and adjacent to the second corner (or the right corner in the figure) of the third portion 123 of the device isolation layer 120. For example, one curved portion BP and the other curved portion BP may be axially symmetrical to each other with respect to a virtual centerline extending across the central portion of the central region AC in the second horizontal direction Y.

[0113] According to an embodiment, an insulating layer 150 covering the gate structure 130 may be disposed on the substrate 110, and a gate contact 146 passing through the insulating layer 150 and connected to the gate structure 130 may be disposed on the substrate 110. A drain contact 142 passing through the insulating layer 150 and connected to the drain region D of the central region AC may be further disposed on the substrate 110. A source contact 144 passing through the insulating layer 150 and connected to the first source regions S1 to the fourth source regions S4 of the first main active regions AM1 to the fourth main active regions AM4 may be further disposed on the substrate 110.

[0114] According to one embodiment, the field plate electrode 160 connected to the gate contact 146 may be disposed on the insulating layer 150. For example... Figure 13 As shown, the field plate electrode 160 may include a first conductive layer portion P1 arranged to vertically overlap with the gate structure 130. The field plate electrode 160 may include a second conductive layer portion P2 arranged to vertically overlap with the third portion 123 of the device isolation layer 120 and not vertically overlap with the gate structure 130. The second conductive layer portion P2 may be integrally connected to the first conductive layer portion P1.

[0115] According to an embodiment, the second conductive layer portion P2 of the field plate electrode 160 can be arranged so as not to overlap with the first main active region AM1 to the fourth main active region AM4 and / or the central region AC. For example... Figure 13 As shown, the second conductive layer portion P2 of the field plate electrode 160 can be arranged on the third portion 123 of the device isolation layer 120.

[0116] According to an embodiment, the field plate electrode 160 is shown to have an L-shape in a plan view. However, the planar shape of the field plate electrode 160 is not limited to this.

[0117] According to an embodiment, the field plate electrode 160 can be electrically connected to the gate structure 130 via the gate contact 146, and the same voltage can be applied to the field plate electrode 160 when a voltage is applied to the gate structure 130. The field plate electrode 160 can be configured to apply an additional electric field to a portion of the active region 112 adjacent to the third portion 123 of the device isolation layer 120. Therefore, electrons can rapidly accumulate in the portion of the active region 112 adjacent to the third portion 123 of the device isolation layer 120 (e.g., in the bent portion BP), and the resistance of the bent portion BP can be reduced. Furthermore, the first conductive layer portion P1 of the field plate electrode 160 can be arranged to vertically overlap with the gate structure 130, thus preventing and / or minimizing undesirable coupling due to the field plate electrode 160.

[0118] Simulation tests determined that the semiconductor device 200 according to the embodiment has further improved electrical performance compared to the semiconductor device according to the comparative embodiment, excluding the field plate electrode. For example, the on-current was measured by applying a high programming voltage of approximately 30V to the gate structure 130 of the through transistor PTR, and the off-current and breakdown voltage were measured by applying a 0V off-current voltage to the gate structure 130 of the through transistor PTR. Compared to the through transistor according to the comparative embodiment, the on-current indication when the programming voltage is applied increases by approximately 15.6%. Compared to the through transistor according to the comparative embodiment, the breakdown voltage when the off-current voltage is applied increases by approximately 5.9V, which corresponds to a 22% increase compared to the through transistor according to the comparative embodiment.

[0119] According to the above embodiments, the semiconductor device 200 including the field plate electrode 160 may have reduced resistance and minimized unwanted coupling in the bent portion BP, thereby having improved operating current and improved breakdown voltage characteristics.

[0120] Figure 16 This is a layout diagram of the semiconductor device 200A according to an embodiment.

[0121] Reference Figure 16 The field plate electrode 160 may include a first conductive layer portion P1 that overlaps with the gate structure 130 and a second conductive layer portion P2 that is integrally connected to the first conductive layer portion P1 and vertically overlaps with the third portion 123 of the device isolation layer 120. Figure 16The first conductive layer portion P1 is shown to have a planar shape with a zigzag pattern. However, this disclosure is not limited thereto, and the first conductive layer portion P1 may have various planar shapes that vertically overlap with the gate structure 130.

[0122] Figure 17 This is a layout diagram of the semiconductor device 200B according to an embodiment.

[0123] Reference Figure 17 Semiconductor device 200B may have the same characteristics as referenced. Figures 5 to 9 The described semiconductor device 100 has similar transistor layout characteristics. For example, the gate structure 130 can be arranged to partially overlap with two adjacent active regions 112. Furthermore, the first active region 112_1 and the second active region 112_2 can be arranged to have a symmetrical structure (e.g., a second gate structure 130_2 can be arranged on the second main active region AM2 of the first active region 112_1 and the first main active region AM1 of the second active region 112_2, and the second main active region AM2 of the first active region 112_1 and the first main active region AM1 of the second active region 112_2 can be configured to apply operating voltages to different word lines WL arranged in the same memory block BLK).

[0124] Semiconductor device 200B may also include a field plate electrode 160 electrically connected to the gate structure 130, and the field plate electrode 160 may have a bent portion BP (see Figure 13 The reduced resistance and minimized unwanted coupling in the process result in improved operating current and improved breakdown voltage characteristics.

[0125] Figure 18 This is a layout diagram of the semiconductor device 200C according to an embodiment.

[0126] Reference Figure 18 Semiconductor device 200C may have the same characteristics as referenced. Figures 5 to 9 The semiconductor device 100 described has similar transistor layout characteristics. For example, the gate structure 130 may be arranged to partially overlap with two adjacent active regions 112. Furthermore, the first active region 112_1 and the second active region 112_2 may be arranged to have a symmetrical structure. The first conductive layer portion P1 of the field plate electrode 160 may have a planar shape with a zigzag pattern. However, this disclosure is not limited to this, and the first conductive layer portion P1 may have various planar shapes that vertically overlap with the gate structure 130.

[0127] Figure 19 and Figure 20 These are cross-sectional views of semiconductor devices 300 and 400 according to the embodiments.

[0128] Reference Figure 19 The semiconductor device 300 may include a cell array structure CS and a peripheral circuit structure PS that overlap each other in the vertical direction (Z direction). According to some embodiments, the cell array structure CS may be arranged vertically above the peripheral circuit structure PS. The cell array structure CS may include a memory cell region MEC and a connection region CON arranged on one side of the memory cell region MEC in a first horizontal direction (X direction).

[0129] According to some embodiments, the semiconductor device 300 may have a chip-to-chip (C2C) structure. A C2C structure can be obtained by forming a cell array structure CS on a first wafer and a peripheral circuit structure PS on a second wafer different from the first wafer, and then connecting the cell array structure CS and the peripheral circuit structure PS by bonding. For example, bonding may instruct a first bonding pad BP1 of the cell array structure CS to bond to a second bonding pad BP2 of the peripheral circuit structure PS for electrically connecting the first bonding pad BP1 to the second bonding pad BP2. According to embodiments, when the first bonding pad BP1 and the second bonding pad BP2 comprise copper (Cu), the bonding may include a Cu-Cu bonding. According to other embodiments, each of the first bonding pad BP1 and the second bonding pad BP2 may comprise aluminum (Al) or tungsten (W).

[0130] The peripheral circuit structure PS includes a substrate 50, peripheral circuit transistors 60TR arranged on the substrate 50, and peripheral circuit line structure 70.

[0131] Substrate 50 may include a semiconductor substrate. For example, substrate 50 may include Si, Ge, or SiGe. An active region ACT may be defined on substrate 50 by a device isolation layer 52, and a plurality of peripheral circuit transistors 60TR may be formed on the active region ACT. The plurality of peripheral circuit transistors 60TR may include a peripheral circuit gate 60G and source / drain regions 62 disposed on substrate 50 at both sides of the peripheral circuit gate 60G. According to some embodiments, the plurality of peripheral circuit transistors 60TR may include those described above. Figures 1 to 18 At least one of the structures of a transistor PTR included in the described semiconductor devices 10, 100, 100A, 200, 200A, 200B and 200C.

[0132] Multiple peripheral circuit line structures 70 may include multiple peripheral circuit contacts 72 and multiple peripheral circuit line layers 74. Some of the multiple peripheral circuit line layers 74 may be configured to be electrically connected to a peripheral circuit transistor 60TR. The multiple peripheral circuit contacts 72 may be configured to connect the multiple peripheral circuit transistors 60TR to some selected from the multiple peripheral circuit line layers 74. The multiple peripheral circuit transistors 60TR and the multiple peripheral circuit line structures 70 included in the peripheral circuit structure PS may be covered by an interlayer insulating layer 80. The interlayer insulating layer 80 may include a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, a silicon oxynitride (SiON) layer, a silicon oxycarbide (SiOCN) layer, or a combination thereof.

[0133] Multiple second bonding pads BP2 may be arranged on the interlayer insulating layer 80. The multiple second bonding pads BP2 may be connected to multiple peripheral circuitry structures 70 via second bonding vias 90. According to some embodiments, the upper surface of the second bonding pads BP2 may be arranged to be coplanar with the upper surface of the interlayer insulating layer 80. The second bonding pads BP2 may include a conductive material, including copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or combinations thereof.

[0134] The cell array structure CS may include a gate stack 320 disposed on a substrate 310. The gate stack 320 may include a plurality of gate electrodes 321 and a plurality of insulating layers 323 alternately arranged in a vertical direction. The plurality of gate electrodes 321 may include, for example, tungsten, nickel, cobalt, tantalum, tungsten nitride, titanium nitride, tantalum nitride, or combinations thereof. The plurality of insulating layers 323 may include silicon oxide, silicon nitride, or silicon oxynitride. The plurality of gate electrodes 321 may correspond to cells included in a memory cell string MS (see...). Figure 4 The ground selection line GSL, word line WL, and at least one string selection line SSL are included.

[0135] The gate stack 320 may have a stepped shape on the connection region CON and may extend to have a decreasing length in the first horizontal direction (X direction) as it moves away from the substrate 310. For example, the gate stack 320 may extend on the connection region CON to have an increasing length in the first horizontal direction (X direction) as it moves away from the peripheral circuit structure PS. According to other embodiments, the gate stack 320 may extend to have the same length in the first horizontal direction (X direction) as it moves away from the substrate 310, instead of having a stepped shape on the connection region CON.

[0136] The substrate 310 and the gate stack 320 may be covered by an insulating layer 330. The insulating layer 330 may include a silicon oxide layer, a silicon nitride layer, or a combination thereof.

[0137] Multiple channel structures CHS may pass through gate stack 320 and extend vertically over the memory cell region (MEC). Each of the multiple channel structures CHS may be disposed in a channel via passing through gate stack 320. Each of the multiple channel structures CHS may include a gate insulating layer, a channel layer, a buried insulating layer, and a conductive plug. The gate insulating layer and the channel layer may be sequentially disposed on the sidewalls of the channel via. A buried insulating layer filling the remaining space of the channel via may be disposed on the channel layer. A conductive plug may be disposed to contact the channel layer to block the entrance of the channel via.

[0138] The lower surface portions of multiple channel structures CHS can contact multiple bit line contacts BLC. The multiple bit line contacts BLC can extend through a first insulating layer 340 in the vertical direction (Z direction) and are insulated from each other through the first insulating layer 340. The lower surface portions of the multiple bit line contacts BLC can contact multiple bit lines BL. The multiple bit lines BL can extend through a second insulating layer 350 in the vertical direction (Z direction) and are insulated from each other through the second insulating layer 350. Each of the multiple channel structures CHS can be connected to its corresponding bit line BL through a bit line contact BLC.

[0139] Multiple contact structures CNTs can pass through the covering insulating layer 330 and the first insulating layer 340 and extend vertically (Z-direction) over the connection area CON. The multiple contact structures CNTs can electrically connect multiple gate electrodes 321 to multiple line layers ML. For example, the upper surface portion of the multiple contact structures CNTs can contact the multiple gate electrodes 321, and the lower surface portion of the multiple contact structures CNTs can contact the multiple line layers ML. The multiple line layers ML can pass through the second insulating layer 350 and extend vertically (Z-direction), and can be insulated from each other through the second insulating layer 350. The lower surface portion of the multiple line layers ML can contact multiple first bonding vias 362. The multiple first bonding vias 362 can pass through the interlayer insulating layer 360 and extend vertically (Z-direction), and can be insulated from each other through the interlayer insulating layer 360. The lower surface portion of the first bonding via 362 can contact the first bonding pad BP1.

[0140] Among the multiple peripheral circuit transistors 60TR, and the reference... Figures 1 to 18 The peripheral circuit transistors 60TRs included in the described semiconductor devices 10, 100, 100A, 200, 200A, 200B, and 200C, via transistor PTRs, are electrically connected to multiple gate electrodes 321 via multiple contact structures CNTs. For example, among the multiple peripheral circuit transistors 60TRs, the above-mentioned references... Figures 1 to 18 The drain region D of the semiconductor devices 10, 100, 100A, 200, 200A, 200B, and 200C described (see...) Figure 8The transistor PTR can be electrically connected to multiple gate electrodes 321 via multiple contact structures CNT, and can transmit operating voltage. According to some embodiments, the drain region D of the transistor PTR and its corresponding contact structure CNT can be electrically connected to each other via peripheral circuit line structure 70, second bonding via 90, second bonding pad BP2, first bonding pad BP1, first bonding via 362 and line layer ML.

[0141] Reference Figure 20 The semiconductor device 400 may include a cell array structure CS and a peripheral circuit structure PS. Figure 20 The components of the semiconductor device 400 can be respectively connected to a reference. Figure 19 The components of the semiconductor device 300 described are substantially the same; therefore, the main differences will be described below.

[0142] The peripheral circuit structure PS of the semiconductor device 400 can be compared with a reference. Figure 19 The peripheral circuit structure PS of the semiconductor device 300 described is substantially the same or similar.

[0143] The cell array structure CS may include a gate stack 420 and a cell substrate 410 disposed between the gate stack 420 and the peripheral circuit structure PS. According to some embodiments, the cell substrate 410 may include a semiconductor material such as polysilicon.

[0144] A gate stack 420 may be disposed on a cell substrate 410. The gate stack 420 may include a plurality of gate electrodes 421 and a plurality of insulating layers 423 arranged alternately in a vertical direction. The gate stack 420 may have a stepped shape on the connection region CON and may extend to have a decreasing length in a first horizontal direction (X direction) as it moves away from the peripheral circuit structure PS and the cell substrate 410. That is, the gate stack 420 may have a stepped shape. The gate stack 420 may be covered by an insulating layer 430. According to other embodiments, the gate stack 420 may extend to have the same length in the first horizontal direction (X direction) as it moves away from the cell substrate 410, instead of having a stepped shape on the connection region CON.

[0145] Multiple channel structures (CHS) can pass through the gate stack 420 and extend vertically (Z-direction) on the memory cell region (MEC). The components of the multiple channel structures (CHS) can be compared with reference to... Figure 19 The components of the multiple channel structures described are substantially the same or similar.

[0146] The upper surface portions of multiple channel structures CHS can contact multiple bit line contacts BLC. The multiple bit line contacts BLC can extend vertically (Z-direction) through a first insulating layer 440 and are insulated from each other through the first insulating layer 440. The upper surface portions of the multiple bit line contacts BLC can contact multiple bit lines BL. The multiple bit lines BL can extend vertically (Z-direction) through a second insulating layer 450 and are insulated from each other through the second insulating layer 450. Each of the multiple channel structures CHS can be connected to its corresponding bit line BL through a bit line contact BLC.

[0147] Multiple contact structures CNTs may extend vertically (Z-direction) through the covering insulation layer 430 and the first insulation layer 440 over the connection area CON. The upper surface portion of the multiple contact structures CNTs may contact multiple wire layers ML. The multiple wire layers ML may extend vertically (Z-direction) through the second insulation layer 450 and may be insulated from each other through the second insulation layer 450.

[0148] The through-electrode TSV can pass through the first insulating layer 440, the covering insulating layer 430, and the interlayer insulating layer 80, and extends in the vertical direction (Z direction), and can be electrically connected between the line layer ML and the peripheral circuit line layer 74. The through-electrode TSV can be electrically connected to multiple gate electrodes 421 through the line layer ML and the contact structure CNT.

[0149] Among the multiple peripheral circuit transistors 60TR, and the reference... Figures 1 to 18 The peripheral circuit transistors 60TRs included in the described semiconductor devices 10, 100, 100A, 200, 200A, 200B, and 200C, corresponding to transistor PTRs, are electrically connected to multiple gate electrodes 321 via through-electrode TSV, line layer ML, and contact structure CNT. For example, among the multiple peripheral circuit transistors 60TRs, refer to... Figures 1 to 18 The semiconductor devices 10, 100, 100A, 200, 200A, 200B, and 200C described include a drain region D through a transistor PTR (see...). Figure 8 The transistor PTR can be electrically connected to multiple gate electrodes 321 via the through-electrode TSV, the line layer ML, and the contact structure CNT, and can transmit an operating voltage. According to some embodiments, the drain region D of the transistor PTR and its corresponding through-electrode TSV can be electrically connected to each other via the peripheral circuit line structure 70.

[0150] Figure 21 This is a schematic diagram of a data storage system 1000 including a semiconductor device according to an embodiment.

[0151] Reference Figure 21The data storage system 1000 may include one or more semiconductor devices 1100 and a memory controller 1200 electrically connected to the one or more semiconductor devices 1100. The data storage system 1000 may include, for example, a solid-state drive (SSD) device including one or more semiconductor devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0152] Semiconductor device 1100 may include a non-volatile semiconductor device. For example, semiconductor device 1100 may include a NAND flash memory semiconductor device, which includes a reference... Figures 1 to 20 The semiconductor device 1100 is described as one of 10, 100, 100A, 200, 200A, 200B, 200C, 300, and 400. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may include peripheral circuitry including a line decoder 1110, a page buffer 1120, and logic circuitry 1130.

[0153] The second structure 1100S may include a memory cell structure, which includes a bit line BL, a common source line CSL, multiple word lines WL, a first string select line UL1 and a second string select line UL2, a first ground select line LL1 and a second ground select line LL2, and multiple memory cell strings CSTR between the bit line BL and the common source line CSL.

[0154] Each of the multiple memory cell strings CSTRs in the second structure 1100S may include ground selection transistors LT1 and LT2 adjacent to the common source line CSL, string selection transistors UT1 and UT2 adjacent to the bit line BL, and multiple memory cell transistors MCTs disposed between the ground selection transistors LT1 and LT2 and the string selection transistors UT1 and UT2. The number of ground selection transistors LT1 and LT2 and the number of string selection transistors UT1 and UT2 may vary depending on the implementation.

[0155] According to the implementation, multiple ground select lines LL1 and LL2 can be connected to the gate electrodes of ground select transistors LT1 and LT2, respectively. A word line WL can be connected to the gate electrode of the memory cell transistor MCT. Multiple string select lines UL1 and UL2 can be connected to the gate electrodes of string select transistors UT1 and UT2, respectively.

[0156] The common-source line CSL, multiple ground select lines LL1 and LL2, multiple word lines WL, and multiple serial select lines UL1 and UL2 can be connected to the line decoder 1110. Multiple bit lines BL can be electrically connected to the page buffer 1120.

[0157] Semiconductor device 1100 can communicate with memory controller 1200 via input and output pads 1101 electrically connected to logic circuit 1130. Input and output pads 1101 can be electrically connected to logic circuit 1130.

[0158] The memory controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. According to some embodiments, the data storage system 1000 may include one or more semiconductor devices 1100, and in this case, the memory controller 1200 may control one or more semiconductor devices 1100.

[0159] Processor 1210 controls the general operation of data storage system 1000, including memory controller 1200. Processor 1210 operates according to certain firmware and controls NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 configured to handle communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to multiple memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from multiple memory cell transistors (MCTs) of semiconductor device 1100 can be sent via NAND interface 1221. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from an external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0160] Figure 22 This is a schematic perspective view of a data storage system 2000 including a semiconductor device according to an embodiment.

[0161] Reference Figure 22 According to some embodiments, a data storage system 2000 may include a main substrate 2001, a memory controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and dynamic random access memory (DRAM) 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the memory controller 2002 via a plurality of line patterns 2005 formed on the main substrate 2001.

[0162] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins of the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. According to embodiments, the data storage system 2000 may communicate with the external host via any of the interfaces, such as USB, Peripheral Component Interconnect (PCI)-High Speed, Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Memory (UFS), etc. According to embodiments, the data storage system 2000 may operate based on power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) configured to distribute power supplied from the external host to the memory controller 2002 and the semiconductor package 2003.

[0163] The memory controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0164] DRAM 2004 may include a buffer memory configured to reduce the speed difference between an external host and the semiconductor package 2003, which serves as data storage space. DRAM 2004 included in the data storage system 2000 may also operate as a type of cache memory and may provide space for temporarily storing data during control operations on the semiconductor package 2003. When DRAM 2004 is included in the data storage system 2000, in addition to the NAND controller 1220 configured to control the semiconductor package 2003, the memory controller 2002 may also include a DRAM controller configured to control DRAM 2004.

[0165] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b, which are separate from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, a bonding layer 2300 disposed on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the plurality of semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0166] The package substrate 2100 may include a printed circuit board including a plurality of package-on-package pads 2130. Each of the plurality of semiconductor chips 2200 may include input and output pads 2210. The input and output pads 2210 may correspond to Figure 21 Input and output pads 1101. Each of the plurality of semiconductor chips 2200 may include references. Figures 1 to 20 At least one of the described semiconductor devices 10, 100, 100A, 200, 200A, 200B, 200C, 300 and 400.

[0167] According to one embodiment, the connection structure 2400 may include bonding wires that electrically connect input and output pads 2210 to package-on-package pads 2130. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other via bonding wires and may be electrically connected to the package-on-package pads 2130 of the package substrate 2100. According to some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of the connection structure 2400 using a bonding wire method.

[0168] According to one embodiment, the memory controller 2002 and the plurality of semiconductor chips 2200 may be included in a single package. According to some embodiments, the memory controller 2002 and the plurality of semiconductor chips 2200 may be mounted on an insert substrate different from the main substrate 2001, and the memory controller 2002 and the plurality of semiconductor chips 2200 may be interconnected by wires formed on the insert substrate.

[0169] Figure 23 This is a schematic cross-sectional view of a semiconductor package 2003 according to an embodiment. Figure 23 It is along Figure 22 A cross-sectional view of semiconductor package 2003 taken from line II-II'.

[0170] Reference Figure 23 In semiconductor package 2003, package substrate 2100 may include a printed circuit board. Package substrate 2100 may include package substrate body portion 2120 and a plurality of package pads 2130 disposed on the upper surface of package substrate body portion 2120 (see See Figure 22 ), a plurality of lower pads 2125 disposed on or exposed therethrough on the lower surface of the main body portion 2120 of the package substrate, and a plurality of upper pads 2130 thereof (see Figure 22 Multiple internal lines 2135 electrically connected to multiple lower pads 2125 in the main body portion 2120 of the packaging substrate. For example... Figure 23As shown, multiple pads 2130 on the package can be electrically connected to multiple connection structures 2400. For example... Figure 23 As shown, multiple lower pads 2125 can be connected to multiple conductive bumps 2800. Figure 23 Multiple line patterns 2005 on the main substrate 2001 of the data storage system 2000 shown. Each of the multiple semiconductor chips 2200 may include reference... Figures 1 to 20 At least one of the described semiconductor devices 10, 100, 100A, 200, 200A, 200B, 200C, 300 and 400.

[0171] According to this disclosure, a semiconductor device may include four through transistors formed on an active region having an H-shape, and because the area of ​​each through transistor can be reduced, the size of the semiconductor device including the through transistors can be reduced. Due to the common gate between adjacent transistors, the operating current can be increased, and the operating current and breakdown voltage can be increased through the field plate electrodes. Therefore, the electrical performance of the semiconductor device can be improved.

[0172] While this specification includes numerous details of specific embodiments, these should not be construed as limiting the scope of any invention or the scope of claims, but rather as descriptions of features specific to particular embodiments of the invention. Specific features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination, one or more features from a combination may be removed from the combination in some cases, and a combination may refer to a sub-combination or a variation of a sub-combination.

[0173] Although this disclosure has been specifically shown and described with reference to its embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A substrate comprising a plurality of active regions defined by a device isolation layer, wherein each of the plurality of active regions comprises: Central area A first primary active region and a second primary active region, the first primary active region and the second primary active region extending from the central region and spaced apart from each other in a first horizontal direction, and A third primary active region and a fourth primary active region extending from the central region, wherein the third primary active region and the fourth primary active region are spaced apart from each other in the first horizontal direction and spaced apart from the first primary active region and the second primary active region in the second horizontal direction, and The plurality of active regions include a first active region and a second active region that are adjacent to each other in the first horizontal direction; A first gate structure is located on the first main active region of the first active region; and The second gate structure is located on the second main active region of the first active region and the first main active region of the second active region, and is spaced apart from the first gate structure.

2. The semiconductor device according to claim 1, wherein, The device isolation layer includes a first portion between the first active region and the second active region, and a second portion between the first main active region and the second main active region of each of the plurality of active regions. The second gate structure includes: The first electrode region vertically overlaps with the second main active region of the first active region. The second electrode region vertically overlaps with the first main active region of the second active region, and The electrode connection portion is located between the first electrode region and the second electrode region.

3. The semiconductor device according to claim 2, wherein, The electrode connection portion vertically overlaps with the first portion of the device isolation layer.

4. The semiconductor device according to claim 2, wherein, The bottom surface of the electrode connection portion is coplanar with the bottom surface of the first electrode region.

5. The semiconductor device according to claim 2, wherein, The bottom surface of the electrode connection portion is vertically lower than the bottom surface of the first electrode region.

6. The semiconductor device according to claim 1, further comprising: A third gate structure is located on the third main active region of the first active region; as well as A fourth gate structure is located on the fourth main active region of the first active region and the third main active region of the second active region, and is spaced apart from the third gate structure.

7. The semiconductor device according to claim 6, wherein, Each of the plurality of active regions includes a drain region in the central region of each of the plurality of active regions, and In the plan view, the drain region is surrounded by the first gate structure to the fourth gate structure.

8. The semiconductor device according to claim 7, wherein, Each of the plurality of active regions includes: The first source region in the first main active region, wherein, in a plan view, the first source region is located on one side of the first gate structure; The second source region in the second main active region, wherein, in a plan view, the second source region is located on one side of the second gate structure; The third source region in the third main active region, wherein, in a plan view, the third source region is located on one side of the third gate structure; and The fourth source region in the fourth main active region, wherein, in a plan view, the fourth source region is located on one side of the fourth gate structure.

9. The semiconductor device according to claim 8, further comprising: Drain contacts on the drain region; The first source contact on the first source region; The second source contact on the second source region; The third source electrode contact on the third source electrode region; as well as The fourth source contact on the fourth source region.

10. The semiconductor device according to claim 1, wherein, Each of the plurality of active regions has an H-shape in the plan view.

11. The semiconductor device according to claim 6, wherein, The plurality of active regions includes a third active region spaced apart from the second active region in the first horizontal direction, wherein the first active region is located between the third active region and the second active region. Wherein, a portion of the first gate structure is located in the second main active region of the third active region, and A portion of the third gate structure is located in the fourth main active region of the third active region.

12. The semiconductor device of claim 1, further comprising a unit array region on the substrate. in, The cell array region includes: Multiple character lines spaced apart vertically Multiple channels extending through the multiple letter lines and in the vertical direction, and The unit contact is connected to one of the multiple word lines, and The unit contact is electrically connected to one of the plurality of active regions.

13. The semiconductor device according to claim 12, wherein, The cell array region includes multiple memory blocks. The first main active region of the first active region is electrically connected to the first word line in the first memory block included among the plurality of memory blocks. Wherein, the second main active region of the first active region is electrically connected to the first word line in the second memory block included among the plurality of memory blocks, and The first main active region of the second active region is electrically connected to the second word line included in the second memory block.

14. A semiconductor device, comprising: A substrate comprising a plurality of active regions defined by a device isolation layer, wherein each of the plurality of active regions comprises: Central area Extending from the central region and spaced apart from each other in a first horizontal direction, the first main active region and the second main active region, and A third main active region and a fourth main active region extending from the central region and spaced apart from the first main active region and the second main active region in a second horizontal direction; and A plurality of gate structures, wherein the plurality of gate structures partially overlap with two adjacent active regions among the plurality of active regions and extend in the first horizontal direction, the plurality of gate structures comprising: The first gate structure is located on the first main active region of the first active region. The second gate structure is located in the second main active region of the first active region and the first main active region of the second active region. A third gate structure, which is located on the third main active region of the first active region, and A fourth gate structure is located on the fourth main active region of the first active region and the third main active region of the second active region.

15. The semiconductor device according to claim 14, wherein, The device isolation layer includes a first portion between the first active region and the second active region, and a second portion between the first main active region and the second main active region of each of the plurality of active regions, wherein the device isolation layer is located between the third main active region and the fourth main active region of each of the plurality of active regions. Each of the plurality of active regions has an H-shape in the planar view.

16. The semiconductor device according to claim 15, wherein, The second gate structure includes a first electrode region vertically overlapping the second main active region of the first active region, a second electrode region vertically overlapping the first main active region of the second active region, and an electrode connection portion between the first electrode region and the second electrode region. The electrode connection portion vertically overlaps with the first portion of the device isolation layer.

17. The semiconductor device according to claim 16, wherein, The first gate structure and the second gate structure are separated from each other in the first horizontal direction on the second portion of the device isolation layer.

18. The semiconductor device of claim 14, further comprising a cell array region on the substrate. in, The unit array area includes multiple character lines spaced apart from each other in the vertical direction, multiple channels passing through the multiple character lines and extending in the vertical direction, and a unit contact connected to one of the multiple character lines. The unit contact is electrically connected to one of the plurality of active regions.

19. The semiconductor device according to claim 18, wherein, The cell array region includes multiple memory blocks. The first main active region of the first active region is electrically connected to the first word line in the first memory block included among the plurality of memory blocks. The second main active region of the first active region is electrically connected to the first word line in the second memory block included among the plurality of memory blocks. The third main active region of the first active region is electrically connected to the first word line in the third memory block included among the plurality of memory blocks. The fourth main active region of the first active region is electrically connected to the first word line in the fourth memory block included among the plurality of memory blocks. Wherein, the first main active region of the second active region is electrically connected to the second word line included in the second memory block, and The third main active region of the second active region is electrically connected to the second word line included in the fourth memory block.

20. A semiconductor device, comprising: A substrate comprising a plurality of active regions, wherein each of the plurality of active regions comprises: Central area; A first main active region and a second main active region extending from the central region and spaced apart from each other in a first horizontal direction; and A third main active region and a fourth main active region extend from the central region and are spaced apart from the first main active region and the second main active region in a second horizontal direction; A device isolation layer is provided on the substrate and defines the plurality of active regions, wherein the device isolation layer includes a first portion between two adjacent active regions among the plurality of active regions and a second portion between a first main active region and a second main active region in each of the plurality of active regions, wherein the device isolation layer is located between a third main active region and a fourth main active region in each of the plurality of active regions. A plurality of gate structures, wherein the plurality of gate structures partially overlap with two adjacent active regions among the plurality of active regions and extend in the first horizontal direction, wherein the plurality of gate structures include: The first gate structure is located on the first main active region of the first active region. The second gate structure is located in the second main active region of the first active region and the first main active region of the second active region. A third gate structure, which is located on the third main active region of the first active region, and A fourth gate structure is located on the fourth main active region of the first active region and the third main active region of the second active region; and A drain contact, which is located in the central region in the plan view and is surrounded by the first gate structure to the fourth gate structure.

Images