Semiconductor device and data storage system including the same

Abstract

A semiconductor device includes a stack of insulating layers and electrodes, a trench structure and a separation region penetrating the stack, and a conductive layer on the stack. The separation region includes a through portion penetrating the stack, a head portion protruding into the conductive layer, and a side protrusion protruding toward the electrodes, a first side insulating layer between the separation region and the electrodes, a second side insulating layer on an inner surface of the first side insulating layer, and an insulating layer on an inner surface of the second side insulating layer. The side protrusion includes a first horizontal insulating layer including a portion of the second side insulating layer protruding toward the electrodes, and a second horizontal insulating layer including a portion of the first side insulating layer folded along the first horizontal insulating layer. The second horizontal insulating layer is in contact with upper and lower surfaces of an adjacent side protrusion.

Description

Cross-references to related applications

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2025-0057418, filed with the Korean Intellectual Property Office on April 30, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to semiconductor devices and data storage systems including such semiconductor devices. Background Technology

[0003] Data storage systems that require data storage need semiconductor devices capable of storing large amounts of data. Therefore, methods for increasing the data storage capacity of semiconductor devices are being investigated. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device comprising three-dimensional memory cells instead of two-dimensional memory cells has been proposed. Summary of the Invention

[0004] A data storage system including a semiconductor device with improved reliability is provided.

[0005] According to one aspect of this disclosure, a semiconductor device includes: a stacked structure including an interlayer insulating layer and a gate electrode stacked in a first direction; a channel structure extending through the stacked structure in the first direction; a conductive layer on the stacked structure; and separation regions extending through the stacked structure in a second direction perpendicular to the first direction and spaced apart from each other in a third direction perpendicular to the first and second directions, wherein each of the separation regions includes: a separation region through-hole portion extending through the stacked structure; at least one separation region head protruding into the conductive layer; and a side protrusion portion protruding from a side surface of the separation region through-hole portion toward the gate electrode, wherein the side protrusion portions are spaced apart from each other in the first direction; and a first side insulating layer on the separation region and the gate electrode. Between the electrodes; a second side insulating layer on the inner surface of the first side insulating layer; and a buried insulating layer on the inner surface of the second side insulating layer, wherein each of the side protrusions in the separation region includes: a first horizontal insulating layer including a portion of the second side insulating layer protruding toward one of the gate electrodes; and a second horizontal insulating layer including a portion of the first side insulating layer folded along the first horizontal insulating layer, wherein the second horizontal insulating layer of each of the side protrusions contacts the upper surface of the first horizontal insulating layer of the first side protrusion in the side protrusion and contacts the lower surface of the first horizontal insulating layer of the second side protrusion in the side protrusion, wherein the first side protrusion is adjacent to the second side protrusion in a first direction.

[0006] According to one aspect of this disclosure, a semiconductor device includes: a first semiconductor structure including a first substrate, circuit elements on the first substrate, a lower interconnect structure connected to the circuit elements, and a lower bonding structure connected to the lower interconnect structure; and a second semiconductor structure on the first semiconductor structure, the second semiconductor structure including an upper bonding structure bonded to the lower bonding structure, wherein the second semiconductor structure includes: a conductive layer; a stacked structure below the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction perpendicular to the upper surface of the conductive layer; an upper interconnect structure below the stacked structure and connected to the upper bonding structure; and a channel structure containing... The system includes a channel layer connected to a conductive layer, the channel structure penetrating a stacked structure in a first direction; and a separation region, wherein the separation region includes: a separation region through-portion penetrating the stacked structure in a second direction perpendicular to the first direction; a separation region head protruding from the separation region through-portion into the conductive layer and spaced apart from each other in the second direction; a side insulating layer contacting a side surface of the separation region through-portion; a buried insulating layer inside the side insulating layer; and an upper buried insulating layer extending from the buried insulating layer in the first direction and protruding into the interior of the conductive layer to form the separation region head, wherein the upper buried insulating layer contacts the conductive layer.

[0007] According to one aspect of this disclosure, a data storage system includes: a semiconductor device including input / output pads; and a controller connected to the semiconductor device via the input / output pads and configured to control the semiconductor device, wherein the semiconductor device includes: a stacked structure including an interlayer insulating layer and a gate electrode stacked in a first direction; a channel structure extending through the stacked structure in the first direction; a conductive layer on the stacked structure; and separation regions extending through the stacked structure in a second direction perpendicular to the first direction and spaced apart from each other in a third direction perpendicular to the first and second directions, wherein each of the separation regions includes: a separation region through-portion extending through the stacked structure; at least one separation region head protruding into the conductive layer; and a side protrusion protruding from a side surface of the separation region through-portion toward the gate electrode. The side protrusions are spaced apart from each other in a first direction; a first side insulating layer is located between the separation region and the gate electrode; a second side insulating layer is located on the inner surface of the first side insulating layer; and a buried insulating layer is located on the inner surface of the second side insulating layer, wherein each of the side protrusions in the separation region includes: a first horizontal insulating layer including a portion of the second side insulating layer protruding toward one of the gate electrodes; and a second horizontal insulating layer including a portion of the first side insulating layer folded along the first horizontal insulating layer, wherein the second horizontal insulating layer of each of the side protrusions contacts the upper surface of the first horizontal insulating layer of the first side protrusion in the side protrusion and contacts the lower surface of the first horizontal insulating layer of the second side protrusion in the side protrusion, wherein the first side protrusion is adjacent to the second side protrusion in a first direction. Attached Figure Description

[0008] The above and other aspects and features of certain embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 It is a schematic plan view of a semiconductor device according to one or more embodiments; Figure 2 This is a schematic cross-sectional view of a semiconductor device according to one or more embodiments; Figures 3 to 5 This is a partially enlarged cross-sectional view of a semiconductor device according to one or more embodiments; Figure 6 This is a schematic cross-sectional view of a semiconductor device according to one or more embodiments; Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G , Figure 7H , Figure 7I , Figure 7J , Figure 7K and Figure 7L This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more embodiments; Figure 8 This is a schematic diagram illustrating a data storage system including a semiconductor device according to one or more embodiments; and Figure 9 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to one or more embodiments. Detailed Implementation

[0009] In the following description, one or more embodiments will be referenced to the accompanying drawings. In the following, unless otherwise indicated by reference numerals, terms such as “upper,” “above,” “superior,” “upper surface,” “lower,” “lower part,” “lower surface,” “side surface,” etc., may be understood to refer to the accompanying drawings.

[0010] Throughout the following description, the same reference numerals refer to the same elements. Terms such as “unit,” “module,” “component,” and “block” can refer to hardware or software. As used herein, multiple “units,” “modules,” “components,” and “blocks” may be implemented as a single component, or a single “unit,” “module,” “component,” and “block” may comprise multiple components.

[0011] It will be understood that when an element is referred to as being “connected” or “attached” to another element, the element may be directly or indirectly connected to that other element, where an indirect connection may include a “connection via a wireless communication network”.

[0012] Furthermore, when a component "comprises" or "includes" an element, the component may also include other elements, without excluding other elements, unless there is a specific description to the contrary.

[0013] Throughout the specification, when a component is “on” another component, this includes not only the configuration where the component is in contact with the other component, but also the configuration where there is another component between the two components.

[0014] As used herein, the expressions “at least one of a, b, or c” and “at least one of a, b, and c” indicate “only a”, “only b”, “only c”, “both a and b”, “both a and c”, “both b and c”, and “all of a, b, and c”.

[0015] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, this disclosure is not limited by these terms, and these terms are only used to distinguish one element from another.

[0016] As used in this article, the singular forms “a (a, an)” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0017] Identification codes may be used for the purpose of description with respect to any method or process described herein, but are not intended to indicate the order of each step or operation. Each step or operation may be performed in a different order than that shown or described, unless the context clearly indicates otherwise. One or more steps or operations may be omitted unless the context of this disclosure clearly indicates otherwise.

[0018] In the following text, reference will be made to Figure 1 and Figure 2 Describes a semiconductor device according to one or more embodiments.

[0019] Figure 1 It is a schematic plan view of a semiconductor device according to one or more embodiments.

[0020] Figure 2 This is a schematic cross-sectional view of a semiconductor device according to one or more embodiments. Figure 2 Show Figure 1 The cross section taken along line I-I'.

[0021] Reference Figure 1 The semiconductor device 100 may include a first region R1 and a second region R2 on one side of the first region R1 in the X direction. An upper contact region R3 may be disposed between the first region R1 and the second region R2. The first region R1 may be a memory cell region in which a string of memory cells is disposed, and may be a region in which a channel structure CH is disposed. A plurality of memory blocks may be disposed in the first region R1, and tens to hundreds of memory blocks may be disposed in the first region R1.

[0022] The channel structure CH can be configured to be spaced apart from each other along rows and columns on the lower surface of the first conductive layer 201 of the first region R1. The channel structure CH can be arranged in a zigzag shape along one direction in the XY plane.

[0023] The separation region MS can be configured to penetrate at least a portion of the gate electrode 230 and extend in the X direction. The separation regions MS can be arranged parallel to each other. The separation regions MS can extend integrally in the X direction, but can extend intermittently in some regions or can be provided only in some regions. The separation region MS can be formed to have a curved surface on its side surface, and can have a structure in which curved surfaces with a convex curvature facing outward space are continuously formed. As described above, the curved structure on the side surface can be obtained by forming a plurality of separation holes that are separate from each other while forming the channel hole, and then expanding the plurality of separation holes to connect with each other through a cleaning process to form the separation region MS.

[0024] The insulating region SS may extend along the X direction between adjacent separation regions MS, spanning the first region R1 and the upper contact region R3. The insulating region SS may be configured to span part of the channel structure CH. The insulating region SS may have a predetermined width in the Y direction and may extend across multiple channel structures CH arranged in a zigzag pattern in the X direction.

[0025] The insulating region SS can penetrate the upper gate electrode 230U located at the uppermost end of the gate electrode 230. For example... Figure 2 As shown, the upper gate electrode 230U can be separated in the Y direction. In one or more embodiments, the number of gate electrodes 230U separated by the insulating region SS can vary. The insulating region SS can penetrate the upper portion of the channel structure CH, for example, the portion of the channel structure CH facing one gate electrode 230U, and thus can remove a portion of the channel structure CH. In this case, the width of the channel structure CH penetrated can be less than the radius of the channel structure CH from the channel central axis to the inner wall of the channel hole. Therefore, the insulating region SS can be configured such that the insulating region SS does not penetrate the channel central axis of the channel structure CH, and half or more of the channel structure CH remains on the upper surface, but this disclosure is not limited thereto. Each of the insulating regions SS may include an upper separating insulating layer 267. The upper separating insulating layer 267 may include an insulating material and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0026] The second region R2 may correspond to the region used for electrically connecting the channel structure CH to the peripheral circuit structure, and may be the region in which multiple word line contact plugs MC2 connected to the gate electrodes at different levels can be provided for this purpose, but this disclosure is not limited thereto.

[0027] The second region R2 may have a pseudo-channel structure DCH. The pseudo-channel structure DCH may have the same or similar structure as the channel structure CH, but may not be electrically connected to the upper interconnect structure, or may not form a memory cell string in the semiconductor device 100, which is different from the channel structure CH.

[0028] The pseudo-channel structure DCH can be arranged regularly in rows and columns in the second region R2. The diameter of the pseudo-channel structure DCH can be smaller than the maximum diameter of the word line contact plug MC2. The shape, number and / or spacing of the pseudo-channel structure DCH can be different. Unlike the channel structure CH in the semiconductor device 100, the pseudo-channel structure DCH may not be electrically connected to the upper interconnect structure, or may not form a memory cell string.

[0029] The upper contact area R3 can be defined as the area in which an upper contact plug MC1 connected to the upper gate electrode 230U is provided, and the area in which upper contact plugs MC1 for connecting the erase gate electrode and the series select gate electrode 230 (which may be a series select line) are respectively provided.

[0030] Reference Figure 2 The semiconductor device 100 may include a peripheral circuit structure PERI and a memory cell structure CELL. The peripheral circuit structure PERI may be a first semiconductor structure S1 in which a peripheral circuit region is formed on a first substrate 101, and the memory cell structure CELL may be a second semiconductor structure S2 including a common source line CSL.

[0031] The semiconductor device 100 may include a first semiconductor structure S1 defined as a peripheral circuit structure PERI, and a second semiconductor structure S2 defined as a memory cell structure CELL on the first semiconductor structure S1. The first semiconductor structure S1 and the second semiconductor structure S2 may be interconnected by bonding structures (180 and 280).

[0032] The first semiconductor structure S1 may include a first substrate 101 and circuit elements 120, a lower interconnect structure 130, a lower bonding structure 180, and a lower capping layer 190 on the first substrate 101.

[0033] The first substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate 101 may be provided as a bulk wafer or an epitaxial layer. An active region may be defined in the first substrate 101 by a device isolation layer 110. A source / drain region 105 including impurities may be disposed in a portion of the active region.

[0034] Circuit element 120 may include a transistor. Each of circuit elements 120 may include a gate dielectric layer 122, a gate electrode 124, a spacer layer 126, and a source / drain region 105. The source / drain regions 105, including impurities, may be disposed on both sides of the gate electrode 124 in a first substrate 101. The spacer layer 126 may be disposed on both sides of the gate electrode 124. The gate dielectric layer 122 may include silicon oxide, silicon nitride, or a high-k material. The gate electrode 124 may include at least one of doped silicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), or ruthenium (Ru). For example, the gate electrode 124 may include a doped polysilicon layer. According to one or more embodiments, the gate electrode 124 may be constructed as two or more multilayers.

[0035] The lower interconnect structure 130 is electrically connected to the circuit gate electrode 124 and the source / drain region 105 of the circuit element 120. The lower interconnect structure 130 may include lower contact plugs 135 and lower interconnect lines 137, at least one region of the lower interconnect line 137 being linear in shape. Some of the lower contact plugs 135 may be connected to the source / drain region 105, while another portion of the lower contact plug 135 may be connected to the circuit gate electrode 124. The lower contact plugs 135 may electrically connect the lower interconnect lines 137 disposed at different levels relative to the upper surface of the first substrate 101. The lower interconnect structure 130 may include a conductive material and may include, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each of its components may further include a diffusion barrier comprising at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). According to one or more embodiments, the number of layers and arrangement of the lower contact plug 135 and the lower interconnect line 137 constituting the lower interconnect structure 130 can be varied.

[0036] The lower bonding structure 180 can be connected to the lower interconnect structure 130. The lower bonding structure 180 may include a lower bonding pass-through 182, a lower bonding pad 184, and a lower bonding insulating layer 186. The lower bonding pass-through 182 can be connected to the lower interconnect structure 130. The lower bonding pad 184 can be connected to the lower bonding pass-through 182. The lower bonding pass-through 182 and the lower bonding pad 184 may include conductive materials, and may include, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may also include a diffusion barrier. The lower bonding insulating layer 186 may also serve as a diffusion barrier for the lower bonding pad 184, and may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The lower bonding insulating layer 186 may have a thickness thinner than the lower bonding pad 184, but this disclosure is not limited thereto. The lower bonding structure 180 may directly contact and connect to or be joined with the upper bonding structure 280 via a hybrid bonding process. For example, the lower bonding pad 184 can contact and couple to the upper bonding pad 284 via a copper-to-copper bonding, and the lower bonding insulating layer 186 can contact and couple to the upper bonding insulating layer 286 via a dielectric-to-dielectric bonding. The lower bonding structure 180, together with the upper bonding structure 280, can provide an electrical connection path between the peripheral circuit structure (S1: PERI) and the memory cell structure (S2: CELL).

[0037] A lower capping layer 190 may be disposed on the first substrate 101 to cover the circuit element 120 and the lower interconnect structure 130. The lower capping layer 190 may include multiple insulating layers. The lower capping layer 190 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.

[0038] The second semiconductor structure S2, which may be a memory cell structure, may include a first conductive layer 201 in a first region R1, which may be a memory cell region; a second conductive layer 202 on the upper surface of the first conductive layer 201; a gate electrode 230 stacked on the lower surface of the first conductive layer 201; an interlayer insulating layer 220 alternately stacked with the gate electrode 230; a channel structure CH configured to penetrate the gate electrode 230; a separation region MS extending through the gate electrode 230 in one direction; and an insulating region SS penetrating a portion of the gate electrode 230. It may also include an upper capping layer 290 covering the gate electrode 230. The gate electrodes 230 may be vertically spaced and stacked on the lower surface of the first conductive layer 201 to form a multi-level stacked structure GS1, GS2, and GS3 together with the interlayer insulating layer 220.

[0039] exist Figure 2 In the example embodiment shown, a first stacking structure to a third stacking structure GS1, GS2 and GS3 are included, but this disclosure is not limited thereto and can be constructed as three to five levels.

[0040] The levels of the stacked structure GS can be classified by the height of the stacked structure. The height of the stacked structure enables the machining of channel holes of a predetermined depth in the channel structure CH, and the levels of the stacked structure GS can be distinguished by each channel portion CH1, CH2, and CH3 of the channel structure CH. The upper and lower stacked structures located on the upper surface of the first conductive layer 201 can be referred to as the first stacked structure GS1, and the stacked structures GS2 and GS3 on the first stacked structure GS1 can be sequentially referred to as the second stacked structure GS2 and the third stacked structure GS3.

[0041] In the stacked structures GS1 to GS3, the gate electrode 230 and the interlayer insulating layer 220 can be stacked alternately in the Z direction, and the length of each of the stacked structures GS1 to GS3 in the Z direction and the number of gate electrodes 230 can be substantially the same, but are not limited thereto.

[0042] The second semiconductor structure S2 may include a channel pillar 272 for electrical connection to the first semiconductor structure S1, upper interconnect structures (271, 272, and 274) below the stacked structures GS1, GS2, and GS3, and an upper bonding structure 280 connected to the upper interconnect structures (271, 272, and 274). The second semiconductor structure S2 may be located at substantially the same level as the channel pillar 272.

[0043] The gate electrode 230 may include at least one lower gate electrode 230L forming the gate of a ground select transistor, a memory gate electrode 230M forming a plurality of memory cells, and an upper gate electrode 230U forming the gate of a string select transistor. In this case, the lower gate electrode 230L and the upper gate electrode 230U may be referred to as "lower" and "upper" based on the orientation during the manufacturing process. The number of memory gate electrodes 230M forming memory cells may be determined according to the capacity of the semiconductor device 100. According to one or more embodiments, the number of upper gate electrodes 230U and lower gate electrodes 230L may be one to two or more, and the upper gate electrodes 230U and lower gate electrodes 230L may have the same or different structures as the memory gate electrode 230M.

[0044] The gate electrode 230 may include a metallic material, such as molybdenum (Mo) or tungsten (W). According to one or more embodiments, the gate electrode 230 may include polycrystalline silicon or a metal silicide material. According to one or more embodiments, the gate electrode 230 may also include a diffusion barrier 231, for example, which may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0045] Interlayer insulating layers 220 may be disposed between gate electrodes 230 to form a stacked structure (GS1, GS2, and GS3). Interlayer insulating layers 220 may also be configured to be spaced apart from each other in a direction perpendicular to the lower surface of the first conductive layer 201, and may extend in the X direction similar to the gate electrodes 230. Interlayer insulating layers 220 may comprise an insulating material such as silicon oxide or silicon nitride.

[0046] In one or more embodiments, the thickness of the interlayer insulating layers 220 may not all be the same. For example, among the interlayer insulating layers 220, the uppermost interlayer insulating layer 222, the lowermost interlayer insulating layer 223, and the intermediate interlayer insulating layer 225 may have a greater thickness than the other interlayer insulating layers 220, but this disclosure is not limited thereto. The intermediate interlayer insulating layer 225 may be defined as the interlayer insulating layer between the stacked structures GS1, GS2, and GS3.

[0047] Each of the channel structures CH may have a configuration in which k channel portions CH1 to CHk (where k is 1, 2 or 3, any positive integer) of k stacked structures (GS1 to GSk) penetrating the gate electrode 230 are connected, and in one or more embodiments, the first channel portions CH1 to the third channel portions CH3 penetrating the three stacked structures GS1 to GS3 may be connected to each other.

[0048] like Figure 2 As shown, each of the first channel portions CH1 to the third channel portions CH3 may extend in a vertical direction (e.g., in the Z direction) perpendicular to the lower surface of the first conductive layer 201, and may have a cylindrical and inclined side surface, the width of which decreases toward the first conductive layer 201 according to the aspect ratio.

[0049] The lower ends of the upper portions of the channel portions CH1 to CH3 and the upper ends of the lower portions of the channel portions CH1 to CH3 may be connected to each other to form a folded portion CH_S. The folded portion CH_S may include a first channel folded portion CH_Sa between the first channel portion CH1 and the second channel portion CH2, and a second channel folded portion CH_Sb between the second channel portion CH2 and the third channel portion CH3.

[0050] As described above, the separation region MS can be set to extend in the X direction by penetrating the gate electrode 230.

[0051] When forming the via, the separation region MS can be formed simultaneously without requiring a separate high aspect ratio etching process for forming the separation region MS, thus performing an integrated high aspect ratio contact (HARC) etching process. Therefore, the separation region MS can be formed as follows: Figure 2The diagram shows a first separation region portion to a third separation region portion MS1, MS2 and MS3, each of which may extend in a vertical direction (e.g. in the Z direction) perpendicular to the lower surface of the first conductive layer 201 and may have an inclined side surface whose width decreases toward the first conductive layer 201 according to the aspect ratio.

[0052] The lower ends of the upper portions of the separated region portions MS1 to MS3 and the upper ends of the lower portions of the separated region portions MS1 to MS3 can be connected to each other to form a folded portion MS_S. The folded portion MS_S may include a first separated region folded portion MS_Sa between the first separated region portion MS1 ​​and the second separated region portion MS2, and a second separated region folded portion MS_Sb between the second separated region portion MS2 and the third separated region portion MS3.

[0053] The first separation region folded portion MS_Sa may be located at substantially the same level as the first channel folded portion CH_Sa. The second separation region folded portion MS_Sb may be located at substantially the same level as the second channel folded portion CH_Sb. The separation region MS may have an insulating layer disposed thereon, which will... Figure 3 Detailed description is provided.

[0054] In the following text, reference will be made to Figure 2 and Figure 3 Describe the channel structure CH and the separation region MS in detail.

[0055] Figure 3 By magnification Figure 2 The area “A” shows a partially enlarged view of the semiconductor device 100.

[0056] Reference Figure 3 Each of the channel structures CH may include a through portion CH_b (also referred to herein as the “channel structure through portion”) that penetrates the stacked structures (GS1 to GS3) and a head CH_a (also referred to herein as the “channel structure head”) that protrudes above the stacked structures (GS1 to GS3) and into the first conductive layer 201.

[0057] The channel layer 240 may be completely disposed on the through portion CH_b and the head CH_a of the channel structure CH, and the channel layer 240 may be formed as an annular shape using the side surface of the buried insulating layer 247 surrounding it. However, according to embodiments, the channel layer 240 may also have a cylindrical shape, such as a cylinder or prism without the buried insulating layer 247. The channel layer 240 may include a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be an undoped material or a material including P-type impurities or N-type impurities.

[0058] The head CH_a can directly contact the first conductive layer 201. Therefore, as Figure 3 As shown, both the upper surface and the side surface of the channel layer 240 constituting the head CH_a can be covered by the first conductive layer 201.

[0059] The channel pad 249 may be disposed in the lower portion of the channel layer 240 in the channel structure CH. The channel pad 249 may be configured to cover the lower surface of the buried insulating layer 247 and be electrically connected to the channel layer 240. The channel pad 249 may comprise, for example, doped polysilicon.

[0060] Information storage structure 245 may be disposed between gate electrode 230 and channel layer 240. Information storage structure 245 may include a tunneling layer 241, a charge storage layer 242, and a barrier layer 243 sequentially stacked from channel layer 240. Tunneling layer 241 can tunnel charge into charge storage layer 242 and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. Charge storage layer 242 may be a charge trapping layer or a floating gate conductive layer. Barrier layer 243 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. According to one or more embodiments, at least a portion of information storage structure 245 may form a channel dielectric layer extending horizontally along gate electrode 230.

[0061] The information storage structure 245 can be removed from the top of the stacked structure (GS1 to GS3) so that the head CH_a of the channel layer 240 can be exposed to the outside in the second part. Therefore, the width of the upper surface of the head CH_a of the channel structure CH can be smaller than the width W1 of the upper surface of the head MS_a of the separation region (also referred to herein as the "separation region head"). The upper end of the information storage structure 245 can contact the first conductive layer 201, and the side surface of the information storage structure 245 can be configured to surround the channel layer 240.

[0062] The channel layer 240, the information storage structure 245, and the buried insulation layer 247 can be connected to each other between the second channel portion CH2 and the first channel portion CH1, and between the third channel portion CH3 and the second channel portion CH2.

[0063] Each separation region MS may include a through portion MS_b (also referred to herein as the “separation region through portion”) that penetrates the stacked structure (GS1 to GS3), at least one head MS_a that protrudes above the stacked structure (GS1 to GS3) and into the first conductive layer 201, and side protrusions MS_c that protrude from the side surface of the through portion MS_b of the separation region MS toward the gate electrode 230 and are spaced apart from each other in the Z direction.

[0064] The through-section MS_b can be a wall structure that occupies most of the separated region MS, configured to penetrate the stacked structure (GS1 to GS3) in the Z direction and extend continuously in the X direction from a first region R1, which may be a memory cell region, to a second region R2. When viewed from above, the through-section MS_b can have a longitudinally elongated structure (longitudinal type) in which the width is narrow in the Y direction and long in the X direction, and can have a continuous curved surface in which the opposing long surfaces protrude in an outward direction. For example, it can be understood that a hemispherical or semi-elliptical shape can be continuous in the structure.

[0065] The through portion MS_b can penetrate the stacked structure (GS1 to GS3) from the top to the bottom, and can be configured such that the upper surface US1 contacts the lower surface of the first conductive layer 201, and the lower surface of the through portion MS_b is coplanar with the lower surface of the bottommost interlayer insulating layer 223 of the stacked structure.

[0066] The head MS_a may have a shape that protrudes from the upper surface US1 of the through portion MS_b into the first conductive layer 201 for a predetermined length h2. When viewed from the upper surface, each head MS_a may have a circular or angular shape and may be configured to be spaced apart from each other in the X direction on the through portion.

[0067] For example, multiple headers MS_a can be arranged in a row along the extension direction of the through portion MS_b. It can be understood that headers MS_a can be set along the center line of the width of the through portion MS_b.

[0068] A side protrusion portion MS_c can be provided from the long surface of the side surface of the through portion MS_b toward the gate electrode 230. The protrusion length of the side protrusion portion MS_c can be substantially the same, but is not limited thereto. According to an embodiment, the protrusion length can be increased toward the head MS_a.

[0069] In each head MS_a, the width W1 of the upper surface in the Y direction can be smaller than the width W2 of the lower surface of the head MS_a in the Y direction, and due to the width difference, an inclined side surface can be formed between the upper and lower surfaces. The width W3 of the upper surface US1 of the through portion MS_b in the Y direction can be at least twice the width W2 of the lower surface of the head MS_a in the Y direction, but this disclosure is not limited thereto. Due to the width difference between the upper surface US1 of the through portion MS_b and the lower surface of the head MS_a, a folded portion can be formed between the through portion MS_b and the head MS_a. The folded portion can be located at a level substantially the same as the upper surface of the uppermost interlayer insulating layer 222 of the stacked structure (GS1 to GS3).

[0070] The width W2 of the lower surface of the head MS_a may be less than or equal to twice the width W4 of the side protrusion MS_c in the Z direction, but this disclosure is not limited thereto.

[0071] A first side insulating layer 266b may be disposed in the through portion MS_b of the separation region MS, having a substantially uniform side thickness t1 from the upper end to the lower end of the through portion MS_b. The first side insulating layer 266b may be disposed between the separation region MS and the gate electrode 230. The first side insulating layer 266b may be referred to as the inner insulating layer. The first side insulating layer 266b may comprise a high-κ material, and for example, may be formed by atomic layer deposition (ALD) of alumina (Al2O3) or hafnium oxide (HfO2) having a uniform thickness t1. For example, the side thickness t1 may be approximately 2 nm, but this disclosure is not limited thereto.

[0072] When viewed in the YZ plane, the first side insulating layer 266b may include a first portion 266b_1 configured to be parallel to the side surface of the through portion MS_b, and a second portion 266b_2 extending in the Y direction parallel to the upper surface US1 of the through portion MS_b by bending the first side insulating layer 266b at a level substantially the same as the upper surface of the uppermost interlayer insulating layer 222 of the stacked structure (GS1 to GS3). The second portion 266b_2 of the first side insulating layer 266b may be disposed on a portion of the upper surface US1 of the through portion MS_b and may be in contact with the first conductive layer 201.

[0073] A second side insulating layer 265b surrounding the inner surface of the first side insulating layer 266b may be disposed in the through portion MS_b to have a uniform thickness t2. The second side insulating layer 265b may include an insulating material and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride. The side thickness t2 of the second side insulating layer 265b may be greater than the side thickness t1 of the first side insulating layer 266b. For example, by atomic layer deposition (ALD) process, the side thickness t2 may be about 25 nm to 35 nm, but this disclosure is not limited thereto.

[0074] The buried insulating layer 264 may include a lower buried insulating layer 264b and an upper buried insulating layer 264a. The lower buried insulating layer 264b is disposed in the through portion MS_b, and the upper buried insulating layer 264a extends from the lower buried insulating layer 264b in the Z direction and protrudes into the interior portion of the first conductive layer 201 to form the head MS_a.

[0075] The buried insulating layer 264 can be formed by chemical vapor deposition (CVD) and may include insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride. The second side insulating layer 265b and the buried insulating layer 264 may include different materials.

[0076] A lower buried insulating layer 264b may be disposed on the second side insulating layer 265b. When viewed in the YZ plane, the lower buried insulating layer 264b may include a first portion 264b_1 that contacts the side surface of the second side insulating layer 265b, and a second portion 264b_2 that bends along the upper surface US2 of the second side insulating layer 265b and protrudes in the Y direction. The second portion 264b_2 may be disposed on a portion of the upper surface US1 of the through portion MS_b to contact the first conductive layer 201, and may contact the side surface of the second portion 266b_2 of the first side insulating layer 266b.

[0077] Therefore, the upper surface US2 of the second side insulating layer 265b can contact the second portion 266b_2 of the first side insulating layer and the second portion 264b_2 of the lower buried insulating layer 264b. The upper surface US2 of the second side insulating layer 265b can be located at a lower level than the upper surface US1 of the through portion MS_b, and can be spaced apart from the upper surface US1 of the through portion MS_b.

[0078] Since the head MS_a of the separation region MS can directly contact the first conductive layer 201, both the upper surface and the side surface of the upper buried insulating layer 264a constituting the head MS_a can contact the first conductive layer 201. Therefore, the conductive material remaining in the head MS_a can be removed, and the upper buried insulating layer 264a can be buried in the head MS_a, thereby preventing leakage current generated when the conductive material remaining in the head MS_a contacts the first conductive layer 201, and preventing defects generated when the remaining conductive material 230R is separated from the separation region MS during the process.

[0079] The height h2 of the head MS_a of the separation region MS in the Z direction from the lower surface of the first conductive layer 201 can be basically the same as the height h1 of the head CH_a of the channel structure CH in the Z direction from the lower surface of the first conductive layer 201.

[0080] Each side protrusion portion MS_c of the separation region MS may include a first horizontal insulating layer 265a, wherein a second side insulating layer 265b is bent toward the gate electrode 230 to extend in the Y direction. The first horizontal insulating layer 265a may be located at the same level as the gate electrode 230 and may have a thickness in the Z direction equal to the thickness of each gate electrode 230. For example, the thickness may be 20 nm to 25 nm, but this disclosure is not limited thereto. The first horizontal insulating layer 265a may contact the side surface of the gate electrode 230 to protect the gate electrode 230. The first horizontal insulating layer 265a may have a length of 20 nm to 25 nm in the Y direction, but this disclosure is not limited thereto.

[0081] Each side protrusion portion MS_c of the separation region MS may include a second horizontal insulating layer 266a, wherein a first side insulating layer 266b bends along and generally conforms to a first horizontal insulating layer 265a and extends in the Y direction to be disposed on the upper and lower surfaces of the first horizontal insulating layer 265a (e.g., the second horizontal insulating layer contacts the upper surface of the first horizontal insulating layer of the first side protrusion portion in the side protrusion portion and contacts the lower surface of the first horizontal insulating layer of the second side protrusion portion in the side protrusion portion, wherein the first side protrusion portion is adjacent to the second side protrusion portion in the Z direction). The second horizontal insulating layer 266a may also be disposed on the upper and lower surfaces of the gate electrode 230 in the stacked structure (GS1 to GS3). The second horizontal insulating layer 266a may serve as a gate dielectric layer to minimize electrical interference between the gate electrodes 230. The second horizontal insulating layer 266a may be formed to have the same uniform thickness t1 as the first side insulating layer 266b. For example, the side thickness t1 may be approximately 2 nm, but this disclosure is not limited thereto.

[0082] In the following text, reference will be made to Figures 4 to 6 Describe one or more embodiments. Figure 4 and Figure 5 This is a partial enlarged view of a semiconductor device according to one or more embodiments, by magnification. Figure 2 The region “A” is used to indicate this.

[0083] Reference Figure 4 Except for the first side insulating layer 266b and the lower buried insulating layer 264b on the upper end of the through portion MS_b, the semiconductor device 100a can be connected with Figures 1 to 3 The semiconductor device 100 is the same.

[0084] Specifically, when viewed in the YZ plane, the first side insulating layer 266b may include a first portion 266b_1 and a second portion 266b_2. The first portion 266b_1 is configured to be parallel to the side surface of the through portion MS_b, and the second portion 266b_2 bends at a level substantially the same as the upper surface of the uppermost interlayer insulating layer 222 of the stacked structure (GS1 to GS3) and extends in the Y direction parallel to the upper surface US1 of the through portion MS_b. The second portion 266b_2 of the first side insulating layer 266b may extend to contact the side surface of the lower buried insulating layer 264b. Therefore, the upper surface US2 of the second side insulating layer 265b may be in complete contact with the first side insulating layer, but this disclosure is not limited thereto.

[0085] The lower buried insulating layer 264b can be disposed on the second side insulating layer 265b, can contact the side surface of the second side insulating layer 265b, and can fill the internal space of the penetrating portion MS_b. The lower buried insulating layer 264b can contact the second portion 266b_2 of the first side insulating layer 266b, and the lower buried insulating layer 264b can contact the first conductive layer 201.

[0086] Reference Figure 5 Except for the first side insulating layer 266b and the lower buried insulating layer 264b on the upper end of the through portion MS_b, the semiconductor device 100b can be connected with Figures 1 to 3 The semiconductor device 100 is the same.

[0087] The first side insulating layer 266b may not be folded to the upper end of the through portion MS_b, and when viewed in the YZ plane, the first side insulating layer 266b may extend parallel to the side surface of the through portion MS_b to contact the first conductive layer 201.

[0088] When viewed in the YZ plane, the lower buried insulating layer 264b may include a first portion 264b_1 that contacts the side surface of the second side insulating layer 265b, and a second portion 264b_2 that is folded along the upper surface US2 of the second side insulating layer 265b and protrudes in the Y direction. The second portion 264b_2 of the lower buried insulating layer 264b may be disposed on a portion of the upper surface US1 of the through portion MS_b to contact the first conductive layer 201, and may extend to contact the first side insulating layer 266b. Therefore, the upper surface US2 of the second side insulating layer 265b may be in complete contact with the second portion 264b_2 of the lower buried insulating layer 264b, but this disclosure is not limited thereto.

[0089] Figure 6 This is a schematic cross-sectional view of a semiconductor device according to one or more embodiments. In addition to including a second channel structure SCH on the channel structure CH, Figure 6 The semiconductor device 100c can be with Figures 1 to 3 The semiconductor device 100 is the same.

[0090] The second channel structure SCH can penetrate the upper gate electrode 293 to extend in the Z direction and can be connected to the channel structure CH. The second channel structure SCH can be disposed on the channel structure CH and can be configured to be offset from the channel structure CH in the horizontal direction, but this disclosure is not limited thereto.

[0091] A horizontal insulating layer 292 may be disposed between the channel structure CH and the second channel structure SCH, and may extend horizontally. The horizontal insulating layer 292 may be disposed between the upper gate electrode 293 and the bottommost interlayer insulating layer 223. The horizontal insulating layer 292 may be used as an etch stop layer when forming the second channel structure SCH, and may also be used when forming the connection pad 295.

[0092] The horizontal insulating layer 292 may include an insulating material and may include a material different from the bottom interlayer insulating layer 223. The horizontal insulating layer 292 may be a hydrogen barrier layer and may include a material that blocks or reduces hydrogen (H) diffusion. The horizontal insulating layer 292 may include a nitride and may include at least one of, for example, SiN, SiON, SiCN, or SiOCN.

[0093] Connector pads 295 can penetrate the horizontal insulating layer 292 between the channel structure CH and the second channel structure SCH to electrically connect the channel structure CH and the second channel structure SCH. Connector pads 295 can be formed by removing a portion of the horizontal insulating layer 292 and can have an upper surface coplanar with the upper surface of the horizontal insulating layer 292. Connector pads 295 can be disposed in a configuration in which the channel pads 249 are partially recessed. The specific arrangement of the connector pads 295 can be varied in embodiments. Connector pads 295 can include a conductive material and can include, for example, polysilicon.

[0094] The upper gate electrode 293 may be disposed on the XY plane and may comprise a conductive material. The upper gate electrode 293 may comprise the same material as the gate electrode 230, but may also comprise doped polysilicon.

[0095] The insulating regions SS may each include an upper separating insulating layer 267. The upper separating insulating layer 267 may include an insulating material, and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0096] The second horizontal insulating layer 294 can be configured to cover the upper gate electrode 293. The second horizontal insulating layer 294 can be disposed on the horizontal insulating layer 292 and can cover the upper surface and side surface of the upper gate electrode 293. The first capping insulating layer 291 can be disposed below the second horizontal insulating layer 294, and the first capping insulating layer 291 and the second horizontal insulating layer 294 can be formed of insulating material and can be formed as multiple insulating layers.

[0097] The second channel structure SCH may include a second channel layer, a second gate dielectric layer, a second channel buried insulating layer, and a second channel pad, each disposed in an upper channel via. The second channel layer may be formed in an annular shape surrounding the second channel buried insulating layer therein. The second channel layer may be connected to a connection pad 295 in its lower portion and may be electrically connected to the channel layer 240 of the channel structure CH via the connection pad 295.

[0098] The description of the materials of the second channel layer, the second gate dielectric layer, the second channel buried insulating layer, and the second channel pad can be applied in the same way to the above description of the channel layer 240, the information storage structure 245, the channel buried insulating layer 247, and the channel pad 249.

[0099] Figures 7A to 7L This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more embodiments.

[0100] Reference Figure 7A A first semiconductor structure S1 (PERI) including circuit elements 120, lower interconnect structure 130, lower bonding structure 180 and lower capping layer 190 and forming peripheral circuit region PERI can be formed on the first substrate 101.

[0101] First, a device isolation layer 110 can be formed in a first substrate 101, and a circuit gate dielectric layer 122 and a circuit gate electrode 124 can be sequentially formed on the first substrate 101. The device isolation layer 110 can be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 122 can be formed on the first substrate 101, and the circuit gate electrode 124 can be formed on the circuit gate dielectric layer 122. The circuit gate dielectric layer 122 and the circuit gate electrode 124 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 122 can be formed of silicon oxide, and the circuit gate electrode 124 can be formed of at least one of polysilicon or a metal silicide layer, but is not limited thereto. Next, spacer layers 126 can be formed on the two sidewalls of the circuit gate dielectric layer 122 and the circuit gate electrode 124, and impurities can be implanted into the active regions of the first substrate 101 on both sides of the circuit gate electrode 124 to form source / drain regions 105.

[0102] In the lower interconnect structure 130, the lower contact plug 135 can be formed by forming a portion of the lower capping layer 190, etching a portion to remove that portion, and filling it with conductive material. The lower interconnect line 137 can be formed, for example, by depositing conductive material and patterning it.

[0103] In the lower bonding structure 180, the lower bonding through-hole 182 can be formed by forming a portion of the lower capping layer 190, etching a portion to remove that portion, and filling it with conductive material. The lower bonding pad 184 can be formed, for example, by depositing conductive material and patterning it. The lower bonding structure 180 can be formed, for example, by a deposition process or a plating process. The lower bonding insulating layer 186 can be formed by covering a portion of the upper surface and side surface of the lower bonding pad 184, and then performing a planarization process until the upper surface of the lower bonding pad 184 is exposed.

[0104] The lower capping layer 190 can be formed as a plurality of insulating layers. The lower capping layer 190 can be part of each operation forming the lower interconnect structure 130 and the lower bonding structure 180. As a result, a first semiconductor structure S1 can be formed, which can be the peripheral circuit region PERI.

[0105] Reference Figure 7B The process for manufacturing the second semiconductor structure S2 (CELL) can then begin. On the substrate 300 (SUB), sacrificial insulating layers 218 and interlayer insulating layers 220 can be alternately stacked to form molded structures (TS1, TS2, and TS3), and sacrificial vertical structures 216a, 216b, 216c, 217a, 217b, and 217c can be formed at the locations where each vertical structure is formed.

[0106] A first channel portion CH1 (see) can be formed on the substrate 300. Figure 3 The first molded structure TS1 is formed at the height of the substrate 300. The substrate 300 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0107] The sacrificial insulating layer 218 may be a layer in which at least a portion is replaced by a portion of the gate electrode 230 through a subsequent process. The sacrificial insulating layer 218 may be formed of a different material than the interlayer insulating layer 220. For example, the interlayer insulating layer 220, as well as the uppermost interlayer insulating layer 222, the middle interlayer insulating layer 225, and the lowermost interlayer insulating layer 223, may be formed of at least one of silicon oxide or silicon nitride, and the sacrificial insulating layer 218 may be formed of a material selected from silicon, silicon oxide, silicon carbide, or silicon nitride, different from the interlayer insulating layer 220. In embodiments, the thickness of the interlayer insulating layer 220 may not all be the same. Furthermore, the thickness of the interlayer insulating layer 220 and the thickness of the sacrificial insulating layer 218, as well as the number of films constituting them, may vary relative to those shown.

[0108] The interlayer insulating layer 220 and the sacrificial insulating layer 218 of the first molded structure TS1 can be alternately stacked on the substrate 300.

[0109] A first vertical sacrificial layer 216a may be formed at a location corresponding to the first channel portion CH1. The first vertical sacrificial layer 216a may be formed by forming holes penetrating the first molding structure TS1, depositing sacrificial layer material in the holes, and performing a planarization process. When forming the holes, a plurality of spaced-apart separation holes may be formed in the region corresponding to the separation region MS, and a first separation sacrificial layer 217a filling the plurality of separation holes may be formed together. The vertical sacrificial layer including the first vertical sacrificial layer 216a and the first separation sacrificial layer 217a may include at least one of, for example, TiN or polysilicon.

[0110] Next, the second molding structure TS2 can be formed in the same manner as the first molding structure TS1, and a high aspect ratio contact (HARC) etching through the second molding structure TS2 can be performed, and a second vertical sacrificial layer 216b and a second separation sacrificial layer 217b can be formed. The third molding structure TS3, the third vertical sacrificial layer 216c, and the third separation sacrificial layer 217c can be formed in the same manner.

[0111] Therefore, it can be formed simultaneously. Figure 2 Multiple vertical sacrificial layers 216a, 216b, 216c, 217a, 217b and 217c of all vertical structures (i.e., channel structure CH and separation region MS).

[0112] Reference Figure 7C Channel structures CH, which penetrate the sacrificial insulating layer 218 and the interlayer insulating layer 220, can be formed on the substrate 300.

[0113] The channel structure CH can be formed by forming top vias on vertical sacrificial layers 216a, 216b, and 216c, then removing the vertical sacrificial layers 216a, 216b, and 216c to form a channel via with a hole shape, and filling the channel via with multiple layers. These multiple layers may include an information storage structure 245, a channel layer 240, a buried insulating layer 247, and channel pads 249.

[0114] Due to the height of the molded structures TS1 to TS3, the sidewalls of the channel structure CH may not be perpendicular to the upper surface of the substrate 300. Depending on the depth of the channel holes, the channel structure CH may be formed to recess a portion of the substrate 300.

[0115] Reference Figure 7DAn upper insulating layer 192 can be formed on the molded structure and the bottommost (topmost in the process) interlayer insulating layer 223, and an opening can be formed in the upper insulating layer 192. Through this opening, the separation sacrificial layers 217a, 217b, and 217c that fill the separation holes formed at the separation regions MS can be removed, and the separation holes can be expanded and connected to each other through cleaning, thereby forming separation region openings OP1 connected to each other in the X direction, such as... Figure 1 As shown. The side surface forming the separation region MS may have a shape in which the convex curve extends outward continuously as the plurality of separation holes extend in the circumferential direction, but this disclosure is not limited thereto. The region where the extending separation region opening OP1 penetrates the molding structure (TS1 to TS3) may have a shape similar to... Figure 3 The shape corresponds to the through portion MS_b of the separation region in the image, and the area of ​​the substrate 300 that is penetrated can have the same shape as... Figure 3 The shape corresponding to the head MS_a of the separation region. The sacrificial insulating layer 218 can be selectively removed relative to the interlayer insulating layer 220 by wet etching in the separation region opening OP1.

[0116] Reference Figure 7E The first insulating layer 266 can be formed by depositing a high-κ material in the region where the sacrificial insulating layer 218 is removed through the separation region opening OP1 and in the separation region opening OP1. Specifically, a second horizontal insulating layer 266a can be formed between the region where the sacrificial insulating layer 218 is removed and the interlayer insulating layer 220 in a direction parallel to the upper surface of the substrate 300, and a first side insulating layer 266b can be formed on the side surface of the separation region opening OP1. The first insulating layer 266 can also be deposited on the lower surface of the separation region opening OP1, but can be partially removed by a subsequent etching process, such as... Figure 7J As shown in the diagram. The first insulating layer 266 can be formed to a uniform thickness using an atomic layer deposition (ALD) process. For example, the first insulating layer 266 may include at least one of aluminum oxide (Al2O3) or hafnium oxide (HfO2), but this disclosure is not limited thereto.

[0117] Reference Figure 7F The gate electrode 230 can be formed by depositing conductive material in the region where the sacrificial insulating layer 218 is removed through the separation region opening OP1. The conductive material may include metal, polysilicon, or metal silicide. When the gate electrode 230 is entirely formed by depositing conductive material, the conductive material deposited in the separation region opening OP1 can be removed.

[0118] In this case, a portion of the gate electrode 230 can be removed in the region contacting the side surface of the separation region opening OP1, and this space can have a similar shape to... Figure 3The shape corresponds to the protruding portion MS_c of the separation region side. When all the conductive material deposited in the separation region opening OP1 is removed and the separation region opening OP1 is exposed, due to the narrow width, the same conductive material 230R as the gate electrode 230 can remain in the area. Figure 3 The header of the separated region corresponds to the region MS_a.

[0119] Reference Figure 7G The second insulating layer 265 can be formed by depositing insulating material through the separation region opening OP1. Specifically, a first horizontal insulating layer 265a can be formed between the interlayer insulating layers 220 in the region where the gate electrode 230 is not formed, within the area where the sacrificial insulating layer 218 is removed. A second side insulating layer 265b can be formed on the side surface of the separation region opening OP1. The second insulating layer 265 can be deposited on the lower surface of the separation region opening OP1, but can be removed by a subsequent etching process, such as... Figure 7H As shown. An atomic layer deposition (ALD) process can be used to form a second insulating layer 265 with an insulating material such as silicon oxide or silicon nitride at a uniform thickness. The first horizontal insulating layer 265a can protect the gate electrode 230 while contacting the side surface of the gate electrode 230.

[0120] Reference Figure 7H The second insulating layer 265 deposited on the lower surface of the separation region opening OP1 can be removed by a back-etching process. Therefore, the insulating layer 265 in the separation region opening OP1... Figure 3 In the region corresponding to the separation region head MS_a, the second insulating layer 265 can be completely removed, and the second insulating layer 265 may include a second side insulating layer 265b and a first horizontal insulating layer 265a. The process for removing the second insulating layer 265 is not limited to an etch-back process, but can be performed by various etching processes.

[0121] Reference Figure 7I The conductive material 230R remaining in the opening OP1 of the separation region can be removed by etching processes such as wet etching and / or dry etching. Therefore, as Figure 7L As shown, when the first semiconductor structure S1 and the second semiconductor structure S2 are connected and the lower end of the channel structure CH and the lower end of the separation region MS are exposed after the substrate 300 is removed (see... Figure 7L This can prevent leakage current caused by the conductive material 230R remaining in the head MS_a of the separation area coming into contact with the first conductive layer 201, and can also prevent defects caused when the remaining conductive material 230R is separated from the separation area MS during the process.

[0122] Reference Figure 7JThe first insulating layer 266 deposited on the lower surface of the separation region opening OP1 can be removed by etching processes such as wet etching and / or dry etching. Therefore, in the separation region opening OP1, in relation to... Figure 3 In the region corresponding to MS_a at the head of the separated region, the first insulating layer 266 can be completely removed. (See reference...) Figure 3 The first portion 266b_1 of the first side insulating layer 266b can be protected by the second side insulating layer 265b and therefore can be left unremoved. The second portion 266b_2 of the first side insulating layer 266b can also be partially retained by the second side insulating layer 265b without being completely removed.

[0123] Following the etching process, a buried insulating layer 264 can be buried through the separation region opening OP1 to form the separation region MS. The buried insulating layer 264 can be formed using chemical vapor deposition (CVD). The buried insulating layer 264 can be formed from at least one of silicon oxide and silicon nitride, and can be a different material from the second insulating layer 265.

[0124] Reference Figure 7K An insulating region SS intersecting with the upper gate electrode 230U can be formed, an upper interconnect structure 271 and 272 including a channel post 272 and an upper interconnect 271 can be formed, and an upper bonding structure 280 can be formed.

[0125] The upper interconnect structures 271, 272, and 274 can be formed by stacking diffusion barriers and conductive materials. The upper bonding structure 280 can be formed on the upper interconnect structures 271, 272, and 274.

[0126] The upper bonding structure 280 can be formed in a manner similar to that used to form the lower bonding structure 180. By doing so, a second semiconductor structure S2, which may be a memory cell structure (CELL), can be formed. During the manufacturing process of the semiconductor device 100, the second semiconductor structure S2 may also include a substrate 300.

[0127] Reference Figure 7L It can connect the first semiconductor structure S1, which can be a peripheral circuit structure PERI, and the second semiconductor structure S2, which can be a memory cell structure CELL.

[0128] The first semiconductor structure S1 and the second semiconductor structure S2 can be connected by applying pressure to bond the lower bonding pad 184 and the upper bonding pad 284. They can also be connected by applying pressure to bond the lower bonding insulating layer 186 and the upper bonding insulating layer 286. The second semiconductor structure S2 can be attached to the first semiconductor structure S1, with the upper bonding pad 284 facing downwards. The first semiconductor structure S1 and the second semiconductor structure S2 can be directly bonded without the intervention of adhesives such as separate adhesive layers.

[0129] When the first semiconductor structure S1 and the second semiconductor structure S2 are connected, the substrate 300 exposed on the upper part of the second semiconductor structure S2 can be removed, and the lower end of the channel structure CH can be exposed. In this case, the information storage structure 245 on the exposed second part of the channel structure CH can be removed. The information storage structure 245 can be removed by photolithography and etching processes such as wet etching and / or dry etching. Therefore, the channel layer 240 protruding above the stacked structures GS1, GS2 and GS3 of the channel structure CH can be exposed, thereby forming the head CH_a of the channel structure CH. Therefore, the channel layer 240 of the head CH_a can be in direct contact with the first conductive layer 201.

[0130] Next, as Figure 2 As shown, the first conductive layer 201 can be formed to completely cover the first region R1, which may be a cell region. The first conductive layer 201 can be formed by depositing a semiconductor layer (specifically, a crystalline silicon layer, such as a polycrystalline silicon layer). The first conductive layer 201 can be formed to have a bend along the protruding channel structure CH, but it can also be formed to have a predetermined thickness such that the upper surface can be flat. The second conductive layer 202 can be formed on the first conductive layer 201. Specifically, the second conductive layer 202 can be formed as multiple layers. A buffer layer can be conformally formed to completely cover the second conductive layer 202, and an oxide film, such as a silicon oxide film, can be formed as the buffer layer.

[0131] Figure 8 This is a schematic diagram illustrating a data storage system including a semiconductor device according to one or more embodiments.

[0132] Reference Figure 8 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a memory device including one or more semiconductor devices 1100 or an electronic device including a memory device. For example, the data storage system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0133] Semiconductor device 1100 may be a non-volatile memory device, and may be, for example, as described above. Figures 1 to 6The NAND flash memory device described herein. Semiconductor device 1100 may include a first semiconductor structure 1100F and a second semiconductor structure 1100S located on the first semiconductor structure 1100F. According to one or more embodiments, the first semiconductor structure 1100F may be configured to be adjacent to the second semiconductor structure 1100S. The first semiconductor structure 1100F may be a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second semiconductor structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR located between the bit line BL and the common source line CSL.

[0134] In the second semiconductor structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

[0135] According to one or more embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of memory cell transistor MCT, and gate upper lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0136] According to one or more embodiments, the lower transistors LT1 and LT2 may include series-connected ground selection transistors LT1 and LT2. The upper transistors UT1 and UT2 may include series selection transistors UT1 and UT2.

[0137] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection line 1125 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0138] In the first semiconductor structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the multiple memory cell transistors (MCTs) to select a memory cell transistor. The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection lines 1135 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0139] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0140] Processor 1210 controls the overall operation of data storage system 1000, including controller 1200. Processor 1210 operates according to predetermined firmware and controls NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted. Host interface 1230 provides communication functionality between data storage system 1000 and an external host. When a control command is received from an external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0141] Figure 9 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to one or more embodiments.

[0142] Reference Figure 9 A data storage system 2000 according to one or more embodiments may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 formed on the motherboard 2001.

[0143] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. According to one or more embodiments, the data storage system 2000 may communicate with the external host via any of an interface such as Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Memory (UFS), etc. According to one or more embodiments, the data storage system 2000 may operate via power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0144] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0145] DRAM 2004 can be a buffer memory used to mitigate the speed difference between the semiconductor package 2003, which may be data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 can also serve as a high-speed cache memory and can provide space for temporary data storage during control operations on the semiconductor package 2003. When the data storage system 2000 includes DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003, controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0146] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may be semiconductor packages including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0147] The package substrate 2100 may be a printed circuit board including pads 2130 on the package. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 8 Input / output pads 1101. Each semiconductor chip 2200 may include a gate stack structure and a channel structure. Each semiconductor chip 2200 may include the above-mentioned references. Figures 1 to 6 The semiconductor device described.

[0148] According to one or more embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the on-package pads 2130 of the package substrate 2100. According to embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of a bonding wire connection structure 2400.

[0149] According to one or more embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. According to one or more embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate, different from the motherboard 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected by wiring formed on the interposer substrate.

[0150] In a structure where two or more semiconductor structures are interconnected, a process for removing conductive material remaining in the header of the separation region can be added before interconnecting the semiconductor structures. This prevents leakage current when the conductive material remaining in the header of the separation region comes into contact with the first conductive layer, and also prevents defects when the remaining conductive material is separated from the separation region during the process. Therefore, a semiconductor device with improved reliability and a data storage system including the semiconductor device can be provided.

[0151] In another example embodiment, a method for manufacturing a semiconductor device includes: alternately stacking interlayer insulating layers and sacrificial insulating layers along a first direction perpendicular to the upper surface of a substrate to form a molded structure; forming a channel hole penetrating the molded structure in the first direction and a separation hole spaced apart in a second direction perpendicular to the first direction; extending the separation holes to form a continuous separation region opening in the second direction; removing the sacrificial insulating layer through the separation region opening; forming a first side insulating layer on the separation region opening; depositing conductive material between the interlayer insulating layers of the molded structure to form a gate electrode and form a stacked structure; forming a second side insulating layer surrounding an inner surface of the first side insulating layer disposed on the separation region opening; removing the second side insulating layer disposed on a lower surface of the separation region opening; removing the conductive material remaining on the lower surface of the separation region opening; removing the first side insulating layer disposed on the lower surface of the separation region opening; and burying a buried insulating layer in the separation region opening to form a separation region structure.

[0152] The separation region structure may include: a separation region through-hole portion forming a through-stack structure and a separation region head protruding into the substrate.

[0153] When forming the first side insulation layer, it may include bending the first side insulation layer and extending it into the area where the sacrificial insulation layer is removed to form a second horizontal insulation layer between the interlayer insulation layers.

[0154] Forming the first side insulating layer may include depositing alumina (Al2O3) or hafnium oxide (HfO2) as a high-κ material.

[0155] Forming the first side insulating layer may include: removing the conductive material from the opening of the separation region; and forming the first side insulating layer along the side surface and the bottom surface of the opening of the separation region, and may form a space between the side surface of the opening of the separation region and the side surface of the gate electrode.

[0156] In the opening of the separation region, the width of the shape penetrating the molded structure can be greater than the width of the shape penetrating the substrate.

[0157] In the separation region, the conductive material remaining in the region corresponding to the head in the separation region may include molybdenum (Mo) or tungsten (W).

[0158] Channel holes and separation holes can be formed using the same hole-forming process.

[0159] When forming the second side insulating layer, it may include: forming a second side insulating layer extending into the space between the side surface of the gate electrode and the opening of the separation region to form a first horizontal insulating layer.

[0160] When forming a separated region structure, the second side insulation layer and the buried insulation layer may include different materials.

[0161] Although one or more embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A stacked structure comprising an interlayer insulating layer and a gate electrode stacked in a first direction; A channel structure that penetrates the stacked structure to extend in the first direction; A conductive layer on the stacked structure; as well as Separating regions that penetrate the stacked structure to extend in a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to both the first and second directions. Each of the separated regions includes: The separation region penetrates the stacked structure; At least one separation region head protruding into the conductive layer; and Side protrusions protruding from the side surface of the portion through the separation region toward the gate electrode, wherein the side protrusions are spaced apart from each other in the first direction; A first insulating layer is located between the separation region and the gate electrode; A second insulating layer, which lies on the inner surface of the first insulating layer; and An insulating layer is buried on the inner surface of the second side insulating layer, and Each of the side protrusions in each of the separation regions includes: A first horizontal insulating layer, comprising a portion of the second side insulating layer protruding toward one of the gate electrodes; and The second horizontal insulating layer includes a portion of the first side insulating layer folded along the first horizontal insulating layer, wherein the second horizontal insulating layer of each of the side protrusions contacts the upper surface of the first horizontal insulating layer of the first side protrusion of the side protrusion and contacts the lower surface of the first horizontal insulating layer of the second side protrusion of the side protrusion, wherein the first side protrusion is adjacent to the second side protrusion in the first direction.

2. The semiconductor device according to claim 1, wherein, The second side insulation layer comprises a material different from the buried insulation layer.

3. The semiconductor device according to claim 1, wherein, The stacked structure includes an uppermost interlayer insulating layer on the lower surface of the conductive layer, and The first side insulating layer is folded at the same level as the upper surface of the uppermost interlayer insulating layer, and on at least a portion of the upper surface of the through portion of the separation region.

4. The semiconductor device according to claim 3, wherein, The upper surface of the second side insulation layer is in contact with the first side insulation layer and the buried insulation layer.

5. The semiconductor device according to claim 3, wherein, The upper surface of the second side insulation layer is in complete contact with the first side insulation layer.

6. The semiconductor device according to claim 1, wherein, The upper surface of the second side insulation layer is in complete contact with the buried insulation layer.

7. The semiconductor device according to claim 1, wherein, The second side insulating layer is spaced apart from the upper surface of the through portion of the separation region.

8. The semiconductor device according to claim 1, wherein, The channel structure includes: The channel structure penetrating the stacked structure and the channel structure head protruding into the conductive layer; A channel layer extending from the through portion of the channel structure to the head of the channel structure; and A channel dielectric layer is located between the stacked structure and the channel layer, and Wherein, the channel layer at the head of the channel structure and the buried insulating layer at the head of at least one separation region of the separation region are in complete contact with the conductive layer.

9. The semiconductor device according to claim 1, wherein, The upper surface of the head of the at least one separation region has a first width, the lower surface of the head of the at least one separation region has a second width, and the first width is smaller than the second width.

10. The semiconductor device according to claim 9, wherein, The upper surface of the through portion of the separation region has a third width, and the third width is at least twice the second width.

11. The semiconductor device according to claim 9, wherein, The side protrusion portion of each of the separated regions has a fourth width in the first direction, and the second width is less than or equal to twice the fourth width.

12. The semiconductor device according to claim 1, wherein, The channel structure includes channel portions that penetrate the stacked structure and connect in the first direction, and channel bends between the channel portions. The separation region through-portion includes a separation region portion that penetrates the stacked structure and connects in the first direction, and a separation region bending portion between the separation region portions. One of the curved portions of the channel and one of the curved portions of the separation region are located at the same level.

13. A semiconductor device, comprising: A first semiconductor structure includes a first substrate, circuit elements on the first substrate, a lower interconnect structure connected to the circuit elements, and a lower bonding structure connected to the lower interconnect structure; and A second semiconductor structure is disposed on the first semiconductor structure, the second semiconductor structure including an upper bonding structure bonded to the lower bonding structure. The second semiconductor structure includes: Conductive layer; A stacked structure, which is below the conductive layer, and includes an interlayer insulating layer and a gate electrode stacked in a first direction perpendicular to the upper surface of the conductive layer; An upper interconnection structure is located below the stacked structure and connected to the upper bonding structure; A channel structure comprising a channel layer connected to the conductive layer, the channel structure penetrating the stacked structure in the first direction; and Separated regions The separation region includes: The separation region penetrates the stacked structure in a second direction perpendicular to the first direction; The separation region heads protrude from the separation region through portion into the conductive layer and are spaced apart from each other in the second direction. A side insulating layer that contacts the side surface of the through portion of the separation region; Buried insulating layer, which is inside the side insulating layer; and An upper buried insulating layer extends from the buried insulating layer in the first direction and protrudes into the interior of the conductive layer to form the head of the separation region. The upper buried insulating layer is in contact with the conductive layer.

14. The semiconductor device according to claim 13, wherein, The side insulation layer comprises a material different from the buried insulation layer.

15. The semiconductor device of claim 13, further comprising an inner insulating layer between the stacked structure and the side insulating layer.

16. The semiconductor device of claim 15, further comprising side protrusions projecting from a side surface of the separation region through portion toward the gate electrode and spaced apart from each other in the first direction. in, The inner insulating layer extends along the side protrusions and on the upper and lower surfaces of each of the side protrusions.

17. The semiconductor device according to claim 13, wherein, The lower surface of each of the separation region heads has a second width, and the upper surface of the through portion of the separation region has a third width, wherein the second width is smaller than the third width, and The curved portion is located between the head of the separation region and the through portion of the separation region.

18. The semiconductor device according to claim 13, wherein, The channel structure includes a channel structure through-port portion penetrating the stacked structure and a channel structure head protruding into the conductive layer, the channel structure head having a first height relative to the lower surface of the conductive layer in the first direction. Wherein, the head of the separation region has a second height relative to the lower surface of the conductive layer in the first direction, and The first height and the second height are substantially the same.

19. The semiconductor device according to claim 18, wherein, The channel layer at the head of the channel structure and the upper buried insulating layer in the separation region are in complete contact with the conductive layer.

20. A data storage system, comprising: A semiconductor device, including input / output pads; as well as A controller, which is connected to the semiconductor device via the input / output pads, and is configured to control the semiconductor device. The semiconductor device includes: A stacked structure comprising an interlayer insulating layer and a gate electrode stacked in a first direction; A channel structure that penetrates the stacked structure to extend in the first direction; A conductive layer is present on the stacked structure; and Separating regions that penetrate the stacked structure to extend in a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to both the first and second directions. Each of the separated regions includes: The separation region penetrates the stacked structure; At least one separation region head protruding into the conductive layer; and Side protrusions protruding from the side surface of the portion through the separation region toward the gate electrode, wherein the side protrusions are spaced apart from each other in the first direction; A first insulating layer is located between the separation region and the gate electrode; A second insulating layer, which lies on the inner surface of the first insulating layer; and An insulating layer is buried on the inner surface of the second side insulating layer, and Each of the side protrusions in each of the separation regions includes: A first horizontal insulating layer, comprising a portion of the second side insulating layer protruding toward one of the gate electrodes; and The second horizontal insulating layer includes a portion of the first side insulating layer folded along the first horizontal insulating layer, wherein the second horizontal insulating layer of each of the side protrusions contacts the upper surface of the first horizontal insulating layer of the first side protrusion of the side protrusion and contacts the lower surface of the first horizontal insulating layer of the second side protrusion of the side protrusion, wherein the first side protrusion is adjacent to the second side protrusion in the first direction.

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