Capacitorless semiconductor memory device with hydrogen barrier layer

Abstract

The present application relates to a capacitorless semiconductor memory device having a hydrogen barrier layer. A memory cell of a capacitorless semiconductor memory device is provided. The memory cell includes a lower insulating layer disposed over a bottom layer; a write transistor disposed over the lower insulating layer; a read transistor disposed over the write transistor; and an upper insulating layer disposed over the read transistor. The upper insulating layer includes a first upper insulating layer; an upper hydrogen barrier layer disposed over the first upper insulating layer; and a second upper insulating layer disposed over the upper hydrogen barrier layer. The upper hydrogen barrier layer includes a metal-organic framework.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority to Korean Patent Application No. 10-2025-0055161, filed on April 28, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a capacitor-free semiconductor memory device. Background Technology

[0004] Semiconductor memory devices have elements for storing data. With the increasing integration of semiconductor memory devices, the proportion of volume occupied by capacitors used for data storage has increased significantly. Therefore, capacitor-free semiconductor memory devices have been proposed. Summary of the Invention

[0005] Embodiments of this disclosure provide a memory cell for a capacitor-free semiconductor memory device having a hydrogen barrier layer capable of trapping hydrogen atoms.

[0006] According to one embodiment of this disclosure, a memory cell of a capacitor-free semiconductor memory device includes: a lower insulating layer disposed above a lower substrate; a write transistor disposed above the lower insulating layer; a read transistor disposed above the write transistor; and an upper insulating layer disposed above the read transistor. The upper insulating layer includes a first upper insulating layer; an upper hydrogen barrier layer disposed above the first upper insulating layer; and a second upper insulating layer disposed above the upper hydrogen barrier layer. The upper hydrogen barrier layer comprises a metal-organic framework.

[0007] According to one embodiment of this disclosure, a memory cell of a capacitor-free semiconductor memory device includes: a lower insulating layer disposed above a bottom layer; a write transistor disposed above the lower insulating layer; a read transistor disposed above the write transistor; and an upper insulating layer disposed above the read transistor. The lower insulating layer includes a first lower insulating layer; a lower hydrogen barrier layer disposed above the first lower insulating layer; and a second lower insulating layer disposed above the lower hydrogen barrier layer. The lower hydrogen barrier layer comprises a metal-organic framework.

[0008] According to one embodiment of this disclosure, a capacitor-free semiconductor memory device includes: a peripheral circuit layer; and a memory cell layer stacked on the peripheral circuit layer. The peripheral circuit layer includes a plurality of transistors, a plurality of contact plugs, and a plurality of horizontal interconnects. The memory cell layer includes a plurality of memory cells arranged in a horizontal direction. Each of the plurality of memory cells includes a lower insulating layer; a write transistor disposed on the lower insulating layer; a read transistor disposed on the write transistor; and an upper insulating layer disposed on the read transistor. The lower insulating layer includes a lower hydrogen barrier layer. The upper insulating layer includes an upper hydrogen barrier layer.

[0009] These and other features and advantages of the embodiments of this disclosure will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a circuit diagram of a memory cell in a capacitorless semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 2 This is a three-dimensional perspective view showing a memory cell of a capacitor-free semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figures 3A to 3C This is a schematic longitudinal cross-sectional view of a memory cell of a capacitor-free semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 4A This is a plan view of the lower hydrogen barrier layer and the upper hydrogen barrier layer of a single-layer metal-organic framework according to an embodiment of the present disclosure.

[0014] Figure 4B yes Figure 4A A magnified view of region A.

[0015] Figure 4C This is a three-dimensional perspective view of a lower hydrogen barrier layer and an upper hydrogen barrier layer comprising a multilayer metal-organic framework according to an embodiment of the present disclosure.

[0016] Figure 5 This is a schematic longitudinal cross-sectional view of a capacitor-free semiconductor memory device according to an embodiment of the present disclosure. Detailed Implementation

[0017] The embodiments disclosed herein will be described in detail with reference to the accompanying drawings. The specific structural or functional descriptions of the particular embodiments are provided merely as examples to illustrate the technical concepts disclosed in this application. However, it should be understood that those skilled in the art can implement various other examples or embodiments based on the technical concepts of this disclosure in various forms without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the described examples or embodiments.

[0018] All the crosshairs in the diagram represent corresponding or similar areas between the diagrams, rather than representing material related to these areas.

[0019] When one element is labeled "connected" or "coupled" to another element, the two elements can be directly connected or coupled, or they can be connected or coupled through an intermediate element between them. When two elements are labeled "directly connected" or "directly coupled," one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.

[0020] When one element is identified as being "above", "on top of", "below", or "under" another element, these elements may be in direct contact with each other, or an intermediate element may be placed between these elements.

[0021] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “up,” “down,” “below,” “below,” “above,” “side,” “above,” “topmost,” “below,” “bottommost,” “front,” “back,” “left,” “right,” “column,” “row,” “layer,” and other terms that suggest relative spatial relationships or directions are used for ease of description or reference to the accompanying drawings and are not intended to be limiting. Within the scope of this disclosure, other spatial relationships or directions not shown in the drawings or described in the specification may exist.

[0022] Terms such as "first" and "second" are used to distinguish individual elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be referred to as the second element, while in another example, the second element may be referred to as the first element.

[0023] In the specification, when an element included in an embodiment is described in the singular, the element may be interpreted as including multiple elements that perform the same or similar functions.

[0024] The relevant concepts are disclosed herein in conjunction with the examples and embodiments described below. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be understood in an illustrative rather than restrictive manner. Therefore, the scope of this disclosure is not limited to the following description. All changes within the equivalent meaning and scope of the claims are included within its scope.

[0025] Figure 1 This is a circuit diagram of a memory cell MC in a capacitorless semiconductor memory device according to an embodiment of the present disclosure. (See also...) Figure 1 The memory cell MC of a semiconductor device may include a write transistor WT and a read transistor RT. The write gate electrode WG of the write transistor WT is electrically connected to the write word line W-WL. The write source electrode WS of the write transistor WT is electrically connected to the write bit line W-BL. The write drain electrode WD of the write transistor WT is electrically connected to the read gate electrode RG of the read transistor RT. The read source electrode RS of the read transistor RT is electrically connected to the read word line R-WL. The read drain electrode RD of the read transistor RT is electrically connected to the read bit line R-BL.

[0026] (Write operation)

[0027] A positive (+) voltage can be applied from the write word line W-WL to the write gate electrode WG of the write transistor WT, and a current corresponding to the input data value can be provided from the write bit line W-BL to the write source electrode WS. The current provided to the write source electrode WS can be provided to the write drain electrode WD through the write channel layer of the write transistor WT. The current provided to the write drain electrode WD can be provided as a voltage to the read gate electrode RG of the read transistor RT. Therefore, charge can be trapped in the gate dielectric layer of the read transistor RT (e.g., the memory node SN). When a positive (+) current is provided to the write drain electrode WD, charge can be trapped in the memory node SN. Therefore, the read channel layer of the read transistor RT can have a low resistance state (logic high, data 1). When a negative (-) current or a zero (0) current is provided to the write drain electrode WD, charge can be released from the memory node SN. Therefore, the read channel layer of the read transistor RT can have a high resistance state (logic low, data 0). During a write operation, the read word line R-WL and the read bit line R-BL can be floated or grounded. In one embodiment, the interpretations of logical high and logical low can be opposite. That is, logical low can be interpreted as data 1, and logical high can be interpreted as data 0.

[0028] (Read operation)

[0029] When current is applied from the read word line R-WL to the read source electrode RS of the read transistor RT, this current is supplied to the read drain electrode RD of the read transistor RT. The current supplied to the read drain electrode RD can have a high or low current value, depending on the data value stored in the memory node SN. Therefore, the current supplied to the read drain electrode RD can be supplied to the read bit line R-BL. The current supplied to the read bit line R-BL can be sensed and amplified by a sense amplifier and interpreted as a logic high or logic low data value. During a read operation, the write word line W-WL and the write bit line W-BL can be in a floating or grounded state.

[0030] Figure 2 This is a three-dimensional perspective view of a memory cell MC of a capacitorless semiconductor memory device according to an embodiment of the present disclosure. (Reference) Figure 2 A capacitor-free semiconductor memory device may include a vertically arranged and stacked write transistor WT and read transistor RT.

[0031] The write transistor WT may include a write source electrode WS, a write channel layer W-CH, a write gate electrode WG, and a write drain electrode WD. The write source electrode WS may be part of a write bit line W-BL. The write bit line W-BL may have a line shape extending along a first horizontal direction X. The write channel layer W-CH may be disposed on the write source electrode WS in a pillar shape extending along a vertical direction Z. The write gate electrode WG may surround a side surface of the write channel layer W-CH. For example, the write channel layer W-CH may perpendicularly pass through the write gate electrode WG. Therefore, the write transistor WT may have a gate-all-around (GAA) channel structure. The write gate electrode WG may be part of a write word line W-WL. The write word line W-WL may have a line shape extending along a second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other. The write drain electrode WD may be disposed on the write channel layer W-CH. The write channel layer W-CH and the write drain electrode WD may form a pillar shape.

[0032] The read transistor RT may include a read gate electrode RG, a memory node SN, a read channel layer R-CH, a read source electrode RS, and a read drain electrode RD. The read gate electrode RG may be a component shared with the write drain electrode WD. In one embodiment, the read gate electrode RG may be a component electrically connected to the write drain electrode WD. The memory node SN may be disposed on the read gate electrode RG. For example, the memory node SN may be the gate dielectric layer of the read transistor RT. The read channel layer R-CH may be disposed on the memory node SN in a pillar shape. The read source electrode RS may be configured to contact a first side surface of the read channel layer R-CH. For example, the read source electrode RS may partially surround the first side surface of the read channel layer R-CH. The read source electrode RS may be a portion of a read word line R-WL. The read word line R-WL may have a line shape extending along a first horizontal direction X. The read drain electrode RD may be configured to contact a second side surface of the read channel layer R-CH. For example, the read drain electrode RD may partially surround the second side surface of the read channel layer R-CH. The first side surface and the second side surface may be opposite each other. The read drain electrode RD may be part of the read bit line R-BL. The read bit line R-BL may extend along a first horizontal direction X. The read word line R-WL and the read bit line R-BL may be parallel to each other. The write channel layer W-CH, the write drain electrode WD and / or the read gate electrode RG, the memory node SN, and the read channel layer R-CH may be formed into a cylindrical shape or a polygonal cylindrical shape.

[0033] Figures 3A to 3C This is a longitudinal cross-sectional schematic diagram of memory cells MCa to MCc of a capacitor-free semiconductor memory device according to an embodiment of the present disclosure. (Reference) Figures 3A to 3CThe memory cells MCa to MCc of the capacitorless semiconductor memory device may each include a lower insulating layer 10 disposed on a bottom layer 50, a write transistor 20 disposed on the lower insulating layer 10, a read transistor 30 disposed on the write transistor 20, and an upper insulating layer 40 disposed on the read transistor 30. The bottom layer 50 may include a silicon oxide-based insulating layer. In one embodiment, the bottom layer 50 may include a peripheral circuit structure.

[0034] refer to Figure 3A and Figure 3C Each of the storage cells MCa and MCc may have a lower insulating layer 10 comprising a first lower insulating layer 11, an insulating lower hydrogen barrier layer 15, and a second lower insulating layer 17. The lower hydrogen barrier layer 15 may be disposed between the first lower insulating layer 11 and the second lower insulating layer 17. In one embodiment, the first lower insulating layer 11 may be omitted. Therefore, the lower hydrogen barrier layer 15 may be disposed between the bottom layer 50 and the second lower insulating layer 17. The lower insulating layer 10 may be formed in a wide plate shape. That is, the first lower insulating layer 11, the lower hydrogen barrier layer 15, and the second lower insulating layer 17 may all be formed in a wide plate shape. (Reference) Figure 3B The lower insulating layer 10 of the memory cell MCb can be a single layer. For example, the lower insulating layer 10 can be one of a first lower insulating layer 11 and a second lower insulating layer 17. Furthermore, the lower insulating layer 10 can be a stack of the first lower insulating layer 11 and the second lower insulating layer 17. That is, the lower hydrogen barrier layer 15 can be omitted.

[0035] refer to Figures 3A to 3C The write transistor 20 may include a write source electrode 21, a write channel layer 23, a write gate dielectric layer 22, a write gate electrode 25, and a write drain electrode 27. The write source electrode 21 may be disposed on the lower insulating layer 10. The write source electrode 21 may be part of a write bit line W-BL having a line shape extending along a first horizontal direction X. The write channel layer 23 may be disposed on the write source electrode 21 in a pillar shape extending along a vertical direction Z. The write gate dielectric layer 22 may have an annular or cylindrical shape surrounding the sidewalls of the write channel layer 23. The write gate electrode 25 may surround the side surface of the write gate dielectric layer 22. That is, the write gate dielectric layer 22 may be disposed between the write channel layer 23 and the write gate electrode 25. The write gate electrode 25 may be part of a write word line W-WL having a line shape extending along a second horizontal direction Y. The write drain electrode 27 may be disposed on the write channel layer 23 to have a pad shape.

[0036] refer to Figures 3A to 3CThe read transistor 30 may include a read gate electrode 31, a memory node 32, a read channel layer 33, a read source electrode 35, and a read drain electrode 37. The read gate electrode 31 may be the same element as the write drain electrode 27. In one embodiment, the read gate electrode 31 may be an element disposed on and electrically connected to the write drain electrode 27. The memory node 32 may be disposed on the read gate electrode 31. For example, the memory node 32 may be a read gate dielectric layer disposed between the read gate electrode 31 and the read channel layer 33. The read channel layer 33 may be disposed in a pillar shape on the memory node 32. The read source electrode 35 may be configured to contact a first side of the read channel layer 33. The read source electrode 35 may be a portion of a read word line R-WL having a line shape extending along a first horizontal direction X. The read drain electrode 37 may be configured to contact a second side of the read channel layer 33. The first and second sides may be opposite each other. The read drain electrode 37 may be a portion of a read bit line R-BL having a line shape extending along a first horizontal direction X. The read word line R-WL and the read bit line R-WL can be parallel to each other. The write channel layer 23, the write drain electrode 27 and / or the read gate electrode 31, the memory node 32 and the read channel layer 33 can have a cylindrical shape or a polygonal cylindrical shape.

[0037] Both the write channel layer 23 and the read channel layer 33 may comprise at least one of doped polysilicon, a metal oxide layer, or a two-dimensional transition metal chalcogenide material layer. The metal oxide layer may include at least one of indium oxide (In₂O₃), titanium (Ti) doped indium oxide (In₂O₃), tungsten (W) doped indium oxide (In₂O₃), silicon (Si) doped indium gallium zinc oxide (IGZO or InGaZnO), gallium silicon doped zinc oxide (SGZO or SnGaZnO), ZnO, or indium gallium oxide (IGO or InGaO). The two-dimensional transition metal chalcogenide material layer may include at least one of molybdenum disulfide (MoS₂), tungsten disulfide (WSe₂), tungsten diselenide (WSe₂), or molybdenum selenide (MoSe). In one embodiment, the write channel layer 23 and the read channel layer 33 may comprise an oxide semiconductor such as IGZO, which exhibits N-type semiconductor characteristics due to its wide bandgap, excellent thermal stability, high mobility, low process temperature, and ample oxygen porosity.

[0038] The write gate dielectric layer 22 and memory node 32 may include at least one of a silicon oxide layer, a silicon nitride layer, or a high-k dielectric layer (e.g., a metal oxide layer). The metal oxide layer may include at least one of a hafnium oxide (HfO) layer, a zirconium oxide (ZrO) layer, or an aluminum oxide (AlO) layer.

[0039] Each of the write source electrode 21, write gate electrode 25, write drain electrode 27, read source electrode 35, and read drain electrode 37 may contain at least one conductor, such as doped polysilicon, metal (e.g., tungsten, platinum, gold, palladium, molybdenum, nickel, silver, or copper), metal compound (e.g., titanium nitride, tantalum nitride, or tungsten nitride), metal silicide, and metal alloy.

[0040] refer to Figure 3A and Figure 3B Each of the storage cells MCa and MCb may have an upper insulating layer 40 comprising a first upper insulating layer 41, an insulating upper hydrogen barrier layer 45, and a second upper insulating layer 47. The upper hydrogen barrier layer 45 may be disposed between the first upper insulating layer 41 and the second upper insulating layer 47. In one embodiment, the second upper insulating layer 47 may be omitted. The upper insulating layer 40 may be formed in a wide plate shape. That is, the first upper insulating layer 41, the upper hydrogen barrier layer 45, and the second upper insulating layer 47 may all be formed in a wide plate shape. (See reference...) Figure 3C The upper insulating layer 40 of the memory cell MCc can be a single layer. For example, the upper insulating layer 40 can be one of the first upper insulating layer 41 and the second upper insulating layer 47, or a stack of the first upper insulating layer 41 and the second upper insulating layer 47. That is, the upper hydrogen barrier layer 45 can be omitted.

[0041] The write transistor 20 and the read transistor 30 may include thin-film transistors (TFTs).

[0042] The first lower insulating layer 11 and the first upper insulating layer 41 may comprise at least one of a silicon oxide-based insulating layer, a silicon nitride-based insulating layer, or a silicon oxynitride-based insulating layer. In one embodiment, the first lower insulating layer 11 and / or the second upper insulating layer 47 may comprise a metal oxide layer. For example, the first lower insulating layer 11 and / or the second upper insulating layer 47 may comprise at least one of an aluminum oxide (AlO) layer, a hafnium oxide (HfO) layer, a zirconium oxide (ZrO) layer, a zinc oxide (ZnO) layer, a titanium oxide (TiO) layer, or a molybdenum oxide (MoO) layer.

[0043] The lower hydrogen barrier layer 15 and the upper hydrogen barrier layer 45 can trap hydrogen atoms or hydrogen ions. The lower hydrogen barrier layer 15 and the upper hydrogen barrier layer 45 can prevent hydrogen atoms or hydrogen ions from diffusing, entering, permeating, or moving into the write channel layer 23 and the read channel layer 33 during manufacturing processes or operations. For example, the lower hydrogen barrier layer 15 can prevent hydrogen atoms, hydrogen ions, and other impurities from diffusing, entering, permeating, or moving into the write channel layer 23 from the lower region, while the upper hydrogen barrier layer 33 can prevent hydrogen atoms, hydrogen ions, and other impurities from diffusing, entering, permeating, or moving into the read channel layer 33 from the upper region. Other impurities can be materials other than those forming the write channel layer 23 and the read channel layer 33. In one embodiment, the lower hydrogen barrier layer 15 and the upper hydrogen barrier layer 45 may comprise a metal-organic framework (MOF).

[0044] The second lower insulating layer 17 and the second upper insulating layer 47 may include at least one of a silicon oxide-based insulating layer, a silicon nitride-based insulating layer, or a silicon oxynitride-based insulating layer.

[0045] Figure 4A This is a plan view of the lower hydrogen barrier layer 15 and the upper hydrogen barrier layer 45 of a single-layer metal-organic framework according to an embodiment of the present disclosure. Figure 4B for Figure 4A A magnified view of region A in the middle. Figure 4C A three-dimensional perspective view of a lower hydrogen barrier layer 15 and an upper hydrogen barrier layer 45 comprising a multilayer metal-organic framework.

[0046] refer to Figure 4A Both the lower hydrogen barrier layer 15 and the upper hydrogen barrier layer 45 can contain a single-layer metal-organic framework, and the metal-organic framework can have a two-dimensional honeycomb network structure, a two-dimensional organic chain structure, or an organic ring structure. (Reference) Figure 4B A metal-organic framework can consist of metal nodes M and organic ligands L. The organic ligands L can interconnect the metal nodes M. (Reference) Figure 4C Both the lower hydrogen barrier layer 15 and the upper hydrogen barrier layer 45 may comprise a multilayer metal-organic framework. In one embodiment, the organic ligand L may comprise an organic linker.

[0047] The metal node M may include metal ions, metal oxide ions, or metal clusters. In one embodiment, the metal node M may include at least one of zinc (Zn), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), manganese (Mn), zinc oxide (ZnO), cobalt oxide (CoO), palladium oxide (PdO), and manganese oxide (MnO), or a metal cluster containing at least one of the above materials.

[0048] The organic ligand L may include at least one of BTA (1,2,4-benzenetribenzoic acid), BPDC (biphenyl-4,4'-dicarboxylate), BTB (1,3,5-benzenetribenzoic acid), TAD (tristyric acid derivative), NDC (2,6-naphthalenedicarboxylate), BTCTB (4,4',4'',4'''-(benzene-1,2,4,5-tetramethyl)tetrabenzoic acid), BBC (4,4',4''-benzene-1,3,5-trimethyltribenzoic acid), TCBPA (tetra(4-carboxyphenyl)porphyrinic acid), or TCBPPA (tetracarboxyphenylporphyrinic acid). In one embodiment, the organic ligand L may include at least one of TP (benzophenanthrene), HTTP (hexabenzophenanthrene), HHTP (hexahydroxybenzophenanthrene), HSTP (hexathiobenzophenanthrene), HITP (hexaiminobenzophenanthrene), HHB (hexahydroxybenzene), HSB (hexathiobenzene), HIB (hexaiminobenzene), oxalic acid, fumaric acid, BHT (benzenehexathiol), TPHT (triphenylhexathiol), BDB (1,4-phthalic acid), HAB (hexaaminobenzene), TCPC (tetra(4-carboxyphenyl)porphyrin cobalt(II), TCP (tetra(4-carboxyphenyl)porphyrin), or DOBSC (1,4-dioxo-2,5-phthalic acid).

[0049] In one embodiment, the lower hydrogen barrier layer 15 and the upper hydrogen barrier layer 45 may include one of (Zn4O)2(BTA)4(BPDC)2, (Zn4O)3(BTCTB)4(BPDC)3, Zn4O(BBC)2, (Zn4O)3(BTB)3, Zn4O(TCBPA)2, or Zn4O(TCBPA)2.

[0050] Figure 5 A longitudinal cross-sectional view is shown schematically of a capacitor-free semiconductor memory device 100 according to an embodiment of the present disclosure. Reference Figure 5 A capacitor-free semiconductor memory device may include a peripheral circuit layer (PCL) and a memory cell layer (MCL). The memory cell layer (MCL) may be stacked on the peripheral circuit layer (PCL). The peripheral circuit layer (PCL) may include transistor structures (71), vertical contact plugs (73), horizontal interconnects (75), and an interlayer insulating layer (65) disposed on a substrate (60). The substrate (60) may include a silicon wafer. The transistors (71), vertical contact plugs (73), and horizontal interconnects (75) may form sense amplifiers, various logic circuits, voltage generators, internal signal generators, and input / output buffers. Each of the vertical contact plugs (73) and horizontal interconnects (75) may contain a conductor, such as a metal. The interlayer insulating layer (65) may include at least one of a silicon oxide-based insulating layer, a silicon nitride-based insulating layer, or a silicon oxynitride-based insulating layer. The peripheral circuit layer (PCL) may include... Figures 3A to 3CThe bottom layer 50. The memory cell layer MCL may include at least one of multiple memory cell layers MCL1, MCL2, MCL3, and MCL4. Each of the memory cell layers MCL1, MCL2, MCL3, and MCL4 may include multiple memory cells MC arranged horizontally. The upper insulating layer 40 of each of the first to third memory cell layers MCL1, MCL2, and MCL3 may be shared with the lower insulating layer 10 of each of the second to fourth memory cell layers MCL2, MCL3, and MCL4, respectively. The interlayer insulating layer 65 may cover the transistor structure 71, the vertical contact plug 73, and the horizontal interconnect 75. The bottom layer 50 may be the peripheral circuit layer PCL, Figures 3A to 3C One of the substrate 10 or the interlayer insulating layer 65.

[0051] According to embodiments of this disclosure, hydrogen atoms or ions can be prevented from diffusing, entering, penetrating, or migrating into the channel layer of a transistor during manufacturing. That is, the channel layer of the transistor can be protected from the effects of hydrogen doping. Therefore, the resistance, threshold voltage, and channel formation of the transistor's channel layer can be stabilized, improving chemical and material stability. In particular, it can improve the threshold voltage drift phenomenon of the channel layer under high-temperature positive bias conditions.

[0052] Although this disclosure has been described in conjunction with specific embodiments, those skilled in the art will understand that various modifications and improvements can be made without departing from the technical concept and scope of protection defined by the claims. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A memory cell for a capacitor-free semiconductor memory device, the memory cell comprising: The lower insulating layer is disposed above the bottom layer; A write transistor is disposed on the lower insulating layer; A read transistor is disposed above the write transistor; as well as An upper insulating layer is disposed above the read transistor. The upper insulating layer includes: First upper insulating layer; An upper hydrogen barrier layer, disposed above the first upper insulating layer, the upper hydrogen barrier layer comprising a metal-organic framework; and A second upper insulating layer is disposed on top of the upper hydrogen barrier layer.

2. The storage unit according to claim 1, wherein: The metal-organic framework comprises metal nodes and organic ligands that connect the metal nodes to each other; Each of the metal nodes comprises at least one of a metal, a metal oxide, or a metal cluster; and Each of the organic ligands comprises at least one of BTA (1,2,4-benzenetribenzoic acid), BPDC (biphenyl-4,4'-dicarboxylate), BTB (1,3,5-benzenetribenzoic acid), NDC (2,6-naphthalenedicarboxylate), BTCTB (4,4',4'',4'''-(benzene-1,2,4,5-tetramethyl)tetrabenzoic acid), BBC (4,4',4''-benzene-1,3,5-trimethyltribenzoic acid), or TCBPA (tetra(4-carboxyphenyl)porphyrinic acid).

3. The storage unit according to claim 2, wherein, Each of the metal nodes includes at least one of zinc (Zn), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), manganese (Mn), zinc oxide (ZnO), cobalt oxide (CoO), palladium oxide (PdO), or manganese oxide (MnO).

4. The storage unit according to claim 1, wherein, Both the first upper insulating layer and the second upper insulating layer include at least one of a silicon oxide-based insulating layer, a silicon nitride-based insulating layer, or a silicon oxynitride-based insulating layer.

5. The storage unit according to claim 1, wherein, The lower insulating layer includes: First lower insulating layer; A lower hydrogen barrier layer is disposed above the first lower insulating layer; and A second lower insulating layer is disposed on top of the lower hydrogen barrier layer.

6. The storage unit according to claim 5, wherein, The upper hydrogen barrier layer comprises the metal-organic framework.

7. The storage unit according to claim 5, wherein, Both the first lower insulating layer and the second lower insulating layer include at least one of a silicon oxide-based insulating layer, a silicon nitride-based insulating layer, or a silicon oxynitride-based insulating layer.

8. The storage unit according to claim 1, wherein, The write transistor includes: A write source electrode is disposed on the lower insulating layer; A write channel layer is disposed above the write source electrode; A gate dielectric layer is written, which is configured to surround the sidewalls of the write channel layer; A write gate electrode, configured to surround the write gate dielectric layer; and A write drain electrode is disposed above the write channel layer.

9. The storage unit according to claim 8, wherein, The read transistor includes: The read gate electrode is shared with the write drain electrode; A read gate dielectric layer is disposed above the read drain electrode; A read channel layer is disposed above the read gate dielectric layer; The read source electrode is configured to contact a first side of the read channel layer; and The readout drain electrode is configured to contact the second side of the readout channel layer.

10. The storage unit according to claim 9, wherein: The read gate electrode, the read gate dielectric layer, and the read channel layer are formed in a pillar shape; as well as The read source electrode and the read drain electrode have a line shape that extends parallel to each other in the horizontal direction.

11. The storage unit according to claim 9, wherein, Both the write channel layer and the read channel layer comprise at least one of doped polysilicon, a metal oxide layer, or a two-dimensional transition metal chalcogenide material layer.

12. The storage unit according to claim 11, wherein, The write channel layer and the read channel layer include at least one of the following: indium oxide (In2O3) layer, titanium-doped indium oxide (In2O3) layer, tungsten-doped indium oxide (In2O3) layer, silicon-doped indium oxide (In2O3) layer, indium gallium zinc oxide (IGZO), silicon gallium-doped zinc oxide (SGZO), zinc oxide (ZnO), or indium gallium oxide (IGO).

13. The storage unit according to claim 9, wherein, Both the write gate dielectric layer and the read gate dielectric layer include at least one of a hafnium oxide layer, a zirconium oxide layer, or an aluminum oxide layer.

14. The storage unit according to claim 8, wherein: The write source electrode is part of a write bit line extending along a first horizontal direction; The write gate electrode is a portion of a write word line extending along a second horizontal direction perpendicular to the first horizontal direction; and The write channel layer passes through the write gate electrode in a vertical direction.

15. The storage unit according to claim 1, wherein: The bottom layer includes a peripheral circuit layer; and The peripheral circuit layer includes multiple transistors, multiple contact plugs, and multiple horizontal interconnects.

16. A memory cell for a capacitor-free semiconductor memory device, the memory cell comprising: The lower insulating layer is disposed above the bottom layer; A write transistor is disposed on the lower insulating layer; A read transistor is disposed above the write transistor; as well as An upper insulating layer is disposed above the read transistor. The lower insulating layer includes: First lower insulating layer; A lower hydrogen barrier layer, disposed above the first lower insulating layer, the lower hydrogen barrier layer comprising a metal-organic framework; and A second lower insulating layer is disposed on top of the lower hydrogen barrier layer.

17. A capacitor-free semiconductor memory device, comprising: The peripheral circuit layer includes multiple transistors, multiple contact plugs, and multiple horizontal interconnects; as well as A storage cell layer, stacked on top of the peripheral circuit layer, comprising a plurality of storage cells arranged horizontally. Each of the plurality of storage units includes: The lower insulating layer includes a lower hydrogen barrier layer; A write transistor is disposed on the lower insulating layer; A read transistor, disposed above the write transistor; and An upper insulating layer is disposed above the readout transistor, the upper insulating layer including an upper hydrogen barrier layer.

18. The capacitor-free semiconductor memory device according to claim 17, wherein: The lower insulating layer further includes a first insulating layer disposed between the lower hydrogen barrier layer and the write transistor. The first insulating layer includes at least one of a silicon oxide-based insulating layer, a silicon nitride-based insulating layer, or a silicon oxynitride-based insulating layer. The upper insulating layer further includes a second insulating layer disposed between the read transistor and the upper hydrogen barrier layer, and The second insulating layer includes at least one of a silicon oxide-based insulating layer, a silicon nitride-based insulating layer, or a silicon oxynitride-based insulating layer.

19. The capacitor-free semiconductor memory device according to claim 17, wherein, Both the lower hydrogen barrier layer and the upper hydrogen barrier layer contain a metal-organic framework.

20. The capacitor-free semiconductor memory device according to claim 19, wherein: The metal-organic framework comprises metal nodes and organic ligands that connect the metal nodes to each other; Each of the metal nodes comprises at least one selected from zinc (Zn), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), manganese (Mn), zinc oxide (ZnO), cobalt oxide (CoO), palladium oxide (PdO), or manganese oxide (MnO); and Each of the organic ligands comprises at least one of BTA (1,2,4-benzenetribenzoic acid), BPDC (biphenyl-4,4'-dicarboxylate), BTB (1,3,5-benzenetribenzoic acid), NDC (2,6-naphthalenedicarboxylate), BTCTB (4,4',4'',4'''-(benzene-1,2,4,5-tetramethyl)tetrabenzoic acid), BBC (4,4',4''-benzene-1,3,5-trimethyltribenzoic acid), or TCBPA (tetra(4-carboxyphenyl)porphyrinic acid).

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