Semiconductor structure, method of manufacturing the same and storage system

Abstract

The embodiment of the present application provides a semiconductor structure, a preparation method of the semiconductor structure and a storage system, wherein the semiconductor structure comprises a first semiconductor layer, a stack structure, a channel structure and a second semiconductor layer, the stack structure is located on one side of the first semiconductor layer along a first direction; the channel structure penetrates through the stack structure and the first semiconductor layer along the first direction; the second semiconductor layer is located on the side of the first semiconductor layer away from the stack structure; wherein the first semiconductor layer protrudes towards the channel structure relative to the stack structure along a direction intersecting with the first direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for fabricating semiconductor structures, and memory systems. Background Technology

[0002] Memory is one of the most important components in electronic systems. Flash memory is an important type of memory. Flash memory (also known as flash storage) is characterized by its ability to retain stored information for extended periods without power, and it boasts advantages such as high integration density, fast access speed, and ease of erasing and rewriting, making it the mainstream non-volatile memory. Based on its structure, flash memory is divided into NOR flash memory and NAND flash memory. Compared to NOR flash memory, NAND flash memory offers higher cell density, achieving higher storage density, and also provides faster write and erase speeds. With significant advancements in semiconductor manufacturing processes, three-dimensional (3D) flash memory applications have emerged to pursue lower production costs per unit of storage cell, such as 3D NAND flash memory. Summary of the Invention

[0003] This application provides a semiconductor structure, a method for fabricating the semiconductor structure, and a storage system.

[0004] This application provides a semiconductor structure, including: a first semiconductor layer, a stacked structure, a channel structure, and a second semiconductor layer; the stacked structure is located on one side of the first semiconductor layer along a first direction; the channel structure penetrates the stacked structure and the first semiconductor layer along the first direction; the second semiconductor layer is located on the side of the first semiconductor layer away from the stacked structure; wherein, the first semiconductor layer protrudes toward the channel structure relative to the stacked structure along a direction intersecting the first direction.

[0005] In some embodiments, the dimension by which the first semiconductor layer protrudes toward the channel structure relative to the stacked structure along a direction intersecting the first direction is a first dimension; the dimension of the portion of the channel structure extending into the stacked structure is a second dimension; wherein the first dimension is 14% to 16% of the second dimension.

[0006] In some implementations, the first semiconductor layer includes an opening; a channel structure passes through the opening and connects to the second semiconductor layer.

[0007] In some embodiments, the size of the opening along the second direction is smaller than the size of the channel structure in the stacked structure along the second direction; wherein the second direction intersects the first direction.

[0008] In some implementations, the channel structure includes a channel layer that is connected to a second semiconductor layer through an opening.

[0009] In some embodiments, the channel structure includes a first channel portion and a second channel portion, the first channel portion being connected to a second semiconductor layer through an opening, and the second channel portion being located on the side of the first channel portion away from the second semiconductor layer; wherein, the dimension of the first channel portion along the second direction is smaller than the dimension of the second channel portion along the second direction.

[0010] In some embodiments, the dimension of the first channel portion along the second direction is smaller than the dimension of the opening along the second direction, and the dimension of the second channel portion along the second direction is larger than the dimension of the opening along the second direction.

[0011] In some embodiments, the second channel portion includes a portion of the channel layer extending into the stacked structure and a filler layer.

[0012] In some embodiments, the first channel portion is continuous on a cross section intersecting the first direction.

[0013] In some embodiments, the surface of the second semiconductor layer facing away from the channel structure has a protrusion.

[0014] Another aspect of this application provides a method for fabricating a semiconductor structure, comprising: forming a first semiconductor layer; forming a stacked structure located on one side of the first semiconductor layer along a first direction; forming a channel structure penetrating the stacked structure and the first semiconductor layer along the first direction; and forming a second semiconductor layer located on the side of the first semiconductor layer away from the stacked structure; wherein the first semiconductor layer protrudes toward the channel structure relative to the stacked structure along a direction intersecting the first direction.

[0015] In some embodiments, the fabrication method further includes: forming an insulating isolation layer on one side of the substrate layer along a first direction; wherein forming a first semiconductor layer includes: forming a first semiconductor layer on the side of the insulating isolation layer away from the substrate layer; wherein forming a stacked structure includes: forming a stacked structure on the side of the first semiconductor layer away from the insulating isolation layer; wherein forming a second semiconductor layer includes: forming a second semiconductor layer after removing the substrate layer and the insulating isolation layer.

[0016] In some embodiments, forming a stacked structure on the side of the first semiconductor layer away from the insulating isolation layer includes: forming a first stacked structure on the side of the first semiconductor layer away from the insulating isolation layer, the first stacked structure including alternating layers of a first insulating layer and a second insulating layer; and replacing the second insulating layer with a gate layer.

[0017] In some embodiments, forming a channel structure includes: forming a channel hole extending in a first direction in a first stacked structure, a first semiconductor layer, and an insulating isolation layer; removing a portion of the first stacked structure and a portion of the insulating isolation layer through the channel hole, wherein the first semiconductor layer protrudes toward the channel hole relative to the first stacked structure and the insulating isolation layer in a direction intersecting the first direction; and forming a channel structure in the channel hole.

[0018] In some embodiments, along a direction intersecting the first direction, the dimension by which the first semiconductor layer protrudes toward the channel hole relative to the first stacked structure and the insulating isolation layer is a first dimension, and the dimension of the portion of the channel hole extending to the first stacked structure and the insulating isolation layer is a second dimension; wherein the first dimension is 14% to 16% of the second dimension.

[0019] In some embodiments, the channel via also extends into the substrate layer along a first direction; wherein, after a portion of the first stacked structure and a portion of the insulating isolation layer are removed via the channel via, the substrate layer of the channel via sidewall protrudes toward the channel via relative to the first stacked structure and the insulating isolation layer in a direction intersecting the first direction.

[0020] In some embodiments, forming a channel structure in a via includes: forming a functional layer and a channel layer in the via; the functional layer is located on the side of the channel layer along a direction intersecting a first direction and between the channel layer and the substrate layer along the first direction; wherein the fabrication method further includes: removing a portion of the functional layer during the removal of the insulating isolation layer.

[0021] In another aspect, this application provides a storage system including a controller and a semiconductor structure as described in any of the embodiments above, wherein the controller is coupled to the semiconductor structure and is used to control the semiconductor structure to store data. Attached Figure Description

[0022] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0023] Figures 1 to 5 This is a schematic diagram of the fabrication process of a semiconductor structure according to an embodiment of this application;

[0024] Figure 6 This is a schematic diagram of the semiconductor structure according to another embodiment of this application;

[0025] Figure 7 This is a flowchart of a method for fabricating a semiconductor structure according to another embodiment of this application;

[0026] Figures 8 to 15 This is a structural diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this application; and

[0027] Figure 16 This is a block diagram of a system having a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0028] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0030] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0031] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0032] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0033] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0034] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0035] This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] Figures 1 to 5 This is a schematic diagram of the fabrication process of a semiconductor structure according to an embodiment of this application.

[0037] refer to Figure 1 An insulating isolation layer 102 is formed on one side of the substrate layer 101 along the first direction Z; a first semiconductor layer 103 is formed on the side of the insulating isolation layer 102 away from the substrate layer 101; a first stacked structure D is formed on the side of the first semiconductor layer 103 away from the insulating isolation layer 102, the first stacked structure D including an alternately stacked first insulating layer 121 and a second insulating layer 122.

[0038] refer to Figure 2 A channel hole 130 extending along the first direction Z is formed in the first stacked structure D, the first semiconductor layer 103, the insulating isolation layer 102 and the partial substrate layer 101.

[0039] refer to Figure 3 The first semiconductor layer 103 is oxidized through the channel hole 130 to form an oxide layer 140 that contacts the sidewall of the first semiconductor layer 103.

[0040] refer to Figure 4 A functional layer 151, a channel layer 152, and a filling layer 153 are formed in the channel hole 130.

[0041] refer to Figure 5 The second insulating layer 122 is replaced with a gate layer 122a, and the gate layer 122a and the first insulating layer 121 form a stacked structure. Then, the substrate layer 101 and the insulating isolation layer 102 are removed, and the second semiconductor layer 100 is deposited. During the removal of the substrate layer 101 and the insulating isolation layer 102, a portion of the functional layer 151 and a portion of the channel layer 152 are removed, and the remaining functional layer 151, the remaining channel layer 152, and the fill layer 153 form a channel structure.

[0042] Another embodiment of this application provides a semiconductor structure. Figure 6This is a schematic diagram of a semiconductor structure according to another embodiment of this application. (Reference) Figure 6 The semiconductor structure includes: a first semiconductor layer 203, a stacked structure D2, a channel structure G, and a second semiconductor layer 200.

[0043] refer to Figure 6 The stacked structure D2 is located on one side of the first semiconductor layer 203 along the first direction Z. The channel structure G penetrates the stacked structure D2 and the first semiconductor layer 203 along the first direction Z. The second semiconductor layer 200 is located on the side of the first semiconductor layer 203 opposite to the stacked structure D2. The first semiconductor layer 203 protrudes towards the channel structure G relative to the stacked structure D2 along a direction intersecting the first direction Z.

[0044] In at least one embodiment of this application, the first semiconductor layer 203 protrudes toward the channel structure G relative to the stacked structure D2 along a direction intersecting with the first direction Z. Since the dimensional controllability of the first semiconductor layer 203 protruding relative to the stacked structure D2 along the direction intersecting with the first direction Z is improved, the dimensional uniformity of the first semiconductor layer 203 protruding relative to the stacked structure D2 is improved. Therefore, the channel structure G can achieve better sealing in the portion of the first semiconductor layer 203, and the contact between the channel structure G in the portion of the first semiconductor layer 203 and the stacked structure D2 is relatively tight.

[0045] For example, the first direction Z is perpendicular to the second semiconductor layer 200.

[0046] In some embodiments, the stacked structure D2 includes a first insulating layer 221 and a gate layer 222a alternately stacked in a first direction Z.

[0047] In some embodiments, the material of the first insulating layer 221 includes, but is not limited to, insulating dielectric materials such as silicon oxide.

[0048] In some embodiments, the material of the gate layer 222a includes any one of a metal gate material and a polysilicon gate material. For example, the material of the gate layer 222a can be any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides.

[0049] The number of layers in the stacked structure D2 is not limited to Figure 6 The number of layers shown can be set separately as needed.

[0050] In some embodiments, the second semiconductor layer 200 is also located on one side of the channel structure G along the first direction Z.

[0051] In some embodiments, the first semiconductor layer 203 is an intrinsic semiconductor layer. The second semiconductor layer 200 is doped with conductive ions.

[0052] In some embodiments, the material of the first semiconductor layer 203 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0053] In some embodiments, the material of the second semiconductor layer 200 may include at least one of the following: single-crystal silicon doped with conductive ions, polycrystalline silicon doped with conductive ions, single-crystal germanium doped with conductive ions, III-V compound semiconductor material doped with conductive ions, II-VI compound semiconductor material doped with conductive ions, or other semiconductor materials known in the art.

[0054] In some embodiments, the first semiconductor layer 203 includes an opening; a channel structure G passes through the opening and is connected to the second semiconductor layer 200.

[0055] In some embodiments, the size of the opening along the second direction is smaller than the size of the channel structure G in the stacked structure D2 along the second direction. The second direction intersects the first direction Z, for example, the second direction is perpendicular to the first direction Z. The second direction can be any direction perpendicular to the first direction Z.

[0056] In some embodiments, the channel structure G includes a channel layer 252 that is connected to the second semiconductor layer 200 through an opening.

[0057] In some embodiments, the channel structure G further includes a functional layer 251 and a fill layer 253. The functional layer 251, fill layer 253, and channel layer 252 all extend along a first direction Z. The channel layer 252 is located between the functional layer 251 and the fill layer 253. The functional layer 251 is located between the channel layer 252 and the stacked structure D2. The functional layer 251 includes a barrier layer, a charge trapping layer, and a tunneling layer. The barrier layer, charge trapping layer, and tunneling layer all extend along the first direction Z. The charge trapping layer is located between the barrier layer and the tunneling layer. The tunneling layer is located between the charge trapping layer and the channel layer 252. The channel structure G may also include a channel plug located on the side of the fill layer 253 facing away from the second semiconductor layer 200 along the first direction Z, and the channel plug is connected to the channel layer 252.

[0058] The channel structure G has a relatively tight contact with the stacked structure D2 at a portion of the first semiconductor layer 203. Correspondingly, the functional layer 251 also has a relatively tight contact with the stacked structure D2 at a portion of the first semiconductor layer 203. This improves the protection of the functional layer 251 between the channel layer 252 and the stacked structure D2, especially the protection of the barrier layer between the channel layer 252 and the stacked structure D2, reducing the possibility of barrier layer failure and improving the charge storage capacity of the functional layer 251.

[0059] In some embodiments, the channel structure G includes a first channel portion and a second channel portion, the first channel portion being connected to the second semiconductor layer 200 through an opening, and the second channel portion being located on the side of the first channel portion away from the second semiconductor layer 200; wherein, the dimension of the first channel portion along the second direction is smaller than the dimension of the second channel portion along the second direction.

[0060] In some embodiments, the dimension of the first channel portion along the second direction is smaller than the dimension of the opening along the second direction, and the dimension of the second channel portion along the second direction is larger than the dimension of the opening along the second direction.

[0061] In some embodiments, the second channel portion includes a portion of the channel layer 252 extending into the stacked structure D2 and a fill layer 253. The portion of the channel layer 252 extending into the first semiconductor layer 203 serves as the first channel portion.

[0062] In some embodiments, the filler layer 253 has voids.

[0063] In some embodiments, the first channel portion is continuous on a cross section intersecting the first direction Z. That is, the portion of the channel layer 252 extending to the first semiconductor layer 203 is a solid structure, and gaps do not extend into the first channel portion.

[0064] In other embodiments, the gap does not extend into the portion of the first channel and does not extend into the second semiconductor layer.

[0065] In some embodiments, the first semiconductor layer 203 protrudes towards the channel structure G relative to the stacked structure D2 by a dimension d1 along a direction intersecting the first direction Z. The dimension of the portion of the channel structure G extending into the stacked structure D2 is a second dimension d2; wherein the first dimension d1 is 14% to 16% of the second dimension d2. The first dimension d1 is greater than or equal to 14% of the second dimension d2, so that the first dimension d1 is not too small, thereby enhancing the positional constraint of the first semiconductor layer 203 on the channel layer 252, and making it less likely for gaps to penetrate the first semiconductor layer 203 along the first direction Z.

[0066] In some embodiments, the surface of the second semiconductor layer 200 facing away from the channel structure G has a protrusion. In other embodiments, the surface of the second semiconductor layer 200 facing away from the channel structure G is planar.

[0067] In some embodiments, the channel layer 252 protrudes relative to the first semiconductor layer 203 toward the second semiconductor layer 200 along a first direction Z. The second semiconductor layer 200 not only contacts the side surface of the channel layer 252 facing the second semiconductor layer 200 along the first direction Z, but also contacts the sidewall of the portion of the channel layer 252 that protrudes relative to the first semiconductor layer 203. This increases the contact area between the channel layer 252 and the second semiconductor layer 200, thereby reducing the contact resistance.

[0068] In some embodiments, the filler layer 253 is made of an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The channel layer 252 is made of polycrystalline silicon or doped polycrystalline silicon. The barrier layer is made of silicon oxide, the charge trapping layer is made of silicon nitride, and the tunneling layer is made of silicon oxide.

[0069] In some embodiments, the semiconductor structure further includes an isolation structure (not shown) that extends through the stacked structure D2 along a first direction Z and is spaced apart from the channel structure G.

[0070] In some implementations, the isolation structure may extend to the second semiconductor layer 200.

[0071] In some embodiments, the isolation structure includes a semiconductor isolation layer (not shown) and an insulating isolation layer (not shown), the insulating isolation layer being located on one side of the semiconductor isolation layer along the first direction Z and on the sidewall of the semiconductor isolation layer. The semiconductor isolation layer is made of a semiconductor material, such as polycrystalline silicon or doped polycrystalline silicon. The insulating isolation layer is made of an insulating dielectric material, such as silicon oxide, silicon oxynitride, or silicon oxycarbide.

[0072] In other embodiments, the material of the isolation structure is an insulating dielectric material, such as silicon oxide, silicon oxynitride, or silicon oxycarbide.

[0073] Another embodiment of this application provides a method for fabricating a semiconductor structure, see reference. Figure 7 ,include:

[0074] Step S1: Form the first semiconductor layer;

[0075] Step S2: Form a stacked structure, the stacked structure being located on one side of the first semiconductor layer along the first direction;

[0076] Step S3: Form a channel structure, the channel structure penetrating the stacked structure and the first semiconductor layer along a first direction; and

[0077] Step S4: Form a second semiconductor layer, which is located on the side of the first semiconductor layer away from the stacked structure;

[0078] The first semiconductor layer protrudes toward the channel structure relative to the stacked structure along a direction intersecting with the first direction.

[0079] In some embodiments, the method for fabricating a semiconductor structure further includes: forming an insulating isolation layer on one side of the substrate layer along a first direction; wherein forming a first semiconductor layer includes: forming a first semiconductor layer on the side of the insulating isolation layer away from the substrate layer; wherein forming a stacked structure includes: forming a stacked structure on the side of the first semiconductor layer away from the insulating isolation layer; wherein forming a second semiconductor layer includes: forming a second semiconductor layer after removing the substrate layer and the insulating isolation layer.

[0080] In some embodiments, forming a stacked structure on the side of the first semiconductor layer away from the insulating isolation layer includes: forming a first stacked structure on the side of the first semiconductor layer away from the insulating isolation layer, the first stacked structure including alternating layers of a first insulating layer and a second insulating layer; and replacing the second insulating layer with a gate layer.

[0081] In some embodiments, forming a channel structure includes: forming a channel hole extending in a first direction in a first stacked structure, a first semiconductor layer, and an insulating isolation layer; removing a portion of the first stacked structure and a portion of the insulating isolation layer through the channel hole, wherein the first semiconductor layer protrudes toward the channel hole relative to the first stacked structure and the insulating isolation layer in a direction intersecting the first direction; and forming a channel structure in the channel hole.

[0082] The following is combined Figures 8 to 15 This paper introduces methods for fabricating semiconductor structures.

[0083] refer to Figure 8 An insulating isolation layer 202 is formed on one side of the substrate layer 201 along the first direction Z; a first semiconductor layer 203 is formed on the side of the insulating isolation layer 202 away from the substrate layer 201; and a first stacked structure D1 is formed on the side of the first semiconductor layer 203 away from the insulating isolation layer 202.

[0084] In some embodiments, the insulating layer 202 is made of materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0085] The material of the first semiconductor layer 203 is as described in the foregoing embodiment.

[0086] refer to Figure 8 The first stacked structure D1 includes an alternately stacked first insulating layer 221 and a second insulating layer 222.

[0087] In some embodiments, the process for forming the first insulating layer 221 is a deposition process, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, as a thin film deposition process.

[0088] In some embodiments, the process for forming the second insulating layer 222 includes a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0089] In some embodiments, the first insulating layer 221 and the second insulating layer 222 are made of different materials.

[0090] refer to Figure 9 A channel hole 230 extending along the first direction Z is formed in the first stacked structure D1, the first semiconductor layer 203 and the insulating isolation layer 202.

[0091] In some embodiments, the process of forming the channel hole 230 includes an etching process, which is one or a combination of wet etching and dry etching processes.

[0092] In some embodiments, the channel via 230 also extends along the first direction Z into the substrate layer 201.

[0093] refer to Figure 10 A portion of the first stacked structure D1 and a portion of the insulating isolation layer 202 are removed via the channel hole 230, wherein, along a direction intersecting the first direction Z, the first semiconductor layer 203 protrudes toward the channel hole 230 relative to the first stacked structure D1 and the insulating isolation layer 202.

[0094] In some embodiments, a portion of the first stacked structure D1 and a portion of the insulating isolation layer 202 are removed via the channel hole 230. For example, the first stacked structure D1 and the insulating isolation layer 202 are etched on the sidewall of the channel hole 230.

[0095] In some embodiments, etching the first stacked structure D1 and the insulating isolation layer 202 on the sidewall of the channel hole 230 includes etching the insulating isolation layer 202 on the sidewall of the channel hole 230 during the etching of the first stacked structure D1 on the sidewall of the channel hole 230.

[0096] In some embodiments, along a direction intersecting the first direction Z, the dimension by which the first semiconductor layer 203 protrudes toward the channel hole 230 relative to the first stacked structure D1 and the insulating isolation layer 202 is a first dimension d1, and the dimension of the portion of the channel hole 230 extending into the first stacked structure D1 and the insulating isolation layer 202 is a second dimension d2. The first dimension d1 is 14% to 16% of the second dimension d2.

[0097] In some embodiments, by etching the first stacked structure D1 and the insulating isolation layer 202 on the sidewalls of the channel hole 230, the first semiconductor layer 203 protrudes relative to the first stacked structure D1 and the insulating isolation layer 202 toward the channel hole 230 in a direction intersecting the first direction Z. Since the dimensional controllability of the protrusion of the first semiconductor layer 203 relative to the first stacked structure D1 and the insulating isolation layer 202 is improved, the dimensional uniformity of the protrusion of the first semiconductor layer 203 in each channel hole 230 is improved, and no thermal stress is introduced in the process. At the same time, increasing the thickness of the first semiconductor layer 203 near the channel hole 230 is also avoided. (Reference) Figure 11 A functional layer 251 and a channel layer 252 are formed in the channel hole 230; the functional layer 251 is located on the side of the channel layer 252 along the direction intersecting with the first direction Z and between the channel layer 252 and the substrate layer 201 along the first direction Z.

[0098] In some embodiments, the process for forming the functional layer 251 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the channel layer 252 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0099] In some embodiments, forming the functional layer 251 includes sequentially forming a barrier layer, a charge trapping layer, and a tunneling layer on the sidewall of the channel via 230 intersecting the first direction Z and on the inner wall of the channel via 230 facing the substrate layer 201. The charge trapping layer is located between the barrier layer and the tunneling layer.

[0100] Since the size uniformity of the first semiconductor layer 203 protrusion in each channel hole 230 is improved, the functional layer 251 and the channel layer 252 have better filling performance in the bottom region of the channel hole 230 facing the substrate layer 201, which can achieve better sealing. Therefore, the contact between the functional layer 251 and the stacked structure D2 is relatively tight.

[0101] refer to Figure 12 The second insulating layer 222 is replaced with the gate layer 222a.

[0102] In some embodiments, replacing the second insulating layer 222 with the gate layer 222a includes: removing the second insulating layer 222 to form a gate opening; and forming the gate layer 222a in the gate opening.

[0103] In some embodiments, the method for fabricating the semiconductor structure further includes forming an isolation trench (not shown) in a first stacked structure D1. The isolation trench extends through the first stacked structure D1 along a first direction Z.

[0104] In some embodiments, the process of forming the isolation trench includes an etching process, which is one or a combination of wet etching and dry etching processes.

[0105] In some embodiments, replacing the second insulating layer 222 with the gate layer 222a includes replacing the second insulating layer 222 with the gate layer 222a via an isolation trench.

[0106] In some embodiments, the process of forming the gate layer 222a in the gate opening includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0107] In some embodiments, the method for fabricating the semiconductor structure further includes forming a dielectric layer. For example, a dielectric layer is formed on the inner wall of the gate opening. The dielectric layer is formed before forming the gate layer 222a.

[0108] In some embodiments, the process for forming the dielectric layer includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0109] After the gate layer 222a is formed, the first stacked structure D1 forms the stacked structure D2.

[0110] In some embodiments, the method for fabricating the semiconductor structure further includes forming an isolation structure in an isolation trench. The isolation structure is described in the foregoing embodiments.

[0111] In some embodiments, the process of forming the isolation structure in the isolation tank includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0112] refer to Figure 13 Remove substrate layer 201 (reference) Figure 12 ).

[0113] In some embodiments, the process for removing the substrate layer 201 includes any one or a combination of etching and chemical mechanical polishing, wherein the etching process is one or a combination of wet etching and dry etching.

[0114] refer to Figure 14Remove the insulating layer 202 (reference) Figure 13 During the removal of the insulating layer 202, a portion of the functional layer 251 is removed.

[0115] In some embodiments, the process of removing the insulating layer 202 includes an etching process, which is one or a combination of wet etching and dry etching processes.

[0116] In some embodiments, as described above, in the bottom region of the channel via 230 facing the substrate layer 201, the functional layer 251 and the channel layer 252 can achieve better sealing, and the contact between the functional layer 251 and the stacked structure D2 is relatively tight. Therefore, when removing a portion of the functional layer 251 and the insulating isolation layer 202, the etching damage to the functional layer 251 between the channel layer 252 and the stacked structure D2 can be reduced, especially the etching damage to the barrier layer between the channel layer 252 and the stacked structure D2 can be reduced, reducing the possibility of barrier layer failure between the channel layer 252 and the stacked structure D2 and improving the charge storage capacity of the functional layer 251. Secondly, it can also reduce the process difficulty of removing a portion of the functional layer 251 and the insulating isolation layer 202, making the selectivity of process parameters used in this step more abundant.

[0117] refer to Figure 15 After removing the substrate layer 201 and the insulating isolation layer 202, a second semiconductor layer 200 is formed. The second semiconductor layer 200 is located on the side of the first semiconductor layer 203 opposite to the stacked structure D2. The second semiconductor layer 200 is also located on the side of the channel structure G along the first direction Z.

[0118] In some embodiments, the second semiconductor layer 200 is doped with conductive ions.

[0119] In some embodiments, the material of the second semiconductor layer 200 may include at least one of the following: single-crystal silicon doped with conductive ions, polycrystalline silicon doped with conductive ions, single-crystal germanium doped with conductive ions, III-V compound semiconductor material doped with conductive ions, II-VI compound semiconductor material doped with conductive ions, or other semiconductor materials known in the art.

[0120] In some embodiments, the process of forming the second semiconductor layer 200 includes a deposition process, such as a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0121] Another embodiment of this application also provides a system 30000 having a storage system 32000. (See reference...) Figure 16 , Figure 16 This is a block diagram of a system 30000 having a storage system 32000 according to one embodiment of this application.

[0122] like Figure 16 As shown, system 30000 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 32000 located therein). Figure 16 As shown, system 30000 may include host 31000 and storage system 32000, the storage system 32000 having one or more semiconductor structures 32100 and controller 32200. Host 31000 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 31000 may be configured to send or receive data to and from semiconductor structure 32100.

[0123] Semiconductor structure 32100 may include the semiconductor structure described in any embodiment of this application. According to some embodiments, controller 32200 is coupled to semiconductor structure 32100 and host 31000 and is configured to control semiconductor structure 32100. Controller 32200 can manage data stored in semiconductor structure 32100 and communicate with host 31000. In some embodiments, controller 32200 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 32200 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device such as a smartphone, tablet computer, laptop, etc. The controller 32200 can be configured to control the operation of the semiconductor structure 32100, such as read, erase, and program operations. The controller 32200 can also be configured to manage various functions related to data stored in or to be stored in the semiconductor structure 32100, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the controller 32200 is further configured to process error correction codes (ECCs) related to data read from or written to the semiconductor structure 32100. The controller 32200 can also perform any other appropriate functions, such as formatting the semiconductor structure 32100. The controller 32200 can communicate with external devices (e.g., host 31000) according to a specific communication protocol. For example, the controller 32200 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-express, PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0124] Although exemplary fabrication methods and structures of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure. Furthermore, the materials of the exemplified layers are merely exemplary.

[0125] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, comprising: First semiconductor layer; A stacked structure is located on one side of the first semiconductor layer along a first direction; as well as A channel structure extends through the stacked structure and the first semiconductor layer along the first direction; The second semiconductor layer is located on the side of the first semiconductor layer that is away from the stacked structure; The first semiconductor layer protrudes toward the channel structure relative to the stacked structure along a direction intersecting the first direction.

2. The semiconductor structure according to claim 1, wherein, The dimension by which the first semiconductor layer protrudes toward the channel structure relative to the stacked structure along the direction intersecting the first direction is a first dimension; the dimension of the portion of the channel structure extending into the stacked structure is a second dimension; The first dimension is 14% to 16% of the second dimension.

3. The semiconductor structure according to claim 1, wherein, The first semiconductor layer includes an opening; the channel structure passes through the opening and connects to the second semiconductor layer.

4. The semiconductor structure according to claim 3, wherein, The size of the opening along the second direction is smaller than the size of the channel structure located in the stacked structure along the second direction; The second direction intersects with the first direction.

5. The semiconductor structure according to claim 3, wherein, The channel structure includes a channel layer that is connected to the second semiconductor layer through the opening.

6. The semiconductor structure according to claim 5, wherein, The channel structure includes a first channel portion and a second channel portion, the first channel portion passing through the opening and connected to the second semiconductor layer, and the second channel portion located on the side of the first channel portion away from the second semiconductor layer. Wherein, the dimension of the first channel portion along the second direction is smaller than the dimension of the second channel portion along the second direction.

7. The semiconductor structure according to claim 6, wherein, The dimension of the first channel portion along the second direction is smaller than the dimension of the opening along the second direction, and the dimension of the second channel portion along the second direction is larger than the dimension of the opening along the second direction.

8. The semiconductor structure according to claim 6, wherein, The second channel portion includes a portion of the channel layer extending into the stacked structure and a filler layer.

9. The semiconductor structure according to claim 6, wherein, The first channel portion is continuous on the cross section intersecting the first direction.

10. The semiconductor structure according to claim 1, wherein, The second semiconductor layer has a protrusion on the side of its surface facing away from the channel structure.

11. A method for fabricating a semiconductor structure, comprising: Form the first semiconductor layer; A stacked structure is formed, wherein the stacked structure is located on one side of the first semiconductor layer along a first direction; A channel structure is formed, the channel structure penetrating the stacked structure and the first semiconductor layer along the first direction; as well as A second semiconductor layer is formed, the second semiconductor layer being located on the side of the first semiconductor layer away from the stacked structure; The first semiconductor layer protrudes toward the channel structure relative to the stacked structure along a direction intersecting the first direction.

12. The preparation method according to claim 11, wherein, The preparation method further includes: An insulating isolation layer is formed on one side of the substrate layer along the first direction; The formation of the first semiconductor layer includes: forming the first semiconductor layer on the side of the insulating isolation layer opposite to the substrate layer; The formation of the stacked structure includes: forming the stacked structure on the side of the first semiconductor layer away from the insulating isolation layer; The formation of the second semiconductor layer includes: After removing the substrate layer and the insulating isolation layer, the second semiconductor layer is formed.

13. The preparation method according to claim 12, wherein, The stacked structure is formed on the side of the first semiconductor layer away from the insulating isolation layer, including: A first stacked structure is formed on the side of the first semiconductor layer opposite to the insulating layer, the first stacked structure comprising alternately stacked first and second insulating layers; and The second insulating layer is replaced with a gate layer.

14. The preparation method according to claim 13, wherein, The formation of the channel structure includes: A channel hole extending along the first direction is formed in the first stacked structure, the first semiconductor layer and the insulating isolation layer; A portion of the first stacked structure and a portion of the insulating isolation layer are removed via the channel via, wherein, along a direction intersecting the first direction, the first semiconductor layer protrudes toward the channel via relative to the first stacked structure and the insulating isolation layer; and A channel structure is formed in the channel hole.

15. The preparation method according to claim 14, wherein, Along the direction intersecting the first direction, the dimension by which the first semiconductor layer protrudes toward the channel hole relative to the first stacked structure and the insulating isolation layer is a first dimension, and the dimension of the portion of the channel hole extending to the first stacked structure and the insulating isolation layer is a second dimension; The first dimension is 14% to 16% of the second dimension.

16. The preparation method according to claim 14, wherein, The channel hole also extends along the first direction into the substrate layer; Wherein, after removing part of the first stacked structure and part of the insulating isolation layer via the channel hole, the substrate layer of the channel hole sidewall protrudes toward the channel hole relative to the first stacked structure and the insulating isolation layer in a direction intersecting the first direction.

17. The preparation method according to claim 14, wherein, Forming the channel structure in the channel hole includes: A functional layer and a channel layer are formed in the channel hole; the functional layer is located on the side of the channel layer along the direction intersecting the first direction and between the channel layer and the substrate layer along the first direction; The preparation method further includes: During the removal of the insulating layer, a portion of the functional layer is also removed.

18. A storage system, comprising: Includes the semiconductor structure as described in any one of claims 1 to 10; as well as A controller, coupled to the semiconductor structure, is used to control the semiconductor structure to store data.

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