Integrated devices and methods for rram memory

Abstract

The application relates to an integrated device and method of RRAM memory, and belongs to the technical field of semiconductors. The device comprises a transistor, a first metal layer located above the transistor layer, a first RRAM layer located above the first metal layer and comprising a plurality of parallel first resistors, wherein each first resistor is connected in series to the drain of the transistor via a plurality of first via contact elements, the first metal layer and a plurality of drain contact elements, a second metal layer located above the first RRAM layer, and a second RRAM layer located above the second metal layer and comprising a plurality of parallel second resistors, wherein each second resistor is connected in series to the drain of the transistor via a plurality of second via contact elements, the second metal layer, a plurality of third via contact elements, the first metal layer and a plurality of drain contact elements. The area utilization is improved by using the 1TnR architecture.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an integrated device and method for RRAM memory. Background Technology

[0002] With the significant improvement in computing power and algorithm refinement of existing computing systems, the performance of artificial neural networks has become increasingly powerful. From perceptrons to multilayer perceptrons and then to deep neural networks, the improvement in network performance shows a significant positive correlation with the number of network layers. ImageNet competition data shows that to achieve an error rate below 5%, the number of neural network layers has exceeded 200, and the total number of network parameters has also exceeded 100 billion (100 billion). Such a huge number of network parameters brings hardware challenges to network training.

[0003] Resistive random access memory (RRAM) boasts a simple structure, low power consumption, compatibility with CMOS processes, and high integration density, making it a candidate for next-generation non-volatile memory. Using a 1T1R structure as an example of RRAM, the transistor size is much larger than the RRAM size. The integration density of the 1T1R structure of RRAM and transistors is limited by the transistor size (6F²). To achieve higher density, transistors need to be miniaturized. However, when transistors are miniaturized, they are more susceptible to process parameters, leading to defects and reduced process yield. As transistors are continuously miniaturized, the drive current becomes very weak, failing to meet the current required for device operation, thus preventing the device from functioning. Furthermore, traditional three-dimensional RRAM architectures suffer from difficulties in fabrication processes, significant crosstalk within the array, and unclear integration schemes between the memory array and logic. Therefore, a mature three-dimensional RRAM chip cannot be realized in the short term.

[0004] However, existing resistive random access memories have the following drawbacks:

[0005] (1) Limited storage density: In the traditional 1T1R architecture, each RRAM cell requires a dedicated transistor, resulting in low area utilization (see reference). Figure 1 );

[0006] (2) Power consumption and leakage current issues: When multiple units are controlled independently, the leakage current is superimposed, and the static power consumption increases significantly.

[0007] (3) High manufacturing complexity: The number of transistors increases linearly with capacity, making it difficult to optimize yield and cost;

[0008] (4) Low efficiency of in-memory computing integration: Traditional architectures are difficult to support high-parallelism matrix operations, which restricts AI acceleration performance. Summary of the Invention

[0009] Based on the above analysis, the embodiments of the present invention aim to provide an integrated device and method for RRAM memory to solve problems such as limited storage density, superposition of leakage current when multiple cells are independently controlled, high manufacturing complexity, and low efficiency of memory-computer integration.

[0010] On one hand, embodiments of the present invention provide an integrated device for an RRAM memory, comprising: a transistor located in and above a semiconductor substrate; a first metal layer located above the transistor layer, connected to the source, drain, and gate of the semiconductor substrate via source contacts, drain contacts, and gate contacts, respectively; a first RRAM layer located above the first metal layer, comprising a plurality of parallel first variable resistors, wherein each first variable resistor is sequentially connected in series to the drain of the transistor via a plurality of first via contacts, the first metal layer, and a plurality of drain contacts; a second metal layer located above the first RRAM layer; a second RRAM layer located above the second metal layer, comprising a plurality of parallel second variable resistors, wherein each second variable resistor is sequentially connected in series to the drain of the transistor via a plurality of second via contacts, the second metal layer, a plurality of third via contacts, the first metal layer, and a plurality of drain contacts, wherein the plurality of first variable resistors and the plurality of second variable resistors do not overlap in the vertical direction, and each first via contact and each third via contact are independently distributed above the drain of the transistor in the vertical direction.

[0011] The beneficial effects of the above technical solution are as follows: In the 1TnR architecture, one transistor is connected in series with n RRAM cells (n RRAM cells are connected in parallel), resulting in improved area utilization and thus increased storage density. 1TnR supports high-parallelism matrix operations, enhancing AI acceleration performance. By implementing two or more layers of vertical stacking, not only can storage density be significantly improved, but also multi-level dynamic control similar to synaptic connections in biological neural networks can be achieved.

[0012] Based on a further improvement of the above-described device, the transistor includes: a U-shaped gate located above a semiconductor substrate, wherein the U-shaped gate includes a first branch, a second branch, and a gate connection portion connecting the first branch and the second branch; a source located in the semiconductor substrate and disposed inside the U-shaped gate; and a U-shaped drain located in the semiconductor substrate, the U-shaped drain surrounding the U-shaped gate from the opening of the U-shaped gate and the U-shaped drain including a first branch, a second branch, and a drain connection portion, wherein the first and second branches of the U-shaped gate extend into the interior of the U-shaped drain while the gate connection portion is not surrounded by the U-shaped drain.

[0013] Based on a further improvement of the above device, the number of the first rheostats is 2N, and N is greater than or equal to 2, wherein N first rheostats are located above the first branch of the drain in the vertical direction; the remaining N first rheostats are located above the second branch of the U-shaped gate in the vertical direction, wherein the first branch of the drain is adjacent to the first branch of the U-shaped gate and away from the second branch of the U-shaped gate, and the 2N first rheostats are set to be located at the corner of the rectangle.

[0014] Based on a further improvement of the above device, the number of the second rheostats is 2N, where N is greater than or equal to 2, wherein N second rheostats are located above the first branch of the U-shaped gate in the vertical direction; the remaining N second rheostats are located above the second branch of the drain in the vertical direction, wherein the second branch of the drain is adjacent to the second branch of the U-shaped gate and away from the first branch of the U-shaped gate, and the 2N second rheostats are configured to be located at the corners of the rectangle.

[0015] Based on further improvements to the above-mentioned device, the first and second rheostats include: a bottom electrode located above the lower electrode through-hole contact; an oxygen storage layer located above the bottom electrode; a resistive switching layer located above the oxygen storage layer, wherein the thickness of the resistive switching layer is less than the thickness of the oxygen storage layer; and a top electrode located above the resistive switching layer, wherein the bottom electrode, the oxygen storage layer, the resistive switching layer, and the top electrode have the same width, and the width of the lower electrode through-hole contact is greater than the width of the first through-hole contact.

[0016] Based on a further improvement of the above device, the gate includes a gate dielectric layer and a gate layer, and a sidewall located on the sidewall of the gate layer, wherein a source metallization layer is located above the source, and a drain metallization layer is located above the drain, wherein the thickness of the source metallization layer and the drain metallization layer is less than the thickness of the gate dielectric layer; the first branch and the second branch of the U-shaped gate are in contact with the inner wall of the drain connection portion via the gate dielectric layer.

[0017] Based on further improvements to the above-described device, the integrated device for RRAM memory also includes:

[0018] An oxide insulating layer is located above the transistor, wherein the source contact, the drain contact, and the gate contact are disposed in the oxide insulating layer;

[0019] A first dielectric layer is located between the oxide insulating layer and the first metal layer;

[0020] A first passivation layer is located above the first dielectric layer and is used to surround the first metal layer;

[0021] The second dielectric layer is located above the first passivation layer;

[0022] A second passivation layer is located above the second dielectric layer and is used to surround the first RRAM layer;

[0023] The third dielectric layer is located above the second passivation layer;

[0024] A third passivation layer is located above the third dielectric layer and is used to surround the second metal layer;

[0025] The fourth dielectric layer is located above the third passivation layer;

[0026] A fourth passivation layer, located above the fourth dielectric layer, is used to surround the second RRAM layer.

[0027] On the other hand, embodiments of the present invention provide forming a transistor in and above a semiconductor substrate; forming an oxide insulating layer above the transistor, and forming a source contact, a drain contact, and a gate contact in the oxide insulating layer; forming a first metal layer above the transistor to connect to the source, the drain, and the gate respectively via the source contact, the drain contact, and the gate contact; forming a first RRAM layer above the first metal layer, and etching the first RRAM layer into a plurality of parallel first rheostats, such that each first rheostat is sequentially connected in series via a first via contact, the first metal layer, and a drain contact. A second metal layer is formed above the first RRAM layer; a second RRAM layer is formed above the second metal layer, and the second RRAM layer is etched into a plurality of parallel second rheostats, such that each second rheostat is sequentially connected in series to the drain of the transistor via a second via contact, the second metal layer, a third via contact, the first metal layer, and a drain contact, wherein the plurality of first rheostats and the plurality of second rheostats do not overlap in the vertical direction, and each first via contact and each third via contact are independently distributed above the drain of the transistor in the vertical direction.

[0028] Based on a further improvement to the above method, the number of both the first and second rheostats is 2N, where N is greater than or equal to 2.

[0029] N first rheostats are located vertically above the first branch of the drain electrode;

[0030] The remaining N first rheostats are located vertically above the second branch of the U-shaped gate, wherein the first branch of the drain is adjacent to the first branch of the U-shaped gate and away from the second branch of the U-shaped gate, and the 2N first rheostats are arranged to be located at the corners of the rectangle.

[0031] N second rheostats are located vertically above the first branch of the U-shaped gate;

[0032] The remaining N second rheostats are located vertically above the second branch of the drain, wherein the second branch of the drain is adjacent to the second branch of the U-shaped gate and away from the first branch of the U-shaped gate, and the 2N second rheostats are arranged at the corners of the rectangle.

[0033] Further improvements to the above method, forming a first RRAM layer above the first metal layer or a second RRAM layer above the second metal layer, further include: depositing a passivation material layer above the first metal layer or the second metal layer, then patterning and etching vias in the passivation material layer, and then filling the vias with a bottom electrode material layer; sequentially depositing an oxygen storage layer and a resistive switching layer above the passivation material layer, wherein the thickness of the oxygen storage layer is greater than the thickness of the resistive switching layer; depositing a top electrode material layer above the resistive switching layer; generating a varistor pattern using deep ultraviolet lithography, and then etching the varistor pattern using reactive ion etching to generate multiple first varistors or multiple second varistors.

[0034] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0035] 1. Increased storage density: In the 1TnR architecture, one transistor is connected in series with n RRAM cells, resulting in increased area utilization.

[0036] 2. The method of increasing storage density with 1TnR is simple in actual manufacturing process. RRAM cells can be prepared by deposition, etching and interconnection between any two interconnect layers.

[0037] 3. 1TnR supports high-parallelism matrix operations, enhancing AI acceleration performance. By implementing three or more layers of vertical stacking, not only can storage density be significantly increased, but multi-level dynamic control of synaptic connections, similar to that in biological neural networks, can also be achieved. Furthermore, the multi-layer stacked structure helps to construct more complex access paths, improving overall data processing speed and energy efficiency.

[0038] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0039] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0040] Figure 1 A diagram illustrating the existing 1T1R resistive random access memory architecture;

[0041] Figure 2 A diagram illustrating a 1TnR high-density resistive switching memory architecture according to an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of a 2-layer integration scheme for the back end of a 1TnR according to an embodiment of the present invention;

[0043] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F This is a schematic diagram of the various fabrication processes for RRAM back-end integration based on CMOS technology according to an embodiment of the present invention;

[0044] Figure 5A , Figure 5B , Figure 5C and Figure 5D These are cross-sectional views of the front-end process completion, RRAM material deposition, RRAM device etching, and back-end interconnection in the RRAM integration process according to embodiments of the present invention.

[0045] Figure 6 A top view of the transistors, rheostats, and 1T1R structure in an existing 1T1R;

[0046] Figure 7 This is a top view of the transistor, rheostat, and 1T8R structure in an embodiment of the present invention;

[0047] Figure 8 This is a schematic diagram of the RRAM version icon layer according to an embodiment of the present invention;

[0048] Figure 9 The array area and chip area of ​​1T1R and 1T8R under different capacities;

[0049] Figure 10 This represents the ratio of the total area of ​​1T1R and 1T8R under different capacities;

[0050] Figure 11 This is a flowchart of an RRAM memory integration method according to an embodiment of the present invention. Detailed Implementation

[0051] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0052] like Figure 3 As shown, a specific embodiment of the present invention discloses an integrated device for an RRAM memory, comprising: a transistor, a first metal layer, a first RRAM layer, a second metal layer, a second RRAM layer, and a third metal layer.

[0053] refer to Figures 4A to 4F , Figure 7 and Figure 8 The transistor is located in and above a semiconductor substrate. The source (S) and drain (D) are located in the semiconductor substrate, and the gate (G) is located above the semiconductor substrate. The transistor includes: a U-shaped gate (G) located above the semiconductor substrate, wherein the U-shaped gate 115 includes a first branch 113, a second branch 114, and a gate connection portion 112 connecting the first branch 113 and the second branch 114; a source 102 located in the semiconductor substrate and disposed inside the U-shaped gate 115; and a U-shaped drain (D) located in the semiconductor substrate, wherein a U-shaped drain 104 surrounds the U-shaped gate 115 from the opening of the U-shaped gate 115, and the U-shaped drain 104 includes a first branch 110, a second branch 111, and a drain connection portion 109 connecting the first branch 110 and the second branch 111, wherein the first branch 113 and the second branch 114 of the U-shaped gate 115 extend into the interior of the U-shaped drain 104, while the gate connection portion 112 is not surrounded by the U-shaped drain.

[0054] Specifically, refer to Figures 4A to 4F The gate G includes a gate dielectric layer 401 and a gate layer 409, and a sidewall 402 located on the sidewall of the gate layer. The source metallization layer is located above the source S, and the drain metallization layer is located above the drain D. The thickness of the source metallization layer and the drain metallization layer is less than the thickness of the gate dielectric layer 401. The first branch 113 and the second branch 114 of the U-shaped gate 115 are in contact with the inner wall of the drain connection portion 109 via the gate dielectric layer 401.

[0055] Specifically, refer to Figure 4A An oxide insulating layer 403 is located above the transistor, wherein the source contact 406, drain contact 404, and gate contact 405 are disposed within the oxide insulating layer 403, for example, the material of the oxide insulating layer is SiO2. (Reference) Figure 7 The source contact 102, drain contact 108 and gate contact 105 are disposed in the oxide insulating layer.

[0056] The first dielectric layer 407 is located between the oxide insulating layer 403 and the first metal layer M4. The material of the first dielectric layer 407 is SiN.

[0057] refer to Figure 4A and Figure 7 A first passivation layer 408 is located above the first dielectric layer 407 and surrounds the first metal layer M4. The first metal layer M4 is located above the transistor layer and is connected to the source S, drain D, and gate G of the semiconductor substrate via source contact 406, drain contact 404, and gate contact 405, respectively. Specifically, the first metal layer M4 is connected to the source S of the semiconductor substrate via source contact 406; the first metal layer M4 is connected to the drain D of the semiconductor substrate via drain contact 404; and the first metal layer M4 is connected to the gate G of the semiconductor substrate via gate contact 405.

[0058] The second dielectric layer 409 is located above the first passivation layer 408.

[0059] refer to Figure 4B The second passivation layer 410 is located above the second dielectric layer 409 and surrounds the first RRAM layer. The first RRAM layer is located above the first metal layer M4 and includes a plurality of first rheostats connected in parallel, wherein each first rheostat is sequentially connected in series to the drain D of the transistor via a plurality of first via contacts, the first metal layer, and a plurality of drain contacts. Specifically, the plurality of first rheostats includes 2N first rheostats, where N is greater than or equal to 2, wherein N first rheostats are located above the first branch 110 of the drain in the vertical direction; the remaining N first rheostats are located above the second branch 114 of the U-shaped gate 115 in the vertical direction, wherein the first branch 110 of the drain is adjacent to the first branch of the U-shaped gate 115 and away from the second branch 114 of the U-shaped gate 115, and the 2N first rheostats are configured to be located at the corners of the rectangle. For example, when N=2, two first rheostats are vertically positioned at both ends of the first branch 110 of the drain, and the remaining two first rheostats are vertically positioned at both ends of the second branch 114 of the U-shaped gate 115. When N=3 or 4, three or four first rheostats are vertically positioned at equal intervals above the first branch 110 of the drain, and the remaining three or four first rheostats are vertically positioned at equal intervals above the second branch 114 of the U-shaped gate 115.

[0060] Each of the plurality of first rheostats 201, 203, 212, and 213 includes: a bottom electrode located above a lower electrode through-hole contact, the bottom electrode being made of TaN; an oxygen storage layer located above the bottom electrode, the oxygen storage layer being made of TaOx; and a resistive switching layer located above the oxygen storage layer, the resistive switching layer being made of HfOx, wherein the thickness of the resistive switching layer is... Less than the thickness of the oxygen storage layer The top electrode is located above the resistive switching layer and is made of TiN. The bottom electrode, oxygen storage layer, resistive switching layer and top electrode have the same width, and the width of the lower electrode through-hole contact is greater than the width of the first through-hole contact.

[0061] The third dielectric layer 411 is located above the second passivation layer 410.

[0062] The third passivation layer 412 is located above the third dielectric layer 411 and surrounds the second metal layer M5. The second metal layer M5 is located above the first RRAM layer.

[0063] The fourth dielectric layer is located above the third passivation layer 412.

[0064] A fourth passivation layer is located above the fourth dielectric layer and surrounds the second RRAM layer. The second RRAM layer is located above the second metal layer and includes multiple parallel second rheostats. Each second rheostat is connected in series to the drain of the transistor via multiple second via contacts, the second metal layer, multiple third via contacts, the first metal layer, and multiple drain contacts. The multiple first rheostats and the multiple second rheostats do not overlap in the vertical direction, and each first via contact and each third via contact is independently distributed above the drain of the transistor in the vertical direction. Specifically, the plurality of second rheostats includes 2N second rheostats, where N is greater than or equal to 2. N second rheostats are located vertically above the first branch 113 of the U-shaped gate 115; the remaining N second rheostats are located vertically above the second branch 111 of the drain. The second branch 111 of the drain is adjacent to the second branch 114 of the U-shaped gate 115 and away from the first branch 113 of the U-shaped gate 115. The 2N second rheostats are positioned at the corners of the rectangle. For example, when N = 2, two second rheostats 209 and 210 are vertically positioned at both ends of the second branch 111 of the drain, and the remaining two second rheostats 204 and 205 are vertically positioned at both ends of the first branch 113 of the U-shaped gate 115. When N=3 or 4, three or four second rheostats are arranged in a perpendicular manner above the second branch 111 of the drain in the vertical direction, and the remaining three or four second rheostats are arranged in a perpendicular manner above the first branch 113 of the U-shaped gate 115 in the vertical direction.

[0065] Specifically, each of the plurality of second rheostats 204, 205, 209, and 210 includes: a bottom electrode located above the lower electrode through-hole contact, the bottom electrode being made of TaN; an oxygen storage layer located above the bottom electrode, the oxygen storage layer being made of TaOx; and a resistive switching layer located above the oxygen storage layer, the resistive switching layer being made of HfOx, wherein the thickness of the resistive switching layer is... Less than the thickness of the oxygen storage layer The top electrode is located above the resistive switching layer. The bottom electrode, oxygen storage layer, resistive switching layer and top electrode have the same width, and the width of the lower electrode through-hole contact is greater than the width of the first through-hole contact.

[0066] Compared with existing technologies, the integrated RRAM memory device provided in this embodiment offers the following advantages: 1. Increased storage density: In the 1TnR architecture, one transistor connects n RRAM cells in series, resulting in improved area utilization. 2. The method for increasing storage density with 1TnR has a simple actual manufacturing process; RRAM cells can be fabricated between any two interconnect layers through deposition, etching, and interconnection. 3. 1TnR supports high-parallelity matrix operations, enhancing AI acceleration performance. By implementing vertical stacking of three or more layers, not only can storage density be significantly increased, but multi-level dynamic control similar to synaptic connections in biological neural networks can also be achieved. Furthermore, the multi-layer stacked structure helps to construct more complex access paths, improving overall data processing speed and energy efficiency.

[0067] like Figure 11 As shown in the figure, a specific embodiment of the present invention discloses an integration method for an RRAM memory, comprising:

[0068] In step S1101, a transistor is formed in and above the semiconductor substrate;

[0069] In step S1102, an oxide insulating layer is formed above the transistor, and a source contact, a drain contact, and a gate contact are formed in the oxide insulating layer;

[0070] In step S1103, a first metal layer is formed above the transistor to be connected to the source, drain and gate respectively via the source contact, drain contact and gate contact;

[0071] In step S1104, a first RRAM layer is formed above the first metal layer, and the first RRAM layer is etched into a plurality of parallel first rheostats, such that each first rheostat is sequentially connected in series to the drain of the transistor via a plurality of first through-hole contacts, the first metal layer and a plurality of drain contacts.

[0072] Specifically, forming a first RRAM layer above the first metal layer further includes: depositing a passivation material layer above the first metal layer, then patterning and etching vias in the passivation material layer, and then filling the vias with a bottom electrode material layer; sequentially depositing an oxygen storage layer and a resistive switching layer above the passivation material layer, wherein the thickness of the oxygen storage layer is greater than the thickness of the resistive switching layer; depositing a top electrode material layer above the resistive switching layer; generating a varistor pattern using deep ultraviolet lithography, and then etching the varistor pattern using reactive ion etching to generate the first varistor, wherein the thickness of the resistive switching layer is less than the thickness of the oxygen storage layer.

[0073] Specifically, the plurality of first rheostats includes 2N first rheostats, where N is greater than or equal to 2, wherein N first rheostats are located above the first branch 110 of the drain in the vertical direction; the remaining N first rheostats are located above the second branch 114 of the U-shaped gate 115 in the vertical direction, wherein the first branch 110 of the drain is adjacent to the first branch 113 of the U-shaped gate 115 and away from the second branch 114 of the U-shaped gate 115, and the 2N first rheostats are configured to be located at the corners of the rectangle.

[0074] In step S1105, a second metal layer is formed over the first RRAM layer;

[0075] In step S1106, a second RRAM layer is formed above the second metal layer, and the second RRAM layer is etched into a plurality of parallel second rheostats, such that each second rheostat is connected in series to the drain of the transistor via a plurality of second via contacts, a second metal layer, a plurality of third via contacts, a first metal layer and a plurality of drain contacts. The plurality of first rheostats and the plurality of second rheostats do not overlap in the vertical direction, and each first via contact and each third via contact are independently distributed above the drain of the transistor in the vertical direction.

[0076] Specifically, forming a second RRAM layer above the second metal layer further includes: depositing a passivation material layer above the second metal layer, then patterning and etching vias in the passivation material layer, and then filling the vias with a bottom electrode material layer; sequentially depositing an oxygen storage layer and a resistive switching layer above the passivation material layer, wherein the thickness of the oxygen storage layer is greater than the thickness of the resistive switching layer; depositing a top electrode material layer above the resistive switching layer; generating a varistor pattern using deep ultraviolet lithography, and then etching the varistor pattern using reactive ion etching to generate a second varistor, wherein the thickness of the resistive switching layer is less than the thickness of the oxygen storage layer.

[0077] Specifically, the plurality of second rheostats includes 2N second rheostats, where N is greater than or equal to 2. N second rheostats are located vertically above the first branch 113 of the U-shaped gate 115; the remaining N second rheostats are located vertically above the second branch 111 of the drain, wherein the second branch 111 of the drain is adjacent to the second branch 114 of the U-shaped gate and away from the first branch 113 of the U-shaped gate 115, and the 2N second rheostats are configured to be located at the corners of the rectangle.

[0078] The integrated apparatus of RRAM memory according to embodiments of the present invention will be described in detail below by way of specific examples.

[0079] Figure 1 It uses a 1T1R resistive random-access memory (RRAM) architecture. Increasing its density requires continuously shrinking the size of transistors, but this shrinking introduces reliability issues. To improve storage density... Figure 2 It is a 1TnR high-density resistive random access memory (IRRAM) architecture, in which n IRRAMs are connected in parallel and one transistor is connected in series with n IRRAMs. Compared with the 1T1R structure, the 1TnR architecture, which connects multiple IRRAMs in parallel and then in series with the transistor, can improve the integration density of IRRAMs. However, since n IRRAMs share one transistor to control their on / off state, electrical crosstalk and thermal crosstalk are easily generated in the circuit. Using bipolar nonlinear IRRAMs to replace traditional IRRAMs can effectively suppress the generation of crosstalk loops, improve reliability, and reduce the power consumption of the circuit.

[0080] RRAM can be integrated between any two interconnect layers in the back end of a CMOS process; by utilizing the vertical spatial position of the back-end interconnects, the RRAM in a 1TnR can be placed on different layers, thereby increasing the integration density. Figure 3 This is an RRAM back-end integration solution; the RRAM material can be used in the front-end process (see reference). Figure 5A After completion, deposition (reference) Figure 5B Etching complete (reference) Figure 5C Interconnection with transistors (reference) Figure 5D The preparation process is simple. Figures 4A to 4F It is a 1TnR high-density back-end integration solution, which uses metal interconnects to form a 1TnR structure, showing the integration solution with two resistive switching layers. Similarly, n layers can be stacked, thus having the potential for high-density integration.

[0081] Based on the above integration scheme, draw the layout of individual cells for 1T1R and 1T8R. Figure 6 The smallest size of a 1T1R cell is approximately 2µm x 3µm. Figure 7The minimum size of a 1T8R cell is approximately 3um*3um. It can be seen that 1T8R increases storage density by using an additional layer of metal, thereby improving the density of the storage array. This verifies the huge potential for increasing the density of RRAM memory.

[0082] Based on the minimum cell size and optimized layout design rules, the relationship between chip capacity and integrated structure is obtained by optimizing the matching of peripheral circuits and array layout area to maximize area savings. Figure 9 These are the array area and chip area of ​​1T1R and 1T8R under different capacities. Figure 10 This represents the ratio of the total area of ​​1T1R to 1T8R under different capacities. It can be seen that when the chip capacity is greater than 1Mb, 1T8R exhibits a significant density advantage. When 1T8R is vertically extended to 1T16R or even more, the density advantage becomes even greater.

[0083] Limited 1T1R storage density: In the traditional 1T1R architecture, each RRAM cell requires a dedicated transistor, resulting in low area utilization. In Example 1, to provide storage density, a 1TnR architecture connects one transistor to n RRAM cells, leading to improved area utilization.

[0084] When increasing storage density by continuously shrinking the T in 1T1R, the reduced driving capability of the transistor after shrinking leads to insufficient driving capability, which not only causes RRAM programming failures but also further affects the stability and reliability of the storage cells. In Example 2, to further improve the stability and reliability of the storage cells, the method of increasing storage density with 1TnR has a simple actual manufacturing process. RRAM cells can be fabricated between any two interconnect layers through deposition, etching, and interconnection.

[0085] The traditional 1T1R architecture struggles to support high-parallel matrix operations, limiting AI acceleration performance. In Example 3, 1TnR supports high-parallel matrix operations, enhancing AI acceleration performance. By implementing three or more layers of vertical stacking, not only can storage density be significantly increased, but multi-level dynamic control of synaptic connections, similar to that in biological neural networks, can also be achieved. Furthermore, the multi-layered stacked structure facilitates the construction of more complex access paths, improving overall data processing speed and energy efficiency.

[0086] refer to Figures 4A to 4FRRAM cells can be fabricated by deposition, etching, and interconnection between any two interconnect layers. Two additional masks are required: one to define the RRAM electrode structure (e.g., bottom and top electrodes), and another to etch the HfOx dielectric layer to achieve resistive switching functionality. This design avoids modifications to the logic layer (FEOL), requiring only adjustments to the back-end process, significantly reducing manufacturing costs. Integration involves four steps: completing the front-end transistor process, depositing RRAM material, etching the RRAM device, and implementing the back-end interconnection. Specific solutions are as follows... Figures 5A to 5D As shown.

[0087] refer to Figures 4A to 4F , Figures 5A to 5D , Figure 6 and Figure 8 The integration density of RRAM is increased by embedding two layers of metal interconnects. First, the process before the logic circuit and V4 layer (fourth metal interconnect) is completed, including standard CMOS processes such as transistor fabrication and shallow interconnects. Then, the back-end integration of the first-layer RRAM cells is achieved between the M4 and M5 metal layers. TEVIA and V4 serve as the top and bottom electrodes of the RRAM. TEVIA is identified as TXT_poly in the layout, and the resistive switching material RAM layer is identified as TXT_well. This completes the integration of the first layer of RRAM. Between the M5 and M6 metal layers, TEVIA and V5 serve as the top and bottom electrodes of the RRAM. TEVIA is identified as TXT_sub in the layout, and the resistive switching material RAM layer is identified as TXT_btxt. This completes the integration of the second layer of RRAM.

[0088] refer to Figure 9 As storage capacity increases, the proportion of 1T1R and 1T8R array area in the overall chip area becomes increasingly larger, better showcasing the array advantages of high-density storage solutions. When the storage capacity exceeds 256Mb, the density of 1T8R chips is 2.5 times that of 1T1R chips, significantly improving integration density. Further increases in capacity have little impact on storage density, and the ratio of chip area to array area gradually approaches that of the array area. With continuous increases in storage capacity, the proportion of array area to the total chip area increases, while the proportion of circuit area decreases. Therefore, the density advantage ultimately translates into an array area advantage, which depends on the advantages of the storage cells. Thus, adopting the 1TnR high-density integrated architecture has great potential for increasing density under high-capacity demands.

[0089] refer to Figure 10In the 1TnR integrated architecture, based on the current two-layer RRAM cell stacking scheme, increasing the number of subsequent stacking layers can significantly improve storage density while maintaining the same array area. As process nodes continue to shrink, the demand for large-capacity embedded storage in high-performance chips is becoming increasingly urgent. From a technical perspective, the 1TnR high-density integration solution, with its unique architectural advantages, can achieve higher storage density within a limited chip area by optimizing the number of stackable cells in each layer and increasing the number of stacking layers. This solution not only effectively meets the stringent storage capacity requirements of high-performance chips but also achieves a good balance between performance and power consumption. Therefore, the 1TnR high-density integration solution will demonstrate enormous application potential in future high-performance chip applications.

[0090] The first step is to complete the front-end process of transistor manufacturing and stop at the intermediate metal layer, such as... Figure 4A As shown. In this experiment, the RRAM is integrated on the fourth metal layer (M4).

[0091] The second step is the etching and deposition of the lower electrode vias. After depositing a dielectric layer (insulating material such as SiN) on M4, the vias are patterned and etched. The vias are then filled with tantalum nitride (TaN) grown by PVD, followed by chemical mechanical polishing (CMP) to ensure the metal layer has good conductivity and surface smoothness. Figure 4B As shown.

[0092] The third step is the deposition of the oxygen storage layer and the resistive switching layer. TaO is grown using PVD, respectively. x Thickness is HfO grown using ALD x Material, thickness is To ensure device reliability, oxygen content and defect density must be precisely controlled, such as Figure 4C As shown.

[0093] The fourth step is the deposition of the upper electrode. TiN is prepared using low-temperature PVD to ensure low interfacial resistance while avoiding the impact of high temperatures on the resistive switching layer properties, such as… Figure 4D As shown.

[0094] The fifth step is photolithography and stack etching. Deep ultraviolet (DUV) lithography is used to define the device pattern, and reactive ion etching (RIE) is used to etch the stack of resistive switching materials. The etching end point needs to be strictly controlled to prevent damage to the underlying structure.

[0095] The sixth step is annealing, which optimizes the crystallinity and oxygen vacancy distribution of the resistive switching layer. The temperature (300℃) and atmosphere (N2) are controlled to optimize the resistance switching characteristics.

[0096] The seventh step is the etching and deposition of interconnect vias. The logic region and resistive switching memory region simultaneously undergo photolithography and etching of contact via 4 (Via4). Utilizing the etching selectivity ratio between the dielectric layer and the top electrode, the etching and deposition of Via4 are completed synchronously. Figure 4E As shown.

[0097] The eighth step is logic wire interconnection and passivation. Finally, the upstream interconnection leads are completed and passivated using standard back-end processes, such as... Figure 4F As shown.

[0098] This patent proposes an integration method to improve RRAM storage density, which can integrate RRAM between any two interconnect layers in the back end of CMOS process; realize 1TnR architecture, and utilize the vertical spatial position of the back-end interconnect to place the RRAM in 1TnR on different layers, thereby improving integration density.

[0099] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0100] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An integrated device for RRAM memory, characterized in that, include: A transistor, located in and above a semiconductor substrate; The first metal layer is located above the transistor layer and is connected to the source, drain and gate of the semiconductor substrate via source contact, drain contact and gate contact, respectively. The first RRAM layer, located above the first metal layer, includes a plurality of first rheostats connected in parallel, wherein each first rheostat is sequentially connected in series to the drain of the transistor via a first through-hole contact, the first metal layer and a drain contact; The second metal layer is located above the first RRAM layer; The second RRAM layer, located above the second metal layer, includes a plurality of parallel second rheostats. Each second rheostat is connected in series to the drain of the transistor via a second via contact, the second metal layer, a third via contact, the first metal layer, and a drain contact. The plurality of first rheostats and the plurality of second rheostats do not overlap in the vertical direction, and each first via contact and each third via contact are independently distributed above the drain of the transistor in the vertical direction.

2. The integrated device for RRAM memory according to claim 1, characterized in that, The transistor includes: The gate is U-shaped and located above the semiconductor substrate, wherein the U-shaped gate includes a first branch, a second branch, and a gate connection portion connecting the first branch and the second branch; The source electrode is located in the semiconductor substrate and disposed inside the U-shaped gate; The drain is U-shaped and located in the semiconductor substrate. The U-shaped drain surrounds the U-shaped gate from the opening of the U-shaped gate and includes a first branch, a second branch, and a drain connection portion. The first and second branches of the U-shaped gate extend into the interior of the U-shaped drain, while the gate connection portion is not surrounded by the U-shaped drain.

3. The integrated device for RRAM memory according to claim 2, characterized in that, The number of the first variable resistors is 2N, and N is greater than or equal to 2, where, N first rheostats are located vertically above the first branch of the drain electrode; The remaining N first rheostats are located vertically above the second branch of the U-shaped gate, wherein the first branch of the drain is adjacent to the first branch of the U-shaped gate and away from the second branch of the U-shaped gate, and the 2N first rheostats are arranged at the corners of the rectangle.

4. The integrated device for RRAM memory according to claim 2, characterized in that, The number of the second rheostats is 2N, and N is greater than or equal to 2, where N second rheostats are located vertically above the first branch of the U-shaped gate; The remaining N second rheostats are located vertically above the second branch of the drain, wherein the second branch of the drain is adjacent to the second branch of the U-shaped gate and away from the first branch of the U-shaped gate, and the 2N second rheostats are arranged at the corners of the rectangle.

5. The integrated device for RRAM memory according to claim 4, characterized in that, The first and second rheostats include: The bottom electrode is located above the lower electrode through-hole contact. An oxygen storage layer is located above the bottom electrode; A resistive switching layer is located above the oxygen storage layer, wherein the thickness of the resistive switching layer is less than the thickness of the oxygen storage layer; The top electrode is located above the resistive switching layer, wherein the bottom electrode, the oxygen storage layer, the resistive switching layer and the top electrode have the same width, and the width of the lower electrode through-hole contact of the first resistor is greater than the width of the first through-hole contact.

6. The integrated device for RRAM memory according to claim 2, characterized in that, The gate includes a gate dielectric layer and a gate layer, and a sidewall located on the sidewall of the gate layer, wherein, A source metallization layer is located above the source electrode, and a drain metallization layer is located above the drain electrode, wherein the thickness of the source metallization layer and the drain metallization layer is less than the thickness of the gate dielectric layer; The first and second branches of the U-shaped gate are in contact with the inner wall of the drain connection via the gate dielectric layer.

7. The integrated device for RRAM memory according to claim 5, characterized in that, Also includes: An oxide insulating layer is located above the transistor, wherein the source contact, the drain contact, and the gate contact are disposed in the oxide insulating layer; A first dielectric layer is located between the oxide insulating layer and the first metal layer; A first passivation layer is located above the first dielectric layer and is used to surround the first metal layer; The second dielectric layer is located above the first passivation layer; A second passivation layer is located above the second dielectric layer and is used to surround the first RRAM layer; The third dielectric layer is located above the second passivation layer; A third passivation layer is located above the third dielectric layer and is used to surround the second metal layer; The fourth dielectric layer is located above the third passivation layer; A fourth passivation layer, located above the fourth dielectric layer, is used to surround the second RRAM layer.

8. A method for integrating an RRAM memory, characterized in that, include: A transistor is formed in and on a semiconductor substrate; An oxide insulating layer is formed above the transistor, and a source contact, a drain contact, and a gate contact are formed in the oxide insulating layer; A first metal layer is formed above the transistor to be connected to the source, drain and gate respectively via the source contact, the drain contact and the gate contact; A first RRAM layer is formed above the first metal layer, and the first RRAM layer is etched into a plurality of parallel first rheostats, such that each first rheostat is sequentially connected in series to the drain of the transistor via a plurality of first through-hole contacts, the first metal layer and a plurality of drain contacts; A second metal layer is formed above the first RRAM layer; A second RRAM layer is formed above the second metal layer, and the second RRAM layer is etched into a plurality of parallel second rheostats, such that each second rheostat is sequentially connected in series to the drain of the transistor via a plurality of second via contacts, the second metal layer, a plurality of third via contacts, the first metal layer, and a plurality of drain contacts. The plurality of first rheostats and the plurality of second rheostats do not overlap in the vertical direction, and each first via contact and each third via contact are independently distributed above the drain of the transistor in the vertical direction.

9. The integration method of RRAM memory according to claim 8, characterized in that, The number of both the first and second rheostats is 2N, where N is greater than or equal to 2. N first rheostats are located vertically above the first branch of the drain electrode; The remaining N first rheostats are located vertically above the second branch of the U-shaped gate, wherein the first branch of the drain is adjacent to the first branch of the U-shaped gate and away from the second branch of the U-shaped gate, and the 2N first rheostats are arranged to be located at the corners of the rectangle. N second rheostats are located vertically above the first branch of the U-shaped gate; The remaining N second rheostats are located vertically above the second branch of the drain, wherein the second branch of the drain is adjacent to the second branch of the U-shaped gate and away from the first branch of the U-shaped gate, and the 2N second rheostats are arranged at the corners of the rectangle.

10. The method for integrating RRAM memory according to claim 9, characterized in that, Forming a first RRAM layer over the first metal layer or forming a second RRAM layer over the second metal layer further includes: A passivation material layer is deposited above the first metal layer or the second metal layer, and then the passivation material layer is patterned and etched with vias, and then the bottom electrode material layer is filled in the vias. An oxygen storage layer and a resistive switching layer are sequentially deposited on top of the passivation material layer, wherein the thickness of the oxygen storage layer is greater than the thickness of the resistive switching layer; A top electrode material layer is deposited above the resistive switching layer; A varistor pattern is generated using deep ultraviolet lithography, and then the varistor pattern is etched using reactive ion etching to generate multiple first varistors or multiple second varistors.

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