Semiconductor device and method of forming the same, package structure and electronic device

Abstract

The embodiments of the present disclosure provide a semiconductor device and a forming method thereof, a packaging structure and an electronic device. The semiconductor device comprises: a first semiconductor structure, a second semiconductor structure and a third semiconductor structure stacked along a first direction; the second semiconductor structure is located between the third semiconductor structure and the first semiconductor structure; wherein the first semiconductor structure comprises an analog-to-digital conversion circuit and a data processing circuit; the third semiconductor structure comprises a storage array for performing a first operation, and the second semiconductor structure comprises a peripheral circuit coupled to the storage array.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a semiconductor device, a method for forming the same, a packaging structure, and an electronic device. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] This disclosure provides a semiconductor device, a method for forming the same, a packaging structure, and an electronic device.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, comprising: a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure stacked along a first direction; the second semiconductor structure being located between the third semiconductor structure and the first semiconductor structure; wherein the first semiconductor structure includes an analog-to-digital conversion circuit and a data processing circuit; the third semiconductor structure includes a memory array for performing a first operation, and the second semiconductor structure includes peripheral circuitry coupled to the memory array.

[0005] In some embodiments, the third semiconductor structure includes a pad layer; the pad layer includes a plurality of pad structures located on one side of the memory array opposite each other along the first direction, away from the second semiconductor structure.

[0006] In some embodiments, the second semiconductor structure further includes a semiconductor layer, a first conductive connection structure, and a second conductive connection structure; the first semiconductor structure further includes a controller; the first conductive connection structure is coupled to the peripheral circuit, and the second conductive connection structure is coupled to the controller; a portion of the peripheral circuit is located in the semiconductor layer; both the first conductive connection structure and the second conductive connection structure penetrate the semiconductor layer along the first direction.

[0007] In some embodiments, the dimension of the portion of the first conductive connection structure near the third semiconductor structure along the first direction along the second direction is smaller than the dimension of the portion of the first conductive connection structure near the first semiconductor structure along the first direction along the second direction; the dimension of the portion of the second conductive connection structure near the third semiconductor structure along the first direction along the second direction is smaller than the dimension of the portion of the second conductive connection structure near the first semiconductor structure along the first direction along the second direction; the second direction is perpendicular to the first direction.

[0008] In some embodiments, the second semiconductor structure further includes a first interconnect layer; the first interconnect layer is located between the peripheral circuit and the third semiconductor structure; the first interconnect layer includes a first interconnect structure; and the first conductive connection structure is connected to the peripheral circuit through the first interconnect structure.

[0009] In some embodiments, the first interconnect structure includes a third conductive connection structure extending along the first direction and a plurality of first conductive lines extending along a third direction and arranged along the second direction; the two ends of the third conductive connection structure opposite to each other along the first direction are respectively connected to the peripheral circuit and the first conductive lines; the second direction, the first direction and the third direction are perpendicular to each other.

[0010] In some embodiments, both the first conductive connection structure and the second conductive connection structure extend into the first interconnect layer, with one end of the first conductive connection structure opposite to each other along the first direction connected to the corresponding first conductive line, and one end of the second conductive connection structure opposite to each other along the first direction connected to the corresponding first conductive line.

[0011] In some embodiments, the first interconnect structure further includes a plurality of fourth conductive connection structures; one end of one of the four fourth conductive connection structures located between the first conductive connection structure and the first conductive line along the first direction is connected to the first conductive connection structure, and the other end is connected to the corresponding first conductive line; one end of one of the four fourth conductive connection structures located between the second conductive connection structure and the first conductive line along the first direction is connected to the second conductive connection structure, and the other end is connected to the corresponding first conductive line.

[0012] In some embodiments, the first interconnect structure further includes a plurality of second conductive lines extending along the third direction and arranged along the second direction, and a plurality of fifth conductive connection structures; one end of one of the opposite ends of the first conductive connection structure along the first direction is connected to the corresponding second conductive line, and one end of one of the opposite ends of the second conductive connection structure along the first direction is connected to the corresponding second conductive line; one end of one of the opposite ends of the fifth conductive connection structure along the first direction is connected to the corresponding first conductive line, and the other end is connected to the corresponding second conductive line.

[0013] In some embodiments, the first semiconductor structure and the second semiconductor structure are bonded together, and the second semiconductor structure is bonded together with the third semiconductor structure.

[0014] In some embodiments, the third semiconductor structure further includes a first bonding layer, and the second semiconductor structure further includes a second bonding layer, the first bonding layer and the second bonding layer being located between the memory array and the peripheral circuit; the first bonding layer includes a first dielectric layer and a first bonding contact located in the first dielectric layer, and the second bonding layer includes a second dielectric layer and a second bonding contact located in the second dielectric layer; the first dielectric layer is bonded to the second dielectric layer, and the first bonding contact is bonded to the second bonding contact.

[0015] In some embodiments, the third semiconductor structure further includes a second interconnect layer and a bit line; the bit line and the second interconnect layer are both located between the memory array and the first bonding layer, and the bit line is located between the memory array and the second interconnect layer; the second interconnect layer includes a second interconnect structure; the memory array is connected to the peripheral circuit through the bit line, the second interconnect structure, the first bonding contact, the second bonding contact, and the first interconnect structure.

[0016] In some embodiments, the third semiconductor structure further includes a sixth conductive connection structure; the sixth conductive connection structure extends through the memory array along the first direction, and the sixth conductive connection structure is connected to the second conductive connection structure through the second interconnect structure, the first bonding contact, the second bonding contact, and the first interconnect structure.

[0017] In some embodiments, the third semiconductor structure further includes a third interconnect layer; the third interconnect layer includes a plurality of third interconnect structures; the third interconnect layer is located between the pad layer and the memory array; the sixth conductive connection structure is connected to a first pad structure among the plurality of pad structures through a corresponding third interconnect structure among the plurality of third interconnect structures.

[0018] In some embodiments, the third semiconductor structure further includes a source line located between the memory array and the third interconnect structure, the source line being connected to the memory array, and the source line being connected to a second pad structure among the plurality of pad structures through a corresponding third interconnect structure among the plurality of third interconnect structures.

[0019] In some embodiments, the third semiconductor structure further includes a seventh conductive connection structure; the seventh conductive connection structure extends through the memory array along the first direction, the seventh conductive connection structure is connected to the memory array through the second interconnect structure, and the seventh conductive connection structure is connected to the third pad structure among the plurality of pad structures through a corresponding third interconnect structure among the plurality of third interconnect structures.

[0020] In some embodiments, the second semiconductor structure further includes a fourth interconnect layer and a third bonding layer; the first semiconductor structure further includes a fifth interconnect layer and a fourth bonding layer; the fourth interconnect layer, the third bonding layer, the fifth interconnect layer, and the fourth bonding layer are all located between the analog-to-digital conversion circuit and the peripheral circuit, and between the data processing circuit and the peripheral circuit; the fourth interconnect layer is located between the third bonding layer and the peripheral circuit; the fifth interconnect layer is located between the fourth bonding layer and the analog-to-digital conversion circuit, and between the fourth bonding layer and the data processing circuit; the third bonding layer includes a third dielectric layer and a third bonding contact located in the third dielectric layer, and the fourth bonding layer includes a fourth dielectric layer and a fourth bonding contact located in the fourth dielectric layer; the third dielectric layer is bonded to the fourth dielectric layer, and the third bonding contact is bonded to the fourth bonding contact; the fourth interconnect layer includes a fourth interconnect structure, and the fifth interconnect layer includes a fifth interconnect structure.

[0021] In some embodiments, the first conductive connection structure is connected to the analog-to-digital conversion circuit through the fourth interconnect structure, the third bonding contact, the fourth bonding contact, and the fifth interconnect structure.

[0022] In some embodiments, the second conductive connection structure is connected to the controller via the fourth interconnect structure, the third bonding contact, the fourth bonding contact, and the fifth interconnect structure.

[0023] In some embodiments, the analog-to-digital conversion circuit is configured to convert the analog computation information obtained by the storage array performing the first operation into digital information; the data processing circuit is configured to perform a second operation on the digital information.

[0024] In some implementations, the first operation includes a multiplication-accumulation operation.

[0025] In some implementations, the second operation includes one or more of the following operations: compensation, activation, shifting, or pooling.

[0026] In some implementations, the storage array includes a three-dimensional NAND-type storage array.

[0027] In a second aspect, embodiments of this disclosure provide a semiconductor device, including: a second semiconductor structure and a third semiconductor structure stacked along a first direction; wherein the third semiconductor structure includes a memory array for performing a first operation; the second semiconductor structure includes peripheral circuitry coupled to the memory array, and a third bonding layer located on one side of the peripheral circuitry opposite to each other along the first direction, away from the third semiconductor structure; the third bonding layer is used for bonding with a first semiconductor structure, the first semiconductor structure including an analog-to-digital conversion circuit and a data processing circuit.

[0028] In some embodiments, the third semiconductor structure includes a pad layer; the pad layer includes a plurality of pad structures located on one side of the memory array opposite each other along the first direction, away from the second semiconductor structure.

[0029] In some embodiments, the second semiconductor structure further includes a semiconductor layer, a first conductive connection structure, and a second conductive connection structure; one end of the first conductive connection structure opposite to each other along the first direction is coupled to the peripheral circuit, and the other end of the first conductive connection structure opposite to each other along the first direction is used to couple to the analog-to-digital conversion circuit; the second conductive connection structure is used to couple to the controller of the first semiconductor structure; a portion of the peripheral circuit is located in the semiconductor layer; both the first conductive connection structure and the second conductive connection structure penetrate the semiconductor layer along the first direction.

[0030] In some embodiments, the third semiconductor structure further includes a sixth conductive connection structure; the sixth conductive connection structure extends through the memory array along the first direction, one end of the sixth conductive connection structure opposite to each other along the first direction is coupled to the second conductive connection structure, and the other end of the sixth conductive connection structure opposite to each other along the first direction is coupled to the first pad structure of the plurality of pad structures.

[0031] In some embodiments, the third semiconductor structure further includes a seventh conductive connection structure; the seventh conductive connection structure extends through the memory array along the first direction, one end of the seventh conductive connection structure opposite to each other along the first direction is coupled to the memory array, and the other end of the seventh conductive connection structure opposite to each other along the first direction is coupled to a third pad structure among the plurality of pad structures.

[0032] Thirdly, this disclosure provides a packaging structure, including: a packaging substrate, a semiconductor device as described in any of the above embodiments, and a molding compound layer; the semiconductor device is disposed on the packaging substrate; and the molding compound layer encapsulates the semiconductor device.

[0033] Fourthly, embodiments of this disclosure provide an electronic device, including: a semiconductor device as described in any of the above embodiments.

[0034] Fifthly, embodiments of this disclosure provide a method for forming a semiconductor device, comprising: forming a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure stacked along a first direction; the second semiconductor structure being located between the third semiconductor structure and the first semiconductor structure; the first semiconductor structure including an analog-to-digital conversion circuit and a data processing circuit; the third semiconductor structure including a memory array for performing a first operation; and the second semiconductor structure including peripheral circuitry coupled to the memory array.

[0035] In some embodiments, forming the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure stacked along a first direction includes: forming the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure respectively; and bonding the second semiconductor structure to the first semiconductor structure and the third semiconductor structure respectively.

[0036] In some embodiments, forming the third semiconductor structure includes forming a pad layer; the pad layer includes a plurality of pad structures located on one side of the memory array opposite each other along the first direction, away from the second semiconductor structure.

[0037] In some embodiments, forming the second semiconductor structure includes: providing a semiconductor layer; forming the peripheral circuit from a first side of two opposing sides of the semiconductor layer along the first direction; forming a first conductive connection structure and a second conductive connection structure through the semiconductor layer from a second side of two opposing sides of the semiconductor layer along the first direction; the first conductive connection structure being coupled to the peripheral circuit; forming the first semiconductor structure includes forming a controller; the second conductive connection structure being coupled to the controller.

[0038] In this embodiment of the disclosure, the first semiconductor structure includes an analog-to-digital converter circuit and a data processing circuit, the second semiconductor structure includes peripheral circuits, and the third semiconductor structure includes a memory array for performing a first operation. The second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure. This allows a pad structure to be formed on the side of the third semiconductor structure that is away from the second semiconductor structure along the first direction, so that it is not necessary to form a conductive connection structure that penetrates the semiconductor layer of the first semiconductor structure. This improves the impact of forming a conductive connection structure that penetrates the semiconductor layer of the first semiconductor structure on advanced logic devices such as the analog-to-digital converter circuit and the data processing circuit in the first semiconductor structure. Attached Figure Description

[0039] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 1 ;

[0040] Figure 2 A schematic diagram showing the distribution of memory cells in a semiconductor device according to an embodiment of this disclosure;

[0041] Figure 3 A schematic diagram of an exemplary semiconductor device including peripheral circuitry provided for an embodiment of this disclosure;

[0042] Figure 4 A schematic cross-sectional view of a storage array including storage strings provided for an embodiment of this disclosure;

[0043] Figure 5A Schematic diagram of a semiconductor device provided in an embodiment of this disclosure Figure 1 ;

[0044] Figure 5B Schematic diagram of a semiconductor device provided in an embodiment of this disclosure Figure 2 ;

[0045] Figure 6 This is a schematic diagram illustrating the input voltage to the memory block via a top selection line, according to an embodiment of this disclosure.

[0046] Figure 7 This is a schematic diagram of a plurality of memory strings coupled to a bit line, provided in an embodiment of the present disclosure;

[0047] Figure 8 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 2 ;

[0048] Figure 9 A schematic cross-sectional structure of a semiconductor device provided in an embodiment of this disclosure. Figure 1 ;

[0049] Figure 10 A partial cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. Figure 1 ;

[0050] Figure 11 A partial cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. Figure 2 ;

[0051] Figure 12 A partial cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. Figure 3 ;

[0052] Figure 13 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 3 ;

[0053] Figure 14 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 4 ;

[0054] Figure 15 A schematic cross-sectional structure of a semiconductor device provided in an embodiment of this disclosure. Figure 2 ;

[0055] Figure 16 A flowchart illustrating a method for forming a semiconductor device according to an embodiment of this disclosure. Figure 1 ;

[0056] Figures 17 to 22 A schematic diagram of the formation process of a semiconductor device provided in an embodiment of this disclosure;

[0057] Figure 23 A flowchart illustrating a method for forming a semiconductor device according to an embodiment of this disclosure. Figure 2 ;

[0058] Figure 24 A schematic diagram of a packaging structure provided in an embodiment of this disclosure;

[0059] Figure 25 This is a schematic diagram of an exemplary electronic device having semiconductor devices according to an embodiment of the present disclosure;

[0060] Figure 26 This is a schematic diagram of an exemplary memory card having semiconductor devices according to an embodiment of the present disclosure;

[0061] Figure 27 This is a schematic diagram of an exemplary solid-state driver having a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0062] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0063] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0064] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0065] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0066] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0067] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0068] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0069] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, processor speed is constrained by memory access speed, severely impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. To address these bottlenecks, in-memory computing chip architecture has emerged. Its basic idea is to embed computing functions within memory and directly utilize memory for logical calculations, thereby reducing the amount and distance of data transfer between memory and processor, lowering power consumption while improving computational performance. This promises to build high-performance, high-bandwidth, and high-energy-efficiency computing systems.

[0070] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by changing their electrical conductance, while computational capability refers to the ability to perform vector-matrix multiplication within a given time by constructing an array of memory devices and applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to, Static Random Access Memory (SRAM), NAND flash memory, and Dynamic Random Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied area of ​​interest in IMC chips. The following section will introduce NAND flash memory as an example.

[0071] Figure 1 A schematic diagram of a semiconductor device is provided as an example, using a three-dimensional NAND flash memory as an example for illustration. Figure 1 As shown, a storage array can include multiple storage planes, such as four storage planes: Plane0, Plane1, Plane2, and Plane3. Each storage plane includes multiple storage banks, and each storage bank includes multiple storage blocks.

[0072] Figure 2 An exemplary schematic diagram of the distribution of memory cells in a semiconductor device is provided. For example... Figure 2 As shown, the memory array consists of several rows of parallel, staggered memory cells parallel to the gate isolation structure. Every four rows of memory cells are separated by a gate isolation structure and a select gate isolation structure. Each row of memory cells includes multiple memory strings arranged along the X direction. The figure shows one memory cell in each memory string, with the remaining memory cells stacked with that cell along the Z direction. The select gate isolation structure can be a top select gate isolation structure, which divides the top select gate into multiple top select lines. Alternatively, it can be a bottom select gate isolation structure, which divides the bottom select gate into multiple bottom select lines. The gate isolation structure can include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple memory blocks, and multiple second gate isolation structures can divide the memory blocks into multiple finger regions. A select gate isolation structure placed in the middle of each finger region can divide the finger region into two parts, thus dividing the finger region into two memory chips. Figure 2The storage block shown contains 6 storage chips. In some embodiments, the number of storage chips in a storage block is not limited to this. Figure 2 The illustration only shows one memory block of a semiconductor device, but the semiconductor device includes multiple such... Figure 2 The memory blocks shown are separated by a first gate isolation structure, and multiple memory blocks can be arranged along the Y-axis.

[0073] It should be noted that, Figure 2 The number of cell rows between the gate isolation structure and the selected gate isolation structure given is merely an example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In some embodiments, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0074] Figure 3 This is a schematic diagram of an exemplary semiconductor device including peripheral circuitry, provided for embodiments of the present disclosure. The semiconductor device may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. Taking a three-dimensional NAND-type memory array as an example, the memory cells 306 are NAND memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically. In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0075] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0076] like Figure 3As shown, each memory string 308 may include a bottom select gate (BSG) 310 at its source end and a top select gate (TSG) 312 at its drain end. The bottom select gate 310 and top select gate 312 can be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the source ends of memory strings 308 within the same memory block 304 can be coupled via a common source line (CSL) 314. In other words, all memory strings 308 within the same memory block 304 have a common source (ACS). According to some embodiments, the top select gate 312 of each memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 312) or a deselection voltage (e.g., 0V) to the corresponding top select transistor 312 via one or more top select lines (TSL) 313 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 310) or a deselection voltage (e.g., 0V) to the corresponding bottom select transistor 310 via one or more bottom select lines (BSL) 315.

[0077] like Figure 3 As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314. In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage bias can be used to couple the common source line 314 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0078] Figure 4 A schematic cross-sectional view of an exemplary storage array including storage string 308 is shown, according to some aspects of this disclosure. Figure 4As shown, the stacked structure 410 includes a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 can be stacked alternately, and two adjacent gate layers 411 are separated by an insulating layer 412. The number of memory cells included in the memory array is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0079] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as a top select line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a bottom select line, and the gate layer 411 extending laterally between the top select line and the bottom select line may serve as a word line layer.

[0080] In some embodiments, the stacked structure 410 may be disposed on the semiconductor layer 401. The semiconductor layer 401 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In other embodiments, the semiconductor device may not include the semiconductor layer.

[0081] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0082] Return to reference Figure 3 Peripheral circuitry 302 can be coupled to memory array 301 via bit line 316, word line 318, source line 314, BSL315, and TSL313. The semiconductor devices can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 301 by applying voltage and / or current signals to and from each target memory cell 306 via bit line 316, word line 318, source line 314, BSL315, and TSL313. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0083] Figure 5A Schematic diagram of a semiconductor device provided in the embodiments of this disclosure Figure 1 Combined with reference Figure 3 and Figure 5A The peripheral circuit 302 may include control logic 512, and also includes a digital-to-analog converter (DAC) circuit 501 coupled to the control logic 512 and the memory array 301. The semiconductor device also includes a controller 520, an analog-to-digital converter (ADC) circuit 521 coupled to the memory array 301 and the controller 520, and a data processing circuit 522 coupled to the controller 520 and the ADC circuit 521. When performing a first operation using the memory array 301, the DAC circuit 501 can convert the digital signal into a voltage signal required by the memory array 301. The ADC circuit 521 can convert the current signal output by the memory array 301 into digital information. The data processing circuit 522 can perform a second operation on the digital information converted by the ADC circuit to obtain the operation result. The control logic 512 may be coupled to the peripheral circuit and configured to control the operation of the peripheral circuit. The controller 520 may be coupled to the ADC circuit 521 and the data processing circuit 522 and configured to control the operation of the data processing circuit 522 and the ADC circuit 521.

[0084] Figure 5B This is a schematic diagram of the composition of a semiconductor device provided in an embodiment of the present disclosure. The peripheral circuitry 302 may include a digital-to-analog converter circuit 501, a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface circuit 516, and a data bus 518. It should be understood that in some examples, it may also include... Figure 5B Additional peripheral circuitry is not shown. It should be noted that this is to further illustrate the connection relationship between the analog-to-digital converter circuit and the peripheral circuitry. Figure 5B The analog-to-digital converter circuit is shown in the diagram, but the peripheral circuit may not include the analog-to-digital converter circuit.

[0085] The digital-to-analog converter circuit 501 is connected to the control logic 512 and the voltage generator 510, and the analog-to-digital converter circuit 521 is connected to the column decoder / bit line driver 506.

[0086] When performing the first operation using the memory array 301, the control logic 512 can receive input data sent by an external device (e.g., a host). The digital-to-analog converter circuit 501 converts the input data into a voltage signal that needs to be applied to the word line, bit line, top select line, or bottom select line. The voltage generator 510 generates the corresponding voltage that needs to be applied to the word line, bit line, top select line, or bottom select line. The row decoder / word line driver 508 is configured to drive the selected word line, selected word top select line, or selected word bottom select line using the voltage generated from the voltage generator 510, or the column decoder / bit line driver 506 is configured to drive the selected bit line using the bit line voltage generated from the voltage generator 510. The analog calculation information obtained after performing the first operation is transmitted to the analog-to-digital converter circuit 521, which converts the analog calculation information into digital information and transmits the final digital information to the data processing circuit, which then performs the second operation on the digital information.

[0087] Control logic 512 can be implemented in and coupled to various parts of the peripheral circuit described above, and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcode (OP code), and command address for each operation of the peripheral circuit.

[0088] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data (write data) to be programmed into memory cell 306 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0089] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of memory array 301 and select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSL 315 and TSL 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc., input voltage), bit line voltages, and source line voltages to be supplied to memory array 301.

[0090] In some embodiments, for in-memory computing chips, it is necessary to perform a first operation between input data and a weight matrix. The input data can be an input vector or an input matrix composed of multiple elements, and the weight matrix is ​​composed of multiple weight data. Each element in the input data needs to be multiplied and added with the multiple weight data in the weight matrix to obtain the corresponding element in the output data.

[0091] To achieve the aforementioned computational functions, the storage array 301 can be configured to store a weight matrix. Specifically, weight data from the weight matrix can be written into the storage array 301 according to a certain mapping rule through programming operations. Storage cells 306 in the storage array 301 can be configured to store weight data. During the computation phase, the semiconductor device can receive input data from an external device. The input data can be an input vector or input matrix composed of multiple elements. Each element in the input data can be converted into an input voltage by a digital-to-analog converter circuit and input to the storage array 301 via bit line 316, word line 318, top select line 313, or bottom select line 315 to obtain analog computation information.

[0092] This embodiment of the disclosure takes the input voltage being input to the memory array 301 via the top select line 313 or the bottom select line 315 as an example for further explanation. In this embodiment of the disclosure, analog computation information can be output via bit lines or via the source terminals. That is, the bit lines of the semiconductor device are analog computation information output terminals, or the source terminals are analog computation information output terminals.

[0093] The following example illustrates the specific process of the first operation, with the input voltage being input to the storage array via the top selection line and the bit line serving as the output terminal for analog computational information.

[0094] In some specific examples, Figure 6 This is a schematic diagram illustrating the input voltage to the memory block via the top selection line, as provided in an embodiment of this disclosure. Figure 7 This is a schematic diagram illustrating multiple memory strings coupled to a bit line, provided in an embodiment of this disclosure. It should be noted that... Figure 6 and Figure 7 The number of bit lines, the number of memory strings coupled to each bit line, and the number of memory cells in each memory string shown are merely examples, and this disclosure does not limit the specific number of each structure.

[0095] like Figure 6 As shown, the input voltage corresponding to an element in the input data can be input via multiple top select lines. During the computation phase of the first operation using the memory array, the peripheral circuitry is configured to apply a second read voltage V to the target word line WLn coupled to the target memory block. rd2 Appropriate input voltages are applied to the multiple top select lines coupled to the target memory block. For example, input voltages V can be applied to the top select lines TSL0, TSL1, and TSL2 coupled to the target memory block. in0 V in1 V in2 A first on-state voltage is applied to a non-target word line coupled to the target memory block. For example, a first on-state voltage V can be applied to word line WLn+1. pass11 A second on-state voltage is applied to the bottom select line coupled to the target memory block; for example, a second on-state voltage V can be applied to the bottom select line BSL. pass22 Analog calculation information can be obtained by sensing the current on the bit line coupled to the target memory block. For example, by sensing the current I0 on bit line BL0 and converting the current I0, information related to the input voltage V can be obtained. in0 Corresponding elements and weights w 00 The product of the input voltage V in1 Corresponding elements and weights w 10 The product of the input voltage V in2 Corresponding elements and weights w 20 The sum of these three products. In some embodiments, the first operation includes a multiplication-accumulation operation.

[0096] In some embodiments, the peripheral circuitry is configured to apply a corresponding programming voltage to a target word line coupled to a target memory block to program the memory cell coupled to the target word line before performing a first operation using the memory array.

[0097] In a specific example, a memory cell in the target memory block is configured to store one bit of data. Multiple memory cells in the target memory block have a first memory state and a second memory state. The threshold voltage of a memory cell having the first memory state is less than the threshold voltage of a memory cell having the second memory state. The second read voltage V... rd2 The threshold voltage is greater than that of the memory cell with the first memory state and less than that of the memory cell with the second memory state. Here, the memory cell in the target memory block can be a single-level cell (SLC) storing one bit of data, the first memory state can be an erase state (E), and the second memory state can be a programmable state (P). The peripheral circuit can be configured to perform a programming operation on the memory cell coupled to the target word line before performing the first operation, writing weight data into the memory cell according to a certain mapping rule. For a single-level cell, the weight data writing process includes applying a corresponding programming voltage to adjust the threshold voltage of the portion of the memory cell coupled to the target word line to the range of the threshold voltage distribution corresponding to the second memory state.

[0098] In some embodiments, such as Figure 7 As shown, taking a target memory block comprising eight memory strings coupled to bit line BL0 as an example, four memory cells coupled to the target word line WLn are in the first memory state (erase state E), and the other four memory cells are in the second memory state (programming state P). Input data can be input from the eight top select lines TSL0 to TSL7. Specifically, the input data can be an input vector comprising eight elements, which can include five "1"s and three "0"s. The digital-to-analog converter circuit can convert each element of the input vector into a corresponding voltage signal, and the voltage signal is converted into an input voltage to be applied to the top select line by a voltage generator. The input voltage is then transmitted to the top select line by a driver coupled to the top select line. Specifically, the eight input voltages can be applied to the eight top select lines simultaneously. Among them, the input voltage corresponding to "1" includes V in0 V in1 V in4 V in5 and V in6 This allows the top selection transistors TSG0, TSG1, TSG4, TSG5, and TSG6, respectively coupled to the top selection lines TSL0, TSL1, TSL4, TSL5, and TSL6, to be turned on. The input voltages corresponding to "0" include V. in2 V in3 V in7 This can turn off the top select transistors TSG2, TSG3, and TSG7, which are coupled to the top select lines TSL2, TSL3, and TSL7, respectively.

[0099] In a specific example, such as Figure 7 As shown, the current I0 on bit line BL0 is the sum of the output currents of the eight memory strings coupled to bit line BL0. The input voltage on the top select line coupled to memory strings Str0, Str4 and Str5 causes the top select transistors TSG0, TSG4 and TSG5 to be in the on state. The memory cells in memory strings Str0, Str4 and Str5 coupled to the target word line WLn have the first memory state (erasure state E). Therefore, memory strings Str0, Str4 and Str5 are turned on and can generate a current greater than or equal to the preset current. The current I0 on bit line BL0 is basically equal to the sum of the output currents of memory strings Str0, Str4 and Str5. The multiple of current I0 relative to the current generated by any memory string in memory strings Str0, Str4 and Str5 is approximately 3. If the weight value stored in the memory cell in the first memory state is equivalent to "1", and the weight value stored in the memory cell in the second memory state is equivalent to "0", then the operation performed by the eight memory strings coupled to the bit line BL0 can be equivalent to: 1*1+1*0+0*1+0*0+1*1+1*1+1*0+0*0=3.

[0100] Based on the specific example above, when there are Y+1 memory strings coupled to bit lines BLx in the target memory block, the Y+1 elements corresponding to the input voltages input by the top selection lines of the Y+1 strings are α0, α1...α... Y The Y+1 memory cells coupled to the target word line WLn store weights w0, w1, ..., w1, respectively. Y Then, the analog calculation information equivalent to the current on bit line BLx relative to the multiple of the output current greater than or equal to the preset current can be α. 0* w0+α 1* w1+……+α Y* w Y .

[0101] In this embodiment of the present disclosure, when multiple memory banks are required to perform a first operation, a first conduction voltage can be applied to the non-target word lines in the multiple memory banks simultaneously. As a result, the voltage establishment phases of the first conduction voltage applied to the non-selection word lines coupled to different memory banks can overlap. Compared with the method of applying the first conduction voltage to the non-selection word lines coupled to different memory banks separately in different operation phases, the overall operation time can be shortened and the operation efficiency of performing the first operation using multiple memory banks can be improved.

[0102] Furthermore, for each memory bank, multiple memory blocks within that bank can be used simultaneously for the first operation. The peripheral circuitry can be configured to: apply a second read voltage to the target word lines coupled to each of the multiple memory blocks in the bank; apply corresponding input voltages to the multiple top select lines coupled to each of the multiple memory blocks in the bank; and sense the current on the bit lines coupled to the multiple memory blocks in the bank. Specifically, a second read voltage Vrd2 can be applied simultaneously to the target word lines coupled to each of the multiple memory blocks Block0 to BlockN in Bank0, and corresponding input voltages Vin can be applied to the multiple top select lines coupled to each of the multiple memory blocks Block0 to BlockN. The current on the bit lines is the analog calculation information after all memory strings coupled to that bit line have performed the first operation. Thus, multiple memory blocks can perform the first operation in parallel, thereby further improving the computational efficiency and power of the semiconductor device.

[0103] This disclosure provides a semiconductor device, with reference to... Figure 8 as well as Figure 9 The semiconductor device includes: a first semiconductor structure 101, a second semiconductor structure 102, and a third semiconductor structure 103 stacked along a first direction; the second semiconductor structure 102 is located between the third semiconductor structure 103 and the first semiconductor structure 101; wherein, the first semiconductor structure 101 includes an analog-to-digital conversion circuit 203 and a data processing circuit 204; the third semiconductor structure 103 includes a memory array 201 for performing a first operation, and the second semiconductor structure 102 includes peripheral circuitry 202 coupled to the memory array 201.

[0104] The first direction in this embodiment can be understood as the Z-axis direction in the attached drawings, the second direction can be understood as the X-axis direction in the attached drawings, and the third direction can be understood as the Y-axis direction in the attached drawings.

[0105] In this embodiment of the present disclosure, the first semiconductor structure 101 includes an analog-to-digital converter circuit 203 and a data processing circuit 204, the second semiconductor structure 102 includes a peripheral circuit 202, and the third semiconductor structure 103 includes a memory array 201 for performing a first operation. The second semiconductor structure 102 is located between the first semiconductor structure 101 and the third semiconductor structure 103. This allows a pad structure to be formed on the side of the third semiconductor structure 103 that is away from the second semiconductor structure 102 along the first direction, so that it is not necessary to form a conductive connection structure that penetrates the semiconductor layer 206 in the first semiconductor structure 101. This improves the impact on advanced logic devices such as the analog-to-digital converter circuit 203 and the data processing circuit 204 in the first semiconductor structure 101 when a conductive connection structure that penetrates the semiconductor layer 206 in the first semiconductor structure 101 is formed.

[0106] In this embodiment of the present disclosure, the first semiconductor structure 101, the second semiconductor structure 102 and the third semiconductor structure 103 are stacked along a first direction, thereby reducing the planar size of the semiconductor device.

[0107] In some embodiments, such as Figure 9 As shown, the third semiconductor structure 103 includes a pad layer 205; the pad layer 205 includes a plurality of pad structures, and the pad layer 205 is located on the side of the memory array 201 opposite to each other along the first direction, away from the second semiconductor structure 102.

[0108] In some embodiments, the material of the pad structure includes at least one of conductive materials, such as doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0109] In some embodiments, the pad structure can be used as an interface circuit between a semiconductor device and an external device.

[0110] In some embodiments, such as Figure 8 as well as Figure 9 As shown, the second semiconductor structure 102 further includes a semiconductor layer 206, a first conductive connection structure 207, and a second conductive connection structure 208; the first semiconductor structure 101 further includes a controller 209; the first conductive connection structure 207 is coupled to the peripheral circuit 202, and the second conductive connection structure 208 is coupled to the controller 209; part of the structure of the peripheral circuit 202 is located in the semiconductor layer 206; the first conductive connection structure 207 and the second conductive connection structure 208 both penetrate the semiconductor layer 206 along a first direction.

[0111] In some embodiments, the semiconductor layer 206 includes, but is not limited to, a substrate. The substrate material includes, but is not limited to, elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. The peripheral circuit 202 may include a plurality of CMOS transistors. The active regions of the CMOS transistors may be located in the semiconductor layer 206. The gate structure and gate dielectric layer of the CMOS transistors are located on one side of the semiconductor layer 206, and the gate dielectric layer is located between the gate structure and the active region.

[0112] In some embodiments, the materials of the first conductive connection structure 207, the second conductive connection structure 208, and other conductive connection structures described below include conductive materials, such as at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0113] In some embodiments, the semiconductor device includes a memory device and a first semiconductor structure 101. The memory device includes a second semiconductor structure 102 and a third semiconductor structure 103. A controller 209 can be configured to control the operation of the first semiconductor structure 101 and the memory device. That is, the controller 209 can act as a memory controller managing data storage and transmission in the memory device and an arithmetic controller managing data processing and transmission in the first semiconductor structure 101. In some embodiments, the controller 209 is also configured to control data transmission between the first semiconductor structure 101 and the memory device. In some embodiments, the controller 209 is also configured to receive input data sent by an external device and send the input data to the memory device.

[0114] In some embodiments, controller 209 is coupled to a memory device and an external device (e.g., a host). It is configured to control the memory device. Controller 209 can manage data stored in the memory device and communicate with the external device.

[0115] In some embodiments, controller 209 may also be configured to manage various functions relating to data stored or to be stored in a memory device, wherein these functions include, but are not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 209 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory device. In some embodiments, controller 209 may also perform any other suitable functions, such as formatting the memory device.

[0116] Figure 10 A partial cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. Figure 1 ; Figure 11 A partial cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. Figure 2 ; Figure 12 A partial cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. Figure 3 .

[0117] In some embodiments, such as Figure 10 , Figure 11 as well as Figure 12 As shown, the dimension D1 of the portion of the first conductive connection structure 207 near the third semiconductor structure 103 along the first direction along the second direction is smaller than the dimension D2 of the portion of the first conductive connection structure 207 near the first semiconductor structure 101 along the first direction along the second direction; the dimension D3 of the portion of the second conductive connection structure 208 near the third semiconductor structure 103 along the first direction along the second direction is smaller than the dimension D4 of the portion of the second conductive connection structure 208 near the first semiconductor structure 101 along the first direction along the second direction; the second direction is perpendicular to the first direction.

[0118] In some embodiments, the first conductive connection structure 207 and the second conductive connection structure 208 may be formed simultaneously. The first conductive connection structure 207 and the second conductive connection structure 208 may be formed from the second side of the semiconductor layer 206 along the first opposite sides in the first direction after the peripheral circuit 202 is formed on the first side of the semiconductor layer 206.

[0119] In some embodiments, such as Figure 9 , Figure 10 , Figure 11 as well as Figure 12As shown, the second semiconductor structure 102 further includes a first interconnect layer 210; the first interconnect layer 210 is located between the peripheral circuit 202 and the third semiconductor structure 103; the first interconnect layer 210 includes a first interconnect structure; the first conductive connection structure 207 is connected to the peripheral circuit 202 through the first interconnect structure.

[0120] In this embodiment of the disclosure, the first interconnect structure, and the second, third, fourth, and fifth interconnect structures described below, include, for example, laterally extending conductive lines and longitudinally extending conductive connection structures. The corresponding interconnect structures can be formed in one or more interlayer dielectric (ILD) layers. The corresponding interconnect structures can include conductive materials, including but not limited to at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The ILD layer in the corresponding interconnect layer can include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0121] In some embodiments, such as Figure 9 , Figure 10 , Figure 11 as well as Figure 12 As shown, the first interconnection structure includes a third conductive connection structure 211 extending along a first direction and a plurality of first conductive lines 212 extending along a third direction and arranged along a second direction; the two ends of the third conductive connection structure 211 opposite to each other along the first direction are respectively connected to the peripheral circuit 202 and the first conductive lines 212; the second direction, the first direction and the third direction are perpendicular to each other.

[0122] In some embodiments, such as Figure 9 as well as Figure 10 As shown, the first interconnect structure further includes a plurality of fourth conductive connection structures 213; one end of the fourth conductive connection structure 213 located between the first conductive connection structure 207 and the first conductive line 212 is connected to the first conductive connection structure 207 at one end and the corresponding first conductive line 212 at the other end; one end of the fourth conductive connection structure 213 located between the second conductive connection structure 208 and the first conductive line 212 is connected to the second conductive connection structure 208 at one end and the corresponding first conductive line 212 at the other end.

[0123] In some embodiments, the third conductive connection structure 211 and the fourth conductive connection structure 213 may be formed simultaneously.

[0124] In some embodiments, such as Figure 11As shown, both the first conductive connection structure 207 and the second conductive connection structure 208 extend into the first interconnect layer 210. One end of the first conductive connection structure 207, which is opposite to the first direction, is connected to the corresponding first conductive line 212. One end of the second conductive connection structure 208, which is opposite to the first direction, is connected to the corresponding first conductive line 212.

[0125] In some embodiments, such as Figure 12 As shown, the first interconnection structure further includes a plurality of second conductive lines 214 extending along a third direction and arranged along a second direction, and a plurality of fifth conductive connection structures 215; one end of the first conductive connection structure 207 is connected to the corresponding second conductive line 214 at one end of its two opposite ends along the first direction, and one end of the second conductive connection structure 208 is connected to the corresponding second conductive line 214 at one end of its two opposite ends along the first direction; one end of the fifth conductive connection structure 215 is connected to the corresponding first conductive line 212 at one end of its two opposite ends along the first direction, and the other end is connected to the corresponding second conductive line 214.

[0126] like Figure 12 As shown, the fifth conductive connection structure 215 extends along the first direction. The fifth conductive connection structure 215 is located between the first conductive line 212 and the second conductive line 214. The second conductive line 214 is located between the second conductive connection structure 208 and the fifth conductive connection structure 215, and the second conductive line 214 is located between the first conductive connection structure 207 and the fifth conductive connection structure 215.

[0127] In some embodiments, such as Figure 9 as well as Figure 13 As shown, the first semiconductor structure 101 and the second semiconductor structure 102 are bonded together, and the second semiconductor structure 102 is bonded together with the third semiconductor structure 103.

[0128] In some embodiments, the bonding connection includes a hybrid bonding connection (also known as a "metal / dielectric hybrid bonding connection"), a direct bonding technique, such as forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive, and simultaneously achieving metal-to-metal and dielectric-to-dielectric bonding. It should be noted that the term "bonding" as used in this disclosure can refer to any suitable bonding technique, such as the hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding mentioned above. The following description uses a hybrid bonding connection as an example.

[0129] In some embodiments, such as Figure 9 as well as Figure 13As shown, the third semiconductor structure 103 further includes a first bonding layer 216, and the second semiconductor structure 102 further includes a second bonding layer 217. The first bonding layer 216 and the second bonding layer 217 are located between the memory array 201 and the peripheral circuit 202. The first bonding layer 216 includes a first dielectric layer and a first bonding contact located in the first dielectric layer. The second bonding layer 217 includes a second dielectric layer and a second bonding contact located in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer, and the first bonding contact is bonded to the second bonding contact.

[0130] In this embodiment, the materials of the first dielectric layer, the second dielectric layer, and the third and fourth dielectric layers (described below) include, but are not limited to, silicon oxide and silicon nitride. The materials of the first bonding contact, the second bonding contact, and the third and fourth bonding contacts (described below) include conductive materials.

[0131] In some embodiments, the semiconductor device may further include a first bonding interface between the first bonding layer 216 and the second bonding layer 217, through which data transfer between the memory array 201 and the peripheral circuitry 202 can be achieved by interconnects (e.g., bonding contacts) across the first bonding interface.

[0132] In some embodiments, such as Figure 9 As shown, the third semiconductor structure 103 also includes a second interconnect layer 221 and a bit line 222; both the bit line 222 and the second interconnect layer 221 are located between the memory array 201 and the first bonding layer 216, and the bit line 222 is located between the memory array 201 and the second interconnect layer 221; the second interconnect layer 221 includes a second interconnect structure; the memory array 201 is connected to the peripheral circuit 202 through the bit line 222, the second interconnect structure, the first bonding contact, the second bonding contact, and the first interconnect structure.

[0133] In some embodiments, such as Figure 9 As shown, the third semiconductor structure 103 also includes a sixth conductive connection structure 223; the sixth conductive connection structure 223 extends through the memory array 201 along the first direction, and the sixth conductive connection structure 223 is connected to the second conductive connection structure 208 through the second interconnect structure, the first bonding contact, the second bonding contact, and the first interconnect structure.

[0134] In some embodiments, such as Figure 9 As shown, the third semiconductor structure 103 further includes a third interconnect layer 224; the third interconnect layer 224 includes a plurality of third interconnect structures; the third interconnect layer 224 is located between the pad layer 205 and the memory array 201; the sixth conductive connection structure 223 is connected to the first pad structure 227 of the plurality of pad structures through the corresponding third interconnect structure in the plurality of third interconnect structures.

[0135] In this embodiment of the disclosure, the sixth conductive connection structure 223 is connected to the first pad structure 227 of the plurality of pad structures through the corresponding third interconnect structure in the plurality of third interconnect structures, and the sixth conductive connection structure 223 is connected to the second conductive connection structure 208 through the second interconnect structure, the first bonding contact, the second bonding contact and the first interconnect structure, and the second conductive connection structure 208 is coupled to the controller 209, thereby enabling the controller 209 to communicate with external devices (e.g., host) through the first pad structure 227.

[0136] In some embodiments, such as Figure 9 As shown, the third semiconductor structure 103 also includes a source line 226, which is located between the memory array 201 and the third interconnect structure. The source line 226 is connected to the memory array 201, and the source line 226 is connected to the second pad structure 228 of the multiple pad structures through the corresponding third interconnect structure in the multiple third interconnect structures.

[0137] In some embodiments, such as Figure 9 As shown, the third semiconductor structure 103 further includes a seventh conductive connection structure 230; the seventh conductive connection structure 230 extends through the memory array 201 along the first direction, the seventh conductive connection structure 230 is connected to the memory array 201 through the second interconnect structure, and the seventh conductive connection structure 230 is connected to the third pad structure 229 of the multiple pad structures through the corresponding third interconnect structure of the multiple third interconnect structures.

[0138] In some embodiments, the seventh conductive connection structure 230 may also be connected to the peripheral circuit 202 of the second semiconductor structure 102 through the second interconnect structure in the second interconnect layer 221, the first bonding contact in the first bonding layer 216, the second bonding contact in the second bonding layer 217, and the first interconnect structure in the first interconnect layer 210.

[0139] In some embodiments, the controller 209 may include a portion of the memory controller structure that manages data storage and transmission in the memory device. Another portion of the memory controller structure may be external to the semiconductor device. The peripheral circuit 202 and the memory array 201 may interact with the other portion of the memory controller structure through the seven conductive connection structure 230 and the third pad structure 229.

[0140] In this embodiment of the disclosure, the first pad structure 227, the second pad structure 228, and the third pad structure 229 may be made of the same material, and the first pad structure 227, the second pad structure 228, and the third pad structure 229 may be formed simultaneously.

[0141] In some embodiments, such as Figure 9 as well as Figure 13As shown, the second semiconductor structure 102 further includes a fourth interconnect layer 231 and a third bonding layer 232; the first semiconductor structure 101 further includes a fifth interconnect layer 233 and a fourth bonding layer 234; the fourth interconnect layer 231, the third bonding layer 232, the fifth interconnect layer 233, and the fourth bonding layer 234 are all located between the analog-to-digital conversion circuit 203 and the peripheral circuit 202, and between the data processing circuit 204 and the peripheral circuit 202; the fourth interconnect layer 231 is located between the third bonding layer 232 and the peripheral circuit 202; the fifth interconnect layer 233... Layer 233 is located between the fourth bonding layer 234 and the analog-to-digital converter circuit 203, and between the fourth bonding layer 234 and the data processing circuit 204; the third bonding layer 232 includes a third dielectric layer and a third bonding contact located in the third dielectric layer, and the fourth bonding layer 234 includes a fourth dielectric layer and a fourth bonding contact located in the fourth dielectric layer; the third dielectric layer is bonded to the fourth dielectric layer, and the third bonding contact is bonded to the fourth bonding contact; the fourth interconnect layer 231 includes a fourth interconnect structure, and the fifth interconnect layer 233 includes a fifth interconnect structure.

[0142] In some embodiments, the semiconductor device may further include a second bonding interface between the third bonding layer 232 and the fourth bonding layer 234, through which data transmission between the first semiconductor structure 101 and the second semiconductor structure 102 can be achieved by interconnection (e.g., bonding contacts) across the second bonding interface.

[0143] In some embodiments, the first conductive connection structure 207 is connected to the analog-to-digital converter circuit 203 through a fourth interconnect structure, a third bonding contact, a fourth bonding contact, and a fifth interconnect structure.

[0144] In some embodiments, the analog-to-digital converter 203 is configured to convert the analog calculation information obtained by the storage array 201 performing a first operation into digital information; the data processing circuit 204 is configured to perform a second operation on the digital information to obtain the operation result.

[0145] In this embodiment, the storage array 201 is connected to the peripheral circuit 202 via bit line 222, a second interconnect structure, a first bonding contact, a second bonding contact, and the first interconnect structure. The peripheral circuit 202 is connected to the analog-to-digital converter (ADC) 203 via the first interconnect structure, a first conductive connection structure 207, a fourth interconnect structure, a third bonding contact, a fourth bonding contact, and a fifth interconnect structure. This allows the analog calculation information output by the storage array 201 after performing the first operation to be transmitted to the ADC 203. The ADC 203 converts the analog calculation information into digital information and transmits the final digital calculation information to the data processing circuit 204, which then performs a second operation on the digital information.

[0146] In some embodiments, the first operation includes a multiplication-accumulation operation.

[0147] In some embodiments, the second operation includes one or more of the following operations: compensation, activation, shifting, or pooling.

[0148] The pad structure in this embodiment is used to receive and transmit data between semiconductor devices and other external devices. Specifically, the pad structure can be used as an interface circuit, which is configured to transmit the result of the second operation performed by the data processing circuit 204 to the external device.

[0149] In some embodiments, the data processing circuit 204 includes a processor, which may include a dedicated processor, including but not limited to a CPU, GPU, digital signal processor (DSP), tensor processing unit (TPU), vision processing unit (VPU), neural processing unit (NPU), collaborative processing unit (SPU), physical processing unit (PPU), and image signal processor (ISP). In a specific example, the data processing circuit 204 is an NPU. The NPU can perform operations such as arithmetic / logic operations, rotation and shift operations, compensation operations, activation operations, and pooling operations.

[0150] In some embodiments, the second conductive connection structure 208 is connected to the controller 209 via a fourth interconnect structure, a third bonding contact, a fourth bonding contact, and a fifth interconnect structure.

[0151] In some embodiments, the memory array performs a first operation to generate a current signal on the corresponding bit line 222. The current signal is transmitted to a converter (e.g., a sense amplifier) ​​in the peripheral circuit 202 through the second interconnect structure in the second interconnect layer 221, the first bonding contact in the first bonding layer 216, the second bonding contact in the second bonding layer 217, and the first interconnect structure in the first interconnect layer 210. The converter converts the current signal into a voltage signal. The voltage signal is transmitted to the analog-to-digital converter circuit in the first semiconductor structure 101 through the fourth conductive connection structure 213, the first conductive connection structure 207, the fourth interconnect layer 231, the third bonding contact in the third bonding layer 232, the fourth bonding contact in the fourth bonding layer 234, and the fifth interconnect layer 233. The analog-to-digital converter circuit transmits the voltage signal to the data processing circuit in the first semiconductor structure 101. The data processing circuit performs a second operation on the voltage signal converted by the analog-to-digital converter circuit to obtain the operation result. The calculation results are transmitted to an external device (e.g., a host computer) through a structure similar to the second conductive connection structure 208, the fourth conductive connection structure 213, the sixth conductive connection structure 223, and the first pad structure 227.

[0152] In some embodiments, the storage array 201 includes a three-dimensional NAND-type storage array 201.

[0153] In the embodiments disclosed herein, the semiconductor device may be implemented as a general-purpose flash memory storage device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash memory (CF) card, a smart media card, or a memory stick, etc. Specifically, the above-mentioned semiconductor device can be used in terminal products such as computers, televisions, set-top boxes, and automotive devices.

[0154] The specific structure and other details of the semiconductor device are similar to those in the aforementioned semiconductor device, and will not be repeated here for the sake of brevity.

[0155] Based on the above semiconductor devices, such as Figure 14 as well as Figure 15 As shown, this disclosure also provides another semiconductor device, including: a second semiconductor structure 102 and a third semiconductor structure 103 stacked along a first direction; wherein, the third semiconductor structure 103 includes a memory array 201 for performing a first operation; the second semiconductor structure 102 includes peripheral circuitry 202 coupled to the memory array 201, and a third bonding layer 232 located on one side of the peripheral circuitry 202 opposite to each other along the first direction, away from the third semiconductor structure 103; the third bonding layer 232 is used for bonding with the first semiconductor structure, the first semiconductor structure including an analog-to-digital conversion circuit and a data processing circuit.

[0156] In some embodiments, such as Figure 15 As shown, the third semiconductor structure 103 includes a pad layer 205; the pad layer 205 includes a plurality of pad structures, and the pad layer 205 is located on the side of the memory array 201 opposite to each other along the first direction, away from the second semiconductor structure 102.

[0157] In some embodiments, such as Figure 15 As shown, the second semiconductor structure 102 further includes a semiconductor layer 206, a first conductive connection structure 207, and a second conductive connection structure 208; one end of the first conductive connection structure 207 opposite to each other along the first direction is coupled to the peripheral circuit 202, and the other end of the first conductive connection structure 207 opposite to each other along the first direction is used to couple to the analog-to-digital conversion circuit 203; the second conductive connection structure 208 is used to couple to the controller of the first semiconductor structure; part of the structure of the peripheral circuit 202 is located in the semiconductor layer 206; both the first conductive connection structure 207 and the second conductive connection structure 208 penetrate the semiconductor layer 206 along the first direction.

[0158] In some embodiments, such as Figure 15 As shown, the third semiconductor structure 103 also includes a sixth conductive connection structure 223; the sixth conductive connection structure 223 extends through the memory array 201 along the first direction, one end of the sixth conductive connection structure 223 along the first direction is coupled to the second conductive connection structure 208, and the other end of the sixth conductive connection structure 223 along the first direction is coupled to the first pad structure 227 of the plurality of pad structures.

[0159] In some embodiments, such as Figure 15 As shown, the third semiconductor structure 103 further includes a seventh conductive connection structure 230; the seventh conductive connection structure 230 extends through the memory array 201 along the first direction, one end of the seventh conductive connection structure 230 at opposite ends along the first direction is coupled to the memory array 201, and the other end of the seventh conductive connection structure 230 at opposite ends along the first direction is coupled to the third pad structure 229 among the multiple pad structures.

[0160] Here, the above Figure 14 as well as Figure 15 Other specific structures of the semiconductor device shown can be referred to the foregoing. Figures 8 to 13 The semiconductor device shown in the embodiment adopts all the technical solutions of all the above embodiments, and therefore has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.

[0161] Based on the above-described semiconductor device, this disclosure also provides a method for forming a semiconductor device. Figure 16 This is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of the present disclosure, as shown below. Figure 16 As shown, the method for forming a semiconductor device includes the following steps: Step S1000: forming a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure stacked along a first direction; the second semiconductor structure is located between the third semiconductor structure and the first semiconductor structure; the first semiconductor structure includes an analog-to-digital conversion circuit and a data processing circuit; the third semiconductor structure includes a memory array for performing a first operation; and the second semiconductor structure includes peripheral circuitry coupled to the memory array.

[0162] Figures 17 to 22 This is a schematic diagram of the fabrication process of the semiconductor device provided in the embodiments of this disclosure. Below, it will be discussed in conjunction with... Figures 17 to 22 The method for fabricating the semiconductor device provided in the embodiments of this disclosure will be described.

[0163] In some embodiments, forming a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure stacked along a first direction includes: forming the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure, respectively.

[0164] In some embodiments, forming the first semiconductor structure 101 includes: Figure 17 As shown, a first substrate 218 is provided, and an analog-to-digital conversion circuit, a data processing circuit, a controller, a fifth interconnect layer 233, and a fourth bonding layer 234 are formed on a first side of two opposite sides of the first substrate 218 along a first direction.

[0165] In some embodiments, forming the second semiconductor structure 102 includes: Figure 18 As shown, a semiconductor layer 206 is provided; a peripheral circuit 202 is formed from a first side of two opposing sides of the semiconductor layer 206 along a first direction; as... Figure 19 As shown, a first conductive connection structure 207 and a second conductive connection structure 208 are formed from the second side of two opposing sides along the first direction of the semiconductor layer 206, penetrating the semiconductor layer 206; the first conductive connection structure 207 is coupled to the peripheral circuit; and the second conductive connection structure 208 is coupled to the controller.

[0166] In some embodiments, forming the second semiconductor structure 102 further includes: Figure 18 As shown, a first interconnect layer 210 and a second bonding layer 217 are formed from the first side of two opposing sides of the semiconductor layer 206 along a first direction; as Figure 19 As shown, a fourth interconnect layer 231 and a third bonding layer 232 are formed from the second side of two opposite sides of the semiconductor layer 206 along the first direction.

[0167] In some embodiments, before forming the fourth interconnect layer 231 and the third bonding layer 232 from the second side of the two sides opposite each other in the first direction of the semiconductor layer 206, the semiconductor layer 206 may be thinned from the second side of the two sides opposite each other in the first direction.

[0168] In some embodiments, the semiconductor layer 206 may be thinned by at least one of chemical mechanical polishing (CMP) and etching processes.

[0169] In some embodiments, forming the third semiconductor structure 103 includes: Figure 20 As shown, a second substrate 219 is provided, and a memory array 201, a second interconnect layer 221, and a first bonding layer 216 are formed from a first side of two opposing sides of the second substrate 219 along a first direction; as Figure 21 As shown, a third interconnect layer 224 and a pad layer 205 are formed from the second side of two opposite sides of the second substrate 219 along the first direction.

[0170] In some embodiments, forming the third semiconductor structure 103 includes forming a pad layer 205; the pad layer 205 includes a plurality of pad structures, and the pad layer 205 is located on one side of the memory array 201 opposite to each other along a first direction, away from the second semiconductor structure 102.

[0171] In some embodiments, forming a semiconductor device further includes: Figure 22 As shown, after forming the first semiconductor structure 101, the second semiconductor structure 102, and the third semiconductor structure 103, the second bonding layer 217 of the second semiconductor structure 102 is bonded to the first bonding layer 216 of the third semiconductor structure 103, and the third bonding layer 232 of the second semiconductor structure 102 is bonded to the fourth bonding layer 234 of the first semiconductor structure 101, thereby making the second semiconductor structure 102 bonded to the first semiconductor structure 101 and the third semiconductor structure 103 respectively, and making the first semiconductor structure 101, the second semiconductor structure 102, and the third semiconductor structure 103 stacked along the first direction.

[0172] In this embodiment of the disclosure, the first semiconductor structure 101, the second semiconductor structure 102, and the third semiconductor structure 103 can be formed in parallel.

[0173] Based on the above-described semiconductor device, this disclosure also provides a method for forming a semiconductor device. Figure 23 A schematic flowchart illustrating another method for forming a semiconductor device according to an embodiment of this disclosure is shown below. Figure 23 As shown, the method for forming a semiconductor device includes the following steps: Step S2000: forming a second semiconductor structure and a third semiconductor structure stacked along a first direction; the third semiconductor structure includes a memory array for performing a first operation; the second semiconductor structure includes peripheral circuitry coupled to the memory array, and a third bonding layer located on one side of the peripheral circuitry opposite to each other along the first direction, away from the third semiconductor structure; the third bonding layer is used for bonding with a first semiconductor structure, the first semiconductor structure including an analog-to-digital conversion circuit and a data processing circuit.

[0174] The method for forming the semiconductor device described above is similar to the method for forming the semiconductor device described above, and can be referred to the method for forming the semiconductor device described above. For the sake of brevity, it will not be described again here.

[0175] Based on the above-described semiconductor device, this disclosure also provides a packaging structure. Figure 24 This is a schematic diagram of a packaging structure provided in an embodiment of the present disclosure, as shown below. Figure 24 As shown, the packaging structure 600 includes: a packaging substrate 602, a semiconductor device 601 of any of the above embodiments, and a molding compound 603; the semiconductor device 601 is disposed on the packaging substrate 602; and the molding compound 603 encapsulates the semiconductor device 601.

[0176] In some embodiments, such as Figure 24 As shown, the packaging substrate 602 includes a substrate 605 and a redistribution layer 604 formed on the substrate. A connection circuit is formed in the redistribution layer 604, and a semiconductor device 601 is disposed on the side of the redistribution layer 604 away from the substrate 605.

[0177] Based on the above-described semiconductor devices, embodiments of this disclosure provide an electronic device. Figure 25 A schematic diagram of an exemplary electronic device having semiconductor devices provided in embodiments of this disclosure, such as... Figure 25 As shown, the electronic device 700 includes a semiconductor device 702 as described in any of the above embodiments.

[0178] In some embodiments, such as Figure 25 As shown, the electronic device 700 also includes a host 701 coupled to the semiconductor device 702.

[0179] In this disclosure, the electronic device 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 25 As shown, electronic device 700 may include host 701 and semiconductor device 702. Semiconductor device 702 may include one or more memory devices 703 and memory controller 704. Host 701 may include a processor of electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). Host 701 may be configured to send data to or receive data from semiconductor device 702. Memory device 703 includes a memory array and peripheral circuitry coupled to the memory array. The memory controller 704 may be a controller as described in the embodiment of the semiconductor device.

[0180] In some embodiments, memory controller 704 is coupled to memory device 703 and host 701 and is configured to control memory device 703. Memory controller 704 can manage data stored in memory device 703 and communicate with host 701. In some embodiments, memory controller 704 is designed to operate in low duty cycle environments, such as in secure digital cards, compact flash cards (CFC), universal serial bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 704 is designed to operate in high duty cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0181] In some embodiments, the memory controller 704 and one or more memory devices 703 can be integrated into various types of storage devices, that is, the semiconductor device 702 can be implemented and packaged into different types of end electronic products.

[0182] In such Figure 26 In one example shown, the memory controller 704 and a single memory device 703 can be integrated into a memory card 801. The memory card 801 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 801 may also include a connection between the memory card 801 and a host device (e.g., Figure 25 The host 701 in the memory card connector 802 is coupled to the host computer. In such a way... Figure 27 In another example shown, the memory controller 704 and multiple memory devices 703 can be integrated into the SSD 803. The SSD 803 may also include components for connecting the SSD 803 to host devices (e.g., ...). Figure 25 The SSD connector 804 is coupled to the host 701. In some embodiments, the storage capacity and / or operating speed of the SSD 803 is greater than the storage capacity and / or operating speed of the memory card 801.

[0183] It should be understood that the phrases "some embodiments" or "embodiments of this disclosure" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "embodiments of this disclosure" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0184] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor structure, a second semiconductor structure, and a third semiconductor structure stacked along a first direction; The second semiconductor structure is located between the third semiconductor structure and the first semiconductor structure; The first semiconductor structure includes an analog-to-digital conversion circuit and a data processing circuit; the third semiconductor structure includes a memory array for performing a first operation; and the second semiconductor structure includes peripheral circuitry coupled to the memory array.

2. The semiconductor device according to claim 1, characterized in that, The third semiconductor structure includes a pad layer; the pad layer includes a plurality of pad structures, and the pad layer is located on the side of the memory array opposite each other along the first direction that is away from the second semiconductor structure.

3. The semiconductor device according to claim 2, characterized in that, The second semiconductor structure further includes a semiconductor layer, a first conductive connection structure, and a second conductive connection structure; the first semiconductor structure further includes a controller; the first conductive connection structure is coupled to the peripheral circuit, and the second conductive connection structure is coupled to the controller; a portion of the peripheral circuit is located in the semiconductor layer; both the first conductive connection structure and the second conductive connection structure penetrate the semiconductor layer along the first direction.

4. The semiconductor device according to claim 3, characterized in that, The dimension of the portion of the first conductive connection structure near the third semiconductor structure along the first direction along the second direction is smaller than the dimension of the portion of the first conductive connection structure near the first semiconductor structure along the first direction along the second direction. The dimension of the portion of the second conductive connection structure near the third semiconductor structure along the first direction along the second direction is smaller than the dimension of the portion of the second conductive connection structure near the first semiconductor structure along the second direction along the second direction. The second direction is perpendicular to the first direction.

5. The semiconductor device according to claim 3, characterized in that, The second semiconductor structure further includes a first interconnect layer; the first interconnect layer is located between the peripheral circuit and the third semiconductor structure; the first interconnect layer includes a first interconnect structure; the first conductive connection structure is connected to the peripheral circuit through the first interconnect structure.

6. The semiconductor device according to claim 5, characterized in that, The first interconnect structure includes a third conductive connection structure extending along the first direction and a plurality of first conductive lines extending along a third direction and arranged along the second direction; the two ends of the third conductive connection structure opposite to each other along the first direction are respectively connected to the peripheral circuit and the first conductive lines; the second direction, the first direction and the third direction are perpendicular to each other.

7. The semiconductor device according to claim 6, characterized in that, Both the first conductive connection structure and the second conductive connection structure extend into the first interconnect layer. One end of the first conductive connection structure at opposite ends along the first direction is connected to the corresponding first conductive line, and one end of the second conductive connection structure at opposite ends along the first direction is connected to the corresponding first conductive line.

8. The semiconductor device according to claim 6, characterized in that, The first interconnect structure further includes a plurality of fourth conductive connection structures; one end of one of the four fourth conductive connection structures located between the first conductive connection structure and the first conductive line is connected to the first conductive connection structure along the first direction, and the other end is connected to the corresponding first conductive line. One end of the fourth conductive connection structure located between the second conductive connection structure and the first conductive line is connected to the second conductive connection structure along the first direction, and the other end is connected to the corresponding first conductive line.

9. The semiconductor device according to claim 6, characterized in that, The first interconnect structure further includes a plurality of second conductive lines extending along the third direction and arranged along the second direction, and a plurality of fifth conductive connection structures; one end of the first conductive connection structure at opposite ends along the first direction is connected to the corresponding second conductive line, and one end of the second conductive connection structure at opposite ends along the first direction is connected to the corresponding second conductive line; one end of the fifth conductive connection structure at opposite ends along the first direction is connected to the corresponding first conductive line, and the other end is connected to the corresponding second conductive line.

10. The semiconductor device according to claim 5, characterized in that, The first semiconductor structure and the second semiconductor structure are bonded together, and the second semiconductor structure is bonded together with the third semiconductor structure.

11. The semiconductor device according to claim 10, characterized in that, The third semiconductor structure further includes a first bonding layer, and the second semiconductor structure further includes a second bonding layer. The first bonding layer and the second bonding layer are located between the memory array and the peripheral circuit. The first bonding layer includes a first dielectric layer and a first bonding contact located in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second bonding contact located in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer, and the first bonding contact is bonded to the second bonding contact.

12. The semiconductor device according to claim 11, characterized in that, The third semiconductor structure further includes a second interconnect layer and a bit line; the bit line and the second interconnect layer are both located between the memory array and the first bonding layer, and the bit line is located between the memory array and the second interconnect layer; the second interconnect layer includes a second interconnect structure; the memory array is connected to the peripheral circuit through the bit line, the second interconnect structure, the first bonding contact, the second bonding contact, and the first interconnect structure.

13. The semiconductor device according to claim 12, characterized in that, The third semiconductor structure further includes a sixth conductive connection structure; the sixth conductive connection structure extends through the memory array along the first direction, and the sixth conductive connection structure is connected to the second conductive connection structure through the second interconnect structure, the first bonding contact, the second bonding contact, and the first interconnect structure.

14. The semiconductor device according to claim 13, characterized in that, The third semiconductor structure further includes a third interconnect layer; the third interconnect layer includes a plurality of third interconnect structures; the third interconnect layer is located between the pad layer and the memory array; the sixth conductive connection structure is connected to the first pad structure among the plurality of pad structures through a corresponding third interconnect structure among the plurality of third interconnect structures.

15. The semiconductor device according to claim 14, characterized in that, The third semiconductor structure further includes a source line located between the memory array and the third interconnect structure. The source line is connected to the memory array and is connected to a second pad structure among the multiple pad structures through a corresponding third interconnect structure.

16. The semiconductor device according to claim 14, characterized in that, The third semiconductor structure further includes a seventh conductive connection structure; the seventh conductive connection structure extends through the memory array along the first direction, the seventh conductive connection structure is connected to the memory array through the second interconnect structure, and the seventh conductive connection structure is connected to the third pad structure among the multiple pad structures through the corresponding third interconnect structure among the multiple third interconnect structures.

17. The semiconductor device according to claim 3, characterized in that, The second semiconductor structure further includes a fourth interconnect layer and a third bonding layer; the first semiconductor structure further includes a fifth interconnect layer and a fourth bonding layer; the fourth interconnect layer, the third bonding layer, the fifth interconnect layer, and the fourth bonding layer are all located between the analog-to-digital conversion circuit and the peripheral circuit, and between the data processing circuit and the peripheral circuit; the fourth interconnect layer is located between the third bonding layer and the peripheral circuit; the fifth interconnect layer is located between the fourth bonding layer and the analog-to-digital conversion circuit, and between the fourth bonding layer and the data processing circuit; The third bonding layer includes a third dielectric layer and a third bonding contact located in the third dielectric layer; the fourth bonding layer includes a fourth dielectric layer and a fourth bonding contact located in the fourth dielectric layer; the third dielectric layer is bonded to the fourth dielectric layer, and the third bonding contact is bonded to the fourth bonding contact; the fourth interconnect layer includes a fourth interconnect structure, and the fifth interconnect layer includes a fifth interconnect structure.

18. The semiconductor device according to claim 17, characterized in that, The first conductive connection structure is connected to the analog-to-digital conversion circuit through the fourth interconnect structure, the third bonding contact, the fourth bonding contact, and the fifth interconnect structure.

19. The semiconductor device according to claim 17, characterized in that, The second conductive connection structure is connected to the controller through the fourth interconnect structure, the third bonding contact, the fourth bonding contact, and the fifth interconnect structure.

20. The semiconductor device according to claim 1, characterized in that, The analog-to-digital conversion circuit is configured to convert the analog computation information obtained by the storage array performing the first operation into digital information; the data processing circuit is configured to perform a second operation on the digital information.

21. The semiconductor device according to claim 1, characterized in that, The first operation includes multiplication and addition operations.

22. The semiconductor device according to claim 20, characterized in that, The second operation includes one or more of the following operations: compensation, activation, shift, or pooling.

23. The semiconductor device according to claim 1, characterized in that, The storage array includes a three-dimensional NAND type storage array.

24. A semiconductor device, characterized in that, include: A second semiconductor structure and a third semiconductor structure stacked along a first direction; The third semiconductor structure includes a memory array for performing the first operation; The second semiconductor structure includes peripheral circuitry coupled to the memory array, and a third bonding layer located on one side of the peripheral circuitry opposite to the third semiconductor structure along the first direction; the third bonding layer is used for bonding with the first semiconductor structure, which includes analog-to-digital conversion circuitry and data processing circuitry.

25. The semiconductor device according to claim 24, characterized in that, The third semiconductor structure includes a pad layer; the pad layer includes a plurality of pad structures, and the pad layer is located on the side of the memory array opposite each other along the first direction that is away from the second semiconductor structure.

26. The semiconductor device according to claim 25, characterized in that, The second semiconductor structure further includes a semiconductor layer, a first conductive connection structure, and a second conductive connection structure; one end of the first conductive connection structure opposite to each other along the first direction is coupled to the peripheral circuit, and the other end of the first conductive connection structure opposite to each other along the first direction is used to couple to the analog-to-digital conversion circuit; the second conductive connection structure is used to couple to the controller of the first semiconductor structure; a portion of the peripheral circuit structure is located in the semiconductor layer; Both the first conductive connection structure and the second conductive connection structure penetrate the semiconductor layer along the first direction.

27. The semiconductor device according to claim 26, characterized in that, The third semiconductor structure further includes a sixth conductive connection structure; the sixth conductive connection structure extends through the memory array along the first direction, one end of the sixth conductive connection structure at opposite ends along the first direction is coupled to the second conductive connection structure, and the other end of the sixth conductive connection structure at opposite ends along the first direction is coupled to the first pad structure among the plurality of pad structures.

28. The semiconductor device according to claim 25, characterized in that, The third semiconductor structure further includes a seventh conductive connection structure; the seventh conductive connection structure extends through the memory array along the first direction, one end of the seventh conductive connection structure at opposite ends along the first direction is coupled to the memory array, and the other end of the seventh conductive connection structure at opposite ends along the first direction is coupled to a third pad structure among the plurality of pad structures.

29. A packaging structure, characterized in that, include: The packaging substrate, the semiconductor device according to any one of claims 1-28, and the molding layer; The semiconductor device is disposed on the packaging substrate; The molding compound encapsulates the semiconductor device.

30. An electronic device, characterized in that, include: The semiconductor device according to any one of claims 1-28.

31. A method for forming a semiconductor device, characterized in that, include: A first semiconductor structure, a second semiconductor structure, and a third semiconductor structure are formed and stacked along a first direction; The second semiconductor structure is located between the third semiconductor structure and the first semiconductor structure; the first semiconductor structure includes an analog-to-digital converter circuit and a data processing circuit. The third semiconductor structure includes a memory array for performing the first operation, and the second semiconductor structure includes peripheral circuitry coupled to the memory array.

32. The forming method according to claim 31, characterized in that, The formation of the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure stacked along the first direction includes: The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are formed respectively; The second semiconductor structure is bonded to the first semiconductor structure and the third semiconductor structure, respectively.

33. The forming method according to claim 31, characterized in that, Forming the third semiconductor structure includes: forming a pad layer; the pad layer includes a plurality of pad structures, the pad layer being located on one side of the memory array opposite each other along the first direction, away from the second semiconductor structure.

34. The forming method according to claim 33, characterized in that, Forming the second semiconductor structure includes: Provides a semiconductor layer; The peripheral circuit is formed from the first side of two opposing sides of the semiconductor layer along the first direction; A first conductive connection structure and a second conductive connection structure are formed from the second side of two opposite sides of the semiconductor layer along the first direction, penetrating the semiconductor layer; the first conductive connection structure is coupled to the peripheral circuit. Forming the first semiconductor structure includes forming a controller; the second conductive connection structure is coupled to the controller.

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