Semiconductor device and method of manufacturing the same, package structure, and electronic device

Abstract

Embodiments of the present disclosure disclose a semiconductor device, a manufacturing method thereof, a packaging structure and an electronic device. The semiconductor device comprises: a first semiconductor structure, a second semiconductor structure and a third semiconductor structure stacked in sequence along a first direction; the first semiconductor structure comprises an analog-to-digital conversion circuit and an interface circuit, the second semiconductor structure comprises a storage array, and the third semiconductor structure comprises a peripheral circuit, the peripheral circuit being coupled to the storage array and the analog-to-digital conversion circuit respectively; the analog-to-digital conversion circuit is configured to receive analog information obtained by the storage array performing an operation; wherein the first semiconductor structure further comprises a pad coupled to the interface circuit, the pad being located on a side away from the second semiconductor structure among two sides opposite to each other of the analog-to-digital conversion circuit along the first direction; or the third semiconductor structure further comprises a pad coupled to the interface circuit, the pad being located on a side far away from the second semiconductor structure among two sides opposite to each other of the peripheral circuit along the first direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor device and its fabrication method, and a memory system. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing instructions, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, processor speed is constrained by memory access speed, severely impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data is making the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure stacked sequentially along a first direction; the first semiconductor structure includes an analog-to-digital converter (ADC) circuit and an interface circuit; the second semiconductor structure includes a memory array; the third semiconductor structure includes peripheral circuitry, the peripheral circuitry being coupled to the memory array and the ADC circuitry respectively; the ADC circuitry is configured to receive analog information obtained by the memory array performing operations; wherein the first semiconductor structure further includes pads coupled to the interface circuitry, the pads being located on one side of the ADC circuitry opposite to each other along the first direction, away from the second semiconductor structure; or the third semiconductor structure further includes pads coupled to the interface circuitry, the pads being located on one side of the peripheral circuitry opposite to each other along the first direction, away from the second semiconductor structure.

[0004] In some embodiments, the first semiconductor structure further includes a first semiconductor layer; the first semiconductor layer is located between the pad and the second semiconductor structure, and portions of the analog-to-digital conversion circuit and the interface circuit are both located in the first semiconductor layer.

[0005] In some embodiments, the first semiconductor structure further includes a first dielectric structure, a first conductive structure, and a second conductive structure; the first dielectric structure is located between the first semiconductor layer and the second semiconductor structure, and the first conductive structure and the second conductive structure are both located in the first dielectric structure; wherein the pads are coupled to the interface circuit through the first conductive structure, and the peripheral circuits are coupled to the analog-to-digital conversion circuit through the second conductive structure.

[0006] In some embodiments, the first semiconductor structure further includes a first connection structure; the first connection structure extends through the first semiconductor layer along the first direction; wherein the first connection structure connects the pad and the first conductive structure at opposite ends along the first direction, respectively.

[0007] In some embodiments, the first dielectric structure includes a first dielectric layer and a first interconnect dielectric layer; the first dielectric layer is located between the first semiconductor layer and the first interconnect dielectric layer, and the first interconnect dielectric layer is located between the first dielectric layer and the second semiconductor structure; the first conductive structure includes a first contact structure and a first interconnect structure; the first contact structure extends through the first dielectric layer along the first direction, and the first interconnect structure is located in the first interconnect dielectric layer; wherein, the opposite ends of the first contact structure along the first direction are respectively connected to the first connection structure and the first interconnect structure; the second conductive structure includes a second contact structure and a second interconnect structure; the second contact structure extends through the first dielectric layer along the first direction, and the second interconnect structure is located in the first interconnect dielectric layer; wherein, the opposite ends of the second contact structure along the first direction are respectively connected to the analog-to-digital conversion circuit and the second interconnect structure.

[0008] In some embodiments, the first semiconductor structure further includes a first dielectric structure, a first conductive structure, and a second conductive structure; the first dielectric structure is located between the pad and the first semiconductor layer, and the first conductive structure and the second conductive structure are both located in the first dielectric structure; wherein the pad is coupled to the interface circuit through the first conductive structure, and the peripheral circuit is coupled to the analog-to-digital conversion circuit through the second conductive structure.

[0009] In some embodiments, the first semiconductor structure further includes a first connection structure; the first connection structure extends through the first semiconductor layer along the first direction; wherein the peripheral circuit is coupled to the second conductive structure through the first connection structure.

[0010] In some embodiments, the first dielectric structure includes a first dielectric layer and a first interconnect dielectric layer; the first dielectric layer is located between the first semiconductor layer and the first interconnect dielectric layer, and the first interconnect dielectric layer is located between the first dielectric layer and the pad; the first conductive structure includes a first contact structure and a first interconnect structure; the first contact structure extends through the first dielectric layer along the first direction, and the first interconnect structure is located in the first interconnect dielectric layer; wherein the pad connects to the first interconnect structure, and the opposite ends of the first contact structure along the first direction are respectively connected to the first interconnect structure and the interface circuit; the second conductive structure includes a second contact structure, a third contact structure, and a conductive line; both the second contact structure and the third contact structure extend through the first dielectric layer along the first direction, and the conductive line is located in the first interconnect dielectric layer; wherein the opposite ends of the second contact structure along the first direction are respectively connected to the analog-to-digital conversion circuit and the conductive line, and the opposite ends of the third contact structure along the first direction are respectively connected to the first connection structure and the conductive line.

[0011] In some embodiments, the first semiconductor structure further includes a second connection structure and a controller; the second connection structure extends through the first semiconductor layer along the first direction, and a portion of the controller is located in the first semiconductor layer; wherein the peripheral circuitry is coupled to the controller via the second connection structure.

[0012] In some embodiments, the second semiconductor structure further includes a second semiconductor layer, a second dielectric structure, a third conductive structure, and a third connection structure; the second semiconductor layer is located between the first semiconductor structure and the second dielectric structure, the second dielectric structure covers the stepped region of the memory array, the third conductive structure is located in the second dielectric structure, and the third connection structure extends through the second semiconductor layer along the first direction; wherein the peripheral circuit is coupled to the analog-to-digital conversion circuit through the third conductive structure and the third connection structure.

[0013] In some embodiments, the first semiconductor structure further includes a controller; a portion of the controller is located in the first semiconductor layer; the second semiconductor structure further includes a fourth conductive structure and a fourth connection structure; the fourth conductive structure is located in the second dielectric structure, and the fourth connection structure extends through the second semiconductor layer along the first direction; wherein the controller is coupled to the peripheral circuit through the fourth connection structure and the fourth conductive structure.

[0014] In some embodiments, the second semiconductor structure further includes a fifth conductive structure and a fifth connection structure; the fifth conductive structure is located in the second dielectric structure, and the fifth connection structure extends through the second semiconductor layer along the first direction; wherein the controller is also coupled to the peripheral circuit through the fifth connection structure and the fifth conductive structure; the fifth connection structure and the fourth connection structure are respectively used to transmit different control signals.

[0015] In some embodiments, the second semiconductor structure further includes a sixth conductive structure and a sixth connection structure; the sixth conductive structure is located in the second dielectric structure, and the sixth connection structure extends through the second semiconductor layer along the first direction; the third semiconductor structure further includes a third semiconductor layer, a third dielectric structure, a seventh conductive structure, and a seventh connection structure; the third semiconductor layer is located between the pad and the third dielectric structure, and a portion of the peripheral circuit is located in the third semiconductor layer; the third dielectric structure is located between the third semiconductor layer and the second semiconductor structure, and the seventh conductive structure is located in the third dielectric structure; the seventh connection structure extends through the third semiconductor layer along the first direction; wherein the pad is coupled to the interface circuit through the seventh connection structure, the seventh conductive structure, the sixth conductive structure, and the sixth connection structure.

[0016] In some embodiments, the second semiconductor structure further includes a bit line coupled to the memory array, the bit line being located between the memory array and the third semiconductor structure; the third semiconductor structure further includes an eighth conductive structure; the eighth conductive structure is located in the third dielectric structure; wherein the peripheral circuit is coupled to the bit line through the eighth conductive structure.

[0017] In some embodiments, the first semiconductor structure further includes a first dielectric structure and a ninth conductive structure; the first dielectric structure is located between the pad and the second semiconductor structure, and the ninth conductive structure is located in the first dielectric structure; the second semiconductor structure further includes a source line coupled to the memory array, the source line being located between the memory array and the first semiconductor structure; wherein the ninth conductive structure is coupled to the source line and the analog-to-digital conversion circuit respectively, and the analog calculation result is transmitted to the analog-to-digital conversion circuit through the source line and the ninth conductive structure.

[0018] In some embodiments, a first side of the second semiconductor structure is bonded to the first semiconductor structure, and a second side of the second semiconductor structure is bonded to the third semiconductor structure; wherein the first side and the second side of the second semiconductor structure are opposite to each other along the first direction.

[0019] In some embodiments, the storage array includes a three-dimensional NAND-type storage array.

[0020] According to a second aspect of the present disclosure, another semiconductor device is provided, comprising: a first semiconductor structure and a second semiconductor structure stacked sequentially along a first direction; the first semiconductor structure includes a memory array and a bonding layer; the bonding layer is located on one side of the memory array opposite to each other along the first direction, away from the second semiconductor structure; the second semiconductor structure includes peripheral circuitry and pads; the peripheral circuitry is coupled to the memory array; wherein the pads are located on one side of the peripheral circuitry opposite to each other along the first direction, away from the first semiconductor structure; the pads are used to output the computation results obtained by the memory array performing operations.

[0021] In some embodiments, the first semiconductor structure further includes a first semiconductor layer, a first dielectric structure, a first conductive structure, and a first connection structure; the first semiconductor layer is located between the first bonding layer and the first dielectric structure, the first dielectric structure covers the stepped region of the memory array, the first conductive structure is located in the first dielectric structure, and the first connection structure extends through the first semiconductor layer along the first direction; wherein the peripheral circuit is coupled to the first connection structure through the first conductive structure, and the first connection structure is used to transmit analog information obtained by the memory array performing operations.

[0022] In some embodiments, the first semiconductor structure further includes a second conductive structure and a second connection structure; the second conductive structure is located in the first dielectric structure, and the second connection structure extends through the first semiconductor layer along the first direction; wherein the peripheral circuit is coupled to the second connection structure through the second conductive structure, and the second connection structure is used to transmit a first control signal.

[0023] In some embodiments, the first semiconductor structure further includes a third conductive structure and a third connection structure; the third conductive structure is located in the first dielectric structure, and the third connection structure extends through the first semiconductor layer along the first direction; wherein the peripheral circuit is coupled to the third connection structure through the third conductive structure, and the third connection structure is used to transmit a second control signal different from the first control signal.

[0024] In some embodiments, the first semiconductor structure further includes a fourth conductive structure and a fourth connection structure; the fourth conductive structure is located in the first dielectric structure, and the fourth connection structure extends through the first semiconductor layer along the first direction; the second semiconductor structure further includes a second semiconductor layer, a second dielectric structure, a fifth conductive structure, and a fifth connection structure; the second semiconductor layer is located between the pad and the second dielectric structure, and a portion of the peripheral circuit is located in the second semiconductor layer; the second dielectric structure is located between the second semiconductor layer and the first semiconductor structure, and the fifth conductive structure is located in the second dielectric structure; the fifth connection structure extends through the second semiconductor layer along the first direction; wherein the pad is connected to the fourth connection structure through the fifth connection structure, the fifth conductive structure, and the fourth conductive structure.

[0025] In some embodiments, the first semiconductor structure further includes a bit line coupled to the memory array, the bit line being located between the memory array and the second semiconductor structure; the second semiconductor structure further includes a sixth conductive structure; the sixth conductive structure is located in the second dielectric structure; wherein the peripheral circuit is coupled to the bit line through the sixth conductive structure.

[0026] In some embodiments, the bonding layer includes a bonding medium layer and bonding contacts, the bonding contacts extending through the bonding medium layer along the first direction.

[0027] In some embodiments, the storage array includes a three-dimensional NAND-type storage array.

[0028] According to a third aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising: forming a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure stacked sequentially along a first direction; wherein the first semiconductor structure includes an analog-to-digital converter (ADC) circuit and an interface circuit, the second semiconductor structure includes a memory array, and the third semiconductor structure includes peripheral circuitry, the peripheral circuitry being coupled to the memory array and the ADC circuitry respectively; the ADC circuitry is configured to receive analog information obtained by the memory array performing operations; the first semiconductor structure further includes pads coupled to the interface circuitry, the pads being located on one side of the ADC circuitry opposite to each other along the first direction, away from the second semiconductor structure; or the third semiconductor structure further includes pads coupled to the interface circuitry, the pads being located on one side of the peripheral circuitry opposite to each other along the first direction, away from the second semiconductor structure.

[0029] In some embodiments, forming a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure stacked sequentially along a first direction includes: forming the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure respectively; bonding a first side of the second semiconductor structure to the first semiconductor structure, and bonding a second side of the second semiconductor structure to the third semiconductor structure; wherein the first side of the second semiconductor structure and the second side of the second semiconductor structure are opposite to each other along the first direction.

[0030] In some embodiments, forming the first semiconductor structure includes: forming the interface circuit and the analog-to-digital conversion circuit based on a first semiconductor layer; wherein a portion of the analog-to-digital conversion circuit and a portion of the interface circuit are both located in the first semiconductor layer; and forming the pad on one side of the first semiconductor layer opposite to each other along the first direction, away from the second semiconductor structure.

[0031] In some embodiments, forming the first semiconductor structure further includes: forming a first connection structure extending through the first semiconductor layer along the first direction; wherein the pads are coupled to the interface circuit through the first connection structure.

[0032] In some embodiments, forming the first semiconductor structure further includes: forming a first conductive structure on one side of the first semiconductor layer opposite to each other along the first direction, away from the second semiconductor structure; wherein the first conductive structure is connected to the interface circuit; the step of forming the pad on one side of the first semiconductor layer opposite to each other along the first direction, away from the second semiconductor structure, includes: forming the pad on one side of the first conductive structure opposite to each other along the first direction, away from the first semiconductor layer; wherein the pad is connected to the first conductive structure.

[0033] In some embodiments, forming the third semiconductor structure includes: forming the peripheral circuit based on the third semiconductor layer; wherein the peripheral portion is located in the third semiconductor layer; and forming the pad on one side of the third semiconductor layer opposite to the second semiconductor structure along the first direction.

[0034] According to a fourth aspect of the present disclosure, a packaging structure is provided, comprising: a packaging substrate, a semiconductor device as described in any of the above embodiments, and a molding compound layer; the semiconductor device is disposed on the packaging substrate; and the molding compound layer encapsulates the semiconductor device.

[0035] According to a fifth aspect of the present disclosure, an electronic device is provided, comprising: a host and a semiconductor device as described in any of the above embodiments; the host is coupled to the semiconductor device.

[0036] In this embodiment, a first semiconductor structure including an interface circuit and an analog-to-digital conversion circuit, a second semiconductor structure including a memory array, and a third semiconductor structure including peripheral circuits are sequentially stacked along a first direction. The pads are integrated within either the first or third semiconductor structure and coupled to the interface circuits. This achieves two advantages: first, it enables three-dimensional integration of semiconductor devices, reducing chip size and increasing storage density; second, it provides a novel pad design for integrating a logic chip with 3D NAND flash memory, which not only enables in-memory computing but also meets the high bandwidth and high computing power requirements of in-memory computing, providing a high-performance and low-cost solution for large-scale, high-computing-power hardware. Attached Figure Description

[0037] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0038] Figure 1A A schematic block diagram of a semiconductor device provided in an embodiment of this disclosure;

[0039] Figure 1B A schematic block diagram of another semiconductor device provided in an embodiment of this disclosure;

[0040] Figure 2 A schematic block diagram of a storage array and peripheral circuitry provided for embodiments of this disclosure;

[0041] Figure 3 A schematic cross-sectional view of a storage array including storage strings is provided for an embodiment of this disclosure;

[0042] Figure 4 A schematic block diagram of another peripheral circuit and memory array provided for an embodiment of this disclosure;

[0043] Figure 5 A schematic diagram of an input voltage input to a storage array via a top select line, provided as an embodiment of this disclosure;

[0044] Figure 6 This is a schematic diagram of a plurality of bit-line coupled memory strings provided in an embodiment of the present disclosure;

[0045] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure;

[0046] Figure 8 A cross-sectional schematic diagram of a semiconductor device provided in the first embodiment of this disclosure;

[0047] Figure 9 A cross-sectional schematic diagram of a semiconductor device provided in the second embodiment of this disclosure;

[0048] Figure 10 A cross-sectional schematic diagram of a semiconductor device provided in the third embodiment of this disclosure;

[0049] Figure 11 A cross-sectional schematic diagram of a semiconductor device provided in the fourth embodiment of this disclosure;

[0050] Figure 12 A cross-sectional schematic diagram of another semiconductor device provided in an embodiment of this disclosure;

[0051] Figure 13 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0052] Figures 14A to 14D A schematic diagram illustrating the fabrication process of a semiconductor device according to the first embodiment of this disclosure;

[0053] Figures 15A to 15D A schematic diagram illustrating the fabrication process of a semiconductor device according to a second embodiment of this disclosure;

[0054] Figures 16A to 16D A schematic diagram illustrating the fabrication process of a semiconductor device according to a third embodiment of this disclosure;

[0055] Figure 17 A schematic diagram of a packaging structure provided in an embodiment of this disclosure;

[0056] Figure 18 A schematic diagram of an exemplary electronic device having semiconductor devices provided for embodiments of this disclosure;

[0057] Figure 19 A schematic diagram of an exemplary memory card with semiconductor devices provided in an embodiment of this disclosure;

[0058] Figure 20 This is a schematic diagram of an exemplary solid-state drive with semiconductor devices provided in an embodiment of this disclosure. Detailed Implementation

[0059] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0060] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0061] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0062] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0063] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0064] In the classic von Neumann computing architecture, the memory device and the processor are separate, and data is transferred between them via a data bus. When executing a command, the processor first reads data from the memory device, processes it, and then writes the updated data back to the memory device. This frequent data movement results in significant power consumption and time overhead. Furthermore, due to the limited bandwidth of the memory device, the processor's processing speed is limited by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, especially the emergence of generative AI large language models, the scale of AI models and related computational demands have increased dramatically. The processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent.

[0065] To address the bottlenecks of the classic von Neumann computing architecture, in-memory computing chip architecture has emerged. Its basic idea is to embed computing functions into memory devices and directly utilize memory devices for logical calculations, thereby reducing the amount and distance of data transfer between memory devices and processors, reducing power consumption while improving computing performance, and thus promising to build high-performance, high-bandwidth, and high-energy-efficiency computing systems.

[0066] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by altering their electrical conductance, while computational capability refers to the ability to perform vector-matrix multiplication within a given time by constructing an array of memory devices and applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to, Static Random Access Memory (SRAM), NAND flash memory, and Dynamic Random Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied and important component in IMC chips.

[0067] Given the extremely high storage density of 3D NAND storage arrays, they can be used to carry large model weights and perform large model inference using in-memory computing. To meet the high bandwidth and high computing power requirements of in-memory computing, the integration of logic chips and 3D NAND flash memory needs to be specially designed to provide a high-performance, low-cost hardware solution for large model computing.

[0068] Based on one or more of the above-mentioned technical problems, this disclosure provides a semiconductor device.

[0069] Figure 1AThis is a schematic block diagram of a semiconductor device provided in an embodiment of the present disclosure. Figure 1B This is a schematic block diagram of another semiconductor device provided in an embodiment of this disclosure. (Refer to...) Figure 1A and Figure 1B As shown, the semiconductor device 100 includes a first semiconductor structure 102, a second semiconductor structure 104 and a third semiconductor structure 106 stacked sequentially along a first direction; wherein, the first side 104a of the second semiconductor structure 104 is bonded to the first semiconductor structure 102, and the second side 104b of the second semiconductor structure 104 is bonded to the third semiconductor structure 106.

[0070] Refer to 1A and Figure 1B As shown, the first side 104a and the second side 104b of the second semiconductor structure 104 are opposite each other along the first direction. The third semiconductor structure 106 and the first semiconductor structure 102 are respectively integrated on opposite sides of the second semiconductor structure 104 along the first direction, such that the first semiconductor structure 102, the second semiconductor structure 104 and the third semiconductor structure 106 are respectively in different planes, that is, the first semiconductor structure 102, the second semiconductor structure 104 and the third semiconductor structure 106 are stacked sequentially along the first direction. In this way, the planar size of the semiconductor device 100 can be reduced, the integration degree can be improved and the storage density can be increased.

[0071] In some embodiments, a first semiconductor structure 102, a second semiconductor structure 104, and a third semiconductor structure 106 may be formed on different substrates. For example, the first semiconductor structure 102 may be formed on a first substrate, the second semiconductor structure 104 on a second substrate, and the third semiconductor structure 106 on a third substrate, and they may be stacked on top of each other using various bonding techniques such as hybrid bonding and transfer bonding.

[0072] The first semiconductor structure 102 includes an analog-to-digital converter circuit 108, which is configured to convert analog signals into digital signals and transmit them to a data processing circuit (e.g., ...). Figure 7 The data processing circuit 502 in the middle. The analog-to-digital conversion circuit 108 includes, but is not limited to, an analog-to-digital converter (ADC).

[0073] As an example, the analog-to-digital converter 108 is configured to receive analog information obtained from performing operations (e.g., a first operation) on the memory array 112 in the second semiconductor structure 104, and to convert the analog computation information into digital information and transmit it to the data processing circuit. In this example, the first operation includes multiplication-accumulation operations, for example, Figure 6Based on the characteristics of NAND flash memory, a multiply-accumulate-add operation can be performed on eight memory strings coupled to the same bit line BL0. The sum of the output currents of the eight memory strings coupled to the bit line BL0 (i.e., the current I0 on the bit line BL0) can be equivalent to the result of the multiply-accumulate-add operation. For the specific process of the multiply-accumulate-add operation, please refer to [link / reference]. Figure 6 Related descriptions.

[0074] It should be noted that both the analog-to-digital converter (ADC) circuit 108 and the data processing circuit can be located within the first semiconductor structure 102, meaning the first semiconductor structure 102 includes both the ADC circuit 108 and the data processing circuit. However, in other examples, the data processing circuit can be located within other semiconductor structures. For example, the data processing circuit can be formed on another substrate and bonded to the first substrate on which the ADC circuit 108 is formed, thereby achieving the connection between the ADC circuit 108 and the data processing circuit.

[0075] The first semiconductor structure 102 also includes an interface circuit 110, which is configured to receive and transmit data between the semiconductor device 100 and other external devices (e.g., a host). Specifically, the interface circuit 110 is configured to output the result of a second operation performed by the data processing circuit to the external device. An interface protocol can be used as the interface circuit 110 between the semiconductor device 100 and the external device, allowing the semiconductor device 100 to communicate with the external device through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE), FireWire, etc. The interface circuit 110 here can also be referred to as a front-end interface.

[0076] The second semiconductor structure 104 includes a memory array 112, which can perform a first operation to obtain analog calculation information, which can be transmitted to an analog-to-digital converter circuit 108. The memory array 112 includes, but is not limited to, a three-dimensional NAND type memory array.

[0077] The third semiconductor structure 106 includes peripheral circuitry 114, which is coupled to the memory array 112 and the analog-to-digital converter circuit 108. Peripheral circuitry 114 can control the memory array 112 to perform storage operations, programming operations, reading operations, and erasing operations.

[0078] As an example, the peripheral circuit 114 can control the storage array 112 to perform storage operations and control the storage array 112 to transmit the analog calculation information obtained from the storage operations to the analog-to-digital conversion circuit 108.

[0079] In some embodiments, the first semiconductor structure further includes pads for coupling interface circuits, the pads being located on the side of the analog-to-digital conversion circuit opposite to each other along the first direction that is farther away from the second semiconductor structure; or the third semiconductor structure further includes pads for coupling interface circuits, the pads being located on the side of the peripheral circuit opposite to each other along the first direction that is farther away from the second semiconductor structure.

[0080] As an example, refer to Figure 1A As shown, the first semiconductor structure 102 also includes a pad 124. The pad 124 is exposed on the surface of the first semiconductor structure 102 that is far from the second semiconductor structure 104 among two opposing surfaces along a first direction, thereby facilitating electrical connection between external devices and the pad 124. It is understood that in this example, the pad 124 is formed on the first semiconductor structure 102, and the pad 124 can be coupled to the interface circuit 110 through wiring inside the first semiconductor structure 102.

[0081] As another example, see Figure 1B As shown, the third semiconductor structure 106 also includes a pad 124. The pad 124 is exposed on the surface of the third semiconductor structure 106 that is far from the second semiconductor structure 104, which is one of the two surfaces opposite each other along the first direction, thereby facilitating electrical connection between external devices and the pad 124. It is understood that in this example, the pad 124 is formed on the third semiconductor structure 106, and the pad 124 can be coupled to the interface circuit 110 through wiring inside the third semiconductor structure 106, wiring inside the second semiconductor structure 104, and wiring inside the first semiconductor structure.

[0082] The material of pad 124 includes at least one of conductive materials, such as doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0083] In the two examples above, pad 124 serves as the physical interface for connecting the semiconductor device 100 to external devices. For instance, signals can be transmitted between the host and the semiconductor device 100 via pad 124. It should be noted that the interface circuit 110 acts as the "logic layer" for communication between the semiconductor device 100 and external devices, responsible for protocol parsing and data management; while pad 124 acts as the "physical layer" for connecting the semiconductor device 100 to external devices, ensuring electrical connections between components. The coordinated operation of the logic layer and the physical layer ensures the efficient and stable operation of the semiconductor device 100.

[0084] In this embodiment, a first semiconductor structure including an interface circuit and an analog-to-digital conversion circuit, a second semiconductor structure including a memory array, and a third semiconductor structure including peripheral circuits are sequentially stacked along a first direction. The pads are integrated within either the first or third semiconductor structure and coupled to the interface circuits. This achieves two advantages: first, it enables three-dimensional integration of semiconductor devices, reducing chip size and increasing storage density; second, it provides a novel pad design for integrating a logic chip with 3D NAND flash memory, which not only enables in-memory computing but also meets the high bandwidth and high computing power requirements of in-memory computing, providing a high-performance and low-cost solution for large-scale, high-computing-power hardware.

[0085] In some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 can be vertically connected by bonding, and the second semiconductor structure 104 and the third semiconductor structure 106 can be vertically connected by bonding. As an example, see... Figure 1A or Figure 1B As shown, the second semiconductor structure 104 includes a first bonding layer 116 and a second bonding layer 118 disposed opposite to each other along a first direction, the first semiconductor structure 102 includes a third bonding layer 120, and the third semiconductor structure 106 includes a fourth bonding layer 122.

[0086] The first bonding layer 116 and the third bonding layer 120 are bonded together, thereby vertically connecting the first semiconductor structure 102 and the second semiconductor structure 104. In the bonded first semiconductor structure 102 and second semiconductor structure 104, the first bonding layer 116 is located between the first semiconductor structure 102 and the memory array 112, and the third bonding layer 120 is located between the analog-to-digital converter circuit 108 and the first bonding layer 116.

[0087] The second bonding layer 118 and the fourth bonding layer 122 are bonded together, thereby vertically connecting the second semiconductor structure 104 and the third semiconductor structure 106. In the bonded second semiconductor structure 104 and third semiconductor structure 106, the second bonding layer 118 is located between the third semiconductor structure 106 and the memory array 112, and the fourth bonding layer 122 is located between the peripheral circuit 114 and the second bonding layer 118.

[0088] It should be noted that the aforementioned bonding connections include hybrid bonding connections (also known as "metal / dielectric hybrid bonding connections"), a direct bonding technique that, for example, forms bonds between surfaces without the use of intermediate layers such as solder or adhesive, and can simultaneously achieve metal-to-metal and dielectric-to-dielectric bonding. It should also be noted that the term "bonding" as used in this disclosure can refer to any suitable bonding technique, such as the hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding mentioned above.

[0089] In some embodiments, the semiconductor device 100 further includes a first bonding interface between the first bonding layer 116 and the third bonding layer 120, and a second bonding interface between the second bonding layer 118 and the fourth bonding layer 122. Data transmission between the first semiconductor structure 102 and the second semiconductor structure 104 can be achieved through interconnects (e.g., bonding contacts) across the first bonding interface. Data transmission between the second semiconductor structure 104 and the third semiconductor structure 106 can be achieved through interconnects (e.g., bonding contacts) across the second bonding interface.

[0090] Figure 2 This is a schematic block diagram of a memory array and peripheral circuitry provided in an embodiment of this disclosure. For ease of understanding, the memory array 202 is described as a three-dimensional NAND type memory array. The memory cells 208 are NAND memory cells, provided in the form of an array of memory strings 210, each extending vertically. In some embodiments, each memory string 210 includes a plurality of memory cells 208 that are series-coupled and vertically stacked. Each memory cell 208 can hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 208. Each memory cell 208 can be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0091] In some embodiments, each memory cell 208 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In other embodiments, each memory cell 208 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0092] Reference Figure 2 As shown, each memory string 210 may include a bottom select gate (BSG) 212 at its source end and a top select gate (TSG) 214 at its drain end. The bottom select gate 212 and the top select gate 214 can be configured to activate the selected memory string 210 during read and program operations. In some embodiments, the source ends of memory strings 210 within the same memory block 206 can be coupled via a common source line (CSL) 218. In other words, all memory strings 210 within the same memory block 206 have a common source (ACS). According to some implementations, the top select gate 214 of each memory string 210 is coupled to a corresponding bit line 222, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 210 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 214) or a deselection voltage (e.g., 0V) to the corresponding top select transistor 214 via one or more top select lines (TSL) 216 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 212) or a deselection voltage (e.g., 0V) to the corresponding bottom select transistor 212 via one or more bottom select lines (BSL) 220.

[0093] Reference Figure 2 As shown, memory strings 210 can be organized into multiple memory blocks 206, each of which may have a common source line 218. In some embodiments, each memory block 206 is a basic data unit for an erase operation, i.e., all memory cells 208 on the same memory block 206 are erased simultaneously. To erase memory cells 208 in a selected memory block, an erase voltage bias can be used to couple the common source line 218 to the selected memory block and to unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 208 of adjacent memory strings 210 can be coupled via word lines 224, which select which row of memory cells 208 is affected by read and program operations.

[0094] Figure 3This is a schematic cross-sectional view of a storage array including storage strings, provided as an embodiment of this disclosure. (Refer to...) Figure 3 As shown, the stacked structure 304 includes a plurality of gate layers 306 and a plurality of insulating layers 308 alternately stacked, and a memory string 210 extending through the gate layers 306 and the insulating layers 308. The gate layers 306 and the insulating layers 308 can be stacked alternately, with adjacent gate layers 306 separated by an insulating layer 308. The number of memory cells included in the memory array is primarily related to the number of pairs of gate layers 306 and insulating layers 308 in the stacked structure 304.

[0095] The constituent materials of the gate layer 306 may include conductive materials. Conductive materials include, but are not limited to, tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate layer 306 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 306 includes a doped polysilicon layer. Each gate layer 306 may include a control gate surrounding a memory cell. The gate layer 306 at the top of the stack 304 may extend laterally as a top select line, the gate layer 306 at the bottom of the stack 304 may extend laterally as a bottom select line, and the gate layer 306 extending laterally between the top select line and the bottom select line may serve as a word line layer.

[0096] In some embodiments, the stacked structure 304 may be disposed on the semiconductor layer 302. The semiconductor layer 302 may include silicon, silicon-germanium, gallium arsenide, germanium, silicon-on-insulator, germanium-on-insulator, or any other suitable material. In other embodiments, the semiconductor device may not include the semiconductor layer.

[0097] In some embodiments, the memory string 210 includes a channel structure extending vertically through the stacked structure 304. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0098] Return to reference Figure 2 The peripheral circuitry 204 can be coupled to the memory array 202 via bit lines 222, word lines 224, source lines 218, bottom select lines 220, and top select lines 216. The peripheral circuitry 204 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 202 by applying voltage and / or current signals to each target memory cell 208 and sensing voltage and / or current signals from each target memory cell 208 via bit lines 222, word lines 224, source lines 218, bottom select lines 220, and top select lines 216. The peripheral circuitry 204 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0099] Figure 4 This is a schematic block diagram of another peripheral circuitry and memory array provided for embodiments of this disclosure. The peripheral circuitry may include a page buffer / sensor amplifier 402, a column decoder / bit line driver 404, a row decoder / word line driver 406, a voltage generator 408, a register 412, and a data bus 416. It should be understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0100] Control logic 410 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 412 can be coupled to control logic 410 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0101] Page buffer / sensor amplifier 402 can be configured to read data from memory array 202 and program (write) data to memory array 202 according to control signals from control logic 410. In one example, page buffer / sensor amplifier 402 can store programming data (write data) to be programmed into memory cell 208 of memory array 202. In another example, page buffer / sensor amplifier 402 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 208 coupled to selected word line 224. Column decoder / bit line driver 404 can be configured to be controlled by control logic 410 and to select one or more NAND memory strings 210 by applying a bit line voltage generated from voltage generator 408.

[0102] The line decoder / word line driver 406 can be configured to be controlled by control logic 410 and to select / deselect memory blocks 206 of the memory array 202 and to select / deselect word lines 224 of memory blocks 206. The line decoder / word line driver 406 can also be configured to drive word lines 224 using word line voltages generated from voltage generator 408. In some embodiments, the line decoder / word line driver 406 can also select / deselect and drive bottom select line 220 and top select line 216. As described in detail below, the line decoder / word line driver 406 is configured to perform programming operations on memory cells 208 coupled to one or more selected word lines 224. The voltage generator 408 can be configured to be controlled by control logic 410 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, input voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 202.

[0103] In some embodiments, for in-memory computing chips, it is necessary to perform a first operation between input data and a weight matrix. The input data can be an input vector or an input matrix composed of multiple elements, and the weight matrix is ​​composed of multiple weights. Each element in the input data needs to be multiplied and added with the multiple weights in the weight matrix to obtain the corresponding element in the output data.

[0104] To achieve the aforementioned computational functions, the storage array 202 can be configured to store a weight matrix. Specifically, the weights in the weight matrix can be written into the storage array 202 according to a certain mapping rule, and each storage cell 208 in the storage array 202 can be configured to store one weight. During the computation phase, the second semiconductor structure 104 in Figure 1 can receive input data from an external device. The input data can be an input vector or an input matrix composed of multiple elements. Each element in the input data can be converted into an input voltage by a digital-to-analog converter circuit and input to the storage array 202 via bit line 222 or word line 224.

[0105] In this embodiment of the disclosure, analog computation information can be output via bit lines or via the source terminal. That is, the bit lines in the second semiconductor structure are analog information output terminals, or the source terminal is an analog information output terminal. For ease of understanding, the following description will use bit lines as an example of analog information output terminals.

[0106] Figure 5 This is a schematic diagram illustrating an embodiment of the present disclosure where the input voltage is input to the storage array via a top select line. Figure 6 This is a schematic diagram of multiple memory strings coupled to bit lines, provided as an embodiment of this disclosure. It should be noted that... Figure 5 and Figure 6The number of bit lines, the number of memory strings coupled to each bit line, and the number of memory cells in each memory string shown are merely examples, and this disclosure does not limit the specific numbers for each structure. The following will combine... Figure 5 and Figure 6 Taking the bit line as an analog information output terminal as an example, the specific process of the first operation will be illustrated by way of example.

[0107] Reference Figure 5 As shown, the input voltage corresponding to an element in the input data can be input via multiple top select lines. During the first operation phase using the memory array, the peripheral circuitry is configured to apply a first read voltage V to the target word line WLn coupled to the target memory block. rd Appropriate input voltages are applied to the multiple top select lines coupled to the target memory block. For example, input voltages V can be applied to the top select lines TSL0, TSL1, and TSL2 coupled to the target memory block. in0 V in1 V in2 A first on-state voltage is applied to a non-target word line coupled to the target memory block. For example, a first on-state voltage V can be applied to word line WLn+1. pass1 A second on-state voltage is applied to the bottom select line coupled to the target memory block; for example, a second on-state voltage V can be applied to the bottom select line BSL. pass2 Analog calculation information can be obtained by sensing the current on the bit line coupled to the target memory block. For example, by sensing the current I0 on bit line BL0 and converting the current I0, information related to the input voltage V can be obtained. in0 Corresponding elements and weights w 00 The product of the input voltage V in1 Corresponding elements and weights w 10 The product of the input voltage V in2 Corresponding elements and weights w 20 The sum of these three products. In some embodiments, the first operation includes a multiplication-accumulation operation.

[0108] In some embodiments, the peripheral circuitry is configured to apply a corresponding programming voltage to a target word line coupled to a target memory block to program the memory cell coupled to the target word line before performing a first operation using the memory array.

[0109] In a specific example, a memory cell in the target memory block is configured to store one bit of data. Multiple memory cells in the target memory block have a first memory state and a second memory state. The threshold voltage of a memory cell having the first memory state is less than the threshold voltage of a memory cell having the second memory state. The first read voltage V... rdThe threshold voltage is greater than that of the memory cell with the first memory state and less than that of the memory cell with the second memory state. Here, the memory cell in the target memory block can be a single-level cell (SLC) storing one bit of data, the first memory state can be an erase state (E), and the second memory state can be a programmable state (P). The peripheral circuit can be configured to perform a programming operation on the memory cell coupled to the target word line before performing the first operation, writing weights to the memory cell according to a certain mapping rule. For a single-level cell, the weight writing process includes applying a corresponding programming voltage to adjust the threshold voltage of a portion of the memory cells coupled to the target word line to the range of the threshold voltage distribution corresponding to the second memory state.

[0110] In some embodiments, refer to Figure 6 As shown, taking a target memory block comprising eight memory strings coupled to bit line BL0 as an example, four memory cells coupled to the target word line WLn are in the first memory state (erase state E), and the other four memory cells are in the second memory state (programming state P). Input data can be input from the eight top select lines TSL0 to TSL7. Specifically, the input data can be an input vector comprising eight elements, which can include five "1"s and three "0"s. The digital-to-analog converter circuit can convert each element of the input vector into a corresponding voltage signal, and then... Figure 4 The voltage generator 408 shown converts the voltage signal into an input voltage to be applied to the top select line, and transmits the input voltage to the top select line via a driver coupled to the top select line. Specifically, eight input voltages can be applied to eight top select lines simultaneously. The input voltages corresponding to "1" include V... in0 V in1 V in4 V in5 and V in6 This allows the top selection transistors TSG0, TSG1, TSG4, TSG5, and TSG6, respectively coupled to the top selection lines TSL0, TSL1, TSL4, TSL5, and TSL6, to be turned on. The input voltages corresponding to "0" include V. in2 V in3 V in7 This can turn off the top select transistors TSG2, TSG3, and TSG7, which are coupled to the top select lines TSL2, TSL3, and TSL7, respectively.

[0111] In a specific example, refer to Figure 6As shown, the current I0 on bit line BL0 is the sum of the output currents of the eight memory strings coupled to bit line BL0. The input voltage on the top select line coupled to memory strings Str0, Str4 and Str5 causes the top select transistors TSG0, TSG4 and TSG5 to be in the on state. The memory cells in memory strings Str0, Str4 and Str5 coupled to the target word line WLn have the first memory state (erasure state E). Therefore, memory strings Str0, Str4 and Str5 are turned on and can generate a current greater than or equal to the preset current. The current I0 on bit line BL0 is basically equal to the sum of the output currents of memory strings Str0, Str4 and Str5. The multiple of current I0 relative to the current generated by any memory string in memory strings Str0, Str4 and Str5 is approximately 3. If the weight value stored in the memory cell in the first memory state is equivalent to "1", and the weight value stored in the memory cell in the second memory state is equivalent to "0", then the operation performed by the eight memory strings coupled to the bit line BL0 can be equivalent to: 1×1+1×0+0×1+0×0+1×1+1×1+1×0+0×0=3.

[0112] Based on the specific example above, when there are Y+1 memory strings coupled to bit lines BLx in the target memory block, the Y+1 elements corresponding to the input voltages input by the top selection lines of the Y+1 strings are α0, α1...α... Y The Y+1 memory cells coupled to the target word line WLn store weights w0, w1, ..., w1, respectively. Y Then, the analog calculation information equivalent to the current on bit line BLx relative to the multiple of the output current greater than or equal to the preset current can be α. 0* w0+α 1* w1+……+α Y* w Y .

[0113] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. It should be noted that... Figure 7 This explanation uses the bit line as an analog signal output terminal as an example. (Refer to...) Figure 7 As shown, the first semiconductor structure 102 also includes a data processing circuit 502 and a controller 504.

[0114] The data processing circuit 502 is configured to perform a second operation on digital information. The second operation includes one or more of compensation, activation, shift, or pooling operations. The data processing circuit includes a processor, which may include a dedicated processor, including but not limited to a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Tensor Processing Unit (TPU), Video Processing Unit (VPU), Neural Processing Unit (NPU), Secure Processing Unit (SPU), Physical Processing Unit (PPU), and Image Signal Processor (ISP).

[0115] In a specific example, the data processing circuitry is an NPU. The NPU can perform operations such as arithmetic / logic operations, rotation and shift operations, compensation operations, activation operations, and pooling operations. In some embodiments, activation operations can be implemented using activation functions stored in the NPU. These activation functions may include, but are not limited to, step functions, correction functions, sigmoid functions, hyperbolic tangent (tanh) functions, and softplus functions (also known as smoothing correction).

[0116] The controller 504 can be configured to control the operation of the semiconductor device 100. That is, the controller 504 can act as a memory controller managing data storage and transmission in the bonded second semiconductor structure 104 and third semiconductor structure 106 (hereinafter referred to as the bonded semiconductor structure), and an arithmetic controller managing data processing and transmission in the first semiconductor structure 102. It should be noted that the process node corresponding to the first semiconductor structure 102 can be smaller than the process node corresponding to the third semiconductor structure 106. In this embodiment, by integrating the controller 504 into the first semiconductor structure 102 with a smaller process node and bonding it to the bonded semiconductor structure, not only can the planar size of the semiconductor device be reduced and the integration density improved, but the data transmission rate can also be increased.

[0117] In some embodiments, controller 504 is coupled to the bonding semiconductor structure and an external device (e.g., a host computer). It is configured to control the bonding semiconductor structure. Controller 504 can manage data stored in the bonding semiconductor structure and communicate with the external device. For example, controller 504 is also configured to control data transmission between the first semiconductor structure 102 and the bonding semiconductor structure. As another example, controller 504 is also configured to receive input data sent by the external device and send the input data to the bonding semiconductor structure. Of course, in other embodiments, part or all of the host computer can be integrated into the first semiconductor structure 102; for example, a host processor can be integrated into the first semiconductor structure.

[0118] In some embodiments, controller 504 may also be configured to manage various functions relating to data stored or to be stored in the bonded semiconductor structure, wherein these functions include, but are not limited to, bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, controller 504 is also configured to process error correction codes (ECCs) relating to data read from or written to the bonded semiconductor structure. In some embodiments, controller 504 may also perform any other suitable functions, such as formatting the bonded semiconductor structure.

[0119] In some embodiments, the controller 504 interacts with the bonded semiconductor structure via a plurality of configured channels, also referred to as back-end interfaces.

[0120] In some embodiments, the third semiconductor structure 106 further includes an interface circuit 506 (e.g., a second interface circuit 506); the third semiconductor structure 106 can be connected to the first semiconductor structure 102 via the second interface circuit 506. That is, the second interface circuit 506 here is the interface coupled to the back-end interface of the controller 504; that is, the second interface circuit 506 can also be the interface for communication between the third semiconductor structure 106 and the first semiconductor structure 102. The second interface circuit 506 can be coupled to the control logic 410 in the peripheral circuit 204 (see...). Figure 4 The second interface circuit 506 also acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 410, and to buffer status information received from control logic 410 and relay it to the host. The second interface circuit 506 can also be used via... Figure 4 The data bus 416 in the middle is coupled to Figure 4 The column decoder / bit line driver 404 in the memory array acts as a data I / O interface and a data buffer to buffer data and relay it to or from the memory array.

[0121] Figure 8 This is a schematic cross-sectional view of a semiconductor device provided in the first embodiment of this disclosure. (Refer to...) Figure 1A and Figure 8 As shown, the semiconductor device includes a first semiconductor structure 102, a second semiconductor structure 104, and a third semiconductor structure 106 stacked sequentially along a first direction. The first semiconductor structure 102 includes an analog-to-digital converter (ADC) circuit 108 and an interface circuit 110. The second semiconductor structure 104 includes a memory array 112, and the third semiconductor structure 106 includes a peripheral circuit 114, which is coupled to both the memory array 112 and the ADC circuit 108. The ADC circuit 108 is configured to receive analog information obtained by the memory array 112 performing calculations. The first semiconductor structure 102 also includes pads 124 coupled to the interface circuit 110, located on the side of the ADC circuit 108 opposite to the second semiconductor structure 104 along the first direction. It should be noted that the first direction in this document can be the D1 direction in the accompanying drawings, and the second direction in the following text can be the D2 direction in the accompanying drawings, where the D1 direction is perpendicular to the D2 direction.

[0122] In some embodiments, refer to Figure 1A and Figure 8 As shown, the first semiconductor structure 102 also includes a first semiconductor layer 602; the first semiconductor layer 602 is located between the pad 124 and the second semiconductor structure 104, and a portion of the analog-to-digital conversion circuit 108 and a portion of the interface circuit 110 are both located in the first semiconductor layer 602.

[0123] The first semiconductor layer 602 includes, but is not limited to, a substrate. The substrate material includes, but is not limited to, elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art.

[0124] Both the analog-to-digital converter circuit 108 and the interface circuit 110 may include one or more CMOS transistors, and the active regions of the CMOS transistors may be located in the first semiconductor layer 602. As an example, see... Figure 8As shown, the first semiconductor layer 602 may include a front side and a back side opposite to each other along a first direction. The active region of the CMOS transistor may be formed on the front side of the first semiconductor layer 602, and the pad dielectric layer 624 is formed on the back side of the first semiconductor layer 602. The pad 124 is located in the pad dielectric layer 624. The material of the pad dielectric layer 624 may include a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, or low-k dielectrics.

[0125] In some embodiments, refer to Figure 1A and Figure 8 As shown, the first semiconductor structure 102 further includes a first dielectric structure 604, a first conductive structure 606, and a second conductive structure 608; the first dielectric structure 604 is located between the first semiconductor layer 602 and the second semiconductor structure 104, and the first conductive structure 606 and the second conductive structure 608 are both located in the first dielectric structure 604; wherein, the pad 124 is coupled to the interface circuit 110 through the first conductive structure 606, and the peripheral circuit 114 is coupled to the analog-to-digital conversion circuit 108 through the second conductive structure 608.

[0126] In some embodiments, refer to Figure 8 As shown, the first semiconductor structure 102 further includes a first connection structure 610; the first connection structure 610 extends through the first semiconductor layer 602 along a first direction; wherein, the opposite ends of the first connection structure 610 along the first direction are respectively connected to the pad 124 and the first conductive structure 606.

[0127] The first dielectric structure 604 covers each circuit formed on the front side of the first semiconductor layer 602. The first dielectric structure 604 is used to physically isolate each conductive structure formed on the front side of the first semiconductor layer 602. For example, the first conductive structure 606 and the second conductive structure 608 are physically isolated by the first dielectric structure 604. The first dielectric structure 604 may include one or more film layers.

[0128] As an example, refer to Figure 8 As shown, the first dielectric structure 604 includes a first dielectric layer 612 and a first interconnect dielectric layer 614; the first dielectric layer 612 is located between the first semiconductor layer 602 and the first interconnect dielectric layer 614, and the first interconnect dielectric layer 614 is located between the first dielectric layer 612 and the second semiconductor structure 104. Specifically, the first interconnect dielectric layer 614 is located between the first dielectric layer 612 and the third bonding layer 120. The material of the first dielectric layer 612 and the other dielectric layers described below may include dielectric materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, or low-k dielectrics.

[0129] The first conductive structure 606 is used to electrically lead out the interface circuit 110. For example, the interface circuit 110 can be coupled to the pad 124 through the first conductive structure 606 and the first connection structure 610. As an example, the first conductive structure 606 includes a first contact structure 616 and a first interconnect structure 618; the first contact structure 616 extends through the first dielectric layer 612 along a first direction, and the first interconnect structure 618 is located in the first interconnect dielectric layer 614; wherein, the opposite ends of the first contact structure 616 along the first direction are respectively connected to the first connection structure 610 and the first interconnect structure 618. The interface circuit 110 can be coupled to the pad 124 in sequence through the first interconnect structure 618, the first contact structure 616, and the first connection structure 610.

[0130] The second conductive structure 608 is used to electrically lead out the analog-to-digital converter circuit 108. For example, the analog-to-digital converter circuit 108 can be coupled to the peripheral circuit 114 through the second conductive structure 608 and other connection structures. As an example, the second conductive structure 608 includes a second contact structure 620 and a second interconnect structure 622; the second contact structure 620 extends through the first dielectric layer 612 along a first direction, and the second interconnect structure 622 is located in the first interconnect dielectric layer 614; wherein, the two opposite ends of the second contact structure 620 along the first direction are respectively connected to the analog-to-digital converter circuit 108 and the second interconnect structure 622. The analog-to-digital converter circuit 108 can be coupled to the peripheral circuit 114 in sequence through the second contact structure 620 and the second interconnect structure 622.

[0131] Both the first conductive structure 606 and the second conductive structure 608 may include one or more sub-conductive structures. For example, multiple contact structures are formed in the first dielectric layer 612, and multiple interconnect structures are formed in the first interconnect dielectric layer 614. The contact structures and interconnect structures connected to each other constitute a conductive structure.

[0132] The contact structures in this disclosure (e.g., the first contact structure 616, the second contact structure 620, and other contact structures hereinafter) may include longitudinally extending contact electrodes. The contact structures may be formed in one or more dielectric layers. The materials of the contact structures may include conductive materials, including but not limited to at least one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0133] The interconnect structures in this disclosure (e.g., the first interconnect structure 618, the second interconnect structure 622, and the third to ninth interconnect structures hereinafter) may include, for example, laterally extending interconnect lines (metal) and longitudinally extending interconnect contacts (via). The interconnect structures may be formed in one or more interconnect dielectric layers. The materials of the interconnect structures may include conductive materials, including but not limited to at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The materials of the interconnect dielectric layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0134] The connection structures in this disclosure (e.g., the first connection structure 610 and the second to seventh connection structures 688 hereinafter) may include longitudinally extending through-silicon vias (TSVs). The connection structures may extend longitudinally through the silicon substrate. The materials of the connection structures may include at least one of the following: conductive materials, such as doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0135] It should be noted that other dielectric layers are also provided between the connection structure and the semiconductor layer it penetrates in this paper, so as to physically isolate the connection structure and the semiconductor layer it penetrates from each other.

[0136] In some embodiments, refer to Figure 8 As shown, the dimension of the first contact structure 616 near the first semiconductor layer 602 in the second direction is less than or equal to the dimension of the first contact structure 616 away from the first semiconductor layer 602 in the second direction; the dimension of the second contact structure 620 near the first semiconductor layer 602 in the second direction is less than or equal to the dimension of the second contact structure 620 away from the first semiconductor layer 602 in the second direction.

[0137] As an example, the first contact structure 616 and the second contact structure 620 can be formed simultaneously, thereby simplifying the manufacturing process. The first contact structure 616 and the second contact structure 620 can be formed after the first dielectric layer 612 is formed on the front side of the first semiconductor layer 602, by etching the first dielectric layer 612 in the direction facing the front side of the first semiconductor layer 602 to form a plurality of contact holes penetrating the first dielectric layer 612, and filling each contact hole with conductive material to form the first contact structure 616 and the second contact structure 620 respectively.

[0138] It should be noted that, due to the limitations of the etching process, the bottom dimension of the formed contact hole in the second direction is usually less than or equal to the top dimension of the contact hole in the second direction, which makes the bottom dimension of the filled contact structure in the second direction less than or equal to the top dimension of the contact structure in the second direction.

[0139] In this embodiment, by providing a first connection structure 610 extending through the first semiconductor layer 602 in a first direction, an electrical connection can be achieved between the bonding pad 124 on the back side of the first semiconductor layer 602 and the interface circuit 110 on the front side of the first semiconductor layer 602. This eliminates the need for the external interface of the semiconductor device to loop back from the first bonding interface. In practical applications, a through-silicon via (TSV) extending through the silicon substrate can be formed by etching from the back side of the silicon substrate, and a conductive material can be filled into the TSV to form a corresponding connection structure.

[0140] In some embodiments, refer to Figure 8 As shown, the dimension of the first connection structure 610 near the pad 124 in the second direction is greater than or equal to the dimension of the first connection structure 610 away from the pad 124 in the second direction.

[0141] It should be noted that, due to the limitations of the etching process, the top dimension of the formed through-silicon via (TSV) in the second direction is usually greater than or equal to the bottom dimension of the TSV in the second direction, which makes the top dimension of the filled interconnect structure in the second direction greater than or equal to the bottom dimension of the interconnect structure in the second direction.

[0142] In some embodiments, refer to Figure 8 As shown, the second semiconductor structure 104 further includes a second semiconductor layer 626, a second dielectric structure 628, a third conductive structure 630, and a third connection structure 632; the second semiconductor layer 626 is located between the first semiconductor structure 102 and the second dielectric structure 628, the second dielectric structure 628 covers the stepped region of the memory array 112, the third conductive structure 630 is located in the second dielectric structure 628, and the third connection structure 632 extends through the second semiconductor layer 626 along a first direction; wherein, the peripheral circuit 114 is coupled to the analog-to-digital converter circuit 108 through the third conductive structure 630 and the third connection structure 632.

[0143] In some embodiments, refer to Figure 7 and Figure 8As shown, the first semiconductor structure 102 further includes a controller 504; a portion of the controller 504 is located in the first semiconductor layer 602; the second semiconductor structure 104 further includes a fourth conductive structure 634 and a fourth connection structure 636; the fourth conductive structure 634 is located in the second dielectric structure 628, and the fourth connection structure 636 extends through the second semiconductor layer 626 along a first direction; wherein, the controller 504 is coupled to the peripheral circuit 114 through the fourth connection structure 636 and the fourth conductive structure 634. Here, the controller 504 may include one or more CMOS transistors, and the active regions of the CMOS transistors may be located in the first semiconductor layer 602.

[0144] In some embodiments, refer to Figure 7 and Figure 8 As shown, the second semiconductor structure 104 further includes a fifth conductive structure 638 and a fifth connection structure 640; the fifth conductive structure 638 is located in the second dielectric structure 628, and the fifth connection structure 640 extends through the second semiconductor layer 626 along the first direction; wherein, the controller 504 is also coupled to the peripheral circuit 114 through the fifth connection structure 640 and the fifth conductive structure 638; the fifth connection structure 640 and the fourth connection structure 636 are respectively used to transmit different control signals.

[0145] The second semiconductor layer 626 includes, but is not limited to, a substrate. The material of the substrate can be referred to the relevant description above, and will not be repeated here. The second semiconductor layer 626 may include a front side and a back side opposite to each other along the first direction. The memory array 112 can be formed on the front side of the second semiconductor layer 626. The structure of the memory array 112 can be referred to... Figure 2 and Figure 3 Related descriptions.

[0146] The second dielectric structure 628 covers the step region of the memory array 112 formed on the front side of the second semiconductor layer 626. The second dielectric structure 628 is used to physically isolate the various conductive structures formed on the front side of the second semiconductor layer 626. For example, the third conductive structure 630, the fourth conductive structure 634 and the fifth conductive structure 638 are physically isolated from each other through the first dielectric structure 604. The second dielectric structure 628 may include one or more film layers.

[0147] As an example, refer to Figure 8 As shown, the second dielectric structure 628 includes a second dielectric layer 642 and a second interconnect dielectric layer 644; the second dielectric layer 642 is located between the second semiconductor layer 626 and the second interconnect dielectric layer 644, and the second interconnect dielectric layer 644 is located between the second dielectric layer 642 and the third semiconductor structure 106. Specifically, the second interconnect dielectric layer 644 is located between the second dielectric layer 642 and the second bonding layer 118.

[0148] The third connection structure 632 and the third conductive structure 630 work together to achieve an electrical connection between the peripheral circuit 114 and the analog-to-digital converter circuit 108. As an example, the third conductive structure 630 includes a contact structure (e.g., a tenth contact structure) extending along a first direction through the second dielectric layer 642 and a third interconnect structure located in the second interconnect dielectric layer 644. The analog-to-digital converter circuit 108 can be coupled to the peripheral circuit 114 in sequence via the second conductive structure 608, a bonding contact across the first bonding interface, the third connection structure 632, the third conductive structure 630, and the bonding contact across the second bonding interface.

[0149] The fourth connection structure 636 and the fourth conductive structure 634 together provide an electrical connection between the peripheral circuit 114 and the controller 504. As an example, the fourth conductive structure 634 includes a fourth contact structure extending along a first direction through the second dielectric layer 642 and a fourth interconnect structure located in the second interconnect dielectric layer 644. The controller 504 can be coupled to the peripheral circuit 114 sequentially via other conductive structures (not shown) on the front side of the first semiconductor layer 602, bonding contacts across the first bonding interface, the fourth connection structure 636, the fourth conductive structure 634, and bonding contacts across the second bonding interface. Here, a first line via the fourth connection structure 636 and the fourth conductive structure 634 is used to transmit a first control signal.

[0150] The fifth connection structure 640 and the fifth conductive structure 638 together provide an electrical connection between the peripheral circuit 114 and the controller 504. As an example, the fifth conductive structure 638 includes a fifth contact structure extending along a first direction through the second dielectric layer 642 and a fifth interconnect structure located in the second interconnect dielectric layer 644. The controller 504 can be coupled to the peripheral circuit 114 sequentially via other conductive structures (not shown) on the front side of the first semiconductor layer 602, bonding contacts across the first bonding interface, the fifth connection structure 640, the fifth conductive structure 638, and bonding contacts across the second bonding interface. Here, a second line via the fifth connection structure 640 and the fifth conductive structure 638 is used to transmit a second control signal, which is different from the first control signal.

[0151] Taking the ONFI interface as an example, the controller 504 and the memory can exchange signals based on the ONFI protocol, which specifies a series of command and data transmission formats. However, with the iteration of chips and the continuous development of semiconductor technology, the standard ONFI interface will face new challenges, such as difficulty in meeting the transmission requirements of other custom control signals. Based on this, in this embodiment of the disclosure, by setting a first line including a fourth connection structure 636 and a fourth conductive structure 634 and a second line including a fifth connection structure 640 and a fifth conductive structure 638, the first line and the second line can be used to transmit different types of control signals, for example, the first line is used to transmit commands specified by the ONFI protocol, and the second line is used to transmit other custom commands. In this way, the standard interface can be expanded to meet the signal interaction requirements in different scenarios.

[0152] In some embodiments, refer to Figure 8 As shown, the dimension of the tenth contact structure near the second semiconductor layer 626 in the second direction is less than or equal to the dimension of the tenth contact structure away from the second semiconductor layer 626 in the second direction; the dimension of the fourth contact structure near the second semiconductor layer 626 in the second direction is less than or equal to the dimension of the fourth contact structure away from the second semiconductor layer 626 in the second direction; and the dimension of the fifth contact structure near the second semiconductor layer 626 in the second direction is less than or equal to the dimension of the fifth contact structure away from the second semiconductor layer 626 in the second direction.

[0153] As an example, the tenth contact structure, the fourth contact structure, and the fifth contact structure can be formed simultaneously, thereby simplifying the fabrication process. The tenth contact structure, the fourth contact structure, and the fifth contact structure can be formed after the second dielectric layer 642 is formed on the front side of the second semiconductor layer 626. The second dielectric layer 642 is then etched along the direction facing the front side of the second semiconductor layer 626 to form multiple contact holes penetrating the second dielectric layer 642. Conductive material is then filled into each contact hole to form the tenth contact structure, the fourth contact structure, and the fifth contact structure, respectively.

[0154] In this embodiment of the disclosure, by providing a third connection structure 632, a fourth connection structure 636, and a fifth connection structure 640 extending through the second semiconductor layer 626 in a first direction, electrical connections can be made between the analog-to-digital converter circuit 108 and the controller 504 located on the back side of the second semiconductor layer 626 and the peripheral circuit 114 located on the front side of the second semiconductor layer 626.

[0155] In some embodiments, the dimension of the third connecting structure 632 near the second medium structure 628 in the second direction is less than or equal to the dimension of the third connecting structure 632 away from the second medium structure 628 in the second direction; the dimension of the fourth connecting structure 636 near the second medium structure 628 in the second direction is less than or equal to the dimension of the fourth connecting structure 636 away from the second medium structure 628 in the second direction; and the dimension of the fifth connecting structure 640 near the second medium structure 628 in the second direction is less than or equal to the dimension of the fifth connecting structure 640 away from the second medium structure 628 in the second direction.

[0156] As an example, the third connection structure 632, the fourth connection structure 636, and the fifth connection structure 640 can be formed simultaneously, thereby simplifying the fabrication process. The third connection structure 632, the fourth connection structure 636, and the fifth connection structure 640 can be formed after the second bonding layer 118 and the fourth bonding layer 122 are bonded. Then, the second semiconductor layer 626 is etched along the direction towards the back side of the second semiconductor layer 626 to form multiple through-silicon vias (TSVs) penetrating the second semiconductor layer 626. Conductive material is then filled into each TSV to form the third connection structure 632, the fourth connection structure 636, and the fifth connection structure 640, respectively.

[0157] In some embodiments, refer to Figure 8 As shown, the second semiconductor structure 104 further includes a bit line 646 coupled to the memory array 112, with the bit line 646 located between the memory array 112 and the third semiconductor structure 106. The third semiconductor structure 106 further includes a third semiconductor layer 648, a third dielectric structure 650, and an eighth conductive structure 652. The third dielectric structure 650 is located between the second semiconductor structure 104 and the third semiconductor layer 648, and the eighth conductive structure 652 is located within the third dielectric structure 650. The peripheral circuit 114 is coupled to the bit line 646 via the eighth conductive structure 652. For more information on the bit line 646, please refer to... Figure 2 Bit line 222 shown Figure 5 The relevant descriptions of bit lines BL0 to BL2 are shown.

[0158] The third semiconductor layer 648 includes, but is not limited to, a substrate. The material of the substrate can be referred to the relevant description above, and will not be repeated here. The third semiconductor layer 648 may include a front side and a back side opposite to each other along the first direction. The peripheral circuit 114 may be formed on the front side of the third semiconductor layer 648. The peripheral circuit 114 can be referred to... Figure 2 and Figure 4 Related descriptions.

[0159] The third dielectric structure 650 covers the peripheral circuit 114 formed on the front side of the third semiconductor layer 648. The third dielectric structure 650 is used to physically isolate the various conductive structures formed on the front side of the third semiconductor layer 648, for example, the eighth conductive structure 652 and... Figure 10 The seventh conductive structures 676 are physically isolated from each other by a third dielectric structure 650, which may include one or more film layers.

[0160] As an example, refer to Figure 8 As shown, the third dielectric structure 650 includes a third dielectric layer 654 and a third interconnect dielectric layer 656; the third dielectric layer 654 is located between the third semiconductor layer 648 and the third interconnect dielectric layer 656, and the third interconnect dielectric layer 656 is located between the third dielectric layer 654 and the second semiconductor structure 104. Specifically, the third interconnect dielectric layer 656 is located between the third dielectric layer 654 and the fourth bonding layer 122.

[0161] The eighth conductive structure 652 is used to realize the electrical connection between the bit line 646 and the peripheral circuit 114. As an example, the eighth conductive structure 652 includes an eighth contact structure and an eighth interconnect structure; the eighth contact structure extends along a first direction through the third dielectric layer 654, and the eighth interconnect structure is located in the third interconnect dielectric layer 656; wherein, the opposite ends of the eighth contact structure along the first direction are connected to the peripheral circuit 114 and the eighth interconnect structure, respectively. The bit line 646 can be coupled to the peripheral circuit 114 in sequence through a bonding contact spanning the second bonding interface and the eighth conductive structure 652.

[0162] In some embodiments, refer to Figure 8 As shown, the size of the eighth contact structure near the third semiconductor layer 648 in the second direction is less than or equal to the size of the eighth contact structure away from the third semiconductor layer 648 in the second direction.

[0163] In some embodiments, refer to 1A and Figure 8 As shown, the first bonding layer 116 includes a first bonding contact 660 and a first bonding dielectric layer that isolates the first bonding contact 660; the second bonding layer 118 includes a second bonding contact 664 and a second bonding dielectric layer that isolates the second bonding contact 664; the third bonding layer 120 includes a third bonding contact 662 and a third bonding dielectric layer that isolates the third bonding contact 662; and the fourth bonding layer 122 includes a fourth bonding contact 666 and a fourth bonding dielectric layer that isolates the fourth bonding contact 666. Specifically, the first bonding contact 660 and the third bonding contact 662 are bonded, and the first bonding dielectric layer and the third bonding dielectric layer are bonded; the second bonding contact 664 and the fourth bonding contact 666 are bonded, and the second bonding dielectric layer and the fourth bonding dielectric layer are bonded.

[0164] In some embodiments, the bonding contacts may include a conductive material, including but not limited to one or more of tungsten, cobalt, copper, aluminum, or polycrystalline silicon. As an example, the bonding contacts of the bonding layer may include copper, and the remaining area of ​​the bonding layer may be formed of a dielectric, including but not limited to one or more of silicon oxide, silicon nitride, silicon oxynitride, or low-k dielectrics. The bonding contacts in the bonding layer and the surrounding dielectric can be used for hybrid bonding, simultaneously achieving metal-to-metal bonding and dielectric-to-dielectric bonding.

[0165] Figure 9 This is a schematic cross-sectional view of a semiconductor device provided in a second embodiment of this disclosure. (Refer to...) Figure 1A and Figure 9 As shown, the semiconductor device includes a first semiconductor structure 102, a second semiconductor structure 104, and a third semiconductor structure 106 stacked sequentially along a first direction; the first semiconductor structure 102 includes an analog-to-digital converter circuit 108 and an interface circuit 110, the second semiconductor structure 104 includes a memory array 112, and the third semiconductor structure 106 includes a peripheral circuit 114, which is coupled to the memory array 112 and the analog-to-digital converter circuit 108 respectively; the analog-to-digital converter circuit 108 is configured to receive analog information obtained by the memory array 112 performing operations; wherein, the first semiconductor structure 102 also includes a pad 124 coupled to the interface circuit 110, and the pad 124 is located on the side of the analog-to-digital converter circuit 108 opposite to each other along the first direction that is away from the second semiconductor structure 104.

[0166] In some embodiments, refer to Figure 1A , Figure 8 and Figure 9 As shown, the first semiconductor structure 102 further includes a first dielectric structure 604 and a ninth conductive structure 668; the first dielectric structure 604 is located between the pad 124 and the second semiconductor structure 104, and the ninth conductive structure 668 is located within the first dielectric structure 604; the second semiconductor structure 104 further includes a source line 670 coupled to the memory array 112, the source line 670 being located between the memory array 112 and the first semiconductor structure 102; wherein, the ninth conductive structure 668 is coupled to the source line 670 and the analog-to-digital converter circuit 108 respectively, and the analog calculation result is transmitted to the analog-to-digital converter circuit 108 through the source line 670 and the ninth conductive structure 668. It is understood that... Figure 9 In the embodiment shown, the source line 670 can be used as an analog information output terminal.

[0167] The ninth conductive structure 668 is used to connect the analog-to-digital converter circuit 108 and the source line 670. As an example, the ninth conductive structure 668 includes a ninth contact structure and a ninth interconnect structure; the ninth contact structure extends through the first dielectric layer 612 along a first direction, and the ninth interconnect structure is located in the first interconnect dielectric layer 614; wherein the opposite ends of the ninth contact structure along the first direction are connected to the analog-to-digital converter circuit 108 and the ninth interconnect structure, respectively. The analog-to-digital converter circuit 108 can be coupled to the source line 670 sequentially through the ninth conductive structure 668, a bonding contact crossing the first bonding interface, and other connection structures extending through the second semiconductor layer 626.

[0168] In some embodiments, the dimension of the ninth contact structure near the first semiconductor layer 602 in the second direction is less than or equal to the dimension of the ninth contact structure away from the first semiconductor layer 602 in the second direction. The ninth contact structure may be... Figure 8 The first contact structure 616 and the second contact structure 620 are formed simultaneously, thereby simplifying the manufacturing process.

[0169] Figure 10 This is a schematic cross-sectional view of a semiconductor device provided in the third embodiment of this disclosure. (Refer to...) Figure 1B and Figure 10 As shown, the semiconductor device includes a first semiconductor structure 102, a second semiconductor structure 104, and a third semiconductor structure 106 stacked sequentially along a first direction. The first semiconductor structure 102 includes an analog-to-digital converter circuit 108 and an interface circuit 110. The second semiconductor structure 104 includes a memory array 112. The third semiconductor structure 106 includes a peripheral circuit 114, which is coupled to the memory array 112 and the analog-to-digital converter circuit 108, respectively. The analog-to-digital converter circuit 108 is configured to receive analog information obtained by the memory array 112 performing operations. The third semiconductor structure 106 also includes a pad 124 coupled to the interface circuit 110. The pad 124 is located on the side of the peripheral circuit 114 opposite to each other along the first direction, away from the second semiconductor structure 104.

[0170] In some embodiments, the second semiconductor structure 104 further includes a sixth conductive structure 672 and a sixth connection structure 674; the sixth conductive structure 672 is located in the second dielectric structure 628, and the sixth connection structure 674 extends through the second semiconductor layer 626 along a first direction; the third semiconductor structure 106 further includes a third semiconductor layer 648, a third dielectric structure 650, a seventh conductive structure 676, and a seventh connection structure 678; the third semiconductor layer 648 is located between the pad 124 and the third dielectric structure 650, and a portion of the peripheral circuit 114 is located in the third semiconductor layer 648; the third dielectric structure 650 is located between the third semiconductor layer 648 and the second semiconductor structure 104, and the seventh conductive structure 676 is located in the third dielectric structure 650; the seventh connection structure 678 extends through the third semiconductor layer 648 along a first direction; wherein the pad 124 is coupled to the interface circuit 110 through the seventh connection structure 678, the seventh conductive structure 676, the sixth conductive structure 672, and the sixth connection structure 674.

[0171] In this embodiment, the pad 124 can be formed on the back side of the third semiconductor layer 648. The sixth connection structure 674, the sixth conductive structure 672, the seventh conductive structure 676, and the seventh connection structure 678 are used together to realize the electrical connection between the interface circuit 110 and the pad 124. For details regarding the second semiconductor layer 626, the second dielectric structure 628, the third semiconductor layer 648, and the third dielectric structure 650, please refer to... Figure 8 The relevant descriptions will not be repeated here.

[0172] As an example, the sixth conductive structure 672 includes a sixth contact structure and a sixth interconnect structure; the sixth contact structure extends through the second dielectric layer 642 along a first direction, and the sixth interconnect structure is located in the second interconnect dielectric layer 644; wherein, the opposite ends of the sixth contact structure along the first direction are respectively connected to the sixth connection structure 674 and the sixth interconnect structure. Here, the sixth contact structure can be formed simultaneously with the tenth contact structure, the fourth contact structure, and the fifth contact structure, thereby simplifying the manufacturing process.

[0173] As an example, the seventh conductive structure 676 includes a seventh contact structure and a seventh interconnect structure; the seventh contact structure extends through the third dielectric layer 654 along a first direction, and the seventh interconnect structure is located in the third interconnect dielectric layer 656; wherein, the opposite ends of the seventh contact structure along the first direction are respectively connected to the seventh connection structure 678 and the seventh interconnect structure. Here, the seventh contact structure can be formed simultaneously with the eighth contact structure, thereby simplifying the manufacturing process.

[0174] As an example, the third semiconductor layer 648 can be etched along the direction toward the back side of the third semiconductor layer 648 to form a through-silicon via (TSV) through the third semiconductor layer 648, and a conductive material can be filled into the TSV to form a seventh connection structure 678.

[0175] Understandable Figure 10 In the illustrated embodiment, the interface circuit 110 can sequentially pass through... Figure 8 The first conductive structure 606, the bonding contact spanning the first bonding interface, the sixth connection structure 674, the sixth conductive structure 672, the bonding contact spanning the second bonding interface, the seventh conductive structure 676, and the seventh connection structure 678 shown are coupled to the pad 124. Of course, in other embodiments, a fourth dielectric layer 680 and an interconnect structure located in the fourth dielectric layer 680 may also be formed between the third semiconductor layer 648 and the pad dielectric layer 624, and this interconnect structure is coupled to the seventh connection structure 678 and the pad 124 respectively.

[0176] In this embodiment, by providing corresponding connection structures and contact structures in the second semiconductor structure 104 and the third semiconductor structure 106, the interface circuit 110 can be led out to the pad 124 provided on the back side of the third semiconductor layer 648. Since the process nodes corresponding to the second semiconductor structure 104 and the third semiconductor structure 106 are larger, the process for forming the connection structures and contact structures has lower requirements for photolithography equipment; for example, lower-cost photolithography equipment can be used, thereby saving costs. Furthermore, the peripheral circuit 114 typically contains high-voltage devices (e.g., high-voltage transistors), and by providing the pad 124 on the back side of the third semiconductor layer 648, high-voltage design is facilitated.

[0177] Figure 11 This is a schematic cross-sectional view of a semiconductor device provided in the fourth embodiment of this disclosure. (Refer to...) Figure 1A and Figure 11 As shown, the semiconductor device includes a first semiconductor structure 102, a second semiconductor structure 104, and a third semiconductor structure 106 stacked sequentially along a first direction; the first semiconductor structure 102 includes an analog-to-digital converter circuit 108 and an interface circuit 110, the second semiconductor structure 104 includes a memory array 112, and the third semiconductor structure 106 includes a peripheral circuit 114, which is coupled to the memory array 112 and the analog-to-digital converter circuit 108 respectively; the analog-to-digital converter circuit 108 is configured to receive analog information obtained by the memory array 112 performing operations; wherein, the first semiconductor structure 102 also includes a pad 124 coupled to the interface circuit 110, and the pad 124 is located on the side of the analog-to-digital converter circuit 108 opposite to each other along the first direction that is away from the second semiconductor structure 104.

[0178] In some embodiments, refer to Figure 1A and Figure 11As shown, the first semiconductor structure 102 further includes a first dielectric structure 604, a first conductive structure 606, and a second conductive structure 608; the first dielectric structure 604 is located between the pad 124 and the first semiconductor layer 602, and the first conductive structure 606 and the second conductive structure 608 are both located in the first dielectric structure 604; wherein, the pad 124 is coupled to the interface circuit 110 through the first conductive structure 606, and the peripheral circuit 114 is coupled to the analog-to-digital conversion circuit 108 through the second conductive structure 608.

[0179] In some embodiments, refer to Figure 11 As shown, the first semiconductor structure 102 further includes a first connection structure 610; the first connection structure 610 extends through the first semiconductor layer 602 along a first direction; wherein, the peripheral circuit 114 is coupled to the second conductive structure 608 through the first connection structure 610.

[0180] As an example, refer to Figure 11 As shown, the first semiconductor layer 602 may include a front side and a back side opposite to each other along a first direction. The active region of the CMOS transistor may be formed on the front side of the first semiconductor layer 602. The pad dielectric layer 624 is formed on the front side of the first semiconductor layer 602, and the pad 124 is located in the pad dielectric layer 624.

[0181] The first dielectric structure 604 covers all circuits formed on the front side of the first semiconductor layer 602. The first dielectric structure 604 is used to physically isolate all conductive structures formed on the front side of the first semiconductor layer 602. The first dielectric structure 604 may include one or more film layers. As an example, see... Figure 11 As shown, the first dielectric structure 604 includes a first dielectric layer 612 and a first interconnect dielectric layer 614; the first dielectric layer 612 is located between the first semiconductor layer 602 and the first interconnect dielectric layer 614, and the first interconnect dielectric layer 614 is located between the first dielectric layer 612 and the pad 124. Specifically, the first interconnect dielectric layer 614 is located between the first dielectric layer 612 and the pad dielectric layer 624.

[0182] The first conductive structure 606 is used to electrically lead out the interface circuit 110. For example, the interface circuit 110 can be coupled to the pad 124 through the first conductive structure 606. As an example, the first conductive structure 606 includes a first contact structure and a first interconnect structure; the first contact structure extends through the first dielectric layer 612 along a first direction, and the first interconnect structure is located in the first interconnect dielectric layer 614; wherein the pad 124 is connected to the first interconnect structure, and the opposite ends of the first contact structure along the first direction are respectively connected to the first interconnect structure and the interface circuit 110.

[0183] The second conductive structure 608 is used to electrically lead out the analog-to-digital converter circuit 108. For example, the analog-to-digital converter circuit 108 can be coupled to the peripheral circuit 114 through the second conductive structure 608. As an example, the second conductive structure 608 includes a second contact structure 620, a third contact structure 684, and a conductive line 686; both the second contact structure 620 and the third contact structure 684 extend along a first direction through the first dielectric layer 612, and the conductive line 686 is located in the first interconnect dielectric layer 614; wherein, the two opposite ends of the second contact structure 620 along the first direction are respectively connected to the analog-to-digital converter circuit 108 and the conductive line 686, and the two opposite ends of the third contact structure 684 along the first direction are respectively connected to the first connection structure 610 and the conductive line 686. The analog-to-digital converter circuit 108 can be sequentially coupled to the peripheral circuit 114 through the second contact structure 620, the conductive line 686, the third contact structure 684, the first connection structure 610, the bonding contact crossing the first bonding interface, the third connection structure 632, the third conductive structure 630, and the bonding contact crossing the second bonding interface.

[0184] In this embodiment, by placing the analog-to-digital conversion circuit 108 and the interface circuit 110 on the front side of the first semiconductor layer 602, and by placing the pad 124 on the front side of the first semiconductor layer 602 (i.e., by extending the pad 124 from the front side of the first semiconductor layer 602), the external interface of the semiconductor device does not need to wrap back from the first bonding interface. This reduces the internal wiring of the first semiconductor structure 102, shortens the signal transmission distance, and thus reduces signal delay.

[0185] In some embodiments, refer to Figure 7 and Figure 11 As shown, the first semiconductor structure 102 further includes a second connection structure 688 and a controller 504; the second connection structure 688 extends through the first semiconductor layer 602 along a first direction, and a portion of the controller 504 is located in the first semiconductor layer 602; wherein, the peripheral circuit 114 is coupled to the controller 504 through the second connection structure 688. As an example, see... Figure 11 As shown, the controller 504 can be sequentially coupled to the peripheral circuit 114 through other conductive structures (not shown in the figure) on the front side of the first semiconductor layer 602, the second connection structure 688, the bonding contact across the first bonding interface, the fifth connection structure 640, the fifth conductive structure 638, and the bonding contact across the second bonding interface.

[0186] As an example, the first connection structure 610 and the second connection structure 688 can be formed simultaneously, thereby simplifying the fabrication process. The first connection structure 610 and the second connection structure 688 can be bonded to the carrier substrate after the front-side process of the first semiconductor layer 602 is completed. The substrate is then inverted so that the back side of the first semiconductor layer 602 faces upward. The first semiconductor layer 602 is etched along the direction towards the back side of the first semiconductor layer 602 to form a plurality of through-silicon vias (TSVs) penetrating the first semiconductor layer 602. Conductive material is filled into each TSV to form the first connection structure 610 and the second connection structure 688, respectively.

[0187] In some embodiments, refer to Figure 8 , Figure 9 , Figure 10 , Figure 11 As shown, the second semiconductor structure 104 further includes a fourth interconnect dielectric layer 658, which is located between the second semiconductor layer 626 and the first bonding layer 116. After forming a plurality of connection structures (e.g., a third connection structure 632, a fourth connection structure 636, and a fifth connection structure 640) in the second semiconductor layer 626, the fourth interconnect dielectric layer 658 and a plurality of interconnect structures can be formed on the back side of the second semiconductor layer 626. The interconnect structures in the fourth interconnect dielectric layer 658 are used to realize the electrical connection between the connection structures in the second semiconductor layer 626 and the first bonding contact 660.

[0188] In some embodiments, refer to Figure 8 , Figure 11 As shown, the first semiconductor structure 102 further includes a fifth interconnect dielectric layer 690, which is located between the first semiconductor layer 602 and the third bonding layer 120. After forming a plurality of connection structures (e.g., the first connection structure 610 and the second connection structure 688) in the first semiconductor layer 602, the fifth interconnect dielectric layer 690 and a plurality of interconnect structures can be formed on the back side of the first semiconductor layer 602. The interconnect structures in the fifth interconnect dielectric layer 690 are used to realize the electrical connection between the connection structures in the first semiconductor layer 602 and the third bonding contact 662.

[0189] Based on a concept similar to the embodiments described above, this disclosure also provides another semiconductor device.

[0190] Figure 12 This is a schematic cross-sectional view of another semiconductor device provided in an embodiment of this disclosure. (Refer to...) Figure 12As shown, the semiconductor device 700 includes a first semiconductor structure 702 and a second semiconductor structure 704 stacked sequentially along a first direction; the first semiconductor structure 702 includes a memory array 706 and a bonding layer 708; the bonding layer 708 is located on the side of the memory array 706 opposite to each other along the first direction, away from the second semiconductor structure 704; the second semiconductor structure 704 includes peripheral circuits 710 and pads 712; the peripheral circuits 710 are coupled to the memory array 706; wherein, the pads 712 are located on the side of the peripheral circuits 710 opposite to each other along the first direction, away from the first semiconductor structure 702; the pads 712 are used to output the calculation results obtained by the memory array 706 performing the calculation.

[0191] Semiconductor device 700 includes, but is not limited to, 3D NAND, and memory array 706 includes a three-dimensional NAND type memory array. Bonding layer 708 is used for bonding with other semiconductor structures (e.g., logic chips including analog-to-digital conversion circuits, front-end interfaces, and controllers), thereby realizing the bonding connection between 3D NAND and logic chips. By providing pads 712 on the side of the peripheral circuit 710 opposite each other along the first direction, away from the first semiconductor structure 702, the calculation results obtained by the memory array 706 can be output through the pads 712, thus reserving an external interface for the device formed by bonding 3D NAND with other logic chips.

[0192] In some embodiments, refer to Figure 12 As shown, the first semiconductor structure 702 further includes a first semiconductor layer 712, a first dielectric structure 714, a first conductive structure 716, and a first connection structure 718. The first semiconductor layer 712 is located between the bonding layer 708 and the first dielectric structure 714. The first dielectric structure 714 covers the stepped region of the memory array 706. The first conductive structure 716 is located in the first dielectric structure 714. The first connection structure 718 extends through the first semiconductor layer 712 along a first direction. The peripheral circuit 710 is coupled to the first connection structure 718 through the first conductive structure 716. The first connection structure 718 is used to transmit analog information obtained by the memory array 706 performing operations.

[0193] The first semiconductor layer 712 includes, but is not limited to, a substrate. The material of the substrate can be referred to the relevant description above, and will not be repeated here. The first semiconductor layer 712 may include a front side and a back side opposite to each other along a first direction. The memory array 706 may be formed on the front side of the first semiconductor layer 712. The structure of the memory array 706 can be referred to... Figure 2 and Figure 3 Related descriptions.

[0194] The first dielectric structure 714 covers the stepped region of the memory array 706 formed on the front side of the first semiconductor layer 712. The first dielectric structure 714 is used to physically isolate the various conductive structures formed on the front side of the first semiconductor layer 712. For example, the first conductive structure 716, the second conductive structure 720, the third conductive structure 724 and the fourth conductive structure 728 are physically isolated from each other through the first dielectric structure 714. The first dielectric structure 714 may include one or more film layers.

[0195] The first connection structure 718 is used to transmit analog information obtained by the memory array 706 performing operations. For example, the analog information obtained by the memory array 706 performing operations can be transmitted to the analog-to-digital conversion circuit in the logic chip through the first conductive structure 716, the first connection structure 718 and the bonding contact 744 in the bonding layer 708.

[0196] In some embodiments, the first semiconductor structure 702 further includes a second conductive structure 720 and a second connection structure 722; the second conductive structure 720 is located in the first dielectric structure 714, and the second connection structure 722 extends through the first semiconductor layer 712 along a first direction; wherein, the peripheral circuit 710 is coupled to the second connection structure 722 through the second conductive structure 720, and the second connection structure 722 is used to transmit a first control signal.

[0197] The second connection structure 722 is used to transmit the first control signal. For example, a first command sent by the controller in the logic chip can be transmitted to the peripheral circuit 710 through the bonding contact 744 in the bonding layer 708, the second connection structure 722, the second conductive structure 720, and the bonding contact across the bonding interface of the first semiconductor structure 702 and the second semiconductor structure 704. Here, the first control signal includes the first command.

[0198] In some embodiments, the first semiconductor structure 702 further includes a third conductive structure 724 and a third connection structure 726; the third conductive structure 724 is located in the first dielectric structure 714, and the third connection structure 726 extends through the first semiconductor layer 712 along a first direction; wherein, the peripheral circuit 710 is coupled to the third connection structure 726 through the third conductive structure 724, and the third connection structure 726 is used to transmit a second control signal different from the first control signal.

[0199] The third connection structure 726 is used to transmit a second control signal. For example, a second command sent by the controller in the logic chip can be transmitted to the peripheral circuit 710 through the bonding contact 744 in the bonding layer 708, the third connection structure 726, the third conductive structure 724, and the bonding contact across the bonding interface of the first semiconductor structure 702 and the second semiconductor structure 704. Here, the second control signal includes a second command, which is different from the first command.

[0200] In this embodiment of the disclosure, by setting a first line including a second connection structure 722 and a second conductive structure 720, and a second line including a third connection structure 726 and a third conductive structure 724, the first line and the second line can be used to transmit different types of commands. For example, the first line is used to transmit commands specified by the ONFI protocol, and the second line is used to transmit other custom commands. In this way, the standard interface can be expanded, and the 3D NAND can meet the signal interaction needs in different scenarios.

[0201] In some embodiments, the first semiconductor structure 702 further includes a fourth conductive structure 728 and a fourth connection structure 730; the fourth conductive structure 728 is located in the first dielectric structure 714, and the fourth connection structure 730 extends through the first semiconductor layer 712 along a first direction; the second semiconductor structure 704 further includes a second semiconductor layer 732, a second dielectric structure 734, a fifth conductive structure 736, and a fifth connection structure 738; the second semiconductor layer 732 is located between the pad 712 and the second dielectric structure 734, and a portion of the peripheral circuit 710 is located in the second semiconductor layer 732; the second dielectric structure 734 is located between the second semiconductor layer 732 and the first semiconductor structure 702, and the fifth conductive structure 736 is located in the second dielectric structure 734; the fifth connection structure 738 extends through the second semiconductor layer 732 along a first direction; wherein the pad 712 is connected to the fourth connection structure 730 through the fifth connection structure 738, the fifth conductive structure 736, and the fourth conductive structure 728.

[0202] The second semiconductor layer 732 includes, but is not limited to, a substrate. The material of the substrate can be referred to the relevant description above, and will not be repeated here. The second semiconductor layer 732 may include a front side and a back side opposite to each other along the first direction. The peripheral circuit 710 may be formed on the front side of the second semiconductor layer 732. For details on the peripheral circuit 710, please refer to... Figure 2 and Figure 4 Related descriptions.

[0203] The second dielectric structure 734 covers the peripheral circuit 710 formed on the front side of the second semiconductor layer 732. The second dielectric structure 734 is used to physically isolate the various conductive structures formed on the front side of the second semiconductor layer 732. For example, the fifth conductive structure 736 and the sixth conductive structure 742 mentioned below are physically isolated from each other through the second dielectric structure 734. The second dielectric structure 734 may include one or more film layers.

[0204] The pad dielectric layer 750 is located on the back side of the second semiconductor layer 732, and the pad 712 is located in the pad dielectric layer 750. The pad 712 can be coupled to the interface circuit in the logic chip through the fifth connection structure 738, the fifth conductive structure 736, the fourth conductive structure 728, and the fourth connection structure 730. Of course, in other embodiments, a dielectric layer 752 and an interconnect structure located in the dielectric layer 752 can also be formed between the second semiconductor layer 732 and the pad dielectric layer 750. This interconnect structure is coupled to the fifth connection structure 738 and the pad 712 respectively.

[0205] In this embodiment, by providing corresponding connection structures and conductive structures in the first semiconductor structure 702 and the second semiconductor structure 704, the pad 712 located on the back side of the second semiconductor layer 732 can be coupled to the interface circuit in the logic chip through the corresponding connection structures and conductive structures. Furthermore, the peripheral circuit 710 typically contains high-voltage devices (e.g., high-voltage transistors), and by placing the pad 712 on the back side of the second semiconductor layer 732, high-voltage design is facilitated.

[0206] In some embodiments, the first semiconductor structure 702 further includes a bit line 740 coupled to the memory array 706, the bit line 740 being located between the memory array 706 and the second semiconductor structure 704; the second semiconductor structure 704 further includes a sixth conductive structure 742; the sixth conductive structure 742 is located in the second dielectric structure 734; wherein, the peripheral circuit 710 is coupled to the bit line 740 through the sixth conductive structure 742. For more information on the bit line 740, please refer to... Figure 2 Bit line 222 shown Figure 5 The relevant descriptions of bit lines BL0 to BL2 are shown.

[0207] The sixth conductive structure 742 is used to realize the electrical connection between the bit line 740 and the peripheral circuit 710. The bit line 740 can be coupled to the peripheral circuit 710 in sequence through the bonding contacts that cross the bonding interface of the first semiconductor structure 702 and the second semiconductor structure 704 and the sixth conductive structure 742.

[0208] In some embodiments, the first semiconductor structure 702 further includes a source line 756 coupled to the memory array 706, the source line 756 being located between the memory array 706 and the bonding layer 708.

[0209] In some embodiments, the bonding layer 708 includes a bonding dielectric layer and bonding contacts 744 extending through the bonding dielectric layer in a first direction. The bonding layer 708 includes a plurality of bonding contacts 744, which are isolated from each other by the bonding dielectric layer. The bonding contacts 744 may include a conductive material, including but not limited to one or more of tungsten, cobalt, copper, aluminum, or polysilicon. As an example, the bonding contacts 744 of the bonding layer 708 may include copper, and the remaining area of ​​the bonding layer 708 may be formed of a dielectric, including but not limited to one or more of silicon oxide, silicon nitride, silicon oxynitride, or low-k dielectrics. The bonding contacts 744 in the bonding layer 708 and the surrounding dielectric can be used for hybrid bonding, simultaneously achieving metal-to-metal bonding and dielectric-to-dielectric bonding.

[0210] In some embodiments, the first semiconductor structure 702 further includes a first bonding layer 746, and the second semiconductor structure 704 further includes a second bonding layer 748. The first bonding layer 746 and the second bonding layer 748 are bonded together, thereby making the first semiconductor structure 702 and the second semiconductor structure 704 vertically connected. In the bonded first semiconductor structure 702 and second semiconductor structure 704, the first bonding layer 746 is located between the second semiconductor structure 704 and the memory array 706, and the second bonding layer 748 is located between the first bonding layer 746 and the peripheral circuit 710.

[0211] In some embodiments, the first semiconductor structure 702 further includes an interconnect dielectric layer 754 located between the bonding layer 708 and the first semiconductor layer 712. After forming a plurality of connection structures (e.g., a first connection structure 718, a second connection structure 722, a third connection structure 726, and a fourth connection structure 730) in the first semiconductor layer 712, the interconnect dielectric layer 754 and a plurality of interconnect structures may be formed on the back side of the first semiconductor layer 712. The interconnect structures in the interconnect dielectric layer 754 are used to realize electrical connections between the connection structures in the first semiconductor layer 712 and the bonding contacts 744.

[0212] Based on the above-described semiconductor device, this disclosure provides a method for manufacturing a semiconductor device. Figure 13 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. (Refer to...) Figure 13As shown, the fabrication method includes at least step S810: forming a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure stacked sequentially along a first direction; wherein, the first semiconductor structure includes an analog-to-digital conversion circuit and an interface circuit, the second semiconductor structure includes a memory array, and the third semiconductor structure includes peripheral circuits, the peripheral circuits being coupled to the memory array and the analog-to-digital conversion circuit respectively; the analog-to-digital conversion circuit is configured to receive analog information obtained by the memory array performing operations; the first semiconductor structure also includes pads coupled to the interface circuit, the pads being located on the side of the analog-to-digital conversion circuit opposite to each other along the first direction that is farther away from the second semiconductor structure; or the third semiconductor structure also includes pads coupled to the interface circuit, the pads being located on the side of the peripheral circuit opposite to each other along the first direction that is farther away from the second semiconductor structure.

[0213] Figures 14A to 14D This is a schematic diagram of the fabrication process of a semiconductor device provided in the first embodiment of this disclosure. The following will be combined with... Figure 13 , Figures 14A to 14D The method for fabricating a semiconductor device provided in the embodiments of this disclosure will be described by way of example.

[0214] In some embodiments, refer to Figures 14A to 14C As shown, step S810 includes: forming a first semiconductor structure 902, a second semiconductor structure 904, and a third semiconductor structure 906 respectively; bonding a first side of the second semiconductor structure 904 to the first semiconductor structure 902, and bonding a second side of the second semiconductor structure 904 to the third semiconductor structure 906; wherein the first side of the second semiconductor structure 904 and the second side of the second semiconductor structure 904 are opposite to each other along a first direction.

[0215] As an example, they can be formed as follows: Figure 14A The first semiconductor structure 902 shown is as follows: Figure 14B The second semiconductor structure 904 and the third semiconductor structure 906 are shown; the second side of the second semiconductor structure 904 is bonded to the third semiconductor structure 906, as shown. Figure 14B As shown; the first side of the second semiconductor structure 904 is bonded to the first semiconductor structure 902, as follows. Figure 14C As shown. In this example, the second side of the second semiconductor structure 904 can be bonded to the third semiconductor structure 906 first, and then the first side of the second semiconductor structure 904 can be bonded to the first semiconductor structure 902. It should be noted that... Figure 14C The front side of the first semiconductor structure 902 faces the second semiconductor structure 904, thus eliminating the need for a carrier substrate.

[0216] In some embodiments, forming a first semiconductor structure 902 includes: forming an interface circuit and an analog-to-digital conversion circuit based on a first semiconductor layer; wherein portions of the analog-to-digital conversion circuit and portions of the interface circuit are both located in the first semiconductor layer.

[0217] As an example, the formation process of the first semiconductor structure 902 includes: providing a first semiconductor layer; forming a structure such as... in the first semiconductor layer. Figure 14A The first active region 908 is shown; analog-to-digital conversion circuits, interface circuits, data processing circuits, and controllers can be formed on the front side of the first semiconductor layer based on the first active region 908. Although Figure 14A Only one first active region 908 is shown, but in actual applications, multiple first active regions 908 can be formed in the first semiconductor layer. Multiple CMOS transistors can be formed based on the multiple first active regions 908, and the multiple CMOS transistors can respectively constitute analog-to-digital conversion circuits and interface circuits, etc.

[0218] In some embodiments, forming the first semiconductor structure 902 further includes forming a first conductive structure on one side of the first semiconductor layer that is closer to the second semiconductor structure 904 on opposite sides along a first direction; wherein the first conductive structure is connected to the interface circuit.

[0219] As an example, the formation process of the first conductive structure includes: forming a first dielectric layer covering the front side of the first semiconductor layer; etching the first dielectric layer to form a contact hole penetrating the first dielectric layer; filling the contact hole with conductive material to form a first contact structure; forming a first interconnect dielectric layer covering the first dielectric layer and the first contact structure; etching the first interconnect dielectric layer to form an interconnect trench exposing the first contact structure; and filling the interconnect trench with conductive material to form a first interconnect structure. It is understood that the first conductive structure includes a first contact structure and a first interconnect structure, and the first conductive structure is used to electrically lead out the interface circuit.

[0220] In some embodiments, forming the first semiconductor structure 902 further includes forming a second conductive structure on one side of the first semiconductor layer opposite to each other along a first direction, closer to the second semiconductor structure 904; wherein the second conductive structure is connected to the analog-to-digital conversion circuit. Here, the second conductive structure is used to electrically lead out the analog-to-digital conversion circuit. The second conductive structure may be formed simultaneously with the first conductive structure, and the formation process of the second conductive structure can be referred to the relevant description of the formation process of the first conductive structure.

[0221] In some embodiments, forming the first semiconductor structure 902 further includes forming a pad 914 on one side of the first semiconductor layer that is away from the second semiconductor structure 904, opposite to each other along a first direction.

[0222] As an example, after bonding the first side of the second semiconductor structure 904 to the first semiconductor structure 902, a structure such as can be formed on the back side of the first semiconductor layer. Figure 14D Pad 914 is shown.

[0223] In some embodiments, forming a first semiconductor structure 902 further includes: forming a first connection structure extending through a first semiconductor layer in a first direction; wherein, the pad 914 is coupled to an interface circuit through the first connection structure.

[0224] As an example, after bonding the first side of the second semiconductor structure 904 to the first semiconductor structure 902, a through-silicon via (TSV) extending through the first semiconductor layer can be etched from the back side of the first semiconductor layer, exposing the first contact structure. Filling the TSV with conductive material forms a first connection structure, through which interface circuitry can be electrically led out. Next, a pad dielectric layer covering the back side of the first semiconductor layer and the first connection structure is formed. Etching the pad dielectric layer forms pad trenches exposing the first connection structure, and filling these trenches with conductive material forms pads 914 connecting the first connection structure. In practical applications, the first semiconductor layer can be thinned first, and then the pads can be formed on the back side of the first semiconductor layer.

[0225] In some embodiments, forming a second semiconductor structure 904 includes forming a memory array 910 based on a second semiconductor layer.

[0226] As an example, the formation process of the second semiconductor structure 904 includes: providing a second semiconductor layer; forming a structure such as... on the front side of the second semiconductor layer. Figure 14B The storage array 910 shown.

[0227] In some embodiments, forming the second semiconductor structure 904 further includes forming a third conductive structure, a fourth conductive structure, and a fifth conductive structure on one side of the second semiconductor layer opposite to each other along a first direction, away from the first semiconductor structure 902; wherein the third conductive structure is used to connect to an analog-to-digital conversion circuit; the fourth conductive structure and the fifth conductive structure are both used to connect to a controller, and the fourth conductive structure and the fifth conductive structure are respectively used to transmit different control signals.

[0228] As an example, the formation process of the third, fourth, and fifth conductive structures includes: forming a second dielectric layer covering a step region of the memory array 910; etching the second dielectric layer to form a plurality of contact holes penetrating the second dielectric layer; filling each contact hole with conductive material to form a tenth contact structure, a fourth contact structure, and a fifth contact structure, respectively; forming a second interconnect dielectric layer covering the second dielectric layer, the tenth contact structure, the fourth contact structure, and the fifth contact structure; etching the second interconnect dielectric layer to form a plurality of interconnect trenches, the plurality of interconnect trenches exposing the tenth contact structure, the fourth contact structure, and the fifth contact structure, respectively; and filling each interconnect trench with conductive material to form a third interconnect structure, a fourth interconnect structure, and a fifth interconnect structure, respectively. It is understood that the third conductive structure includes a tenth contact structure and a third interconnect structure, the fourth conductive structure includes a fourth contact structure and a fourth interconnect structure, and the fifth conductive structure includes a fifth contact structure and a fifth interconnect structure.

[0229] In some embodiments, forming a second semiconductor structure 904 further includes forming a third connection structure, a fourth connection structure, and a fifth connection structure extending through the second semiconductor layer along a first direction; wherein the third connection structure is connected to a third conductive structure, the fourth connection structure is connected to a fourth conductive structure, and the fifth connection structure is connected to a fifth conductive structure.

[0230] As an example, after bonding the second side of the second semiconductor structure 904 to the third semiconductor structure 906, a plurality of through-silicon vias (TSVs) extending through the second semiconductor layer can be etched from the back side of the second semiconductor layer, exposing the tenth contact structure, the fourth contact structure and the fifth contact structure respectively; by filling each TSV with conductive material, a third connection structure, a fourth connection structure and a fifth connection structure can be formed.

[0231] In some embodiments, forming a third semiconductor structure 906 includes: forming a peripheral circuit based on a third semiconductor layer; wherein the peripheral portion is located in the third semiconductor layer.

[0232] As an example, the formation process of the third semiconductor structure 906 includes: providing a third semiconductor layer; forming, for example, in the third semiconductor layer... Figure 14B The second active region 912 is shown; peripheral circuitry can be formed on the front side of the third semiconductor layer based on the second active region 912. Although Figure 14B Only one second active region 912 is shown, but in actual applications, multiple second active regions 912 can be formed in the third semiconductor layer, and peripheral circuits can be formed based on multiple second active regions 912.

[0233] In some embodiments, forming a third semiconductor structure 906 further includes forming an eighth conductive structure on one side of the third semiconductor layer that is closer to the second semiconductor structure 904 on opposite sides along a first direction; wherein the eighth conductive structure is connected to a peripheral circuit.

[0234] As an example, the formation process of the eighth conductive structure includes: forming a third dielectric layer covering the peripheral circuit; etching the third dielectric layer to form a contact hole penetrating the third dielectric layer; filling the contact hole with conductive material to form an eighth contact structure, the eighth contact structure connecting to the peripheral circuit; forming a third interconnect dielectric layer covering the third dielectric layer and the eighth contact structure; etching the third interconnect dielectric layer to form an interconnect trench exposing the eighth contact structure; and filling the interconnect trench with conductive material to form an eighth interconnect structure. It is understood that the eighth conductive structure includes both the eighth contact structure and the eighth interconnect structure.

[0235] After the second semiconductor structure 904 and the third semiconductor structure 906 are bonded, the peripheral circuit can be coupled to the bit line through the eighth conductive structure and the bonding contacts that cross the bonding interface between the second semiconductor structure 904 and the third semiconductor structure 906.

[0236] Understandably, by executing Figures 14A to 14D The process steps shown can form as follows: Figure 8 The semiconductor device shown.

[0237] Figures 15A to 15D This is a schematic diagram of the fabrication process of a semiconductor device provided in the second embodiment of this disclosure. The following will be combined with... Figure 13 , Figures 15A to 15D The method for fabricating a semiconductor device provided in the embodiments of this disclosure will be described by way of example.

[0238] In some embodiments, refer to Figures 15A to 15C As shown, step S810 includes: forming a first semiconductor structure 1002, a second semiconductor structure 1004, and a third semiconductor structure 1006 respectively; bonding a first side of the second semiconductor structure 1004 to the first semiconductor structure 1002, and bonding a second side of the second semiconductor structure 1004 to the third semiconductor structure 1006; wherein the first side of the second semiconductor structure 1004 and the second side of the second semiconductor structure 1004 are opposite to each other along a first direction.

[0239] As an example, they can be formed as follows: Figure 15A The first semiconductor structure 1002 shown is as follows: Figure 15B The second semiconductor structure 1004 and the third semiconductor structure 1006 are shown; the second side of the second semiconductor structure 1004 is bonded to the third semiconductor structure 1006, as shown. Figure 15BAs shown; the first side of the second semiconductor structure 1004 is bonded to the first semiconductor structure 1002, as follows. Figure 15C As shown. In this example, the second side of the second semiconductor structure 1004 can be bonded to the third semiconductor structure 1006 first, and then the first side of the second semiconductor structure 1004 can be bonded to the first semiconductor structure 1002. It should be noted that... Figure 15C The front side of the first semiconductor structure 1002 faces the second semiconductor structure 1004, thus eliminating the need for a carrier substrate.

[0240] In some embodiments, forming a first semiconductor structure 1002 includes: forming an interface circuit and an analog-to-digital conversion circuit based on a first semiconductor layer; wherein portions of the analog-to-digital conversion circuit and portions of the interface circuit are both located in the first semiconductor layer.

[0241] As an example, the formation process of the first semiconductor structure 1002 includes: providing a first semiconductor layer; forming a structure such as... in the first semiconductor layer. Figure 15A The first active region 1008 shown; based on the first active region 1008, analog-to-digital conversion circuits, interface circuits, data processing circuits, and controllers can be formed on the front side of the first semiconductor layer. Although Figure 15A Only one first active region 1008 is shown, but in actual applications, multiple first active regions 1008 can be formed in the first semiconductor layer. Multiple CMOS transistors can be formed based on the multiple first active regions 1008, and the multiple CMOS transistors can respectively constitute analog-to-digital conversion circuits and interface circuits, etc.

[0242] In some embodiments, forming the first semiconductor structure 1002 further includes forming a first conductive structure and a second conductive structure on one side of the first semiconductor layer that is opposite to each other along a first direction, closer to the second semiconductor structure 1004; wherein the first conductive structure is connected to an interface circuit, and the second conductive structure is connected to an analog-to-digital conversion circuit. The formation process of the first conductive structure and the second conductive structure can be referred to the relevant description above.

[0243] In some embodiments, forming a second semiconductor structure 1004 includes forming a memory array 1010 based on a second semiconductor layer.

[0244] As an example, the formation process of the second semiconductor structure 1004 includes: providing a second semiconductor layer; forming a structure on the front side of the second semiconductor layer as shown in the image. Figure 15B The storage array 1010 is shown.

[0245] In some embodiments, forming the second semiconductor structure 1004 further includes: forming a third conductive structure, a fourth conductive structure, a fifth conductive structure, and a sixth conductive structure on one side of the second semiconductor layer opposite to each other along a first direction, away from the first semiconductor structure 1002; wherein the third conductive structure is used to connect to an analog-to-digital conversion circuit; the fourth and fifth conductive structures are both used to connect to a controller, and the fourth and fifth conductive structures are respectively used to transmit different control signals; the sixth conductive structure is used to connect to the first conductive structure. Here, the sixth conductive structure can be formed simultaneously with the third, fourth, and fifth conductive structures, and the formation process of the third, fourth, and fifth conductive structures can be referred to the relevant description above.

[0246] In some embodiments, forming the second semiconductor structure 1004 further includes forming a third connection structure, a fourth connection structure, a fifth connection structure, and a sixth connection structure extending through the second semiconductor layer along a first direction; wherein the third connection structure is connected to the third conductive structure, the fourth connection structure is connected to the fourth conductive structure, the fifth connection structure is connected to the fifth conductive structure, and the sixth connection structure is connected to the sixth conductive structure. Here, the sixth connection structure may be formed simultaneously with the third, fourth, and fifth connection structures, and the formation process of the third, fourth, and fifth connection structures can be referred to the relevant description above.

[0247] In some embodiments, forming a third semiconductor structure 1006 includes: forming a peripheral circuit based on a third semiconductor layer; wherein the peripheral portion is located in the third semiconductor layer.

[0248] As an example, the formation process of the third semiconductor structure 1006 includes: providing a third semiconductor layer; forming, for example, in the third semiconductor layer... Figure 15B The second active region 1012 is shown; peripheral circuitry can be formed on the front side of the third semiconductor layer based on the second active region 1012. Although Figure 15B Only one second active region 1012 is shown, but in actual applications, multiple second active regions 1012 can be formed in the third semiconductor layer, and peripheral circuits can be formed based on multiple second active regions 1012.

[0249] In some embodiments, forming the third semiconductor structure 1006 further includes forming a seventh conductive structure and an eighth conductive structure on one side of the third semiconductor layer opposite to each other along a first direction, closer to the second semiconductor structure 1004; wherein the seventh conductive structure is used to connect to the sixth conductive structure, and the eighth conductive structure is used to connect to the peripheral circuit. Here, the seventh conductive structure can be formed simultaneously with the eighth conductive structure, and the formation process of the eighth conductive structure can be referred to the relevant description above.

[0250] After the second semiconductor structure 1004 and the third semiconductor structure 1006 are bonded, the seventh conductive structure can be coupled to the sixth conductive structure through bonding contacts that span the bonding interface between the second semiconductor structure 1004 and the third semiconductor structure 1006.

[0251] In some embodiments, forming a third semiconductor structure 1006 further includes forming a pad 1014 on one side of the third semiconductor layer that is away from the second semiconductor structure 1004, opposite to each other along a first direction.

[0252] As an example, after bonding the second side of the second semiconductor structure 1004 to the third semiconductor structure 1006, a structure such as can be formed on the back side of the third semiconductor layer. Figure 15D Pad 1014 is shown.

[0253] In some embodiments, forming a third semiconductor structure 1006 further includes forming a seventh connection structure extending through the third semiconductor layer along a first direction; wherein the seventh connection structure connects a seventh conductive structure and a pad 1014.

[0254] As an example, after bonding the second side of the second semiconductor structure 1004 to the third semiconductor structure 1006, a through-silicon via (TSV) extending through the third semiconductor layer can be etched from the back side of the third semiconductor layer, exposing the seventh contact structure. Filling the TSV with conductive material forms the seventh connection structure. Next, a pad dielectric layer covering the back side of the third semiconductor layer and the seventh connection structure is formed. The pad dielectric layer is etched to form pad trenches exposing the seventh connection structure, and filling the pad trenches with conductive material forms the pad 1014 connecting the seventh connection structure. In practical applications, the third semiconductor layer can be thinned first, and then the pads can be formed on the back side of the third semiconductor layer.

[0255] Understandably, by executing Figures 15A to 15D The process steps shown can form as follows: Figure 10 The semiconductor device shown.

[0256] Figures 16A to 16D This is a schematic diagram of the fabrication process of a semiconductor device according to the third embodiment of this disclosure. The following will be combined with... Figure 13 , Figures 16A to 16D The method for fabricating a semiconductor device provided in the embodiments of this disclosure will be described by way of example.

[0257] In some embodiments, step S810 includes: forming a first semiconductor structure 1102, a second semiconductor structure 1104, and a third semiconductor structure 1106 respectively; bonding a first side of the second semiconductor structure 1104 to the first semiconductor structure 1102, and bonding a second side of the second semiconductor structure 1104 to the third semiconductor structure 1106; wherein the first side of the second semiconductor structure 1104 and the second side of the second semiconductor structure 1104 are opposite to each other along a first direction.

[0258] As an example, they can be formed as follows: Figure 16A The first semiconductor structure 1102 shown is as follows: Figure 16B The second semiconductor structure 1104 and the third semiconductor structure 1106 are shown; the second side of the second semiconductor structure 1104 is bonded to the third semiconductor structure 1106, as shown. Figure 16B As shown; the first side of the second semiconductor structure 1104 is bonded to the first semiconductor structure 1102, as follows. Figure 16C As shown. In this example, the second side of the second semiconductor structure 1104 can be bonded to the third semiconductor structure 1106 first, and then the first side of the second semiconductor structure 1104 can be bonded to the first semiconductor structure 1102.

[0259] It should be noted that, Figure 16C In the first semiconductor structure 1102, the back side faces the second semiconductor structure 1104. To protect the structure already formed on the front side of the first semiconductor structure 1102, before bonding the first side of the second semiconductor structure 1104 to the first semiconductor structure 1102, the front side of the first semiconductor structure 1102 needs to be bonded to the carrier substrate 1116, such as... Figure 16A and Figure 16C As shown; after bonding the first side of the second semiconductor structure 1104 to the first semiconductor structure 1102, the carrier substrate 1116 can be removed, as shown. Figure 16D As shown.

[0260] In some embodiments, forming a first semiconductor structure 1102 includes: forming an interface circuit and an analog-to-digital conversion circuit based on a first semiconductor layer; wherein portions of the analog-to-digital conversion circuit and portions of the interface circuit are both located in the first semiconductor layer.

[0261] As an example, the formation process of the first semiconductor structure 1102 includes: providing a first semiconductor layer; forming a structure such as... in the first semiconductor layer. Figure 16A The first active region 1108 shown; analog-to-digital conversion circuits, interface circuits, data processing circuits, and controllers can be formed on the front side of the first semiconductor layer based on the first active region 1108. Although Figure 16AOnly one first active region 1108 is shown, but in actual applications, multiple first active regions 1108 can be formed in the first semiconductor layer. Multiple CMOS transistors can be formed based on the multiple first active regions 1108, and the multiple CMOS transistors can respectively constitute analog-to-digital conversion circuits and interface circuits, etc.

[0262] In some embodiments, forming the first semiconductor structure 1102 further includes forming a first conductive structure on one side of the first semiconductor layer that is away from the second semiconductor structure 1104, opposite to each other along a first direction; wherein the first conductive structure is connected to an interface circuit.

[0263] As an example, the formation process of the first conductive structure includes: forming a first dielectric layer covering the front side of the first semiconductor layer; etching the first dielectric layer to form a contact hole penetrating the first dielectric layer; filling the contact hole with conductive material to form a first contact structure; forming a first interconnect dielectric layer covering the first dielectric layer and the first contact structure; etching the first interconnect dielectric layer to form an interconnect trench exposing the first contact structure; and filling the interconnect trench with conductive material to form a first interconnect structure. It is understood that the first conductive structure includes a first contact structure and a first interconnect structure, and the first conductive structure is used to electrically lead out the interface circuit.

[0264] In some embodiments, forming the first semiconductor structure 1102 further includes forming a pad 1114 on one side of the first semiconductor layer that is away from the second semiconductor structure 1104, opposite to each other along a first direction.

[0265] As an example, after bonding the first side of the second semiconductor structure 1104 to the first semiconductor structure 1102, a structure such as can be formed on the front side of the first semiconductor layer. Figure 16D The pad shown is 1114.

[0266] In some embodiments, a pad 1114 is formed on one side of the first semiconductor layer opposite to each other along a first direction, away from the second semiconductor structure 1104, including: forming the pad 1114 on one side of the first conductive structure opposite to each other along a first direction, away from the first semiconductor layer; wherein the pad 1114 is connected to the first conductive structure.

[0267] As an example, after forming the first conductive structure, a pad dielectric layer covering the first interconnect dielectric layer and the first interconnect structure can be formed; the pad dielectric layer is etched to form a pad trench exposing the first interconnect structure, and a conductive material is filled into the pad trench to form a pad 1114 connecting the first interconnect structure.

[0268] In some embodiments, forming a second semiconductor structure 1104 includes forming a memory array 1110 based on a second semiconductor layer.

[0269] As an example, the formation process of the second semiconductor structure 1104 includes: providing a second semiconductor layer; forming a structure on the front side of the second semiconductor layer as shown in the image. Figure 16B The storage array 1110 shown is shown.

[0270] In some embodiments, forming a third semiconductor structure 1106 includes: forming a peripheral circuit based on a third semiconductor layer; wherein the peripheral portion is located in the third semiconductor layer.

[0271] As an example, the formation process of the third semiconductor structure 1106 includes: providing a third semiconductor layer; forming, for example, in the third semiconductor layer... Figure 16B The second active region 1112 is shown; peripheral circuitry can be formed on the front side of the third semiconductor layer based on the second active region 1112. Although Figure 16B Only one second active region 1112 is shown, but in actual applications, multiple second active regions 1112 can be formed in the third semiconductor layer, and peripheral circuits can be formed based on multiple second active regions 1112.

[0272] Understandably, by executing Figures 16A to 16D The process steps shown can form as follows: Figure 11 The semiconductor device shown.

[0273] Based on the above-described semiconductor device, this disclosure also provides a packaging structure.

[0274] Figure 17 This is a schematic diagram of a packaging structure provided in an embodiment of this disclosure. (Refer to...) Figure 17 As shown, the packaging structure 1200 includes: a packaging substrate 1202, a semiconductor device 1204, and a molding compound 1206; the semiconductor device 1204 is disposed on the packaging substrate 1202; and the molding compound 1206 encapsulates the semiconductor device 1204.

[0275] In some embodiments, refer to Figure 17 As shown, the packaging substrate 1202 includes a base layer 1208 and a redistribution layer 1210 (interposer) formed on the base layer. A connection circuit is formed in the redistribution layer 1210, and a semiconductor device 1204 is disposed on the side of the redistribution layer 1210 away from the base layer 1208.

[0276] Here, semiconductor device 1204 can be any of the semiconductor devices in the above embodiments. Since the packaging structure in this embodiment adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0277] Based on the above-described semiconductor devices, this disclosure also provides an electronic device.

[0278] Figure 18 A schematic diagram of an exemplary electronic device having a semiconductor device provided for embodiments of this disclosure. (Refer to...) Figure 18 As shown, the electronic device 1400 includes a host 1402 and a semiconductor device 1404; the host 1402 is coupled to the semiconductor device 1404.

[0279] In this embodiment of the disclosure, the electronic device 1400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0280] like Figure 18 As shown, semiconductor device 1404 may include one or more memory devices 1406 and memory controller 1408. Host 1402 may include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). Host 1402 may be configured to send data to semiconductor device 1404 or receive data from semiconductor device 1404. Memory device 1406 includes a memory array and peripheral circuitry coupled to the memory array. The memory controller 1408 here may be a controller as described in the above-described embodiment of the semiconductor device.

[0281] In some embodiments, memory controller 1408 is coupled to memory device 1406 and host 1402 and is configured to control memory device 1406. Memory controller 1408 can manage data stored in memory device 1406 and communicate with host 1402. In some embodiments, memory controller 1408 is designed to operate in low duty cycle environments, such as in secure digital cards, compact flash cards (CFC), universal serial bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 1408 is designed to operate in high duty cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0282] In some embodiments, the memory controller 1408 and one or more memory devices 1406 can be integrated into various types of storage devices, that is, the semiconductor device 1404 can be implemented and packaged into different types of end electronic products.

[0283] In such Figure 19 In one example shown, the memory controller 1408 and a single memory device 1406 can be integrated into a memory card 1502. The memory card 1502 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 1502 may also include a connection between the memory card 1502 and a host device (e.g., Figure 18 The memory card connector 1504 is coupled to the host 1402.

[0284] In such Figure 20 In another example shown, the memory controller 1408 and multiple memory devices 1406 can be integrated into the SSD 1506. The SSD 1506 may also include components for connecting the SSD 1506 to host devices (e.g., ...). Figure 18 The SSD connector 1508 is coupled to the host 1402. In some embodiments, the storage capacity and / or operating speed of the SSD 1506 is greater than the storage capacity and / or operating speed of the memory card 1502.

[0285] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0286] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0287] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0288] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0289] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor structure, a second semiconductor structure, and a third semiconductor structure are stacked sequentially along a first direction; the first semiconductor structure includes an analog-to-digital conversion circuit and an interface circuit, the second semiconductor structure includes a memory array, and the third semiconductor structure includes peripheral circuitry, the peripheral circuitry being coupled to the memory array and the analog-to-digital conversion circuitry respectively. The analog-to-digital conversion circuit is configured to receive analog information obtained by the storage array performing operations; The first semiconductor structure further includes a pad coupled to the interface circuit, the pad being located on the side of the analog-to-digital conversion circuit opposite to each other along the first direction that is farther away from the second semiconductor structure; or the third semiconductor structure further includes a pad coupled to the interface circuit, the pad being located on the side of the peripheral circuit opposite to each other along the first direction that is farther away from the second semiconductor structure.

2. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes a first semiconductor layer; the first semiconductor layer is located between the pad and the second semiconductor structure, and both the analog-to-digital conversion circuit portion and the interface circuit portion are located in the first semiconductor layer.

3. The semiconductor device according to claim 2, characterized in that, The first semiconductor structure further includes a first dielectric structure, a first conductive structure, and a second conductive structure; the first dielectric structure is located between the first semiconductor layer and the second semiconductor structure, and the first conductive structure and the second conductive structure are both located in the first dielectric structure; wherein, the pads are coupled to the interface circuit through the first conductive structure, and the peripheral circuits are coupled to the analog-to-digital conversion circuit through the second conductive structure.

4. The semiconductor device according to claim 3, characterized in that, The first semiconductor structure further includes a first connection structure; the first connection structure extends through the first semiconductor layer along the first direction; wherein, the opposite ends of the first connection structure along the first direction are respectively connected to the pad and the first conductive structure.

5. The semiconductor device according to claim 4, characterized in that, The first dielectric structure includes a first dielectric layer and a first interconnect dielectric layer; the first dielectric layer is located between the first semiconductor layer and the first interconnect dielectric layer, and the first interconnect dielectric layer is located between the first dielectric layer and the second semiconductor structure; The first conductive structure includes a first contact structure and a first interconnect structure; the first contact structure extends through the first dielectric layer along the first direction, and the first interconnect structure is located in the first interconnect dielectric layer; wherein, the opposite ends of the first contact structure along the first direction are respectively connected to the first connection structure and the first interconnect structure; The second conductive structure includes a second contact structure and a second interconnect structure; the second contact structure extends through the first dielectric layer along the first direction, and the second interconnect structure is located in the first interconnect dielectric layer; wherein, the two opposite ends of the second contact structure along the first direction are respectively connected to the analog-to-digital conversion circuit and the second interconnect structure.

6. The semiconductor device according to claim 2, characterized in that, The first semiconductor structure further includes a first dielectric structure, a first conductive structure, and a second conductive structure; the first dielectric structure is located between the pad and the first semiconductor layer, and the first conductive structure and the second conductive structure are both located in the first dielectric structure; wherein, the pad is coupled to the interface circuit through the first conductive structure, and the peripheral circuit is coupled to the analog-to-digital conversion circuit through the second conductive structure.

7. The semiconductor device according to claim 6, characterized in that, The first semiconductor structure further includes a first connection structure; the first connection structure extends through the first semiconductor layer along the first direction; wherein the peripheral circuit is coupled to the second conductive structure through the first connection structure.

8. The semiconductor device according to claim 7, characterized in that, The first dielectric structure includes a first dielectric layer and a first interconnect dielectric layer; the first dielectric layer is located between the first semiconductor layer and the first interconnect dielectric layer, and the first interconnect dielectric layer is located between the first dielectric layer and the pad; The first conductive structure includes a first contact structure and a first interconnect structure; the first contact structure extends through the first dielectric layer along the first direction, and the first interconnect structure is located in the first interconnect dielectric layer; wherein, the pad connects to the first interconnect structure, and the opposite ends of the first contact structure along the first direction are respectively connected to the first interconnect structure and the interface circuit; The second conductive structure includes a second contact structure, a third contact structure, and a conductive line; both the second contact structure and the third contact structure extend through the first dielectric layer along the first direction, and the conductive line is located in the first interconnect dielectric layer; wherein, the two opposite ends of the second contact structure along the first direction are respectively connected to the analog-to-digital conversion circuit and the conductive line, and the two opposite ends of the third contact structure along the first direction are respectively connected to the first connection structure and the conductive line.

9. The semiconductor device according to claim 7, characterized in that, The first semiconductor structure further includes a second connection structure and a controller; the second connection structure extends through the first semiconductor layer along the first direction, and a portion of the controller is located in the first semiconductor layer; wherein the peripheral circuit is coupled to the controller through the second connection structure.

10. The semiconductor device according to claim 1, characterized in that, The second semiconductor structure further includes a second semiconductor layer, a second dielectric structure, a third conductive structure, and a third connection structure; the second semiconductor layer is located between the first semiconductor structure and the second dielectric structure, the second dielectric structure covers the stepped region of the memory array, the third conductive structure is located in the second dielectric structure, and the third connection structure extends through the second semiconductor layer along the first direction; wherein, the peripheral circuit is coupled to the analog-to-digital conversion circuit through the third conductive structure and the third connection structure.

11. The semiconductor device according to claim 10, characterized in that, The first semiconductor structure further includes a controller; a portion of the controller is located within the first semiconductor layer; The second semiconductor structure further includes a fourth conductive structure and a fourth connection structure; the fourth conductive structure is located in the second dielectric structure, and the fourth connection structure extends through the second semiconductor layer along the first direction; wherein the controller is coupled to the peripheral circuit through the fourth connection structure and the fourth conductive structure.

12. The semiconductor device according to claim 11, characterized in that, The second semiconductor structure further includes a fifth conductive structure and a fifth connection structure; the fifth conductive structure is located in the second dielectric structure, and the fifth connection structure extends through the second semiconductor layer along the first direction; wherein, the controller is also coupled to the peripheral circuit through the fifth connection structure and the fifth conductive structure; the fifth connection structure and the fourth connection structure are respectively used to transmit different control signals.

13. The semiconductor device according to claim 10, characterized in that, The second semiconductor structure further includes a sixth conductive structure and a sixth connection structure; the sixth conductive structure is located in the second dielectric structure, and the sixth connection structure extends through the second semiconductor layer along the first direction; The third semiconductor structure further includes a third semiconductor layer, a third dielectric structure, a seventh conductive structure, and a seventh connection structure; the third semiconductor layer is located between the pad and the third dielectric structure, and a portion of the peripheral circuit is located within the third semiconductor layer; The third dielectric structure is located between the third semiconductor layer and the second semiconductor structure, and the seventh conductive structure is located within the third dielectric structure; The seventh connection structure extends through the third semiconductor layer along the first direction; wherein the pad is coupled to the interface circuit through the seventh connection structure, the seventh conductive structure, the sixth conductive structure, and the sixth connection structure.

14. The semiconductor device according to claim 13, characterized in that, The second semiconductor structure further includes a bit line coupled to the memory array, the bit line being located between the memory array and the third semiconductor structure; The third semiconductor structure further includes an eighth conductive structure; the eighth conductive structure is located in the third dielectric structure; wherein the peripheral circuit is coupled to the bit line through the eighth conductive structure.

15. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes a first dielectric structure and a ninth conductive structure; the first dielectric structure is located between the pad and the second semiconductor structure, and the ninth conductive structure is located within the first dielectric structure; The second semiconductor structure further includes a source line coupled to the memory array, the source line being located between the memory array and the first semiconductor structure; wherein, the ninth conductive structure is coupled to the source line and the analog-to-digital conversion circuit respectively, and the analog calculation result is transmitted to the analog-to-digital conversion circuit through the source line and the ninth conductive structure.

16. The semiconductor device according to claim 1, characterized in that, The first side of the second semiconductor structure is bonded to the first semiconductor structure, and the second side of the second semiconductor structure is bonded to the third semiconductor structure; wherein the first side and the second side of the second semiconductor structure are opposite to each other along the first direction.

17. The semiconductor device according to claim 1, characterized in that, The storage array includes a three-dimensional NAND type storage array.

18. A semiconductor device, characterized in that, include: A first semiconductor structure and a second semiconductor structure are stacked sequentially along a first direction; The first semiconductor structure includes a memory array and a bonding layer; the bonding layer is located on one side of the memory array opposite to each other along the first direction, away from the second semiconductor structure. The second semiconductor structure includes peripheral circuitry and pads; the peripheral circuitry is coupled to the memory array; wherein the pads are located on the side of the peripheral circuitry opposite to each other along the first direction, away from the first semiconductor structure; the pads are used to output the computation results obtained by the memory array performing operations.

19. The semiconductor device according to claim 18, characterized in that, The first semiconductor structure further includes a first semiconductor layer, a first dielectric structure, a first conductive structure, and a first connection structure; the first semiconductor layer is located between the first bonding layer and the first dielectric structure, the first dielectric structure covers the stepped region of the memory array, the first conductive structure is located in the first dielectric structure, and the first connection structure extends through the first semiconductor layer along the first direction; wherein, the peripheral circuit is coupled to the first connection structure through the first conductive structure, and the first connection structure is used to transmit analog information obtained by the memory array performing operations.

20. The semiconductor device according to claim 19, characterized in that, The first semiconductor structure further includes a second conductive structure and a second connection structure; the second conductive structure is located in the first dielectric structure, and the second connection structure extends through the first semiconductor layer along the first direction; wherein the peripheral circuit is coupled to the second connection structure through the second conductive structure, and the second connection structure is used to transmit a first control signal.

21. The semiconductor device according to claim 20, characterized in that, The first semiconductor structure further includes a third conductive structure and a third connection structure; the third conductive structure is located in the first dielectric structure, and the third connection structure extends through the first semiconductor layer along the first direction; wherein the peripheral circuit is coupled to the third connection structure through the third conductive structure, and the third connection structure is used to transmit a second control signal different from the first control signal.

22. The semiconductor device according to claim 19, characterized in that, The first semiconductor structure further includes a fourth conductive structure and a fourth connection structure; the fourth conductive structure is located in the first dielectric structure, and the fourth connection structure extends through the first semiconductor layer along the first direction; The second semiconductor structure further includes a second semiconductor layer, a second dielectric structure, a fifth conductive structure, and a fifth connection structure; the second semiconductor layer is located between the pad and the second dielectric structure, and a portion of the peripheral circuit is located within the second semiconductor layer; The second dielectric structure is located between the second semiconductor layer and the first semiconductor structure, and the fifth conductive structure is located in the second dielectric structure; The fifth connection structure extends through the second semiconductor layer along the first direction; wherein the pad is connected to the fourth connection structure through the fifth connection structure, the fifth conductive structure, and the fourth conductive structure.

23. The semiconductor device according to claim 22, characterized in that, The first semiconductor structure further includes a bit line coupled to the memory array, the bit line being located between the memory array and the second semiconductor structure; The second semiconductor structure further includes a sixth conductive structure; the sixth conductive structure is located in the second dielectric structure; wherein the peripheral circuit is coupled to the bit line through the sixth conductive structure.

24. The semiconductor device according to claim 18, characterized in that, The bonding layer includes a bonding medium layer and bonding contacts, wherein the bonding contacts extend through the bonding medium layer along the first direction.

25. The semiconductor device according to claim 18, characterized in that, The storage array includes a three-dimensional NAND type storage array.

26. A method for fabricating a semiconductor device, characterized in that, include: A first semiconductor structure, a second semiconductor structure, and a third semiconductor structure are formed and stacked sequentially along a first direction; wherein, the first semiconductor structure includes an analog-to-digital converter circuit and an interface circuit, the second semiconductor structure includes a memory array, and the third semiconductor structure includes peripheral circuits, the peripheral circuits being respectively coupled to the memory array and the analog-to-digital converter circuit; The analog-to-digital conversion circuit is configured to receive analog information obtained by the memory array performing operations; the first semiconductor structure further includes pads coupled to the interface circuit, the pads being located on the side of the analog-to-digital conversion circuit opposite to each other along the first direction that is away from the second semiconductor structure; or the third semiconductor structure further includes pads coupled to the interface circuit, the pads being located on the side of the peripheral circuit opposite to each other along the first direction that is away from the second semiconductor structure.

27. The manufacturing method according to claim 26, characterized in that, The formation of the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure stacked sequentially along the first direction includes: The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are respectively formed; The first side of the second semiconductor structure is bonded to the first semiconductor structure, and the second side of the second semiconductor structure is bonded to the third semiconductor structure; wherein the first side and the second side of the second semiconductor structure are opposite to each other along the first direction.

28. The manufacturing method according to claim 26, characterized in that, Forming the first semiconductor structure includes: The interface circuit and the analog-to-digital conversion circuit are formed on the first semiconductor layer; wherein, portions of the analog-to-digital conversion circuit and portions of the interface circuit are both located in the first semiconductor layer; The pad is formed on the side of the first semiconductor layer opposite to each other along the first direction, away from the second semiconductor structure.

29. The manufacturing method according to claim 28, characterized in that, Forming the first semiconductor structure further includes: A first connection structure is formed extending through the first semiconductor layer along the first direction; wherein the pads are coupled to the interface circuit through the first connection structure.

30. The manufacturing method according to claim 28, characterized in that, Forming the first semiconductor structure further includes: A first conductive structure is formed on one side of the first semiconductor layer that is opposite to the second semiconductor structure along the first direction; wherein the first conductive structure is connected to the interface circuit. The step of forming the pad on the side of the first semiconductor layer opposite to each other along the first direction, away from the second semiconductor structure, includes: The pad is formed on one side of the first conductive structure opposite to each other along the first direction, away from the first semiconductor layer; wherein the pad is connected to the first conductive structure.

31. The manufacturing method according to claim 26, characterized in that, Forming the third semiconductor structure includes: The peripheral circuit is formed based on a third semiconductor layer; wherein the peripheral portion is located within the third semiconductor layer; The pad is formed on the side of the third semiconductor layer opposite to each other along the first direction, away from the second semiconductor structure.

32. A packaging structure, characterized in that, include: The packaging substrate, the semiconductor device as described in any one of claims 1 to 25, and the molding layer; The semiconductor device is disposed on the packaging substrate; The molding compound encapsulates the semiconductor device.

33. An electronic device, characterized in that, include: The host computer and the semiconductor device as described in any one of claims 1 to 25; The host is coupled to the semiconductor device.

Images