Chip inductance packaging structure and preparation method thereof

Abstract

The application provides a chip inductance packaging structure and a preparation method thereof, and relates to the technical field of chip packaging. The chip inductance packaging structure comprises a substrate, a first inductance coil, a first chip, a second chip and a plastic packaging layer. The front surface of the substrate is provided with a first groove. The first inductance coil is arranged in the first groove. The back surface of the first chip is attached to the front surface of the substrate and covers the first groove. The first chip is further provided with a conductive column. The second chip is attached to the front surface of the substrate. The plastic packaging layer covers the first chip and the second chip. Compared with the prior art, the application adopts a vertically placed inductance coil, which can greatly improve the inductance and has smaller parasitic parameters. The inductance coil is accommodated by the groove on the substrate, which effectively reduces the occupied volume of the inductance, is beneficial to reducing the overall packaging volume and realizes the miniaturization of the packaging structure.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a chip inductor packaging structure and its fabrication method. Background Technology

[0002] Inductors are core passive components in wireless communication devices and RF chips. Relying on their own electromagnetic induction characteristics, they meet the core requirements of high-frequency transmission, reception, and filtering of wireless signals. Integrating inductors into chips can realize functions such as power supply voltage regulation, RF frequency selection and matching, and circuit anti-interference. They are indispensable passive components in analog, RF, and power management chips. They can be paired with capacitors to form LC filter circuits and DC-DC step-down circuits. At the same time, they can realize functions such as energy storage to buffer current fluctuations, filter power supply ripple, and high-frequency noise.

[0003] Integrated inductor packaging solutions have emerged in existing chip packaging structures. However, these integrated inductors have the following drawbacks: small inductance, large area occupation, and severe parasitic and loss problems, which seriously restrict their application in high-efficiency power and high-performance radio frequency scenarios. Summary of the Invention

[0004] The purpose of this invention is to provide a chip inductor packaging structure and a method for preparing the chip inductor packaging structure, which can significantly increase inductance, reduce occupied area, and reduce parasitic parameters.

[0005] In a first aspect, embodiments of the present invention provide a chip inductor packaging structure, comprising: The substrate has a first groove on its front side; A first inductor coil is disposed in the first groove and extends out of the first groove, and the central axis of the first inductor coil is perpendicular to the front side of the substrate; The first chip is back-mounted on the front side of the substrate and covers the first groove. An electrical connection layer is provided on the front side of the first chip. The electrical connection layer is provided with connecting lines and is electrically connected to the substrate through the connecting lines. The first chip is also provided with conductive pillars that extend to the electrical connection layer and are electrically connected to the first inductor coil. The second chip is mounted on the front side of the substrate and is spaced apart from the first chip, and the second chip is electrically connected to the substrate. A molding layer is disposed on the front side of the substrate and covers the first chip and the second chip.

[0006] In an optional embodiment, the first chip is further provided with a second inductor coil, one end of which is connected to the first inductor coil, and the other end of which is connected to the conductive post, so that the conductive post is electrically connected to the first inductor coil.

[0007] In an optional embodiment, the center lines of the first inductor and the second inductor overlap, and the first inductor and the second inductor are spliced ​​together to form a tapered coil.

[0008] In an optional embodiment, the back of the first chip is further provided with a plurality of metal pillars, which extend into the first groove and surround the first inductor coil and the second inductor coil.

[0009] In an optional embodiment, a second groove is further provided on the back side of the first chip, the second groove being connected to the first groove, the first inductor coil extending into the second groove, and the conductive post extending to the inner wall of the second groove and making electrical contact with the portion of the first inductor coil extending into the second groove.

[0010] In an optional embodiment, a first structural post is further provided in the first groove, the surface of the first structural post is covered with a first metal layer, and the first inductor coil is disposed around the first structural post.

[0011] In an optional embodiment, a second structural post is provided in the second groove, the surface of the second structural post is covered with a second metal layer, and the first inductor coil is disposed around the second structural post.

[0012] In an optional embodiment, the first structural column and the second structural column are coaxially arranged and correspondingly joined to join the first metal layer and the second metal layer.

[0013] In an optional embodiment, the first structural column and the second structural column are coaxially arranged and spaced apart from each other, so as to form a barrier gap between the first metal layer and the second metal layer.

[0014] In an optional embodiment, a thin-film metal layer is further formed on the inner sidewall of the second groove, the thin-film metal layer being spaced apart from the first inductor coil and the conductive post.

[0015] In an optional embodiment, the width of the second groove is smaller than the width of the first groove, and a plurality of metal pillars are also provided on the back side of the first chip, the plurality of metal pillars surrounding the second groove.

[0016] In an optional embodiment, the first groove is filled with a covering adhesive layer that covers the first inductor coil; and / or, the encapsulation layer extends into the first groove and covers the first inductor coil.

[0017] In an optional embodiment, the bottom wall of the first groove is further provided with a coil pad, and the back side of the substrate is further provided with an electrical connection pad. The first inductor coil is connected to the coil pad, and the coil pad is electrically connected to the electrical connection pad.

[0018] In another aspect, embodiments of the present invention provide a method for fabricating a chip inductor packaging structure, used to fabricate the aforementioned chip inductor packaging structure, the fabrication method comprising: A first groove is formed on the front side of the substrate; A first inductor coil is formed in the first groove, wherein the first inductor coil extends out of the first groove and the central axis of the first inductor coil is perpendicular to the front side of the substrate; The back side of the first chip is attached to the front side of the substrate and covers the first groove. An electrical connection layer is provided on the front side of the first chip, and a conductive post is also provided inside the first chip. The conductive post extends to the electrical connection layer and is electrically connected to the first inductor coil. A wire bonding process is performed on the electrical connection layer to form a connection line connected to the substrate, so that the electrical connection layer is electrically connected to the substrate through the connection line. A second chip is mounted on the front side of the substrate, wherein the second chip is spaced apart from the first chip and is electrically connected to the substrate; A molding compound is formed on the front side of the substrate, wherein the molding compound covers the first chip and the second chip.

[0019] In an optional implementation, prior to the step of forming the first inductor coil in the first groove, the method further includes: A first structural column is formed in the first groove; A first metal layer is formed by coating the surface of the first structural column.

[0020] In an optional embodiment, prior to the step of attaching the back side of the first chip to the front side of the substrate, the method further includes: A wafer having a plurality of first chips is provided, wherein a first electrical connection layer is formed on the front side of each first chip, and a conductive pillar is formed within each first chip; The front side of the wafer is attached to the carrier; Metal pillars are formed on the back side of the wafer; A second groove and a second structural pillar are formed on the back side of the wafer, wherein the metal pillar surrounds the second groove and the second structural pillar is located in the first groove; A second metal layer is formed by coating the surface of the second structural column; The first chip is cut into individual pieces, and the carrier is removed.

[0021] The beneficial effects of the embodiments of the present invention include: The chip inductor packaging structure provided in this embodiment of the invention has a first groove on the front side of the substrate. A first inductor coil is placed in the first groove and extends out of the groove, with the central axis of the first inductor coil perpendicular to the front side of the substrate, achieving vertical placement. Simultaneously, the back side of the first chip is mounted on the front side of the substrate, covering the first groove. An electrical connection layer is provided on the front side of the first chip, which is electrically connected to the substrate via connecting wires. Conductive pillars are also provided within the first chip, and these conductive pillars are electrically connected to the first inductor coil, thus ensuring electrical connection between the electrical connection layer on the front side of the first chip and the first inductor coil. A second chip is mounted on the front side of the substrate, and a molding compound covers both the first and second chips.

[0022] Compared to existing technologies, the chip inductor packaging structure provided in this invention uses a vertically placed inductor coil, which significantly increases the inductance and reduces parasitic parameters. Furthermore, by using slots in the substrate to accommodate the inductor coil, the volume occupied by the inductor is effectively reduced, which helps to reduce the overall package size and achieve miniaturization of the packaging structure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the chip inductor packaging structure provided in the first embodiment of the present invention; Figure 2 for Figure 1 A magnified view of a section at point II; Figure 3 This is a schematic diagram of the structure corresponding to step S1 in the method for preparing the chip inductor packaging structure provided in the first embodiment of the present invention. Figure 4 This is a schematic diagram of the structure corresponding to step S2 in the method for preparing the chip inductor packaging structure provided in the first embodiment of the present invention; Figure 5 This is a schematic diagram of the structure corresponding to step S3 in the method for preparing the chip inductor packaging structure provided in the first embodiment of the present invention. Figure 6 This is a schematic diagram of the structure corresponding to the step of preparing the first chip before step S3 in the method for preparing the chip inductor packaging structure provided in the first embodiment of the present invention. Figure 7This is a schematic diagram of the structure corresponding to step S4 in the method for preparing the chip inductor packaging structure provided in the first embodiment of the present invention. Figure 8 This is a schematic diagram of the structure corresponding to step S5 in the method for preparing the chip inductor packaging structure provided in the first embodiment of the present invention. Figure 9 This is a schematic diagram of the structure corresponding to step S6 in the method for preparing the chip inductor packaging structure provided in the first embodiment of the present invention. Figure 10 This is a schematic diagram of the chip inductor packaging structure provided in the second embodiment of the present invention; Figure 11 for Figure 10 A magnified view of a portion of point XI in the middle; Figure 12 This is a schematic diagram of the chip inductor packaging structure provided in the third embodiment of the present invention.

[0025] Icons: 100 - Chip inductor package structure; 110 - Substrate; 111 - First recess; 112 - Overlay layer; 113 - Coil pad; 114 - Electrical connection pad; 120 - First inductor coil; 130 - First chip; 131 - Electrical connection layer; 132 - Conductive pillar; 133 - Second recess; 134 - Connecting line; 135 - Thin film metal layer; 136 - Metal pillar; 140 - Second chip; 150 - Molding layer; 160 - First structural pillar; 161 - First metal layer; 170 - Second structural pillar; 171 - Second metal layer; 180 - Second inductor coil; 200 - Carrier. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0028] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0029] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0030] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0031] As disclosed in the background section, integrated inductor packaging solutions have emerged in existing chip packaging structures. However, these integrated inductors have the following drawbacks: small inductance, large area occupation, severe parasitic and loss problems, strong electromagnetic interference, high difficulty in manufacturing and modeling, and limited power and voltage withstand capability, which severely restricts their application in high-efficiency power and high-performance radio frequency scenarios.

[0032] To address the aforementioned problems, embodiments of the present invention provide a novel chip inductor packaging structure and a method for fabricating the chip inductor packaging structure. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0033] First Embodiment See Figure 1 and Figure 2 This invention provides a chip inductor packaging structure 100, which can significantly increase inductance, reduce footprint, and minimize parasitic parameters. It also offers stronger electromagnetic interference resistance, lower manufacturing and modeling complexity, better power and voltage withstand capability, making it more suitable for high-power and high-performance radio frequency applications.

[0034] This invention provides a chip inductor packaging structure 100, including a substrate 110, a first inductor coil 120, a first chip 130, a second chip 140, and a molding compound 150. A first groove 111 is formed on the front side of the substrate 110; the first inductor coil 120 is disposed in the first groove 111 and extends out of the first groove 111, with its central axis perpendicular to the front side of the substrate 110; the back side of the first chip 130 is mounted on the front side of the substrate 110 and covers the first groove 111, and the front side of the first chip 130 is provided with... An electrical connection layer 131 is provided, and a connection line 134 is provided on the electrical connection layer 131. The connection line 134 is electrically connected to the substrate 110. A conductive post 132 is also provided in the first chip 130. The conductive post 132 extends to the electrical connection layer 131 and is electrically connected to the first inductor coil 120. A second chip 140 is mounted on the front side of the substrate 110 and is spaced apart from the first chip 130. The second chip 140 is electrically connected to the substrate 110. A molding layer 150 is provided on the front side of the substrate 110 and covers the first chip 130 and the second chip 140.

[0035] It should be noted that the substrate 110 here can be an organic substrate, ceramic substrate, lead frame substrate, multilayer organic wiring stacked substrate, silicon substrate, or glass substrate, etc., and has a wiring structure formed inside. The first chip 130 is a front-mounted chip, which achieves electrical connection with the substrate 110 through the connecting lines 134 formed by the wire bonding process. The second chip 140 is preferably a flip chip, which achieves direct electrical connection with the substrate 110 through the bottom bumps. Here, the first inductor coil 120 is a spiral coil, which is formed by the wire bonding process. The first groove 111 can accommodate the first inductor coil 120, and the inductor coil is placed vertically, which can significantly increase the inductance and reduce parasitic parameters compared with the planar coil structure. Moreover, by accommodating the inductor coil through the groove, the volume occupied by the inductor can be effectively reduced, which is conducive to reducing the overall package volume and realizing the miniaturization of the package structure.

[0036] Furthermore, a second groove 133 is provided on the back side of the first chip 130. The second groove 133 is correspondingly connected to the first groove 111. The first inductor coil 120 extends into the second groove 133, and the conductive post 132 extends to the inner wall of the second groove 133 and makes electrical contact with the portion of the first inductor coil 120 that extends into the second groove 133. Specifically, the second groove 133 is correspondingly connected to the first groove 111, forming a cavity structure. This cavity structure can achieve convection conduction and remove the heat generated by the copper loss of the coil through heat conduction and convection, thereby reducing the temperature rise. At the same time, the second groove 133 can accommodate the first inductor coil 120, ensuring that the first inductor coil 120 is connected to the end of the conductive post 132.

[0037] In this embodiment, a first structural post 160 is disposed in the first groove 111, and the surface of the first structural post 160 is covered with a first metal layer 161. The first inductor coil 120 is disposed around the first structural post 160. Specifically, the first structural post 160 is a cylindrical structure located at the center of the bottom wall of the first groove 111, and its material is the same as that of the substrate 110, such as silicon-based material. The first structural post 160 protrudes towards the first chip 130 and forms the first metal layer 161 on its surface. The first metal layer 161 can be a metal or alloy such as Fe-Ni-Mo, Fe-Ni, or Fe-Si-B-Cu-Nb. By arranging the first metal layer 161, the first structural post 160 can serve as a magnetic core structure, significantly increasing the inductance of the inductor coil. At the same time, the first structural post 160 can support the first inductor coil 120 and play an adhesive role during subsequent colloid filling, significantly improving the structural strength of the first inductor coil 120.

[0038] Furthermore, a second structural post 170 is provided in the second groove 133, and the surface of the second structural post 170 is covered with a second metal layer 171. The first inductor coil 120 is disposed around the second structural post 170. Specifically, the second structural post 170 is a cylindrical structure located at the center of the second groove 133, and its material is the same as the back material of the first chip 130, such as silicon-based material. The second structural post 170 protrudes towards the substrate 110 and forms a second metal layer 171 on its surface. The second metal layer 171 can be a metal or alloy such as Fe-Ni-Mo, Fe-Ni, or Fe-Si-B-Cu-Nb. By arranging the second metal layer 171, the second structural post 170 can serve as a magnetic core structure, significantly increasing the inductance of the inductor coil. At the same time, the second structural post 170 can support the first inductor coil 120 and play an adhesive role during subsequent colloid filling, significantly improving the structural strength of the first inductor coil 120.

[0039] In this embodiment, the first structural post 160 and the second structural post 170 are coaxially arranged and correspondingly joined to allow the first metal layer 161 and the second metal layer 171 to join. Specifically, the first structural post 160 and the second structural post 170 are arranged opposite each other and connected, allowing the first metal layer 161 and the second metal layer 171 to directly contact each other, forming an integral magnetic core structure. This provides better structural support, improving the overall structural strength and the support for the coil. Furthermore, it allows for a continuous distribution of the magnetic core, further increasing the inductance of the inductor coil.

[0040] In this embodiment, a thin-film metal layer 135 is also formed on the inner sidewall of the second groove 133, and the thin-film metal layer 135 is spaced apart from the first inductor coil 120 and the conductive post 132. Specifically, the thin-film metal layer 135 can be made of the same material as the second metal layer 171 and is formed together. The thin-film metal layer 135 can cover the sidewall of the second groove 133, and the first inductor coil 120 is spaced apart from the thin-film metal layer 135 to achieve electrical isolation. By setting the thin-film metal layer 135, the heat dissipation effect can be greatly improved, and the heat generated by the copper loss of the coil can be removed through heat conduction and convection, thereby reducing the temperature rise.

[0041] In this embodiment, the width of the second groove 133 is smaller than the width of the first groove 111. A plurality of metal pillars 136 are also disposed on the back side of the first chip 130, surrounding the second groove 133. Specifically, each metal pillar 136 is disposed on the back side of the first chip 130 and can be formed using electroplating or sputtering processes, including a seed layer and an electroplated layer. The metal pillar 136 can be at least one of any metal such as gold, copper, nickel, vanadium, or titanium, and its height is less than the depth of the first groove 111. The plurality of metal pillars 136 surrounding the conical coil can form a cage-like structure, which on the one hand can improve the adhesion of the adhesive, that is, improve the adhesion between the coating adhesive layer 112 and the first chip 130, and utilize capillary action to improve the filling effect of the coating adhesive layer 112, avoiding voids. On the other hand, the plurality of metal pillars 136 can also act as a shield, preventing the electric field generated by the inductor coil from interfering with surrounding devices. Furthermore, the multiple metal pillars 136 can also play a heat dissipation role, quickly transferring the heat generated by the first chip 130 and improving the chip's heat dissipation performance.

[0042] In this embodiment, the first groove 111 is filled with a coating adhesive layer 112, which covers the first inductor coil 120. Specifically, the coating adhesive layer 112 can be a filler adhesive, which fills and protects the back of the first chip 130 and the first groove 111. It covers the lower part of the first inductor coil 120, serving to protect and bond it.

[0043] It should be noted that the second groove 133 here can be a cavity structure, meaning the filling adhesive does not fill the second groove 133, allowing the cavity to form an air convection channel. This conduction and convection remove the heat generated by the coil copper losses, reducing the temperature rise. Furthermore, the first groove 111 is a covering adhesive layer 112, and the second groove 133 is a cavity structure, allowing the first inductor coil 120 to be distributed simultaneously in both the adhesive layer and the cavity. Therefore, the current can be transmitted at different interface layers, avoiding excessive eddy currents. This also reduces the coupling of eddy currents and magnetic fields between adjacent layers, significantly reducing high-frequency losses.

[0044] In other preferred embodiments of the present invention, a molding compound 150 can also be used for bottom filling and covering, that is, the molding compound 150 extends to the first groove 111 and covers the first inductor coil 120. In actual molding, the corners of the first groove 111 can be exposed (for example, the width of the first chip 130 is greater than the first groove 111, and the length is less than the first groove 111), so that the molding compound can directly enter the first groove 111 for filling and covering, eliminating the bottom filling process.

[0045] In this embodiment, a coil pad 113 is further provided on the bottom wall of the first groove 111, and an electrical connection pad 114 is further provided on the back side of the substrate 110. The first inductor coil 120 is connected to the coil pad 113, and the coil pad 113 is electrically connected to the electrical connection pad 114. Specifically, a connection line 134 is also provided inside the substrate 110, and the electrical connection between the coil pad 113 and the electrical connection pad 114 is realized through the internal connection line 134.

[0046] This invention also provides a method for fabricating a chip inductor package structure 100, which includes the following steps: S1: A first groove 111 is formed on the front side of the substrate 110.

[0047] See Figure 3 Specifically, a substrate 110 can be taken first. This substrate 110 can be an organic substrate 110, a ceramic substrate 110, a lead frame substrate 110, a multilayer organic wiring stacked substrate 110, a silicon-based substrate, or a glass substrate 110, etc. Then, a groove 111 is formed on the front side of the substrate 110. A first structural pillar 160 is then formed at the center of the first groove 111. Finally, a first metal layer 161 is formed on the surface of the first structural pillar 160 by electroplating or sputtering. The first metal layer 161 can be a metal or alloy such as Fe-Ni-Mo, Fe-Ni, or Fe-Si-B-Cu-Nb.

[0048] S2: A first inductor coil 120 is formed in the first groove 111.

[0049] See Figure 4 The first inductor coil 120 extends out of the first groove 111, and the central axis of the first inductor coil 120 is perpendicular to the front side of the substrate 110. Specifically, a wire bonding process can be used to bond a coil around the cylindrical first structural pillar 160. The first inductor coil 120 can be made of copper wire, aluminum wire, or silver wire, and the coil diameter of the first inductor coil 120 can be gradually reduced during wire bonding, thereby forming a conical coil surrounding the first structural pillar 160. Directly forming a conical coil by wire bonding can significantly reduce the coil fabrication steps and lower the difficulty of the process and modeling.

[0050] S3: Attach the back side of the first chip 130 to the front side of the substrate 110 and cover the first groove 111.

[0051] See Figure 5 The first chip 130 has an electrical connection layer 131 on its front side, and a conductive post 132 is also provided inside the first chip 130. The conductive post 132 extends to the electrical connection layer 131 and is electrically connected to the first inductor coil 120. Specifically, the chip can be attached to the front side of the substrate 110 by a mounting process.

[0052] In actual mounting, the first groove 111 can be filled with adhesive to form a coating layer 112 using a dispensing process, and then the chip can be mounted. The coating layer 112 serves to bond and fix the chip. At the same time, the coating layer 112 is an insulating colloid, which can also provide insulation, heat dissipation, vibration reduction and noise reduction, structural reinforcement, moisture and corrosion protection, shielding and anti-interference, etc. The colloid can effectively fix the first inductor coil 120 and prevent coil vibration.

[0053] See Figure 6 It is worth noting that the fabrication of the first chip 130 needs to be completed before mounting the first chip 130. Specifically, a wafer with multiple first chips 130 can be provided first, wherein a first electrical connection layer 131 is formed on the front side of each first chip 130, and a conductive pillar 132 is formed in each first chip 130.

[0054] The front side of the wafer is then bonded to a carrier 200, which can be made of metal or glass. A temporary bonding adhesive layer is used for fixation, and this temporary bonding adhesive layer is debonded using UV light or a laser. The temporary bonding adhesive layer can be composed of self-crosslinking resins such as water-based acrylic emulsions or water-based styrene-acrylic emulsions.

[0055] Next, metal pillars 136 are formed on the back side of the wafer. Specifically, a metal seed layer can be formed through electroplating, followed by photoresist coating and exposure and development to form conductive holes. Metal is then electroplated or sputtered into the conductive holes to form the metal pillars 136. Finally, the photoresist is removed using a photoresist stripping process, and the surrounding seed layer is removed using a micro-etching process (plasma micro-etching or chemical etching) to form multiple metal pillars 136.

[0056] Then, a second groove 133 and a second structural pillar 170 are formed on the back side of the wafer, wherein a metal pillar 136 surrounds the second groove 133, and the second structural pillar 170 is located in the first groove 111. Specifically, the second groove 133 can be formed by etching the back side of the wafer using etching processes, such as dry etching (carbon tetrafluoride / sulfur hexafluoride / nitrogen trifluoride / hydrogen, etc.) or chemical etching (hydrofluoric acid / buffered oxide etchant / a mixture of sulfuric acid and hydrogen peroxide, etc.). A silicon pillar structure remains at the center of the second groove 133, forming the second structural pillar 170.

[0057] Then, a second metal layer 171 is formed on the surface of the second structural pillar 170. Using methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), a metal layer is deposited on the surface of the second structural pillar 170 as a magnetic material to form the second metal layer 171. The second metal layer 171 can be a metal or alloy such as Fe-Ni-Mo, Fe-Ni, or Fe-Si-B-Cu-Nb.

[0058] Finally, the wafer is cut to form a single first chip 130, and the carrier 200 is removed. Specifically, a cutting process (mechanical cutting or laser cutting) can be used to form a half-cut adhesive layer on the carrier 200, the wafer is separated, and then a debonding process is used to separate the first chip 130 from the carrier 200 through a mounting and picking method.

[0059] S4: A connection line 134 is formed on the electrical connection layer 131 to connect to the substrate 110, so that the electrical connection layer 131 is electrically connected to the substrate 110 through the connection line 134.

[0060] See Figure 7 Specifically, after chip mounting is completed, a wire bonding process is used to form a connection line 134, which can be a gold wire, copper wire or silver wire, so that the electrical connection layer 131 is electrically interconnected with the substrate 110.

[0061] S5: The second chip 140 is mounted on the front side of the substrate 110.

[0062] See Figure 8 The second chip 140 is spaced apart from the first chip 130 and electrically connected to the substrate 110. The second chip 140 is flip-chip bonded to the front side of the substrate 110 using a chip mounting process.

[0063] S6: A molding layer 150 is formed on the front side of the substrate 110.

[0064] See Figure 9The molding compound 150 encapsulates the first chip 130 and the second chip 140. Specifically, the molding compound 150 is formed using a molding process, which encapsulates the chip and the mounting structure. Finally, the product is cut into individual chips using a dicing process.

[0065] In summary, the chip inductor packaging structure 100 and its fabrication method provided in this embodiment of the invention involve forming a first groove 111 on the front side of a substrate 110, placing a first inductor coil 120 within the first groove 111 and extending it outwards, with the central axis of the first inductor coil 120 perpendicular to the front side of the substrate 110, achieving vertical placement. Simultaneously, the back side of a first chip 130 is mounted on the front side of the substrate 110, covering the first groove 111. An electrical connection layer 131 is provided on the front side of the first chip 130, electrically connected to the substrate 110 via a connecting line 134. A conductive pillar 132 is also provided within the first chip 130, electrically connected to the first inductor coil 120, thus electrically connecting the electrical connection layer 131 on the front side of the first chip 130 to the first inductor coil 120. A second chip 140 is mounted on the front side of the substrate 110, and a molding compound 150 covers both the first chip 130 and the second chip 140. Compared to existing technologies, the chip inductor packaging structure 100 provided in this embodiment of the invention uses a vertically placed inductor coil and forms a magnetic core structure through the first structural pillar 160 and the second structural pillar 170, which can significantly increase the inductance and reduce parasitic parameters. Furthermore, the inductor coil is accommodated by slots in the substrate 110, effectively reducing the inductor's footprint, which helps to reduce the overall package size and achieve miniaturization of the package structure. The design of the metal pillar 136 can improve bonding strength while also providing shielding to prevent the inductor coil from interfering with surrounding devices, and also improve heat dissipation.

[0066] Second Embodiment See Figure 10 and Figure 11 This embodiment of the invention provides a chip inductor packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0067] In this embodiment, the chip inductor package structure 100 includes a substrate 110, a first inductor coil 120, a first chip 130, a second chip 140, and a molding compound layer 150. A first groove 111 is provided on the front side of the substrate 110, and a second groove 133 is provided on the back side of the first chip 130. The second groove 133 is correspondingly connected to the first groove 111. A first structural post 160 is provided in the first groove 111, and a second structural post 170 is provided in the second groove 133. The first structural post 160 and the second structural post 170 are coaxially arranged and spaced apart from each other, so that a barrier gap is formed between the first metal layer 161 and the second metal layer 171.

[0068] It should be noted that the height of the first structural post 160 is less than the depth of the first groove 111, and there is a certain gap height H between the second structural post 170 and the first structural post 160, so that the metal layer and the second metal layer 171 can be separated from each other, forming a segmented magnetic core structure. The segmented magnetic core can cut off the eddy current backflow inside the magnetic core, significantly reduce the eddy current area, disperse edge magnetic flux, and reduce leakage inductance and localized overheating. At the same time, the adhesive layer 112 can cover the barrier gap between the first metal layer 161 and the second metal layer 171, so that the adhesive insulatingly isolates the first metal layer 161 and the second metal layer 171, ensuring the separation effect.

[0069] Third Embodiment See Figure 12 This embodiment of the invention provides a chip inductor packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0070] This invention provides a chip inductor packaging structure 100, including a substrate 110, a first inductor coil 120, a first chip 130, a second chip 140, and a molding compound 150. A first groove 111 is formed on the front side of the substrate 110; the first inductor coil 120 is disposed in the first groove 111 and extends out of the first groove 111, with its central axis perpendicular to the front side of the substrate 110; the back side of the first chip 130 is mounted on the front side of the substrate 110 and covers the first groove 111, and the front side of the first chip 130 is provided with... An electrical connection layer 131 is provided, and a connection line 134 is provided on the electrical connection layer 131. The connection line 134 is electrically connected to the substrate 110. A conductive post 132 is also provided in the first chip 130. The conductive post 132 extends to the electrical connection layer 131 and is electrically connected to the first inductor coil 120. A second chip 140 is mounted on the front side of the substrate 110 and is spaced apart from the first chip 130. The second chip 140 is electrically connected to the substrate 110. A molding layer 150 is provided on the front side of the substrate 110 and covers the first chip 130 and the second chip 140.

[0071] Furthermore, a second inductor coil 180 is also provided within the first chip 130. One end of the second inductor coil 180 is connected to the first inductor coil 120, and the other end of the second inductor coil 180 is connected to the conductive post 132, so that the conductive post 132 is electrically connected to the first inductor coil 120. Specifically, the second inductor coil 180 extends to the back side of the first chip 130. Preferably, a groove can be formed on the back side of the first chip 130 by laser grooving, and then the second inductor coil 180 can be formed by electroplating. The top end of the second inductor coil 180 is directly connected to the conductive post 132, and the bottom end is bonded to the top end of the first inductor coil 120 by a mounting process.

[0072] Furthermore, the center lines of the first inductor coil 120 and the second inductor coil 180 overlap, and the first inductor coil 120 and the second inductor coil 180 are joined to form a tapered coil. Specifically, the diameter of the first inductor coil 120 decreases sequentially from bottom to top (i.e., towards the front of the first chip 130), and the diameter of the second inductor coil 180 also decreases sequentially from bottom to top. The first inductor coil 120 and the second inductor coil 180 are joined to form a tapered coil, thereby forming a tapered inductor structure. This gradual structure can disperse the coil, further reduce parasitic capacitance, resulting in smaller parasitic parameters and more stable high-frequency characteristics.

[0073] In this embodiment, the first groove 111 is filled with a covering adhesive layer 112, which covers the first inductor coil 120. Specifically, the covering adhesive layer 112 can be a filling adhesive, which fills and protects the back of the first chip 130 and the first groove 111. The first inductor coil 120 is completely covered, which serves to protect and bond it.

[0074] In other preferred embodiments of the present invention, a molding compound 150 can also be used for bottom filling and covering, that is, the molding compound 150 extends to the first groove 111 and covers the first inductor coil 120. In actual molding, the corners of the first groove 111 can be exposed (for example, the width of the first chip 130 is greater than the first groove 111, and the length is less than the first groove 111), so that the molding compound can directly enter the first groove 111 for filling and covering, eliminating the bottom filling process.

[0075] In this embodiment, a plurality of metal pillars 136 are also provided on the back side of the first chip 130. The plurality of metal pillars 136 extend into the first groove 111 and surround the first inductor coil 120 and the second inductor coil 180. Specifically, each metal pillar 136 is provided on the back side of the first chip 130 and can be formed by electroplating or sputtering processes, including a seed layer and an electroplated layer. The metal pillar 136 can be at least one of copper, titanium, and gold, and its height is less than the depth of the first groove 111. The plurality of metal pillars 136 surrounding the conical coil can form a cage-like structure, which can improve the bonding force of the adhesive, that is, improve the bonding force between the coating adhesive layer 112 and the first chip 130, and improve the filling effect of the coating adhesive layer 112 by utilizing capillary action to avoid voids. On the other hand, the plurality of metal pillars 136 can also play a shielding role to prevent the electric field generated by the inductor coil from interfering with surrounding devices. Moreover, the plurality of metal pillars 136 can also play a heat dissipation role, quickly transferring the heat generated by the first chip 130 away.

[0076] The chip inductor packaging structure 100 provided in this embodiment of the invention significantly increases inductance and reduces parasitic parameters by forming a second inductor coil 180 on the back side of the first chip 130 and splicing the second inductor coil 180 with the first inductor coil 120 to form a vertically conical inductor structure. Furthermore, the inductor coil is accommodated by slots in the substrate 110, effectively reducing the inductor's footprint, which helps to reduce the overall package size and achieve miniaturization of the package structure. Simultaneously, it simplifies the process steps and reduces the process difficulty.

[0077] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip inductor packaging structure, characterized in that, include: The substrate has a first groove on its front side; A first inductor coil is disposed in the first groove and extends out of the first groove, and the central axis of the first inductor coil is perpendicular to the front side of the substrate; The first chip is back-mounted on the front side of the substrate and covers the first groove. An electrical connection layer is provided on the front side of the first chip. The electrical connection layer is provided with connecting lines and is electrically connected to the substrate through the connecting lines. The first chip is also provided with conductive pillars that extend to the electrical connection layer and are electrically connected to the first inductor coil. The second chip is mounted on the front side of the substrate and is spaced apart from the first chip, and the second chip is electrically connected to the substrate. A molding layer is disposed on the front side of the substrate and covers the first chip and the second chip.

2. The chip inductor packaging structure according to claim 1, characterized in that, The first chip also includes a second inductor coil, one end of which is connected to the first inductor coil, and the other end of which is connected to the conductive post, so that the conductive post is electrically connected to the first inductor coil.

3. The chip inductor packaging structure according to claim 2, characterized in that, The center lines of the first inductor and the second inductor overlap, and the first inductor and the second inductor are joined together to form a tapered coil.

4. The chip inductor packaging structure according to claim 3, characterized in that, The back of the first chip is also provided with a plurality of metal pillars, which extend into the first groove and surround the first inductor coil and the second inductor coil.

5. The chip inductor packaging structure according to claim 1, characterized in that, The back of the first chip is also provided with a second groove, which is connected to the first groove. The first inductor coil extends into the second groove, and the conductive post extends to the inner wall of the second groove and makes electrical contact with the part of the first inductor coil that extends into the second groove.

6. The chip inductor packaging structure according to claim 5, characterized in that, The first groove is further provided with a first structural post, the surface of the first structural post is covered with a first metal layer, and the first inductor coil is arranged around the first structural post.

7. The chip inductor packaging structure according to claim 6, characterized in that, A second structural post is provided in the second groove, and the surface of the second structural post is covered with a second metal layer. The first inductor coil is surrounded by the second structural post.

8. The chip inductor packaging structure according to claim 7, characterized in that, The first structural column and the second structural column are coaxially arranged and correspondingly joined to join the first metal layer and the second metal layer.

9. The chip inductor packaging structure according to claim 7, characterized in that, The first structural column and the second structural column are coaxially arranged and spaced apart from each other to form a barrier gap between the first metal layer and the second metal layer.

10. The chip inductor packaging structure according to claim 5, characterized in that, A thin-film metal layer is also formed on the inner sidewall of the second groove, and the thin-film metal layer is spaced apart from the first inductor coil and the conductive post.

11. The chip inductor packaging structure according to claim 5, characterized in that, The width of the second groove is smaller than the width of the first groove, and a plurality of metal pillars are provided on the back side of the first chip, the plurality of metal pillars surrounding the second groove.

12. The chip inductor packaging structure according to claim 1, characterized in that, The first groove is filled with a coating adhesive layer, which covers the first inductor coil; and / or, The molding layer extends into the first groove and covers the first inductor coil.

13. The chip inductor packaging structure according to claim 1, characterized in that, The bottom wall of the first groove is also provided with a coil pad, and the back side of the substrate is also provided with an electrical connection pad. The first inductor coil is connected to the coil pad, and the coil pad is electrically connected to the electrical connection pad.

14. A method for fabricating a chip inductor packaging structure, used to fabricate the chip inductor packaging structure as described in claim 1, characterized in that, The preparation method includes: A first groove is formed on the front side of the substrate; A first inductor coil is formed in the first groove, wherein the first inductor coil extends out of the first groove and the central axis of the first inductor coil is perpendicular to the front side of the substrate; The back side of the first chip is attached to the front side of the substrate and covers the first groove. An electrical connection layer is provided on the front side of the first chip, and a conductive post is also provided inside the first chip. The conductive post extends to the electrical connection layer and is electrically connected to the first inductor coil. A wire bonding process is performed on the electrical connection layer to form a connection line connected to the substrate, so that the electrical connection layer is electrically connected to the substrate through the connection line. A second chip is mounted on the front side of the substrate, wherein the second chip is spaced apart from the first chip and is electrically connected to the substrate; A molding compound is formed on the front side of the substrate, wherein the molding compound covers the first chip and the second chip.

15. The method for fabricating a chip inductor packaging structure according to claim 14, characterized in that, Prior to the step of forming the first inductor coil in the first groove, the method further includes: A first structural column is formed in the first groove; A first metal layer is formed by coating the surface of the first structural column.

16. The method for fabricating a chip inductor packaging structure according to claim 14, characterized in that, Before the step of attaching the back side of the first chip to the front side of the substrate, the method further includes: A wafer having a plurality of first chips is provided, wherein a first electrical connection layer is formed on the front side of each first chip, and a conductive pillar is formed within each first chip; The front side of the wafer is attached to the carrier; Metal pillars are formed on the back side of the wafer; A second groove and a second structural pillar are formed on the back side of the wafer, wherein the metal pillar surrounds the second groove and the second structural pillar is located in the first groove; A second metal layer is formed by coating the surface of the second structural column; The first chip is cut into individual pieces, and the carrier is removed.

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