A method for manufacturing a silicon-based high-voltage capacitor and a silicon-based high-voltage capacitor
Patent Information
- Application Number
- CN202510551485.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2026-10-30
AI Technical Summary
[0032]本发明提供的硅基高压电容器制作方法中，在硅衬底加工出贯穿衬底两面的通孔，通过原子层吸附反应外延技术在硅衬底上生长出高K介质层，高K介质层覆盖硅衬底的两面，以及通孔的内壁上，然后去除位于硅衬底至少一面上的部分高K介质层，使得硅衬底的部分表面露出形成了第一图形区，再在硅衬底的两面、第一图形区，以及通孔的内壁均覆盖金属层，再次去除位于硅衬底的两面上的部分金属层，使得部分高K介质层露出形成了隔断区，最后将位于第一图形区上方金属层刻蚀部分厚度形成了凹槽结构的沟槽区，该沟槽区则作为金属焊盘。与现有技术相比，本发明提供的硅基高压电容器制作方法采用了原子层吸附反应外延技术沉积制备高K介质层，可精确控制高K介电层的厚度，降低了高K介电层薄膜表面粗糙度，使得高K介质层厚度均匀，具有较好的保形性，并可以对电容器表面进行全覆盖包绕，有效解决了现有中电容器通过热氧化生长的二氧化硅无法全覆盖，而导致击穿电压不达标的问题。
Smart Images
Figure CN123021675A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon-based high-voltage capacitor technology, and more particularly to a method for manufacturing a silicon-based high-voltage capacitor and a silicon-based high-voltage capacitor. Background Technology
[0002] Capacitors, as fundamental electronic components, play a crucial role in circuit systems. To meet higher capacitance density and capacitance value requirements, a silicon-based high-voltage capacitor based on through-silicon via (TSV) technology has emerged. Its fabrication process involves growing a silicon dioxide layer using double-polished low-resistivity silicon through thermal oxidation, etching through-holes using reactive ion etching, then growing another silicon dioxide layer as a dielectric layer on the sidewalls of the through-holes using thermal oxidation, followed by double-sided sputtering of metal seed layers and patterning and thickening of the metal layer using photolithography. Finally, metal ion milling is used to remove the seed layer on the capacitor surface, obtaining metal pads, thus realizing the TSV capacitor structure. However, in the above-described capacitor fabrication process, the dielectric layer grown by thermal oxidation cannot completely cover the sidewalls of the through-holes, leading to a problem where the breakdown voltage does not meet the capacitor design requirements.
[0003] Therefore, ensuring that the breakdown voltage of silicon-based high-voltage capacitors meets the design requirements is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide a method for manufacturing a silicon-based high-voltage capacitor and a silicon-based high-voltage capacitor. The method for manufacturing a silicon-based high-voltage capacitor provided by this invention ensures that the breakdown voltage of the silicon-based high-voltage capacitor can meet the design requirements of the capacitor.
[0005] To achieve the above objectives, the present invention provides the following technical solution:
[0006] On one hand, the present invention provides a method for manufacturing a silicon-based high-voltage capacitor, comprising:
[0007] A silicon substrate is provided, the silicon substrate having two opposing sides;
[0008] Through-holes penetrating both sides of the silicon substrate are processed on the silicon substrate;
[0009] A high-k dielectric layer is grown on the silicon substrate using atomic layer adsorption reaction epitaxy. The high-k dielectric layer covers both sides of the silicon substrate and the inner wall of the via.
[0010] A portion of the high-k dielectric layer located on at least one side of the silicon substrate is removed to expose the surface of the silicon substrate, thereby forming a first patterned region;
[0011] A metal layer is covered on both sides of the silicon substrate, the first patterned area, and the inner wall of the via.
[0012] Remove portions of the metal layer on both sides of the silicon substrate to expose the high-k dielectric layer, thereby forming a barrier region;
[0013] The metal layer located above the first pattern area is etched to a certain thickness to form a trench area with a groove structure, the trench area serving as a metal pad.
[0014] Optionally, in the above method for manufacturing a silicon-based high-voltage capacitor, the silicon substrate is made of a silicon wafer that has been polished on both sides and has low resistance.
[0015] Optionally, in the above method for fabricating a silicon-based high-voltage capacitor, processing a through-hole penetrating both sides of the silicon substrate includes:
[0016] A photoresist layer is formed by coating one side of the silicon substrate with photoresist;
[0017] After the photoresist layer covers the mask and is exposed and developed, a window area extending through the silicon substrate is etched into the photoresist layer to form a first photoresist mask.
[0018] The through-hole is etched through the window area onto the silicon substrate, penetrating both sides of the silicon substrate;
[0019] Remove the first photoresist mask.
[0020] Optionally, in the above method for manufacturing a silicon-based high-voltage capacitor, the radius of the through-hole is smaller than the thickness of the silicon substrate.
[0021] Optionally, in the above method for manufacturing a silicon-based high-voltage capacitor, the high-K dielectric layer is an aluminum oxide layer or a hafnium dioxide layer;
[0022] When the high-K dielectric layer is an alumina layer, the metal source in the precursor used in the atomic layer adsorption reaction epitaxy technology is trimethylaluminum, and the oxygen source is deionized water.
[0023] When the high-K dielectric layer is a hafnium dioxide layer, the metal source in the precursor used in the atomic layer adsorption reaction epitaxy technology is tetrabis(ethylmethylamino)hafnium, and the oxygen source is high-purity water or ozone.
[0024] Optionally, in the above method for fabricating a silicon-based high-voltage capacitor, removing a portion of the high-k dielectric layer located on at least one side of the silicon substrate includes:
[0025] A portion of the high-k dielectric layer located on at least one side of the silicon substrate is removed by reactive ion etching.
[0026] Optionally, in the above method for fabricating a silicon-based high-voltage capacitor, the metal layer covering both sides of the silicon substrate, the first patterned area, and the inner wall of the via includes:
[0027] A metal seed layer is formed by magnetron sputtering on both sides of the silicon substrate, the first patterned area, and the inner wall of the via.
[0028] The metal layer is formed by thickening the metal seed layer using electroplating.
[0029] Optionally, in the above method for fabricating a silicon-based high-voltage capacitor, removing a portion of the metal layer located on both sides of the silicon substrate to expose the high-k dielectric layer to form an isolation region includes: removing a portion of the metal layer by wet etching.
[0030] Optionally, in the above method for fabricating a silicon-based high-voltage capacitor, the etching of a portion of the metal layer above the first patterned area to form a trench region with a recessed structure, wherein the trench region serves as a metal pad, includes:
[0031] The trench region is prepared by removing part of the thickness of the metal layer through a metal ion milling process.
[0032] In the method for fabricating a silicon-based high-voltage capacitor provided by the present invention, through-holes penetrating both sides of a silicon substrate are processed. A high-k dielectric layer is grown on the silicon substrate using atomic layer adsorption reactive epitaxy (ALI). The high-k dielectric layer covers both sides of the silicon substrate and the inner walls of the through-holes. Then, a portion of the high-k dielectric layer on at least one side of the silicon substrate is removed, exposing a portion of the silicon substrate surface to form a first patterned region. A metal layer is then covered on both sides of the silicon substrate, the first patterned region, and the inner walls of the through-holes. A portion of the metal layer on both sides of the silicon substrate is removed again, exposing a portion of the high-k dielectric layer to form a partition region. Finally, a portion of the metal layer above the first patterned region is etched to form a trench region with a groove structure, which serves as a metal pad. Compared with existing technologies, the silicon-based high-voltage capacitor manufacturing method provided by this invention uses atomic layer adsorption reactive epitaxy (ALI) to deposit and prepare a high-k dielectric layer. This allows for precise control of the high-k dielectric layer thickness, reduces the surface roughness of the high-k dielectric layer film, and results in a uniform high-k dielectric layer thickness with good shape retention. Furthermore, it can fully cover the capacitor surface, effectively solving the problem that existing capacitors, where silicon dioxide grown by thermal oxidation cannot fully cover the surface, leading to substandard breakdown voltage.
[0033] On the other hand, the present invention also provides a silicon-based high-voltage capacitor, which is manufactured by the silicon-based high-voltage capacitor manufacturing method described in any of the preceding claims. Since the silicon-based high-voltage capacitor provided by the present invention is manufactured by the aforementioned silicon-based high-voltage capacitor manufacturing method, it possesses all the technical effects of the aforementioned silicon-based high-voltage capacitor manufacturing method, which will not be elaborated further here. Attached Figure Description
[0034] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0035] Figure 1 This is a schematic flowchart of the method for manufacturing a silicon-based high-voltage capacitor disclosed in an embodiment of the present invention;
[0036] Figures 2 to 5 A flowchart illustrating the process of creating vias in a silicon substrate according to an embodiment of the invention.
[0037] Figures 6 to 9 A flowchart illustrating the process of creating a first graphic region in a high-K dielectric layer, as disclosed in an embodiment of the invention.
[0038] Figures 10 to 13 This is a flowchart illustrating the process of setting up a partition area and metal pads in a metal layer according to an embodiment of the invention.
[0039] Figure label:
[0040] 10 is a silicon substrate, and 11 is a through-hole;
[0041] 20 represents the first photoresist mask;
[0042] 30 is the high-K dielectric layer, and 31 is the first pattern area;
[0043] 40 is the metal layer, 41 is the partition area, and 42 is the metal pad;
[0044] 50 is the second photoresist mask;
[0045] 60 represents the third photoresist mask. Detailed Implementation
[0046] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
[0047] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.
[0049] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0050] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0051] The core of this invention lies in providing a method for manufacturing a silicon-based high-voltage capacitor, which ensures that the breakdown voltage of the silicon-based high-voltage capacitor can meet the design requirements of the capacitor.
[0052] Another key aspect of this invention is to provide a silicon-based high-voltage capacitor manufactured using the aforementioned silicon-based high-voltage capacitor manufacturing method.
[0053] like Figures 1-13 As shown in the figure, an embodiment of the present invention discloses a method for manufacturing a silicon-based high-voltage capacitor, including the following steps:
[0054] Step S100, as follows Figure 1 As shown, a silicon substrate 10 is provided, the silicon substrate 10 having two opposing sides;
[0055] The size of the silicon substrate 10 can be adjusted according to actual needs. Both sides of the silicon substrate 10 need to be kept clean to prepare for subsequent processes such as coating.
[0056] Step S200, as follows Figure 5 As shown, through holes 11 are processed on the silicon substrate 10, penetrating both sides of the silicon substrate 10;
[0057] Through-silicon vias (TSVs) are fabricated on the prepared silicon substrate 10, penetrating both sides of the silicon substrate 10. These TSVs penetrate the vertical interconnect structure of the silicon wafer and are used for electrical signal connections between chips in three-dimensional integrated circuits or advanced packaging. The ratio of their depth to diameter is relatively large.
[0058] Step S300, as follows Figure 6 As shown, a high-k dielectric layer 30 is grown on a silicon substrate 10 using atomic layer adsorption reactive epitaxy. The high-k dielectric layer 30 covers both sides of the silicon substrate 10 and the inner wall of the via 11.
[0059] The high-K dielectric layer 30 is an insulating layer with a high valence constant. Atomic layer adsorption reactive epitaxy (ARE) is a self-limiting reaction. The reaction proceeds to different stages as the temperature increases, including three stages: low-temperature adsorption, medium-temperature reaction, and high-temperature crystallization. In the initial low-temperature stage, the temperature of the reaction chamber is generally adjusted to 200°C. A first precursor source is introduced into the device and adsorbed on the silicon substrate 10. After adsorption is complete, an inert gas is introduced to purge away any remaining precursor source. Then, a second precursor source is introduced into the device, causing a preliminary ligand exchange between the second precursor source and the first precursor source adsorbed on the surface of the silicon substrate 10. However, the reaction is not yet complete. An inert gas is then introduced again to purge away any remaining gas. After purging, the reaction chamber is heated to the medium-temperature reaction stage, with a temperature range of 200°C-500°C. At this stage, the adsorbed first and second precursors undergo a solid-state surface reaction, generating an amorphous or microcrystalline phase of the target material. Finally, further heating leads to a high-temperature crystallization stage, with a temperature range of 500℃-800℃. This further heating causes in-situ crystallization of the amorphous or microcrystalline film, resulting in atomic rearrangement into a single-crystal structure that matches the lattice of the silicon substrate 10. After multiple cycles of low-temperature adsorption, medium-temperature reaction, and high-temperature crystallization, an annealing treatment is performed to prevent film transfer, repair defects, and improve film growth quality. In this embodiment, the high-K dielectric layer 30 grown using atomic layer adsorption-reactive epitaxy covers both sides of the silicon substrate 10 and the inner wall of the via 11, providing uniform coverage and consistent thickness at all locations on the silicon substrate 10.
[0060] Step S400, as follows Figure 9 As shown, a portion of the high-k dielectric layer 30 located on at least one side of the silicon substrate 10 is removed to expose the surface of the silicon substrate 10 in order to form a first patterned region 31;
[0061] After the high-K dielectric layer 30 of the silicon substrate 10 is completed, a portion of the high-K dielectric layer 30 on at least one side of the silicon substrate 10 is removed to form a groove structure. The bottom of the groove structure is the silicon substrate 10, so that a portion of the surface of the silicon substrate 10 is exposed through the groove structure, forming a first pattern area 31. The size of the first pattern area 31 can be designed according to actual needs.
[0062] Step S500, as follows Figure 10 As shown, a metal layer 40 is formed on both sides of the silicon substrate 10, the first patterned area 31, and the inner wall of the via 11.
[0063] After the first patterned region 31 of the silicon substrate 10 is completed, a metal layer 40 is deposited on the surface of the silicon substrate 10. The metal layer 40 covers both sides of the silicon substrate 10, the first patterned region 31, and the inner wall of the via 11. The coverage is uniform and the thickness is consistent. At this time, the high-K dielectric layer 30 is located between the surface of the silicon substrate 10 and the metal layer 40. The metal layer 40 is in contact with the high-K dielectric layer 30 to store charge, avoid electric field concentration, and improve the breakdown voltage.
[0064] Step S600, as follows Figure 12 As shown, a portion of the metal layer 40 on both sides of the silicon substrate 10 is removed to expose the high-k dielectric layer 30, thereby forming a barrier region 41;
[0065] After the metal layer 40 is covered, a portion of the metal layer 40 on both sides of the silicon substrate 10 is removed, resulting in a groove structure. The bottom of the groove structure is a high-K dielectric layer 30, which is exposed through the groove opening of the groove structure. The electrical connection between the electrode and the metal layer 40 is isolated by the isolation region 41, as well as the electrical connection between the metal layer 40 and the surrounding electrical devices, thus preventing capacitor failure.
[0066] Step S700, as follows Figure 13 As shown, a portion of the thickness of the metal layer 40 located above the first pattern area 31 is etched away to form a trench area with a groove structure, and the trench area serves as a metal pad 42.
[0067] After the metal layer 40 is covered, the thickness of the metal layer 40 above the first pattern area 31 is etched, but the metal layer 40 above the first pattern area 31 is not completely removed. A groove area with a groove structure is formed in the metal layer 40. The depth of the groove area can be set according to actual needs. Then, the groove area above the first pattern area 31 serves as a metal pad 42 for electrical connection.
[0068] In one specific embodiment, the silicon substrate 10 is made of a silicon wafer that is polished on both sides and has low resistance. Polishing both sides of the silicon substrate 10 can facilitate the adhesion of the deposition layer and photoresist to the surface of the silicon substrate 10. The resistivity of the silicon substrate 10 can make the silicon wafer equivalent to adding an extra metal layer 40 to the capacitor, thereby increasing the capacitance value of the capacitor to meet higher capacitance requirements.
[0069] like Figures 2 to 5 As shown, specifically, processing through-holes 11 penetrating both sides of the silicon substrate 10 on the silicon substrate 10 further includes the following steps:
[0070] Step S201: Photoresist is coated on one side of the silicon substrate 10 to form a photoresist layer;
[0071] The side of the silicon substrate 10 to be coated with photoresist is cleaned with a cleaning solution to remove contaminants such as organic or metal contaminants from the surface of the silicon substrate 10, ensuring uniform photoresist adhesion and reducing the occurrence of defects. The natural oxide layer on the surface of the silicon substrate 10 is removed by rinsing with hydrofluoric acid to improve the purity of the silicon layer of the silicon substrate 10. After the surface of the silicon substrate 10 is cleaned, photoresist is applied to one side of the silicon substrate 10 using a photoresist device to form a photoresist layer.
[0072] In step S202, after covering the photoresist layer with a photomask and undergoing exposure and development, a window region penetrating to the surface of the silicon substrate 10 is etched into the photoresist layer to form the first photoresist mask 20. Figure 3 As shown;
[0073] A photomask with a covered area and a cutout area is fabricated. The size of the cutout area of the photomask is designed according to the size of the via 11 formed on the silicon substrate 10. The fabricated photomask is laid on the photoresist layer. After exposure and development, the portion of the photoresist layer corresponding to the cutout area of the photomask is etched to form a window area that extends through to the surface of the silicon substrate 10. Finally, the photomask covering the photoresist layer is removed. At this point, the photoresist layer with the window area forms the first photoresist mask 20.
[0074] Step S203, as follows Figure 4 As shown, through-holes 11 penetrating both sides of the silicon substrate 10 are etched on the silicon substrate 10 through the window area;
[0075] After the photoresist layer window area is etched, the silicon substrate 10 can be placed in an inductively coupled plasma etching machine, and the silicon substrate 10 in the corresponding window area can be etched by inductively coupled plasma (ICP) to prepare a through hole 11 that runs through both sides of the silicon substrate 10.
[0076] Step S204, as follows Figure 5 As shown, the first photoresist mask 20 is removed;
[0077] After the via 11 of the silicon substrate 10 is etched, the first photoresist mask 20 on the surface of the silicon substrate 10 can be removed by wet method such as soaking in acetone and then rinsing with isopropanol, or by dry method. After removing the first photoresist mask 20, the surface of the silicon substrate 10 needs to be inspected to confirm that there is no photoresist residue.
[0078] Meanwhile, in this embodiment, the radius of the via 11 formed in the silicon substrate 10 needs to be smaller than the thickness of the silicon substrate 10, so that the via 11 has a high aspect ratio to achieve compact interconnection of 3D stacking. In addition, the smaller diameter of the via 11 has less impact on the overall structural strength of the silicon substrate 10, reducing the problem of the silicon substrate 10 being easily broken during processing. Furthermore, it can reduce the stress of the copper-filled via 11 and the thermal expansion coefficient of silicon, thus avoiding the generation of cracks.
[0079] In another specific embodiment, the high-K dielectric layer 30 is an alumina layer or a hafnium dioxide layer. When the high-K dielectric layer 30 is an alumina layer, during the growth of the high-K dielectric layer 30 using atomic layer adsorption-reactive epitaxy (ALI) technology, a trimethylaluminum source bottle and a deionized water source bottle are installed on the equipment. The metal source in the precursor input into the reaction chamber of the equipment is trimethylaluminum, and the oxygen source is deionized water. When the material of the high-K dielectric layer 30 is hafnium dioxide, during the growth of the high-K dielectric layer 30 using ALI technology, a tetrakis(ethylmethylamino)hafnium (TEMAHf) source bottle and a high-purity water source bottle are installed on the equipment. In this case, the metal source in the precursor input into the reaction chamber is tetrakis(ethylmethylamino)hafnium, and the oxygen source is high-purity water, or ozone can also be used as the oxygen source. Those skilled in the art can select the process formula and run the process according to the thickness design requirements of the high-K dielectric layer, and obtain the high-K dielectric layer of the required thickness after a certain period of cyclic growth.
[0080] like Figures 7 to 9 As shown, the step of removing a portion of the high-k dielectric layer 30 located on at least one side of the silicon substrate 10 includes: removing a portion of the high-k dielectric layer 30 located on at least one side of the silicon substrate 10 by reactive ion etching;
[0081] Step S401: Photoresist is applied to the high-k dielectric layer 30 on one side of the silicon substrate 10 to form a photoresist layer;
[0082] The outer surface of the high-K dielectric layer 30 to be coated with photoresist is cleaned with a cleaning solution to remove contaminants on the surface, ensuring uniform photoresist adhesion and reducing the occurrence of defects. After the surface of the high-K dielectric layer 30 is cleaned, photoresist is applied to the surface of the high-K dielectric layer 30 using a photoresist device to form a photoresist layer.
[0083] In step S402, after covering the photoresist layer with a photomask and undergoing exposure and development, a window region penetrating to the surface of the high-k dielectric layer 30 is etched into the photoresist layer to form the second photoresist mask 50. Figure 7 As shown;
[0084] A photomask with a covered area and a cutout area is fabricated. The size of the cutout area of the photomask is determined according to the size of the part to be removed from the high-K dielectric layer 30. The fabricated photomask is laid on the photoresist layer. After exposure and development, the part of the photoresist layer corresponding to the cutout area of the photomask is etched to form a window area. The window area extends to the surface of the high-K dielectric layer 30. Finally, the photomask covering the photoresist layer is removed. At this time, the photoresist layer with the window area forms the second photoresist mask 50.
[0085] Step S403, as follows Figure 8 As shown, a portion of the high-k dielectric layer 30 is etched through the window area;
[0086] After the photoresist layer window area is etched, the silicon substrate 10 is placed in a reactive ion etching machine. The high-K dielectric layer 30 in the corresponding window area is etched and removed by reactive ion etching, so that the surface of the silicon substrate 10 in the corresponding removed part is exposed, thus completing the removal of a portion of the high-K dielectric on at least one side of the silicon substrate 10.
[0087] Step S404, as follows Figure 9 As shown, the second photoresist mask 50 is removed;
[0088] After the removal of part of the high-K dielectric layer is completed, the second photoresist mask 50 on the surface of the silicon substrate 10 can be removed by wet method such as soaking in acetone and then rinsing with isopropanol, or by dry method. After removing the second photoresist mask 50, the surface of the silicon substrate 10 needs to be inspected to confirm that there is no photoresist residue.
[0089] like Figure 10 As shown, the specific steps in step S500 of forming a metal layer 40 on both sides of the silicon substrate 10, the first patterned area 31, and the inner wall of the via 11 include:
[0090] Step S501: A metal seed layer is formed by magnetron sputtering on both sides of the silicon substrate 10, the first patterned area 31, and the inner wall of the via 11.
[0091] After the surface of the silicon substrate 10 is cleaned, the silicon substrate 10 is placed in the reaction chamber of the magnetron sputtering equipment. The reaction chamber is evacuated, and the magnetron sputtering system is run to sputter metal seed layers on both sides of the silicon substrate 10, the first pattern area 31, and the inner wall of the via 11, ensuring that the metal seed layer is uniformly covered. The material of the metal seed layer can be copper, aluminum, or tungsten.
[0092] Step S502: The metal seed layer is thickened by electroplating to form the metal layer 40;
[0093] After the metal seed layer is completed, before thickening the metal seed layer by electroplating, the surface of the metal seed layer is activated, such as by soaking in dilute sulfuric acid, which can remove the oxides on the surface of the metal seed layer. At the same time, the surface of the metal seed layer is polished to reduce the surface roughness of the metal seed layer. Then, the metal seed layer is thickened by electroplating to form the metal layer 40.
[0094] like Figures 10 to 13 As shown, the removal of a portion of the metal layer 40 located on both sides of the silicon substrate 10 in step S600 specifically includes: removing a portion of the metal layer 40 on both sides of the silicon substrate 10 by wet etching.
[0095] Specifically, in step S601, photoresist is applied to the outer surface of the metal layer 40 to form a photoresist layer;
[0096] The outer surface of the metal layer 40 is cleaned with a cleaning solution to remove contaminants and ensure uniform and firm adhesion of the photoresist, reducing the occurrence of defects. After the surface of the metal layer 40 is cleaned, photoresist is applied to the outer surface of the metal layer 40 using a photoresist device to form a photoresist layer.
[0097] Step S602, as follows Figure 11 As shown, after the photoresist layer covers the mask and is exposed and developed, a window area penetrating to the surface of the metal layer 40 is etched in the photoresist layer to form the third photoresist mask 60.
[0098] A photomask with a covered area and a cutout area is fabricated. The size of the cutout area of the photomask is determined according to the size of the partition area 41 in the metal layer 40. The fabricated photomask is laid on the photoresist layer. After exposure and development, the part of the photoresist layer corresponding to the cutout area of the photomask is etched to form a window area. The window area extends to the surface of the metal layer 40. Finally, the photomask covering the photoresist layer is removed. At this time, the photoresist layer with the window area forms the third photoresist mask 60.
[0099] Step S603, as follows Figure 12 As shown, the partition region 41 is prepared by wet etching in the window area;
[0100] After etching the window area of the photoresist layer, the silicon substrate 10 is immersed in the etching solution and the solution is continuously stirred to ensure the uniformity of the solution. Samples are taken periodically for testing to avoid over-etching until part of the metal layer 40 is completely removed, exposing the high-K dielectric layer 30, thus completing the formation of the isolation region 41 of the metal layer 40.
[0101] Step S604: Remove the third photoresist mask 60;
[0102] After the partition region 41 of the metal layer 40 is formed, the third photoresist mask 60 on the surface of the silicon substrate 10 can be removed by wet method such as soaking in acetone and then rinsing with isopropanol, or by dry method. After removing the third photoresist mask 60, the surface of the silicon substrate 10 needs to be inspected to confirm that there is no photoresist residue.
[0103] like Figure 13 As shown, in step S700, a portion of the thickness of the metal layer 40 located above the first pattern area 31 is etched to form a trench area with a groove structure. The trench area serves as a metal pad 42. A portion of the thickness of the metal layer 40 located above the first pattern area 31 can be removed by a metal ion milling process to prepare the trench area. The metal layer 40 can be precisely thinned by the metal ion milling process to form a trench structure with steep sidewalls. The portion of the metal with higher impurities located on the outermost layer is removed, so that the remaining metal with higher purity serves as the metal pad 42, thereby improving the overall performance of the metal pad 42.
[0104] This invention also discloses a silicon-based high-voltage capacitor. Since the silicon-based high-voltage capacitor is manufactured by the above-described silicon-based high-voltage capacitor manufacturing method, it possesses all the technical effects of the above-described silicon-based high-voltage capacitor manufacturing method, which will not be repeated here.
[0105] The silicon-based high-voltage capacitor fabricated by the method provided in this embodiment, compared to planar MIS (Metal-Insulator-Semiconductor) capacitors, features through-holes that sacrifice the capacitance area of the top and bottom surfaces of the capacitor to increase the capacitance area of the sidewalls. This increases the total capacitance surface area and improves the capacitance value, according to the capacitor capacitance formula. Where C is the capacitance, ε0 is the vacuum permittivity, and ε γ Where K is the relative permittivity, S is the effective area of the metal plate, and d is the distance between the two plates. Under the premise of the same dielectric layer thickness, the high dielectric constant of the high K dielectric layer further improves the capacitance value, so that the silicon-based high voltage capacitor provided in this example can still meet the capacitance design requirements as electronic systems continue to miniaturize.
[0106] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for manufacturing a silicon-based high-voltage capacitor, characterized in that, include: A silicon substrate is provided, the silicon substrate having two opposing sides; Through-holes penetrating both sides of the silicon substrate are processed on the silicon substrate; A high-k dielectric layer is grown on the silicon substrate using atomic layer adsorption reaction epitaxy, and the high-k dielectric layer covers both sides of the silicon substrate and the inner wall of the via. A portion of the high-k dielectric layer located on at least one side of the silicon substrate is removed to expose the surface of the silicon substrate, thereby forming a first patterned region; Metal layers are formed on both sides of the silicon substrate, the first patterned area, and the inner wall of the via. Remove portions of the metal layer on both sides of the silicon substrate to expose the high-k dielectric layer, thereby forming a barrier region; A portion of the thickness of the metal layer located above the first pattern area is etched away to form a trench area with a groove structure, the trench area serving as a metal pad.
2. The method for manufacturing a silicon-based high-voltage capacitor according to claim 1, characterized in that, The silicon substrate is made from a silicon wafer that has been polished on both sides and has low resistance.
3. The method for manufacturing a silicon-based high-voltage capacitor according to claim 1, characterized in that, Processing through-holes through both sides of the silicon substrate includes: A photoresist layer is formed by coating one side of the silicon substrate with photoresist; After the photoresist layer covers the mask and is exposed and developed, a window area extending through the silicon substrate is etched into the photoresist layer to form a first photoresist mask. The through-hole is etched through the window area onto the silicon substrate, penetrating both sides of the silicon substrate; Remove the first photoresist mask.
4. The method for manufacturing a silicon-based high-voltage capacitor according to claim 1, characterized in that, The radius of the via is smaller than the thickness of the silicon substrate.
5. The method for manufacturing a silicon-based high-voltage capacitor according to claim 1, characterized in that, The high-K dielectric layer is an alumina layer or a hafnium dioxide layer; When the high-K dielectric layer is an alumina layer, the metal source in the precursor used in the atomic layer adsorption reaction epitaxy technology is trimethylaluminum, and the oxygen source is deionized water. When the high-K dielectric layer is a hafnium dioxide layer, the metal source in the precursor used in the atomic layer adsorption reaction epitaxy technology is tetrabis(ethylmethylamino)hafnium, and the oxygen source is high-purity water or ozone.
6. The method for manufacturing a silicon-based high-voltage capacitor according to claim 1, characterized in that, The removal of a portion of the high-k dielectric layer located on at least one side of the silicon substrate includes: A portion of the high-k dielectric layer located on at least one side of the silicon substrate is removed by reactive ion etching.
7. The method for manufacturing a silicon-based high-voltage capacitor according to claim 1, characterized in that, The metal layer formed on both sides of the silicon substrate, the first patterned area, and the inner wall of the via includes: A metal seed layer is formed by magnetron sputtering on both sides of the silicon substrate, the first patterned area, and the inner wall of the via. The metal layer is formed by thickening the metal seed layer using electroplating.
8. The method for manufacturing a silicon-based high-voltage capacitor according to claim 1, characterized in that, The removal includes: removing portions of the metal layer on both sides of the silicon substrate by wet etching.
9. The method for manufacturing a silicon-based high-voltage capacitor according to claim 1, characterized in that, The step of etching away a portion of the thickness of the metal layer located above the first patterned area includes: A portion of the thickness of the metal layer located above the first patterned area is removed by a metal ion milling process.
10. A silicon-based high-voltage capacitor, characterized in that, It is prepared by the method for manufacturing silicon-based high-voltage capacitors as described in any one of claims 1-9.