Ferroelectric memory device, method of manufacturing ferroelectric memory device, and related electronic device

Abstract

The embodiment of the application discloses a ferroelectric memory device, a preparation method of the ferroelectric memory device and related electronic equipment, and the ferroelectric memory device comprises a substrate, a laminated structure and a first electrode layer; the first electrode layer comprises a first protective layer and a first electrode; the first protective layer is arranged around the first electrode, and the first protective layer has conductivity; the laminated structure comprises a plurality of alternately arranged insulating layers and ferroelectric layers and a plurality of second electrodes; the laminated structure has a groove perpendicular to the substrate, and the first electrode layer is arranged in the groove; the ferroelectric layer comprises a ferroelectric film layer and an interface interlayer, and the interface interlayer is arranged at least partially around the ferroelectric film layer; and the ferroelectric layer is arranged at least partially around the second electrode. The embodiment of the application can improve the stability of the memory device.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to ferroelectric memory devices, methods for fabricating ferroelectric memory devices, and related electronic equipment. Background Technology

[0002] With the rapid development and deep integration of emerging technologies such as the Internet of Things and artificial intelligence, the demand for massive data collection, transmission, and computation is increasing daily. This presents unprecedented performance challenges for memory, a key component of modern information systems. Traditional memory technologies are gradually showing bottlenecks in terms of speed, power consumption, and non-volatility. In recent years, hafnium-based ferroelectric memories (HFCs) have emerged as a promising next-generation memory technology due to their high read / write speeds, non-volatility, excellent cycle performance, low power consumption, and good compatibility with CMOS processes. Compared to traditional ferroelectric materials, HFCs can achieve ferroelectric properties in thinner multilayer thin-film structures (tens of nanometers or even sub-tens of nanometers), making high-density and even three-dimensional integration possible and giving them a unique advantage in building ultra-high-density memory chips. Therefore, HFCs are considered strong contenders for the core unit of future novel ferroelectric memories. However, the manufacturing process of 3D stacked HFCs is complex, involving multiple process steps and techniques. In actual production, this process faces significant risks, such as thin-film quality control, interface characteristic optimization, and stress management, which directly affect the performance and reliability of the devices.

[0003] Therefore, improving the stability of ferroelectric memories is an urgent problem to be solved in order to realize the large-scale application of ferroelectric memories. Summary of the Invention

[0004] This application provides ferroelectric storage devices, methods for manufacturing ferroelectric storage devices, and related electronic devices to improve the stability of ferroelectric storage devices.

[0005] In a first aspect, embodiments of this application provide a ferroelectric memory device, which includes a substrate, a stacked structure, and a first electrode layer; the first electrode layer includes a first protective layer and a first electrode; the first protective layer is disposed around the first electrode and is conductive; the stacked structure includes a plurality of alternately disposed insulating layers and ferroelectric layers, and a plurality of second electrodes; the stacked structure has a groove perpendicular to the substrate, and the first electrode layer is disposed in the groove; the ferroelectric layer includes a ferroelectric thin film layer and an interface intercalation layer, the interface intercalation layer being at least partially disposed around the ferroelectric thin film layer; the ferroelectric layer being at least partially disposed around the second electrode.

[0006] In this embodiment, a first protective layer is added, which at least surrounds the side surface of the first electrode. During the fabrication of the ferroelectric memory device, this prevents the first electrode from contacting the etching solution, thus preventing the etching solution from eroding the first electrode and providing comprehensive protection for the electrode side surface. Furthermore, because the first protective layer is conductive, it possesses interface optimization capabilities and can work synergistically with interface intercalation layers in a stacked structure to regulate parameters such as the crystal structure and interface characteristics of the ferroelectric thin film layer, thereby improving its performance. In contrast, existing technologies do not have a protective layer on the side surface of the first electrode. During the fabrication of the ferroelectric memory device, an insulating material may be used to prepare a temporary protective layer for the first electrode. After the etching process is completed, this protective layer needs to be removed to ensure normal device operation. However, removing the temporary protective layer can cause irreparable damage to the first electrode, reducing device stability. Compared to existing technologies, this application uses a conductive material as the protective layer for the first electrode. After the etching step is completed, the first protective layer does not need to be removed, thus protecting the first electrode and enabling it to work synergistically with interface intercalation layers to improve device performance.

[0007] In some embodiments, the ferroelectric layer is at least partially disposed between the first protective layer and the second electrode.

[0008] In this embodiment, the ferroelectric layer is at least partially disposed between the first protective layer and the second electrode to ensure that the first electrode and the second electrode can function normally.

[0009] In some embodiments, the first protective layer comprises one or more of tantalum nitride (TaN), tantalum oxide (TaO), tantalum oxynitride (TaON), hafnium nitride (HfN), zirconium nitride (ZrN), and niobium nitride (NbN).

[0010] In this embodiment, tantalum nitride (TaN) is a ceramic material with high hardness, high melting point, good conductivity, and chemical stability. Tantalum oxide (TaO) has a certain dielectric constant, good chemical stability, and high temperature resistance. TaO actually refers to tantalum oxide in an indefinite ratio, i.e., TaOx, where x is not equal to 2.5. By controlling x, the properties of tantalum oxide can be adjusted to give it certain conductivity or semiconductor characteristics. Tantalum oxynitride (TaON) is a compound between tantalum nitride and tantalum oxide; its conductivity, dielectric constant, and chemical stability can be adjusted by regulating the ratio of nitrogen and oxygen. Materials such as tantalum nitride (TaN), tantalum oxide (TaO), tantalum oxynitride (TaON), hafnium nitride (HfN), zirconium nitride (ZrN), and niobium nitride (NbN) are not easily reacted with etching solutions (such as phosphoric acid solutions), thus protecting the first electrode during the manufacturing process. In addition, since these materials have a certain degree of conductivity, the first protective layer can also have the function of interface optimization. That is, the first protective layer has conductivity and can play the role of an interface layer. Especially when working together with the interface intercalation layer in the stacked structure, it can effectively improve the performance of the ferroelectric thin film layer, thereby significantly improving the overall performance of the device.

[0011] In some embodiments, the interface intercalation layer includes one or more of niobium oxide (NbOx) and titanium oxide (TiOx).

[0012] In this embodiment, niobium oxide (NbOx) is a metal oxide, such as niobium pentoxide, which exhibits metallic conductivity and is chemically stable and corrosion-resistant. Titanium oxide (TiOx) is a metal oxide, such as titanium dioxide, which also exhibits metallic conductivity under certain conditions and has good chemical stability. Both niobium oxide (NbOx) and titanium oxide (TiOx) exhibit good metallic conductivity under specific conditions. Using them as interfacial intercalators helps to form good electrical contacts, reduce interfacial resistance, and thus improve the overall performance of the device. Niobium oxide and titanium oxide can form good interfaces with ferroelectric thin film materials, improving the crystal quality and orientation of the ferroelectric thin film layer, thereby increasing the polarization intensity of the ferroelectric thin film layer.

[0013] In some embodiments, the thickness of the first protective layer along the direction parallel to the substrate is greater than or equal to 0.2 nanometers and less than or equal to 5 nanometers.

[0014] In this embodiment, the thickness of the first protective layer is greater than or equal to 0.2 nanometers, ensuring sufficient thickness to provide effective electrode protection and interface optimization. If the thickness is too thin, it may not fully cover the electrode sides or effectively regulate interface characteristics. A thickness of less than or equal to 5 nanometers limits the thickness of the first protective layer to avoid adverse effects on device performance. Excessive thickness may increase device resistance, reduce switching speed, or affect the crystal quality of the ferroelectric thin film. Ensuring sufficient thickness of the first protective layer effectively prevents erosion of the electrode sides by etching solutions or other corrosive media, thereby avoiding electrode size reduction and performance degradation. Furthermore, controlling the thickness of the first protective layer allows for the regulation of interface characteristics, thereby improving the crystal quality and polarization intensity of the ferroelectric thin film.

[0015] In some embodiments, the conductivity of the first protective layer is greater than that of the interface intercalation layer.

[0016] In this embodiment, the conductivity of the first protective layer is higher than that of the interface intercalation layer; that is, the first protective layer conducts electricity more easily and has lower resistance than the interface intercalation layer. The first protective layer is used to protect the first electrode and can also serve as an interface layer to optimize interface characteristics. The interface intercalation layer is disposed between the ferroelectric thin film layer and the insulating layer and the first protective layer, and can be used to regulate the interface characteristics of the ferroelectric thin film layer and improve its performance. When the first protective layer 101 serves as the interface layer, in some embodiments, the interface layer surrounds the interface intercalation layer in a direction perpendicular to the substrate and is located between the first electrode and the interface intercalation layer in a direction parallel to the substrate. Since the interface layer may be directly connected to other electrodes or device structures, this arrangement may lead to leakage. In this embodiment, the interface layer (i.e., the first protective layer) only covers the side surface of the first electrode and contacts a specific portion of the interface intercalation layer. This structure avoids direct connection between the interface layer and other electrodes or device structures, thereby significantly reducing the risk of leakage. At the same time, since the conductivity of the first protective layer is higher than that of the interface intercalation layer, even if the interface intercalation layer may be in direct contact with other electrodes or device structures, the first protective layer is not in direct contact with other electrodes or devices, and leakage is still effectively suppressed. This design optimizes the overall performance and reliability of the device, minimizes leakage current, and improves electrode stability and device lifespan.

[0017] In some embodiments, the grain size of the first protective layer is smaller than the grain size of the interface intercalation layer.

[0018] In this embodiment, the grain size of the first protective layer is smaller than that of the interfacial intercalation layer, which prevents the diffusion of impurities (such as fluoride ions F and chloride ions Cl) into the ferroelectric thin film layer, thereby ensuring its working performance. The smaller grain size of the first protective layer provides more grain boundaries, preventing impurities from penetrating into the ferroelectric thin film layer, while a larger grain size may form channels, making it easier for impurities to diffuse. The presence of impurities will reduce the polarization ability of the ferroelectric thin film layer, affecting storage performance, mechanical stability, and interfacial conductivity. In particular, chloride ions may react with ferroelectric materials through chemical reactions to form undesirable compounds, further deteriorating the performance of the ferroelectric thin film layer. Controlling the grain size of the first protective layer helps to reduce impurity diffusion, maintain the electrical characteristics and long-term stability of the ferroelectric thin film layer, improve the reliability and efficiency of the device, and thus optimize the overall performance of the ferroelectric memory device.

[0019] In some embodiments, the thermal conductivity of the first protective layer is greater than that of the first electrode.

[0020] In this embodiment, the thermal conductivity of the first protective layer is greater than that of the first electrode, which solves the problem of uneven heat conduction and ensures uniform temperature distribution across different electrode layers. Thermal conductivity is a measure of a material's ability to conduct heat; the higher the thermal conductivity, the more efficient the material is at transferring heat. The first protective layer effectively absorbs heat from the first electrode and rapidly and evenly transfers it to the underlying ferroelectric layer and the second electrode. Due to the high thermal conductivity of the first protective layer, it achieves rapid and uniform heat distribution, ensuring that the bottom ferroelectric layer and the second electrode maintain the same temperature as the upper ferroelectric layer and the second electrode. Without the first protective layer, the thermal conductivity of the first electrode is low, and heat cannot be efficiently transferred to the ferroelectric layer and the second electrode. Under high power or high frequency operation, more heat accumulates on the first electrode, causing heat concentration in the upper electrode layer, while the lower ferroelectric layer and the second electrode cannot reach the same temperature due to a lack of effective heat transfer. This thermal non-uniformity may lead to a decrease in the performance of the lower electrode layer, thereby affecting the efficiency and reliability of the entire device. Furthermore, excessive temperature differences may lead to the generation of thermal stress, ultimately causing failures such as material collapse, peeling, or cracking. Therefore, by ensuring that the thermal conductivity of the first protective layer is higher than that of the first electrode, the design not only avoids the thermal non-uniformity problem caused by low thermal conductivity but also optimizes the performance and reliability of the device during operation. Uniform heat distribution reduces the risk of failure due to temperature differences, enabling the device to operate more stably under high temperature and high power conditions, thereby improving the overall performance and durability of the device. Furthermore, during the fabrication process, the ferroelectric material requires post-annealing to form crystals, so the high thermal conductivity of the first protective layer ensures uniform heating of each layer and makes the electrical properties as consistent as possible.

[0021] In some embodiments, the first electrode and the second electrode comprise one or more of tungsten (W), titanium nitride (TiN), aluminum (Al), and copper (Cu).

[0022] In the embodiments of this application, the first electrode and the second electrode have specific electrical conductivity. The first electrode and the second electrode can be made of tungsten, titanium nitride, aluminum, copper, or combinations thereof, and appropriate electrode materials can be selected to optimize electrode performance according to actual needs. For example, copper or aluminum can be used to improve conductivity, titanium nitride can be used as a barrier layer, or the high stability and high melting point of tungsten can be utilized to achieve the best balance between device performance, reliability, cost-effectiveness, and process compatibility.

[0023] In some embodiments, the ferroelectric thin film layer includes one or more of hafnium (Hf), zirconium (Zr), silicon (Si), aluminum (Al), and yttrium (Y).

[0024] In the embodiments of this application, the ferroelectric thin film layer can be composed of one or more elements selected from hafnium (Hf), zirconium (Zr), silicon (Si), aluminum (Al), and yttrium (Y). It should be noted that ferroelectric thin films are typically oxides; therefore, these elements usually exist in the film in oxide form (e.g., HfO2, ZrO2, SiO2, Al2O3, Y2O3) or form solid solutions (e.g., HfZrOx). The ferroelectric thin film layer may contain only one of the above elements, such as pure hafnium oxide (HfO2). To obtain better ferroelectric performance, the ferroelectric thin film layer may also contain a combination of multiple elements, such as HfZrOx, HfSiOy, HfAlOx, and HfYOz. In summary, the ferroelectric thin film layer, composed of one or more elements selected from hafnium, zirconium, silicon, aluminum, and yttrium, can achieve a balance between ferroelectric induction and stabilization, performance regulation, improved reliability, improved film quality, and reduced cost, thereby meeting the needs of different application scenarios.

[0025] In some embodiments, the insulating layer comprises silicon oxide (SiO2).

[0026] In this embodiment, silicon oxide (SiO2) can be selected as the insulating layer material in the three-dimensional ferroelectric memory structure. Its core advantage lies in its excellent electrical insulation properties. In the 3D ferroelectric memory structure, the main function of the insulating layer is to build a solid barrier between different conductive layers, preventing current leakage along paths where it should not flow, thereby avoiding short circuits. Silicon oxide has high resistivity and breakdown voltage, effectively blocking the free movement of charges and ensuring that each memory cell operates independently without interference. This excellent electrical isolation characteristic is particularly important for 3D memory structures because in the complex structure of vertical stacking, the distance between layers is very close, and any tiny insulation failure can lead to serious performance problems. Secondly, silicon oxide exhibits excellent chemical and thermal stability. In the manufacturing process of memory devices, harsh process steps such as high-temperature annealing and chemical etching are often required. Silicon oxide exhibits excellent stability under these conditions, is not prone to chemical reactions with other materials, and is not easily decomposed or degraded due to high temperatures. This stability ensures that the insulating layer maintains its original insulating properties throughout the entire manufacturing process, thereby ensuring the reliability and long-term stability of the final device. Especially in 3D structures, where the manufacturing process is more complex and the requirements for material stability are higher, the advantages of silicon oxide become even more prominent. In summary, choosing silicon oxide as the insulating layer material in 3D ferroelectric memory structures not only provides high electrical insulation performance, ensuring normal device operation, but also improves device reliability and long-term stability due to its excellent chemical and thermal stability.

[0027] Secondly, embodiments of this application provide a method for fabricating a ferroelectric memory device. The method includes: forming a first stacked structure on a substrate, the first stacked structure including a plurality of alternately arranged first insulating layers and second insulating layers; etching columnar grooves on the first stacked structure along a direction perpendicular to the substrate until the bottom is completely exposed; depositing a first protective layer on the sidewalls and bottom of the columnar grooves, and depositing a first electrode on the first protective layer to prepare a first electrode layer, such that the first protective layer surrounds the first electrode and the first protective layer is conductive; etching a plurality of second insulating layers with an etching solution to form a plurality of grooves, and sequentially depositing a ferroelectric layer and a second electrode on each groove by atomic layer deposition, such that the ferroelectric layer at least partially surrounds the second electrode; wherein the ferroelectric layer includes a ferroelectric thin film layer and an interface intercalation layer, the interface intercalation layer at least partially surrounding the ferroelectric thin film layer.

[0028] In this embodiment, a conductive first protective layer is deposited before fabricating the first electrode. This first protective layer surrounds the first electrode, fully protecting the electrode's side surface and preventing direct contact between the first electron and the first and second insulating layers. It also effectively prevents erosion by the etching solution. After fabricating the first electrode, it is not necessary to remove the first protective layer. Only the second insulating layer needs to be etched to form grooves, and the ferroelectric layer and the second electrode are sequentially deposited on each groove using atomic layer deposition. Because the first protective layer is conductive, it has an interface optimization function and can work synergistically with the interface intercalation in the stacked structure to improve the performance of the ferroelectric thin film layer. In the prior art, no protective layer is provided on the side surface of the first electrode. During the fabrication of the ferroelectric memory device, a temporary protective layer for the first electrode may be prepared using insulating material. After the etching process is completed, this protective layer needs to be removed to ensure normal device operation. However, removing the temporary protective layer can cause irreparable damage to the first electrode, reducing device stability. Compared to existing technologies, this application uses a conductive material as the protective layer for the first electrode. After the etching step is completed, there is no need to remove the first protective layer. This not only protects the first electrode but also works in conjunction with the interface intercalation layer to improve device performance.

[0029] In some embodiments, the etching rate of the second insulating layer is greater than the etching rate of the first protective layer.

[0030] In this embodiment, the etching rate of the second insulating layer is greater than that of the first protective layer, that is, the second insulating layer is etched away, but the first protective layer is retained, so that it can work together with the interface intercalation layer in the stacked structure to improve the performance of the ferroelectric thin film layer.

[0031] Thirdly, embodiments of this application provide a semiconductor packaging structure, including a packaging substrate and a ferroelectric memory device, wherein the packaging substrate and the ferroelectric memory device are electrically connected, and the ferroelectric memory device is any one of the ferroelectric memory devices described in the first aspect above.

[0032] Fourthly, embodiments of this application provide an electronic device, including a circuit board and a semiconductor packaging structure as described in any of the third aspects above, wherein the circuit board and the semiconductor packaging structure are electrically connected. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of a ferroelectric storage device provided in an embodiment of this application.

[0034] Figure 2 This is a schematic diagram of a first electrode layer provided in an embodiment of this application.

[0035] Figure 3 This is a schematic diagram of a stacked structure provided in an embodiment of this application.

[0036] Figure 4 This is a vertical projection view of a first electrode layer provided in an embodiment of this application.

[0037] Figure 5 This is a schematic diagram of a ferroelectric layer provided in an embodiment of this application.

[0038] Figure 6 This is a schematic diagram of the thickness of a first protective layer provided in an embodiment of this application.

[0039] Figure 7 This is a schematic diagram showing the position between a first protective layer and an interface interpolation layer, provided for an embodiment of this application.

[0040] Figure 8 This is a schematic diagram of heat conduction provided in an embodiment of this application.

[0041] Figure 9 This is a schematic flowchart illustrating a method for fabricating a ferroelectric storage device according to an embodiment of this application.

[0042] Figure 10 This is a schematic diagram of a method for fabricating a ferroelectric storage device provided in an embodiment of this application.

[0043] Figure 11 This is a cross-sectional schematic diagram of a ferroelectric storage device provided in an embodiment of this application. Detailed Implementation

[0044] The embodiments of this application will now be described with reference to the accompanying drawings.

[0045] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0046] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0047] The ferroelectric storage devices on which the embodiments of this application are based are described below.

[0048] Ferroelectric memory (FEM) is a type of non-volatile memory that combines the speed of random access memory (RAM) and the characteristics of dynamic random access memory (DRAM) with the data retention capabilities of non-volatile memory (such as flash memory). FEM utilizes the properties of ferroelectric materials to store data, making it a viable alternative to flash memory and other non-volatile memories in certain applications. At the heart of FEM is the ferroelectric material, which retains its polarization after an electric field is applied, even after the field is removed. This phenomenon is similar to how ferromagnetic materials retain their magnetization, hence the name "ferroelectric." In FEM cells, the ferroelectric material acts as the dielectric in a capacitor. By applying a voltage, the ferroelectric material can be polarized into one of two stable states, representing binary 0 and 1. Because the polarization of the ferroelectric material is stable, data is retained even after power is removed. When a write operation is needed to the FEM, the polarization direction of the ferroelectric material can be changed by applying an appropriate voltage to the ferroelectric capacitor, thus writing data. In this process, a positive voltage polarizes the material to the 1 state, and a negative voltage polarizes it to the 0 state. However, the structure of ferroelectric memory devices affects their storage performance. Therefore, this application optimizes the structure of ferroelectric memory devices to improve their stability. Next, we will combine... Figure 1 This application provides a detailed description of the structure of a ferroelectric storage device, which is a three-dimensional (3D) ferroelectric storage structure.

[0049] For example, please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a ferroelectric memory device provided in an embodiment of this application. The ferroelectric memory device includes a substrate, a first electrode layer 10, and a stacked structure 20. The X-axis is parallel to the substrate direction (i.e., left-right direction), the Z-axis is perpendicular to the substrate direction (i.e., up-down direction), and the Y-axis is perpendicular to both the X and Z axes. The X-axis represents the length of the substrate, the first electrode layer 10, and the stacked structure 20; the Z-axis represents the height of the substrate, the first electrode layer 10, and the stacked structure 20. Furthermore, the cross-sectional views of the ferroelectric memory devices and other related devices in this application and the following related embodiments are also applicable. Figure 1 The coordinate system shown (X-axis, Y-axis, and Z-axis).

[0050] like Figure 2 As shown, Figure 2This is a schematic diagram of a first electrode layer provided in an embodiment of the present application. The first electrode layer 10 includes a first protective layer 101 and a first electrode 102. The first protective layer 101 is disposed around the first electrode 102 and is conductive.

[0051] In some embodiments, the first protective layer 101 may surround the first electrode 102 in a direction parallel to the substrate, and the first protective layer 101 may also be disposed between the substrate and the first electrode 102 in a direction perpendicular to the substrate.

[0052] Specifically, the ferroelectric memory device includes two types of electrodes: an upper electrode and a lower electrode. The upper and lower electrodes together form a capacitor structure. By applying an electric field between the upper and lower electrodes, the polarization direction of the ferroelectric thin film can be controlled. Ferroelectric materials exhibit spontaneous polarization characteristics; that is, in the absence of an external electric field, the electric dipoles within the material spontaneously align in a certain direction, forming polarization. Applying an electric field can reverse the polarization direction of the ferroelectric thin film, thereby enabling data writing operations. In the ferroelectric memory device, the first electrode layer 10 exists in a cylindrical shape. The first electrode 102 included in the first electrode layer 10 can be the upper electrode in the ferroelectric memory device. The first protective layer 101 can surround the first electrode 102 in a direction parallel to the substrate, and the first protective layer 101 can also be disposed between the substrate and the first electrode 102 in a direction perpendicular to the substrate. The first protective layer 101 can be used to prevent the first electrode 102 from directly contacting the stacked structure 20 and the substrate. Since the first protective layer 101 is conductive, it will not affect the normal operation of the ferroelectric memory device.

[0053] like Figure 3 As shown, Figure 3 This is a schematic diagram of a stacked structure provided in an embodiment of this application. The stacked structure 20 includes a plurality of alternately arranged insulating layers 201 and ferroelectric layers 202, and a plurality of second electrodes 203. The stacked structure 20 has a groove perpendicular to the substrate, and a first electrode layer 10 is disposed in the groove, that is, the first electrode layer 10 is inserted into the stacked structure 20 along a direction perpendicular to the substrate. The ferroelectric layer 202 includes a ferroelectric thin film layer 2021 and an interface intercalation layer 2022, the interface intercalation layer 2022 being disposed at least partially around the ferroelectric thin film layer 2021. The ferroelectric layer 202 is disposed at least partially around the second electrodes 203.

[0054] In some embodiments, the ferroelectric layer 202 is at least partially disposed between the first protective layer 101 and the second electrode 203.

[0055] In this embodiment, the ferroelectric layer 202 is at least partially disposed between the first protective layer 101 and the second electrode 203 to ensure that the first electrode 102 and the second electrode 203 can work normally.

[0056] In some embodiments, an interface intercalation layer 2022 is disposed between the ferroelectric thin film layer 2021 and the adjacent insulating layer 201 along a direction perpendicular to the substrate, and the interface intercalation layer 2022 is also disposed between the ferroelectric thin film layer 2021 and the first protective layer 101 along a direction parallel to the substrate.

[0057] Specifically, the stacked structure 20 refers to a composite structure containing multiple layers of materials. In this structure, an insulating layer 201, a ferroelectric layer 202, and a second electrode 203 are alternately placed in a specific order. The insulating layer 201 serves as electrical isolation, preventing current leakage or short circuits between different electrode layers and ensuring the normal operation of the device. The second electrode 203 can be the lower electrode in a ferroelectric memory device. The interface intercalation layer 2022 is a material layer disposed between the insulating layer 201 and the ferroelectric thin film layer 2021, with the aim of optimizing interface characteristics. It should be noted that the performance of the ferroelectric thin film is highly dependent on its interface characteristics. The interface intercalation layer 2022 can adjust the interface energy, interface state density, lattice matching, etc., between the ferroelectric thin film and adjacent layers, thereby improving the performance of the ferroelectric thin film. For example, by selecting a suitable interface intercalation material, a good chemical bond can be formed with the ferroelectric thin film layer 2021, reducing the interface state density and increasing the polarization intensity of the ferroelectric thin film. Perpendicular to the substrate direction, an interface intercalation layer 2022 is disposed between the ferroelectric thin film layer 2021 and the adjacent insulating layer 201. This means that in the vertical direction of the stacked structure 20, each layer is staggered with the others. To improve electrical isolation and interface characteristics, the interface intercalation layer 2022 can be inserted between the insulating layer 201 and the ferroelectric thin film layer 2021. Parallel to the substrate direction, the interface intercalation layer 2022 can also be disposed between the ferroelectric thin film layer 2021 and the first protective layer 101, which covers the first electrode 102. Furthermore, the placement of the interface intercalation layer 2022 between the ferroelectric thin film layer 2021 and the first protective layer 101 can optimize the contact performance of these two layers, improving the conductivity and overall performance of the electrode.

[0058] For example Figure 4 As shown, Figure 4 This is a vertical projection view of a first electrode layer provided in an embodiment of the present application. In a ferroelectric storage device, the first electrode layer 10 exists in a cylindrical shape and serves as the upper electrode. The first electrode layer 10 is inserted into the stacked structure 20 along a direction perpendicular to the substrate.

[0059] It should be noted that in ferroelectric storage devices, one or more first electrode layers 10 may exist, but... Figure 4 Only one first electrode layer 10 is shown in the diagram.

[0060] like Figure 5 As shown, Figure 5This is a schematic diagram of a ferroelectric layer provided in an embodiment of this application. The ferroelectric layer 202 includes a ferroelectric thin film layer 2021 and an interface intercalation layer 2022. The ferroelectric thin film layer 2021 can surround the second electrode 203 in a direction perpendicular to the substrate, and the ferroelectric thin film layer 2021 can also be disposed between the interface intercalation layer 2022 and the second electrode 203 in a direction parallel to the substrate.

[0061] Specifically, the ferroelectric thin film layer 2021 is used to store data and can cooperate with the second electrode 203 to perform data read and write operations. The ferroelectric thin film layer 2021 can surround the second electrode 203 in a direction perpendicular to the substrate, that is, the ferroelectric thin film layer 2021 completely wraps the second electrode 203 from the side. In addition, the ferroelectric thin film layer 2021 can also be disposed between the interface intercalation layer 2022 and the second electrode 203 in a direction parallel to the substrate. That is, in addition to the side surround coverage, the ferroelectric thin film layer 2021 is also located in the horizontal direction between the interface intercalation layer 2022 and the second electrode 203. This structure can increase the contact area between the ferroelectric thin film layer 2021 and the second electrode 203, thereby improving the charge injection efficiency and thus improving the performance of the device.

[0062] For example Figure 5 As shown, the first protective layer 101 also contacts each insulating layer 201.

[0063] This application proposes a ferroelectric memory device structure that improves device performance, reliability, and manufacturing process by optimizing the design of the first electrode layer 10. The core of this device structure lies in the introduction of a first protective layer 101, and the ingenious design of its position and function within the device, thereby overcoming the challenges faced by traditional ferroelectric memory devices in multi-layer stacked structures. In detail, in traditional ferroelectric memory devices, the first electrode 102 is often susceptible to various factors during the manufacturing process, such as etching damage, interface reactions, and material diffusion, which can reduce device performance and lifespan. To address this issue, this application proposes a conductive first protective layer 101 that surrounds the first electrode 102, thus protecting the electrode. This design effectively prevents erosion of the electrode sides by etching solutions or other corrosive media, thereby avoiding reduction in electrode size and performance degradation. Furthermore, in the vertical direction, the first protective layer 101 can also be placed between the substrate and the first electrode 102 to provide bottom protection. Since the first protective layer 101 is conductive, the electrode and the substrate do not need to be in direct contact, avoiding interface reactions and material diffusion, and improving device stability. In addition to its protective function, the first protective layer 101 proposed in this application also has an interface optimization function. The first protective layer 101 is conductive and can function as an interface layer, especially when working in conjunction with the interface intercalation layer 2022 in the stacked structure 20, it can effectively improve the performance of the ferroelectric thin film layer 2021. Specifically, the interface intercalation layer 2022 is disposed between the ferroelectric thin film layer 2021 and the adjacent insulating layer 201, and extends in a direction parallel to the substrate to the space between the ferroelectric thin film layer 2021 and the first protective layer 101. The first protective layer 101 and the interface intercalation layer 2022 cooperate with each other to more precisely control the crystal structure, interface characteristics and other parameters of the ferroelectric thin film layer 2021, thereby significantly improving the overall performance of the device. In existing technologies, no protective layer is provided on the surface of the first electrode. During the fabrication of ferroelectric memory devices, an insulating material may be used to prepare a temporary protective layer for the first electrode. After the etching process is completed, this protective layer needs to be removed to ensure normal device operation. However, removing the temporary protective layer can cause irreparable damage to the first electrode, reducing device stability. In contrast to existing technologies, this application uses a conductive material as the protective layer for the first electrode. After the etching step is completed, there is no need to remove the first protective layer. This not only protects the first electrode but also allows it to work synergistically with the interface intercalation layer, improving device performance.

[0064] Furthermore, the ferroelectric storage device structure proposed in this application has significant advantages in reducing leakage risk. When the first protective layer 101 serves as an interface layer, unlike some prior art, the first protective layer 101 in this application does not need to completely cover the interface intercalation layer 2022 as in conventional methods. In the prior art, if the first protective layer 101 serves as an interface layer, it needs to surround the interface intercalation layer 2022, and an additional interface layer is also required between the first electrode 102 and the interface intercalation layer 2022. This design is prone to leakage when multiple first electrodes share a second electrode in the ferroelectric storage device. In the structure proposed in this application, the first protective layer 101 only covers the side surface of the first electrode 102 and makes precise contact with a specific portion of the interface intercalation layer 2022, avoiding direct connection with other electrodes or device structures. This local contact design effectively isolates the potential between electrodes, thereby significantly reducing the risk of leakage. In addition to the advantages mentioned above, the ferroelectric storage device structure proposed in this application also has the advantage of enhanced structural stability, namely, the first protective layer 101 is in contact with each insulating layer 201, which enhances the overall structural stability.

[0065] In summary, the ferroelectric memory device structure proposed in this application, through the design of the position of the first protective layer 101, not only comprehensively protects the first electrode 102 and extends the device lifespan, but also integrates protection and interface optimization functions, simplifies the process, and improves performance. Furthermore, this structure can reduce the risk of leakage current between electrodes, achieve higher storage density, enhance structural stability, and improve device reliability.

[0066] In some embodiments, the first protective layer 101 includes one or more of tantalum nitride (TaN), tantalum oxide (TaO), and tantalum oxynitride (TaON).

[0067] Specifically, the first protective layer 101 can be composed of one material or a combination of multiple materials, and this application does not impose specific limitations. Tantalum nitride (TaN) is a ceramic material with high hardness, high melting point, good conductivity, and chemical stability. Tantalum oxide (TaO) has a certain dielectric constant, good chemical stability, and high temperature resistance. TaO actually refers to tantalum oxide in an indefinite ratio, i.e., TaOx, where x is not equal to 2.5. By controlling x, the properties of tantalum oxide can be adjusted to give it certain conductivity or semiconductor characteristics. Tantalum oxynitride (TaON) is a compound between tantalum nitride and tantalum oxide, and its conductivity, dielectric constant, and chemical stability can be adjusted by regulating the ratio of nitrogen and oxygen. These materials—tantalum nitride (TaN), tantalum oxide (TaO), and tantalum oxynitride (TaON)—do not readily react with etching solutions (such as phosphoric acid solutions), thus protecting the first electrode 102 during the manufacturing process. Furthermore, since these materials possess a certain degree of conductivity, the first protective layer 101 can also perform interface optimization without requiring additional processing to remove it. In other words, the first protective layer 101, being conductive, can function as an interface layer. Especially when working in conjunction with the interface intercalation layer 2022 in the stacked structure 20, it can effectively improve the performance of the ferroelectric thin film layer 2021. Specifically, the interface intercalation layer 2022 is disposed between the ferroelectric thin film layer 2021 and the adjacent insulating layer 201, and extends parallel to the substrate to the space between each ferroelectric thin film layer 2021 and the first protective layer 101. The first protective layer 101 and the interface intercalation layer 2022 work together to more precisely control parameters such as the crystal structure and interface characteristics of the ferroelectric thin film layer 2021, thereby significantly improving the overall performance of the device.

[0068] In some embodiments, the material of the first protective layer 101 may also include hafnium nitride (HfN), zirconium nitride (ZrN), niobium nitride (NbN), etc.

[0069] In some embodiments, see Figure 6 , Figure 6 This is a schematic diagram of the thickness of a first protective layer provided in an embodiment of this application. The thickness of the first protective layer 101 along the direction parallel to the substrate is greater than or equal to 0.2 nanometers and less than or equal to 5 nanometers.

[0070] Specifically, the thickness of the first protective layer 101 is controlled within a certain range, namely greater than or equal to 0.2 nanometers (nm) and less than or equal to 5 nanometers (nm). The thickness parallel to the substrate direction refers to the direction parallel to the substrate surface, which is the width of the first protective layer 101 in the horizontal direction. A thickness of 0.2 nanometers or more ensures that the first protective layer 101 has sufficient thickness to provide effective electrode protection and interface optimization. If the thickness is too thin, it may not completely cover the electrode sides or effectively regulate interface characteristics. A thickness of 5 nanometers or less limits the thickness of the first protective layer 101 to avoid adverse effects on device performance. If the thickness is too thick, it may increase the device resistance, reduce switching speed, or affect the crystal quality of the ferroelectric thin film. By ensuring that the first protective layer 101 has sufficient thickness, the erosion of the electrode side by etching solution or other corrosive media can be effectively prevented, thereby avoiding the reduction of electrode size and performance degradation. Furthermore, by controlling the thickness of the first protective layer 101, the interface characteristics can be regulated, thereby improving the crystal quality and polarization intensity of the ferroelectric thin film.

[0071] In some embodiments, the conductivity of the first protective layer 101 is greater than that of the interface intercalation layer 2022.

[0072] Specifically, the conductivity of the first protective layer 101 is higher than that of the interface intercalation layer 2022; that is, the first protective layer 101 conducts electricity more easily and has lower resistance than the interface intercalation layer 2022. The first protective layer 101 is used to protect the first electrode 102 and can also serve as an interface layer to optimize interface characteristics. The interface intercalation layer 2022 is disposed between the ferroelectric thin film layer 2021 and the insulating layer 201 and the first protective layer 101, and is used to regulate the interface characteristics of the ferroelectric thin film layer 2021 and improve its performance.

[0073] When the first protective layer 101 serves as the interface layer Figure 7 This diagram illustrates the position between a first protective layer and an interface interpolation layer, as provided in an embodiment of this application. Figure 7 In part (a), in some embodiments, the interface layer surrounds the interface intercalation layer 2022 in a direction perpendicular to the substrate and is located between the first electrode 102 and the interface intercalation layer 2022 in a direction parallel to the substrate. Since the interface layer may be directly connected to other electrodes or device structures, this arrangement may lead to leakage current. Figure 7Part (b) shows an embodiment of this application where the interface layer (i.e., the first protective layer 101) only covers the side surface of the first electrode 102 and contacts a specific portion of the interface intercalation layer 2022. This structure avoids direct connection between the interface layer and other electrodes or device structures, thereby significantly reducing the risk of leakage. Simultaneously, since the conductivity of the first protective layer 101 is higher than that of the interface intercalation layer 2022, even if the interface intercalation layer 2022 may be in direct contact with other electrodes or device structures, the first protective layer 101 is not in direct contact with other electrodes or devices, and leakage is still effectively suppressed. This design optimizes the overall performance and reliability of the device, minimizes the occurrence of leakage, and improves the stability of the electrodes and the lifespan of the device.

[0074] In some embodiments, the conductivity of the first protective layer 101 is between 1E5 S / m and 1E6 S / m; the conductivity of the interface intercalation layer 2022 is below 1E4 S / m.

[0075] In some embodiments, the grain size of the first protective layer 101 is smaller than the grain size of the interface intercalation layer 2022.

[0076] Specifically, the grain size of the first protective layer 101 is smaller than that of the intercalation layer 2022, aiming to prevent the diffusion of impurities (such as fluoride ions F and chloride ions Cl) into the ferroelectric thin film layer 2021, thereby ensuring its operating performance. The smaller grain size of the first protective layer 101 provides more grain boundaries, preventing impurities from penetrating into the ferroelectric thin film layer 2021, while a larger grain size may form channels, making it easier for impurities to diffuse. The presence of impurities will lead to a decrease in the polarization ability of the ferroelectric thin film layer 2021, affecting storage performance, mechanical stability, and interfacial conductivity. In particular, chloride ions may react with ferroelectric materials through chemical reactions to form undesirable compounds, further deteriorating the performance of the ferroelectric thin film layer 2021. Controlling the grain size of the first protective layer 101 helps to reduce impurity diffusion, maintain the electrical characteristics and long-term stability of the ferroelectric thin film layer 2021, improve the reliability and efficiency of the device, and thus optimize the overall performance of the ferroelectric memory device.

[0077] In some embodiments, the thermal conductivity of the first protective layer 101 is greater than that of the first electrode 102.

[0078] Specifically, the thermal conductivity of the first protective layer 101 is greater than that of the first electrode 102. This design aims to address the problem of uneven heat conduction, thereby ensuring a uniform temperature distribution across different electrode layers. Thermal conductivity is a measure of a material's ability to conduct heat; the higher the thermal conductivity, the more efficient the material is at transferring heat. The first protective layer 101 effectively absorbs heat from the first electrode 102 and rapidly and evenly transfers it to the underlying ferroelectric layer 202. Due to the high thermal conductivity of the first protective layer 101, it achieves rapid and uniform heat distribution, ensuring that the bottom and upper ferroelectric layers 202 maintain the same temperature. Figure 8 As shown, Figure 8 This is a schematic diagram of heat conduction provided in an embodiment of this application. Without the first protective layer 101, the thermal conductivity of the first electrode 102 is low, and heat cannot be efficiently transferred to the ferroelectric layer 202. Under high power or high frequency operation, more heat accumulates on the first electrode 102, causing heat concentration in the upper electrode layer, while the lower ferroelectric layer 202 cannot reach the same temperature due to the lack of effective heat transfer. This thermal non-uniformity may lead to a decrease in the performance of the lower electrode layer, thereby affecting the efficiency and reliability of the entire device. In addition, excessive temperature difference may lead to the generation of thermal stress, ultimately causing failures such as material collapse, peeling, or cracking. Therefore, by ensuring that the thermal conductivity of the first protective layer 101 is higher than that of the first electrode 102, the design not only avoids the thermal non-uniformity problem caused by low thermal conductivity, but also optimizes the performance and reliability of the device during operation. Uniform heat distribution reduces the risk of failure caused by temperature difference, enabling the device to operate more stably under high temperature and high power conditions, thereby improving the overall performance and durability of the device. In addition, during the preparation process, ferroelectric materials need to be annealed to form crystals, so the high thermal conductivity of the first protective layer 101 can make each layer heat up evenly and have as consistent electrical properties as possible.

[0079] In some embodiments, the thermal conductivity of the first protective layer 101 is between 47.5 and 1000 W / (mK); the thermal conductivity of the first electrode 102 is between 19.25 and 174 W / (mK).

[0080] In some embodiments, the interface intercalation layer 2022 includes one or more of niobium oxide (NbOx) and titanium oxide (TiOx).

[0081] Specifically, the interface intercalation layer 2022 can be composed of one material or a combination of multiple materials, and this application does not impose specific limitations. Niobium oxide (NbOx) is a metal oxide, usually referring to niobium monoxide, which exhibits metallic conductivity, chemical stability, and corrosion resistance. Titanium oxide (TiOx) is a metal oxide, usually referring to titanium monoxide, which also exhibits metallic conductivity under certain conditions and has good chemical stability. Both niobium oxide (NbOx) and titanium oxide (TiOx) exhibit good metallic conductivity under specific conditions. Using them as the interface intercalation layer 2022 helps to form good electrical contacts, reduce interface resistance, and thus improve the overall performance of the device. Niobium oxide and titanium oxide can form good interfaces with ferroelectric thin film materials, improve the crystal quality and orientation of the ferroelectric thin film layer 2021, and thus increase the polarization intensity of the ferroelectric thin film layer 2021.

[0082] In some embodiments, the first electrode 102 and the second electrode 203 include one or more of tungsten (W), titanium nitride (TiN), aluminum (Al), and copper (Cu).

[0083] Specifically, the first electrode 102 and the second electrode 203 have specific electrical conductivity characteristics. Tungsten (W) is a high-melting-point, high-hardness metal with good electrical conductivity and chemical stability; titanium nitride (TiN) is a ceramic material with high hardness, wear resistance, and corrosion resistance, and is also a good conductive material; aluminum (Al) is a lightweight, highly conductive metal with low cost; copper (Cu) is a metal with excellent electrical conductivity. The first electrode 102 and the second electrode 203 can use only one of the above materials, such as being made entirely of tungsten. The first electrode 102 and the second electrode 203 can also use a combination of the above materials, such as a stacked structure of tungsten and titanium nitride. The first electrode 102 and the second electrode 203 can also be composed of other conductive materials, which are not specifically limited in this application. It should be noted that titanium nitride (TiN) is often used as a barrier layer to prevent electrode materials (e.g., W) from diffusing into the ferroelectric thin film, causing a decrease in device performance. TiN can also improve the corrosion resistance of the electrode. The first electrode 102 and the second electrode 203 can be made of tungsten, titanium nitride, aluminum, copper, or combinations thereof. Appropriate electrode materials can be selected to optimize electrode performance according to actual needs. For example, copper or aluminum can be used to improve conductivity, titanium nitride can be used as a barrier layer, or the high stability and high melting point of tungsten can be utilized to achieve the best balance between device performance, reliability, cost-effectiveness, and process compatibility.

[0084] In some embodiments, the ferroelectric thin film layer 2022 includes one or more of hafnium (Hf), zirconium (Zr), silicon (Si), aluminum (Al), and yttrium (Y).

[0085] Specifically, the ferroelectric thin film layer 2022 can be composed of one or more elements selected from hafnium (Hf), zirconium (Zr), silicon (Si), aluminum (Al), and yttrium (Y). It should be noted that ferroelectric thin films are typically oxides, therefore these elements usually exist in the film in oxide form (e.g., HfO2, ZrO2, SiO2, Al2O3, Y2O3) or form solid solutions (e.g., HfZrOx). Among them, hafnium oxide (HfO2) is a paraelectric phase (not ferroelectric), but by doping with other elements (such as Zr, Si, Al, Y, etc.) or introducing oxygen vacancies, a ferroelectric phase can be induced. Zirconia (ZrO2) is similar to hafnium oxide and is usually a paraelectric phase itself. Zirconia is often used in combination with hafnium to form HfZrOx solid solution to adjust ferroelectric properties. Silicon oxide (SiO2) is not a ferroelectric material itself, but doping it into hafnium oxide can stabilize the ferroelectric phase and improve the performance of the thin film. Aluminum oxide (Al2O3) is also not a ferroelectric material, but doping it into hafnium oxide can stabilize the ferroelectric phase and improve the performance of the thin film. Yttrium oxide (Y2O3) is also not a ferroelectric material, but doping it into hafnium oxide can stabilize the ferroelectric phase and improve the performance of the thin film. Ferroelectric thin film layers can contain only one of the aforementioned elements, such as pure hafnium oxide (HfO2). To obtain better ferroelectric performance, ferroelectric thin film layers can also contain combinations of multiple elements, such as HfZrOx, HfSiOy, HfAlOx, and HfYOz. In summary, ferroelectric thin film layers 2022 are composed of one or more elements selected from hafnium, zirconium, silicon, aluminum, and yttrium. This allows for a balance between ferroelectric induction and stabilization, performance regulation, improved reliability, improved film quality, and reduced cost, thereby meeting the needs of different application scenarios.

[0086] In some embodiments, the insulating layer 201 comprises silicon oxide (SiO2).

[0087] Specifically, in three-dimensional (3D) ferroelectric memory structures, silicon oxide (SiO2) can be chosen as the insulating layer material 201, with its core advantage being its superior electrical insulation properties. In 3D ferroelectric memory structures, the main function of the insulating layer 201 is to build a robust barrier between different conductive layers, preventing current leakage along inappropriate paths and thus avoiding short circuits. Silicon oxide has high resistivity and breakdown voltage, effectively blocking the free movement of charges and ensuring that each memory cell operates independently without interference. This excellent electrical isolation characteristic is particularly important for 3D memory structures because in complex vertically stacked structures, the distance between layers is very close, and any minute insulation failure can lead to serious performance problems. Secondly, silicon oxide exhibits excellent chemical and thermal stability. The manufacturing process of memory devices often involves stringent processes such as high-temperature annealing and chemical etching. Silicon oxide demonstrates excellent stability under these conditions, is not prone to chemical reactions with other materials, and is not easily decomposed or degraded by high temperatures. This stability ensures that the insulating layer maintains its original insulating properties throughout the entire manufacturing process, thereby guaranteeing the reliability and long-term stability of the final device. Especially in 3D structures, where the manufacturing process is more complex and the requirements for material stability are higher, the advantages of silicon oxide become even more prominent. In summary, choosing silicon oxide as the insulating layer material in 3D ferroelectric memory structures not only provides high electrical insulation performance, ensuring normal device operation, but also improves the reliability and long-term stability of the device due to its excellent chemical and thermal stability.

[0088] Please see Figure 9 , Figure 9 A flowchart illustrating a method for fabricating a ferroelectric storage device provided in this application is described in detail below:

[0089] Step S301: Form a first stacked structure on a substrate.

[0090] Specifically, the first laminated structure includes multiple alternating first and second insulating layers. For example... Figure 10 The above, Figure 10 This is a schematic diagram of a method for fabricating a ferroelectric storage device provided in an embodiment of this application. Figure 10 As shown in (a), an alternating first insulating layer and a second insulating layer can be prepared on a substrate, wherein the first insulating layer may be composed of a silicon oxide compound, such as silicon dioxide; and the second insulating layer may be composed of a silicon nitride compound, such as silicon carbide.

[0091] Step S302: Etch columnar grooves on the first stacked structure along a direction perpendicular to the substrate until the bottom is fully exposed.

[0092] Specifically, such as Figure 10As shown in (b), a columnar groove can be etched on the first stacked structure until the substrate is exposed at the bottom, so as to facilitate the subsequent fabrication of the first electrode layer (i.e., the upper electrode) of the ferroelectric memory device.

[0093] Step S303: A first protective layer is deposited on the sidewalls and bottom of the columnar groove, and a first electrode is deposited on the first protective layer to prepare a first electrode layer.

[0094] Specifically, the first protective layer is disposed around the first electrode, that is, the first protective layer can surround the first electrode in a direction parallel to the substrate, and the first protective layer can also be disposed between the substrate and the first electrode in a direction perpendicular to the substrate. The first protective layer is conductive. Figure 10 As shown in (c), before fabricating the first electrode, a first protective layer is deposited in the columnar groove to protect the sidewalls and treat the bottom of the first electrode. If the first electrode is fabricated directly without filling the first protective layer, direct contact between the electrode material and SiNx may lead to interfacial reactions or diffusion, affecting the stability and reliability of the electrode. For example, some metal electrodes may react with SiNx to form metal nitrides, thereby altering the conductivity and structure of the electrode. Furthermore, if the depth-to-width ratio of the opening is large, direct deposition of the electrode material may not completely fill the hole, resulting in voids or gaps within the hole. These voids or gaps can affect the conductivity and mechanical strength of the electrode, reducing the performance and reliability of the device. If there are defects or inhomogeneities on the sidewalls of the hole, direct deposition of the electrode material may also cause the electrode material to form continuous conductive paths on the sidewalls, resulting in a short circuit. For example... Figure 10 As shown in (d), after the first protective layer is deposited, the first electrode is formed by deposition, thereby protecting the first electrode.

[0095] Step S304: Etch multiple second insulating layers with an etching solution to form multiple grooves, and deposit a ferroelectric layer and a second electrode sequentially on each groove using atomic layer deposition.

[0096] Specifically, the interface intercalation layer is disposed between the ferroelectric thin film layer and the adjacent insulating layer in a direction perpendicular to the substrate, and also between the ferroelectric thin film layer and the first protective layer in a direction parallel to the substrate; the ferroelectric thin film layer surrounds the second electrode in a direction perpendicular to the substrate, and is also disposed between the interface intercalation layer and the second electrode in a direction parallel to the substrate; the first protective layer is also in contact with each insulating layer. Figure 10 As shown in (e), after the first electrode layer is prepared, the second insulating layer can be etched away to prepare the ferroelectric layer and the second electrode. Since the first protective layer is conductive and can also serve as an interface layer, it does not need to be removed and can be retained; that is, the etching solution does not react with the first protective layer. Further, as... Figure 10As shown in (f), an interface intercalation layer can be formed on each groove by atomic layer deposition, as shown in... Figure 10 As shown in (g), a ferroelectric thin film layer is deposited on the interface layer using atomic layer deposition. Then, as... Figure 10 As shown in (h), a second electrode is deposited on the ferroelectric thin film layer.

[0097] In some embodiments, the etching rate of the second insulating layer is greater than the etching rate of the first protective layer.

[0098] Specifically, the etching rate of the second insulating layer is greater than that of the first protective layer, meaning that the second insulating layer is etched away, but the first protective layer is still retained.

[0099] For example, such as Figure 11 As shown, Figure 11 This is a cross-sectional schematic diagram of a ferroelectric memory device provided in an embodiment of this application. First, a stack of SiO2 and SiNx is deposited using atomic layer deposition (PVD). High aspect ratio etching is used to create openings in the stack to obtain columnar deep trenches. 1 nm of TaN or TaO and 5 nm of TiN are deposited on the sidewalls of the trenches using ALD. Then, W is filled into the holes as electrodes. After wet etching with phosphoric acid to clean the SiNx on the sidewalls, 2 nm of NbTiO and 8 nm of HZO are filled using ALD. Subsequently, TiN and W are deposited using ALD as composite electrodes, and rapid thermal annealing is used to form the HZO into a ferroelectric material.

[0100] In this embodiment, a conductive first protective layer is deposited before fabricating the first electrode. This first protective layer surrounds the first electrode along a direction parallel to the substrate, fully protecting the side of the electrode and preventing the first electron from directly contacting the first and second insulating layers. It also effectively prevents erosion by the etching solution. In the vertical direction, the first protective layer is placed between the substrate and the first electrode, providing bottom protection. Since the first protective layer is conductive, it is not necessary to remove the bottom first protective layer, reducing the manufacturing process. At the same time, the electrode and the substrate do not need to be in direct contact, avoiding interface reactions and material diffusion, thus improving device stability. Furthermore, after fabricating the first electrode, it is not necessary to remove the first protective layer. Only the second insulating layer needs to be etched to form grooves, and an interface intercalation layer, a ferroelectric thin film layer, and the second electrode are sequentially deposited on each groove using atomic layer deposition. Since the first protective layer is conductive, it has an interface optimization function and can work synergistically with the interface intercalation layer in the stacked structure to improve the performance of the ferroelectric thin film layer. The interface intercalation layer is disposed between the ferroelectric thin film layer and the adjacent insulating layer, and extends along a direction parallel to the substrate to the space between the ferroelectric thin film layer and the first protective layer. The first protective layer and the interface intercalation layer work together to control parameters such as the crystal structure and interface characteristics of the ferroelectric thin film layer, significantly improving device performance. In existing technologies, no protective layer is provided on the surface of the first electrode. During the fabrication of ferroelectric memory devices, an insulating material may be used to prepare a temporary protective layer for the first electrode. After the etching process is completed, this protective layer needs to be removed to ensure normal device operation. However, removing the temporary protective layer can cause irreparable damage to the first electrode, reducing device stability. Compared to existing technologies, this application uses a conductive material as the protective layer for the first electrode. After the etching step, it is not necessary to remove the first protective layer, which not only protects the first electrode but also works synergistically with the interface intercalation layer to improve device performance.

[0101] Furthermore, the structure of this application also has advantages in reducing leakage risk. Compared with the prior art, the first protective layer does not completely cover the interface intercalation layer. In the prior art, if the first protective layer is used as an interface layer, it needs to surround the interface intercalation layer, and an additional interface layer is set between the first electrode and the interface intercalation layer, which can easily lead to leakage when multiple first electrodes share the second electrode. In the structure of this application, the first protective layer only covers the side surface of the first electrode and makes precise contact with a specific part of the interface intercalation layer, avoiding direct connection with other electrodes or structures, effectively isolating the electrode potential, and significantly reducing the risk of leakage. In summary, by designing the position and function of the first protective layer, this application achieves comprehensive protection of the first electrode, extends device life, integrates protection and interface optimization functions, simplifies the process, improves performance, reduces leakage risk, achieves higher storage density, enhances structural stability, and improves device reliability.

[0102] This application provides a semiconductor packaging structure, including a packaging substrate and a ferroelectric memory device, wherein the packaging substrate and the ferroelectric memory device are electrically connected, and the ferroelectric memory device is any of the ferroelectric memory devices described above.

[0103] This application provides an electronic device, including a circuit board and a semiconductor package structure as described above, wherein the circuit board is electrically connected to the semiconductor package structure.

[0104] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0105] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0106] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0107] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0108] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0109] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM).

[0110] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A ferroelectric storage device, characterized in that, The ferroelectric memory device includes a substrate, a stacked structure, and a first electrode layer; The first electrode layer includes a first protective layer and a first electrode; the first protective layer is disposed around the first electrode and is conductive; The stacked structure includes multiple alternating insulating layers and ferroelectric layers, as well as multiple second electrodes; the stacked structure has a groove perpendicular to the substrate, and the first electrode layer is disposed in the groove; The ferroelectric layer includes a ferroelectric thin film layer and an interface intercalation layer, wherein the interface intercalation layer is at least partially disposed around the ferroelectric thin film layer. The ferroelectric layer is disposed at least partially around the second electrode.

2. The ferroelectric storage device according to claim 1, characterized in that, The ferroelectric layer is at least partially disposed between the first protective layer and the second electrode.

3. The ferroelectric storage device according to claim 1 or 2, characterized in that, The first protective layer includes one or more of tantalum nitride (TaN), tantalum oxide (TaO), tantalum oxynitride (TaON), hafnium nitride (HfN), zirconium nitride (ZrN), and niobium nitride (NbN).

4. The ferroelectric storage device according to any one of claims 1-3, characterized in that, The thickness of the first protective layer along the direction parallel to the substrate is greater than or equal to 0.2 nanometers and less than or equal to 5 nanometers.

5. The ferroelectric storage device according to any one of claims 1-4, characterized in that, The conductivity of the first protective layer is greater than that of the interface intercalation layer.

6. The ferroelectric storage device according to any one of claims 1-5, characterized in that, The grain size of the first protective layer is smaller than that of the interface intercalation layer.

7. The ferroelectric storage device according to any one of claims 1-6, characterized in that, The thermal conductivity of the first protective layer is greater than that of the first electrode.

8. The ferroelectric storage device according to any one of claims 1-7, characterized in that, The interfacial intercalation layer includes one or more of niobium oxide (NbOx) and titanium oxide (TiOx).

9. The ferroelectric storage device according to any one of claims 1-8, characterized in that, The first electrode and the second electrode comprise one or more of tungsten (W), titanium nitride (TiN), aluminum (Al), and copper (Cu).

10. The ferroelectric storage device according to any one of claims 1-9, characterized in that, The ferroelectric thin film layer includes one or more of hafnium (Hf), zirconium (Zr), silicon (Si), aluminum (Al), and yttrium (Y).

11. The ferroelectric storage device according to any one of claims 1-10, characterized in that, The insulating layer comprises silicon oxide (SiO2).

12. A method for fabricating a ferroelectric storage device, characterized in that, The method includes: A first stacked structure is fabricated on a substrate, the first stacked structure comprising a plurality of alternating first insulating layers and second insulating layers; A columnar groove is etched on the first stacked structure along a direction perpendicular to the substrate until the bottom is fully exposed; A first protective layer is deposited on the sidewalls and bottom of the columnar groove, and a first electrode is deposited on the first protective layer to prepare a first electrode layer, such that the first protective layer is disposed around the first electrode and the first protective layer is conductive; Multiple second insulating layers are etched by an etching solution to form multiple grooves, and a ferroelectric layer and a second electrode are sequentially deposited on each groove by atomic layer deposition, such that the ferroelectric layer is at least partially disposed around the second electrode; wherein, the ferroelectric layer includes a ferroelectric thin film layer and an interface intercalation layer, and the interface intercalation layer is at least partially disposed around the ferroelectric thin film layer.

13. The method according to claim 12, characterized in that, The etching rate of the second insulating layer is greater than that of the first protective layer.

14. A semiconductor packaging structure, characterized in that, It includes a packaging substrate and a ferroelectric memory device, wherein the packaging substrate and the ferroelectric memory device are electrically connected, and the ferroelectric memory device is the ferroelectric memory device as described in any one of claims 1-11.

15. An electronic device, characterized in that, It includes a circuit board and a semiconductor package structure as described in claim 14 above, wherein the circuit board is electrically connected to the semiconductor package structure.

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