Semiconductor structure and method of forming the same
Patent Information
- Application Number
- CN202510570062.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2026-10-30
AI Technical Summary
[0002]集成电路((integrated circuit，IC)中通常集成有各种电子元器件，如用于储能、滤波、去耦、时序控制、信号耦合以及调谐和振荡等多种作用的电容器，电容器是一种由两块导体中间夹着一块绝缘体(介质)构成的电子元件，集成电路中常用电容有MOS电容(Metal-Oxide-Semiconductor Capacitor)、MOM电容(Metal-Oxide-Metal Capacitor)，但其存在电容值精确度低和稳定性差的缺点，而MIM电容(Metal-Insulator-MetalCapacitor)的电容值较精确，不会随偏压变化而变化，还具电容密度高和低寄生电容特点，使得其成为了研究热点
[0038]本申请实施例提供的半导体结构包括位于基底上的介质层以及位于介质层中的第一电极层、绝缘层和第二电极层，绝缘层位于第二电极层上，第一电极层位于绝缘层上，且第二电极层的端部伸出第一电极层和绝缘层的端部，暴露出第二电极层的部分顶表面；第一电极层包括具有凹槽的第一金属电极结构，以及位于凹槽中的第一阻挡层，所述第一电极层、所述绝缘层和所述第二电极层构成金属-绝缘层-金属电容结构。通过将第一阻挡层嵌入第一金属电极结构的槽中，可以有效避免加工过程中该半导体结构顶部发生开裂的问题，由于整体结构尺寸不变，有利于其用于高集成度的器件或者电路中。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Integrated circuits (ICs) typically integrate various electronic components, such as capacitors used for energy storage, filtering, decoupling, timing control, signal coupling, tuning, and oscillation. A capacitor is an electronic component consisting of two conductors sandwiching an insulator (dielectric). Commonly used capacitors in integrated circuits include MOS capacitors (Metal-Oxide-Semiconductor Capacitors) and MOM capacitors (Metal-Oxide-Metal Capacitors), but they suffer from low capacitance accuracy and poor stability. In contrast, MIM capacitors (Metal-Insulator-Metal Capacitors) have more accurate capacitance values that do not change with bias voltage, and they also feature high capacitance density and low parasitic capacitance, making them a hot research topic.
[0003] However, current MIM capacitors are usually large in area and have high integration density, with a thin dielectric layer between the upper and lower plates. This makes them prone to cracking at the top of the capacitor during processing, affecting the capacitor's performance. Therefore, how to provide a capacitor that can maintain a small size while also having high structural reliability has become an urgent technical problem to be solved. Summary of the Invention
[0004] To address the aforementioned technical problems, this application discloses a semiconductor structure comprising:
[0005] A dielectric layer located on a substrate;
[0006] A first electrode layer, an insulating layer, and a second electrode layer are located in the dielectric layer, the insulating layer is located on the second electrode layer, the first electrode layer is located on the insulating layer, and the end of the second electrode layer extends out of the ends of the first electrode layer and the insulating layer, exposing a portion of the top surface of the second electrode layer;
[0007] The first electrode layer includes a first metal electrode structure with a groove and a first barrier layer located in the groove. The first electrode layer, the insulating layer and the second electrode layer constitute a metal-insulating layer-metal capacitor structure.
[0008] In one feasible implementation, the first metal electrode structure further includes a second outer surface; the second outer surface is connected to the first outer surface.
[0009] The groove further includes a second inner wall disposed opposite to the second outer side, and the second inner wall is connected to the first inner wall;
[0010] The distance between the second outer surface and the second inner wall is not equal to the distance between the first outer surface and the first inner wall.
[0011] In one feasible implementation, the top of the first barrier layer is flush with the top of the first metal electrode structure.
[0012] In one feasible implementation, the thickness of the first metal electrode structure is 2 to 4 times the thickness of the first barrier layer.
[0013] In one feasible implementation, the thickness of the first metal electrode structure is 130 to 230 nanometers;
[0014] The depth of the groove is 20 to 100 nanometers.
[0015] In one feasible implementation, the second electrode layer includes a stacked second barrier layer, a second metal electrode structure, and a third barrier layer;
[0016] The insulating layer is provided on the second barrier layer.
[0017] In one feasible implementation, the thickness of the second metal electrode structure is greater than the thickness of the second barrier layer and the thickness of the third barrier layer.
[0018] In one feasible implementation, it also includes:
[0019] A contact structure that penetrates the dielectric layer and is electrically connected to the first electrode layer and the second electrode layer, respectively;
[0020] The dielectric layer is located on the surface of the first electrode layer and the surface of the second electrode layer.
[0021] In another aspect, this application also discloses a method for forming a semiconductor structure, which includes:
[0022] Provide a base;
[0023] A dielectric layer is formed on the substrate;
[0024] A second electrode layer and an insulating material layer are formed within the dielectric layer, the insulating material layer being on the second electrode layer;
[0025] A first electrode material layer is formed on the insulating material layer;
[0026] The first electrode material layer is patterned to form a groove in the first electrode material layer;
[0027] A first barrier layer is formed in the groove;
[0028] A portion of the first electrode material layer and a portion of the insulating material layer are removed to expose a portion of the top surface of the second electrode layer. An insulating layer and a first electrode layer are formed on the second electrode layer. The first electrode layer, the insulating layer, and the second electrode layer constitute a metal-insulating layer-metal capacitor structure.
[0029] In one feasible implementation, forming the first barrier layer in the groove includes:
[0030] A barrier material layer is formed on top of the first electrode material layer and within the groove;
[0031] The barrier material layer is planarized to remove the barrier material layer on top of the first electrode material layer, while retaining the barrier material layer within the groove.
[0032] In one feasible implementation, the insulating material layer comprises one or more of silicon oxide and high dielectric materials.
[0033] In one feasible implementation, the material of the first barrier layer includes tantalum nitride or titanium nitride;
[0034] The insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.
[0035] In one feasible implementation, it also includes:
[0036] A contact structure is formed in the dielectric layer that penetrates the dielectric layer and is electrically connected to the first electrode layer and the second electrode layer, respectively.
[0037] The dielectric layer is located on the surface of the first electrode layer and the surface of the second electrode layer.
[0038] The semiconductor structure provided in this application includes a dielectric layer on a substrate and a first electrode layer, an insulating layer, and a second electrode layer located within the dielectric layer. The insulating layer is located on the second electrode layer, and the first electrode layer is located on the insulating layer. The end of the second electrode layer extends beyond the ends of the first electrode layer and the insulating layer, exposing a portion of the top surface of the second electrode layer. The first electrode layer includes a first metal electrode structure with a groove and a first barrier layer located within the groove. The first electrode layer, the insulating layer, and the second electrode layer constitute a metal-insulating layer-metal capacitor structure. By embedding the first barrier layer into the groove of the first metal electrode structure, the problem of cracking at the top of the semiconductor structure during processing can be effectively avoided. Since the overall structural dimensions remain unchanged, it is advantageous for use in highly integrated devices or circuits. Attached Figure Description
[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0040] Figure 1 This is a top view of an exemplary existing capacitor according to this application;
[0041] Figure 2 This is a partial schematic diagram of an exemplary conventional capacitor of this application;
[0042] Figure 3 This is a schematic diagram of a semiconductor structure exemplified in this application;
[0043] Figure 4 This is a schematic diagram of the structure of a first electrode layer as exemplarily provided in this application;
[0044] Figure 5 This is a schematic diagram of another exemplary semiconductor structure of this application;
[0045] Figures 6 to 15 This is a schematic diagram illustrating a process for forming a semiconductor structure, as exemplified in this application.
[0046] The following is supplementary explanation of the attached figures:
[0047] 1-Substrate; 2-Dielectric layer; 201-First interlayer dielectric layer; 202-Second interlayer dielectric layer; 3-Capacitor structure; 301-First electrode layer; 3011-First metal electrode structure; 3012-First barrier layer; 3013-Groove; 3014-First outer surface; 3015-First inner wall; 302-Insulating layer; 303-Second electrode layer; 3031-Second barrier layer; 3032-Second metal electrode structure; 3033-Third barrier layer; 4-Contact structure; 5-Insulating material layer; 6-First electrode material layer; 7-Blocking material layer; 8-Light blocking layer; 9-Through hole. Detailed Implementation
[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0049] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.
[0050] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range from “1 to 10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.
[0051] Capacitors are often used in high-density applications, such as capacitor arrays in integrated circuits and large-scale capacitor manufacturing processes (such as processing capacitor arrays on a large wafer). These processes result in multiple capacitors being arranged densely, and the deposition and planarization of materials are inevitably involved in the process, which can further increase the stress in certain material layers and easily lead to cracks and defects in some weak points.
[0052] Please see Figure 1 and Figure 2The figures shown are a top view and a partial schematic diagram of an exemplary conventional capacitor according to this application. The capacitor includes at least a first electrode layer 301, an insulating layer, and a second electrode layer 303. The first electrode layer 301 is typically composed of a metal layer and a high-density barrier structure. Due to the high density and rigidity of the barrier structure, it not only achieves good adhesion to the metal layer but also prevents the photoresist from diffusing and contaminating the metal layer during subsequent photolithography processes and also prevents electromigration. However, capacitors usually need to be interconnected with upper and lower devices. To avoid unnecessary electrical conduction between the upper and lower devices and the capacitor, an insulating material is usually provided on the first electrode layer 301 of the capacitor. However, since the insulating material is mostly a loose and porous material, there is a stress mismatch problem between it and the high-density barrier structure. In particular, the presence of the first electrode layer 301 compresses the thickness of the dielectric material, making the dielectric material on the first electrode layer 301 thinner, making it more difficult to balance the stress of the first electrode layer 301, and easily causing cracks.
[0053] Furthermore, when the integration density of the capacitor is high, the coverage area of the first electrode layer 301 also increases, which further aggravates the stress mismatch between the first electrode layer 301 and the upper dielectric material, thereby causing cracks. Figure 1 and Figure 2 It can be seen that there are large areas of crack defects at the edge of the first electrode layer 301 (such as...). Figure 1 and Figure 2 (The area within the dashed box) will cause a short circuit between the first electrode layer 301 and the second electrode layer 303 of the capacitor.
[0054] To this end, this application provides a semiconductor structure, which includes at least a dielectric layer on a substrate and a first electrode layer, an insulating layer, and a second electrode layer located in the dielectric layer. The first electrode layer, the insulating layer, and the second electrode layer constitute a metal-insulating layer-metal capacitor structure. By designing the first metal electrode structure in the first electrode layer as a groove and placing a first barrier layer in the groove, the first barrier layer can effectively prevent cracks from occurring at the weak points at the top of the semiconductor structure by being enclosed by the groove. Moreover, the improvement of the semiconductor structure does not increase the size or complexity of the semiconductor structure, and it is still beneficial for the application of the semiconductor structure in the fields of miniaturization and high-density integration.
[0055] For details, please refer to Figure 3The diagram shows a schematic representation of a semiconductor structure exemplified in this application. This application discloses a semiconductor structure comprising a dielectric layer 2 on a substrate 1, and a first electrode layer 301, an insulating layer 302, and a second electrode layer 303 located within the dielectric layer 2. The insulating layer 302 is located on the second electrode layer 303. The first electrode layer 301 is located on the insulating layer 302, and the end of the second electrode layer 303 extends beyond the ends of the first electrode layer 301 and the insulating layer 302, exposing a portion of the top surface of the second electrode layer 303. The first electrode layer 301 includes a first metal electrode structure 3011 with a groove 3013, and a first barrier layer 3012 located within the groove 3013. The first electrode layer 301, the insulating layer 302, and the second electrode layer 303 constitute a metal-insulating layer-metal capacitor structure 3.
[0056] By setting the first barrier layer 3012 in the groove 3013 of the first metal electrode structure 3011, the problem of cracking at the top of the semiconductor structure can be effectively avoided, and the overall structural dimensions remain unchanged.
[0057] In one feasible implementation, please refer to Figure 4 The diagram illustrates a schematic representation of the structure of a first electrode layer 301 according to this application. The first metal electrode structure 3011 includes a first outer surface 3014 and a first side; the groove 3013 includes a first inner wall 3015 disposed opposite to the first outer surface 3014, and the first inner wall 3015 is the inner wall of the groove 3013 adjacent to the first outer surface 3014; the first inner wall 3015 and the first outer surface 3014 are sequentially disposed along the length direction of the first side; the distance D1 between the first outer surface 3014 and the first inner wall 3015 is 5% to 15% of the length of the first side, specifically, D1 can be 5%, 7%, 9%, 11%, 13%, or 15% of the length of the first side. This further ensures the storage performance of the capacitor structure 3 while also preventing cracking in the semiconductor structure.
[0058] In another feasible embodiment, the first metal electrode structure 3011 further includes a second outer side surface; the second outer side surface is connected to the first outer side surface 3014; the groove 3013 further includes a second inner wall disposed opposite to the second outer side surface, and the second inner wall is connected to the first inner wall 3015; the distance between the second outer side surface and the second inner wall is not equal to the distance between the first outer side surface 3014 and the first inner wall 3015, that is, the distances D2 and D1 between the second inner wall and the second outer side surface are not equal. In another feasible embodiment, the first metal electrode structure 3011 further includes a third outer side surface, the third outer side surface being disposed opposite to the first outer side surface 3014; the groove 3013 further includes a third inner wall disposed opposite to the third outer side surface, and the third inner wall being disposed opposite to the first inner wall 3015; the distance D3 between the third outer side surface and the third inner wall is not equal to the distance D1 between the first outer side surface 3014 and the first inner wall 3015. In another feasible embodiment, the first metal electrode structure 3011 further includes a fourth outer side surface, which is disposed opposite to the second outer side surface; the groove 3013 further includes a fourth inner wall, which is disposed opposite to the second inner wall; the distance D4 between the fourth outer side surface and the fourth inner wall is not equal to the distance D1 between the first outer side surface 3014 and the first inner wall 3015.
[0059] The above example shows a tetrahedral semiconductor structure. In practice, other regular or irregular shapes can be used as needed, without limitation. Optionally, the sum of D1 and D3 can be 10% to 30% of the length of the first side. Specifically, the sum of D1 and D3 can be 10%, 12%, 14%, 16%, 18%, 20%, 22%, 24%, 26%, 28%, or 30% of the length of the first side. The first metal electrode structure 3011 also includes a second side connected to the first side. The sum of D2 and D4 can be 10% to 30% of the length of the second side. Specifically, the sum of D2 and D4 can be 10%, 12%, 14%, 16%, 18%, 20%, 22%, 24%, 26%, 28%, or 30% of the length of the first side. In other embodiments, the distances between D1, D2, D3 and D4 can be equal, or any two distance values can be equal, or any three distance values can be equal. Specifically, the distance between the inner wall of the groove 3013 and the outer side of the first metal electrode structure 3011 can be set as needed, as long as the above-mentioned crack phenomenon can be avoided and the area of the first barrier layer 3012 is as large as possible.
[0060] In one feasible implementation, the thickness H1 of the first metal electrode structure 3011 is 100 to 300 nanometers; specifically, the thickness H1 of the first metal electrode structure 3011 can be 100 nanometers, 120 nanometers, 140 nanometers, 160 nanometers, 180 nanometers, 200 nanometers, 220 nanometers, 240 nanometers, 260 nanometers, 280 nanometers, or 300 nanometers. The depth of the groove 3013 is 1 / 4 to 1 / 2 of the thickness H1 of the first metal electrode structure 3011, for example, the depth of the groove 3013 can be 1 / 4, 1 / 3, or 1 / 2 of the thickness H1 of the first metal electrode structure 3011. Optionally, since the depth of the groove 3013 determines the thickness of the first barrier layer 3012, the specific depth of the groove 3013 can be determined according to the thickness of the barrier layer to be filled.
[0061] In one feasible implementation, the top of the first barrier layer 3012 is flush with the top of the first metal electrode structure 3011. Specifically, after the material of the first barrier layer 3012 is filled into the groove 3013, the material of the first barrier layer 3012 can be ground by a planarization process to make the top of the first barrier layer 3012 flush with the top of the first metal electrode structure 3011. Alternatively, a combination of etching and planarization processes can be used, and this is not limited. Optionally, the planarization process includes chemical mechanical polishing.
[0062] In one feasible implementation, the thickness of the first metal electrode structure 3011 is 2 to 4 times the thickness of the first barrier layer 3012. Specifically, the thickness of the first metal electrode structure 3011 is 2, 2.5, 3, 3.5, or 4 times the thickness of the first barrier layer 3012. Since the first metal electrode structure 3011 is the main structure of the first electrode layer 301, its thickness determines the capacity and voltage withstand capability of the semiconductor structure. Generally, the voltage withstand capability is directly proportional to the thickness of the first metal electrode structure 3011, and the capacity is inversely proportional to the thickness of the first metal electrode structure 3011. Therefore, it is necessary to set an appropriate thickness for the first metal electrode structure 3011. The barrier layer, as a structural layer to prevent photoresist contamination of the first metal electrode structure 3011 in subsequent photolithography processes and to prevent electron migration, achieves the above functions while having the smallest possible thickness. Considering factors such as stress matching, the thicknesses of the first metal electrode structure 3011 and the first barrier layer 3012 are set in the above proportional relationship.
[0063] For example, the material of the first metal electrode structure 3011 may include one or more combinations of titanium, silver, copper, tungsten, cobalt, aluminum, nickel, and platinum. In the embodiments of this application, the material of the first metal electrode structure 3011 may be aluminum or copper.
[0064] In one feasible implementation, the first barrier layer 3012 and the first metal electrode structure 3011 need to have good adhesion properties and high density, thereby avoiding contamination of the first metal electrode structure 3011 by photoresist in subsequent photolithography processes, preventing electron migration, and serving as an etching stop layer for subsequent etching of the contact structure 4. Therefore, the material of the first barrier layer 3012 may include relatively high-density dielectric materials such as tantalum nitride or titanium nitride.
[0065] In one feasible embodiment, the thickness of the insulating layer 302 is 20 to 50 nanometers. Specifically, the thickness of the insulating layer 302 can be 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, or 50 nanometers. The material of the insulating layer 302 includes one or more of silicon oxide and high dielectric materials. The high dielectric material refers to a dielectric material with a dielectric constant greater than 3.9, and the high dielectric material can include any one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, Al2O3, SrTiO3, and BaSrTiO.
[0066] In one feasible implementation, please refer to Figure 5 The diagram illustrates another exemplary semiconductor structure according to this application. Specifically, the dielectric layer 2 is located on the surfaces of the first electrode layer and the second electrode layer; the dielectric layer 2 serves as the dielectric for forming the metal-insulator-metal capacitor structure 3, and also serves for electrical isolation between signal lines and between semiconductor devices in semiconductor integrated circuits. Furthermore, the dielectric layer 2 can prevent external impurities from entering the semiconductor structure through the bottom of the substrate 1 and causing semiconductor device failure.
[0067] In this embodiment, the substrate 1 provides a process platform for the formation of the metal-insulator-metal capacitor structure 3. The substrate 1 is a silicon substrate, and the material of the substrate 1 is single-crystal silicon. In other embodiments, the material of the substrate 1 may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The substrate 1 may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0068] Specifically, the dielectric layer 2 includes a first interlayer dielectric layer 201 and a second interlayer dielectric layer 202. For example, the material of the first interlayer dielectric layer 201 is an insulating material; the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.
[0069] For example, the second interlayer dielectric layer 202 is used to isolate the semiconductor structure from the upper-layer device, providing good isolation. The material of the second interlayer dielectric layer 202 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. Since the second interlayer dielectric layer 202 is distributed on the first electrode layer 301 and part of the second electrode layer 303, the thickness of the second interlayer dielectric layer 202 on the first electrode layer 301 is less than the thickness of the second interlayer dielectric layer 202 on the second electrode layer 303. To ensure isolation while achieving device miniaturization, the thickness of the second interlayer dielectric layer 202 on the first electrode layer 301 cannot be too large; its thickness can be 500 to 1000 nanometers. Specifically, the thickness of the second interlayer dielectric layer 202 can be 500 nanometers, 600 nanometers, 700 nanometers, 800 nanometers, 900 nanometers, or 1000 nanometers. However, this is still relatively thin and cannot balance the stress in the large-sized first barrier layer 3012. As a result, cracks are easily generated at the edge where the first barrier layer 3012 contacts the second interlayer dielectric layer 202. This solution avoids the contact between the end of the first barrier layer 3012 and the second interlayer dielectric layer 202 by placing the first barrier layer 3012 in the groove 3013 of the first metal electrode structure 3011. It also reduces the size and area of the first barrier layer 3012 to a certain extent, thereby effectively avoiding the cracking phenomenon at the end of the first barrier layer 3012 and improving the electrical performance of the capacitor.
[0070] Please continue reading. Figure 5 The second electrode layer 303 includes a stacked second barrier layer 3031, a second metal electrode structure 3032 and a third barrier layer 3033; the second barrier layer 3031 is provided with the insulating layer 302.
[0071] For example, the thickness of the second metal electrode structure 3032 is 2 to 4 times the thickness of the first metal electrode structure 3031. Specifically, the thickness of the second metal electrode structure 3032 is 2, 2.5, 3, 3.5, or 4 times the thickness of the first metal electrode structure 3031. The thickness of the second metal electrode structure 3032 is greater than the thickness of the second barrier layer 3031 and the thickness of the third barrier layer 3033.
[0072] For example, the thickness of the second barrier layer 3031 is 25 to 150 nanometers; specifically, the thickness of the second barrier layer 3031 is 25 nanometers, 50 nanometers, 75 nanometers, 100 nanometers, 125 nanometers, or 150 nanometers, and the thickness of the third barrier layer 3033 is 25 to 150 nanometers; specifically, the thickness of the third barrier layer 3033 is 25 nanometers, 50 nanometers, 75 nanometers, 100 nanometers, 125 nanometers, or 150 nanometers. The thickness of the second barrier layer 3031 can be the same as or different from the thickness of the third barrier layer 3033, and this is not limited here. Optionally, the thickness of the second barrier layer 3031 can be the same as or different from the thickness of the first barrier layer 3012, and the thickness of the third barrier layer 3033 can be the same as or different from the thickness of the first barrier layer 3012. The second barrier layer 3031 and the third barrier layer 3033 have the same function as the first barrier layer 3012. They need to have good adhesion to the second metal electrode structure 3032 and have high density, so as to avoid the contamination of the first metal electrode structure 3011 by photoresist in subsequent photolithography processes, as well as prevent electron migration. They can also serve as an etching stop layer for subsequent etching of the contact structure 4.
[0073] For example, the materials of the second barrier layer 3031 and the third barrier layer 3033 include dielectric materials with relatively high density such as tantalum nitride or titanium nitride.
[0074] For example, the material of the second metal electrode structure 3032 may include one or more combinations of titanium, silver, copper, tungsten, cobalt, aluminum, nickel, and platinum. In the embodiments of this application, the material of the second metal electrode structure 3032 may be aluminum or copper.
[0075] For example, the thickness of the second metal electrode structure 3032, which forms the main structure of the second electrode layer 303, determines the capacitance and voltage withstand capability of the capacitor structure 3. Generally, the voltage withstand capability is directly proportional to the thickness of the second metal electrode structure 3032, while the capacitance is inversely proportional to the thickness of the second metal electrode structure 3032. Therefore, it is necessary to set an appropriate thickness for the first metal electrode structure 3011. The barrier layer, as a structural layer to prevent photoresist from contaminating the second metal electrode structure 3032 in subsequent photolithography processes and to prevent electron migration, needs to achieve the above functions while keeping its thickness as small as possible. Considering factors such as stress matching, it is necessary to set an appropriate ratio between the thicknesses of the second metal electrode structure 3032, the second barrier layer 3031, and the third barrier layer. In this embodiment, the thickness of the second barrier layer 3031 is equal to the thickness of the third barrier layer 3033.
[0076] For example, please continue reading Figure 5The area of the second electrode layer 303 is larger than the area of the first electrode layer 301. Specifically, the first electrode layer 301 includes a first side and a second side disposed opposite to each other; the second electrode layer 303 includes a third side and a fourth side disposed opposite to each other; the first side and the third side are aligned, and there is a preset distance between the second side and the fourth side. Furthermore, the distance between the third side and the fourth side is greater than the distance between the first side and the second side, so that the second electrode layer 303 can be connected to an external circuit through the area protruding from the first electrode layer 301.
[0077] In one feasible implementation, the semiconductor structure further includes a contact structure 4 that penetrates the dielectric layer 2 and is electrically connected to the first electrode layer 301 and the second electrode layer 303, respectively. Specifically, a contact structure 4 is provided on the first barrier layer 3012 and the second barrier layer 3031, and the contact structure 4 is used to communicate with the metal layer of the upper device. Optionally, the material of the contact structure 4 is a conductive material, such as one or more metal materials such as copper, tungsten, cobalt, and nickel.
[0078] This application also provides a method for forming a semiconductor structure, which is described below:
[0079] Please see Figure 6 The system provides a substrate 1; a dielectric layer 2 is formed on the substrate 1; the dielectric layer 2 is located on the surface of the first electrode layer and the surface of the second electrode layer; the dielectric layer 2 is used to form the dielectric of the metal-insulator-metal capacitor structure 3, and also for electrical isolation between signal lines and between semiconductor devices in semiconductor integrated circuits. In addition, the dielectric layer 2 can also prevent external impurities from entering the semiconductor structure through the bottom of the substrate 1 and causing failure of the semiconductor device.
[0080] In this embodiment, the substrate 1 provides a process platform for the formation of the metal-insulator-metal capacitor structure 3. The substrate 1 is a silicon substrate, and the material of the substrate 1 is single-crystal silicon. In other embodiments, the material of the substrate 1 may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The substrate 1 may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0081] A second electrode layer 303 and an insulating material layer 5 are formed within the dielectric layer 2, wherein the insulating material layer 5 is located on the second electrode layer 303. Specifically, the structures of the second electrode layer 303 and the insulating layer 5 can be as follows: Figure 7 As shown.
[0082] For example, a third barrier layer 3033 may be formed first, then a second metal electrode structure 3032 may be formed on the third barrier layer 3033, and then a second barrier layer 3031 may be formed on the second metal electrode structure 3032.
[0083] For example, the forming process of the second barrier layer 3031 and the third barrier layer 3033 may include chemical vapor deposition, low-pressure chemical vapor deposition, ion-enhanced chemical vapor deposition, or atomic layer deposition.
[0084] For example, the thickness of the second barrier layer 3031 is 25 to 150 nanometers; specifically, the thickness of the second barrier layer 3031 can be 25 nanometers, 50 nanometers, 75 nanometers, 100 nanometers, 125 nanometers, or 150 nanometers. The thickness of the third barrier layer 3033 is 25 to 150 nanometers; specifically, the thickness of the third barrier layer 3033 can be 25 nanometers, 50 nanometers, 75 nanometers, 100 nanometers, 125 nanometers, or 150 nanometers. The thickness of the second barrier layer 3031 can be the same as or different from the thickness of the third barrier layer 3033; this is not limited here. Optionally, the thickness of the second barrier layer 3031 can be the same as or different from the thickness of the first barrier layer 3012, and the thickness of the third barrier layer 3033 can be the same as or different from the thickness of the first barrier layer 3012. The second barrier layer 3031 and the third barrier layer 3033 need to have good adhesion properties to the second metal electrode structure 3032, and also have high density. This can prevent the photoresist from contaminating the first metal electrode structure 3011 in the subsequent photolithography process, as well as prevent electron migration. They can also serve as an etching stop layer for the subsequent etching of the contact structure 4.
[0085] For example, the materials of the second barrier layer 3031 and the third barrier layer 3033 include dielectric materials with relatively high density such as tantalum nitride or titanium nitride.
[0086] For example, the forming process of the second metal electrode structure 3032 may include atomic layer deposition, ion reactive sputtering, chemical vapor deposition, physical vapor deposition or electroplating.
[0087] For example, the material of the second metal electrode structure 3032 may include one or more combinations of titanium, silver, copper, tungsten, cobalt, aluminum, nickel, and platinum. In this embodiment, the material of the second metal electrode structure 3032 may be copper or aluminum.
[0088] For example, the thickness of the second metal electrode structure 3032 is 2 to 4 times the thickness of the first metal electrode structure 3031. Specifically, the thickness of the second metal electrode structure 3032 is 2, 2.5, 3, 3.5, or 4 times the thickness of the first metal electrode structure 3031. The thickness of the second metal electrode structure 3032 is greater than the thickness of the second barrier layer 3031 and the thickness of the third barrier layer 3033.
[0089] In this embodiment, multiple semiconductor structures (or capacitor structures 3) may be formed in the semiconductor, or only one semiconductor structure (or capacitor structure 3) may be formed. Since these semiconductor structures (or capacitor structures 3) have the same structure, the forming steps are also the same. Subsequently, they can be divided into individual capacitors as needed after forming. This application can also be used to form multilayer stacked capacitors. The capacitors of different layers can be interconnected through contact structures 4. Therefore, this application only describes the formation of a certain layer structure. Other layers can be formed using the same forming scheme.
[0090] For example, the forming process of the insulating material layer 5 may include chemical vapor deposition, low-pressure chemical vapor deposition, ion-enhanced chemical vapor deposition, or atomic layer deposition.
[0091] The thickness of the insulating material layer 5 is 20 to 50 nanometers. Specifically, the thickness of the insulating layer 302 can be 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, or 50 nanometers. The material of the insulating layer 302 includes one or more of silicon oxide and high dielectric materials. The high dielectric material refers to a dielectric material with a dielectric constant greater than 3.9, and the high dielectric material can include any one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, Al2O3, SrTiO3, and BaSrTiO.
[0092] By forming a first electrode material layer 6 on the insulating material layer 5, the following can be obtained: Figure 8 The structure shown.
[0093] For example, forming the first electrode material layer 6 may include atomic layer deposition, ion reactive sputtering, chemical vapor deposition, physical vapor deposition, or electroplating.
[0094] For example, the material of the first electrode material layer 6 may include one or more combinations of titanium, silver, copper, tungsten, cobalt, aluminum, nickel and platinum.
[0095] For example, the thickness of the first electrode material layer 6 is 100 to 300 nanometers; specifically, the thickness of the first electrode material layer 6 can be 100 nanometers, 120 nanometers, 140 nanometers, 160 nanometers, 180 nanometers, 200 nanometers, 220 nanometers, 240 nanometers, 260 nanometers, 280 or 300 nanometers.
[0096] The first electrode material layer 6 is patterned to form a groove 3013 in the first electrode material layer 6.
[0097] Specifically, the process of patterning the first electrode material layer 6 can be described as follows: First, a photoblock layer 8 is formed on the first electrode material layer 6. This photoblock can specifically be a photoresist. Exposure and development processes are performed on the photoblock layer 8 to pattern it, forming an etching window on the photoblock. Subsequently, based on this etching window, the first electrode material layer 6 is etched to form a groove 3013 in the first electrode material layer 6, resulting in... Figure 9 The structure shown is then followed by the removal of the light-blocking layer 8.
[0098] The depth of the groove 3013 is 1 / 4 to 1 / 2 of the thickness of the first electrode material layer 6. For example, the depth of the groove 3013 can be 1 / 4, 1 / 3, or 1 / 2 of the thickness of the first electrode material layer 6. Optionally, since the depth of the groove 3013 determines the thickness of the first barrier layer 3012, the specific depth of the groove 3013 can be determined according to the thickness of the barrier layer to be filled.
[0099] A first barrier layer 3012 is formed in the groove 3013, resulting in the following: Figure 10 The structure shown.
[0100] In one feasible implementation, forming the first barrier layer 3012 in the groove 3013 includes: forming a barrier material layer 7 on top of the first electrode material layer 6 and within the groove 3013, to obtain... Figure 11 The structure shown; by planarizing the barrier material layer 7 to remove the barrier material layer 7 located on top of the first electrode material layer 6, and retaining the barrier material layer 7 within the groove 3013, the following can be obtained: Figure 10 The structure shown.
[0101] For example, the planarization process can be a chemical mechanical polishing process.
[0102] For example, the forming process of the barrier material layer 7 may include chemical vapor deposition, low-pressure chemical vapor deposition, ion-enhanced chemical vapor deposition, or atomic layer deposition.
[0103] For example, the material of the barrier material layer 7 includes a relatively high-density dielectric material such as tantalum nitride or titanium nitride.
[0104] A portion of the first electrode material layer 6 and a portion of the insulating material layer 5 are removed to expose a portion of the top surface of the second electrode layer 303. An insulating layer 302 and a first electrode layer 301 are formed on the second electrode layer 303. The first electrode layer 301, the insulating layer 302, and the second electrode layer 303 constitute a metal-insulating layer-metal capacitor structure 3.
[0105] For example, the process of removing part of the first electrode material layer 6 and part of the insulating material layer 5 described above can be as follows: First, a light-blocking layer 8 is formed on the top of the first electrode layer 301. This light-blocking layer can specifically be photoresist. Exposure and development processes are performed on the light-blocking layer 8 to pattern it, forming an etching window on the light-blocking layer. Subsequently, based on this etching window, the metal material layer and the insulating material layer 5 are etched to expose part of the top surface of the second electrode layer 303. An insulating layer 302 and the first electrode layer 301 are then formed on the second electrode layer 303, resulting in the desired appearance. Figure 12 The structure shown is then followed by the removal of the light-blocking layer 8.
[0106] The above steps can yield the following result: Figure 13 The semiconductor structure shown can be obtained by performing photolithography, etching and filling processes on the dielectric layer 2 in sequence.
[0107] For example, the dielectric layer 2 may include a first interlayer dielectric layer 201 and a second interlayer dielectric layer 202, wherein the first interlayer dielectric layer 201 is located below the third barrier layer, the material density of the first barrier layer 3012 is greater than the material density of the second interlayer dielectric layer 202, and the second interlayer dielectric layer 202 is located on a portion of the top surface of the second electrode layer 303, the top and sidewalls of the first electrode layer 301, and the sidewalls of the insulating layer 302, i.e. Figure 13 The structure shown.
[0108] For example, the material of the first interlayer dielectric layer 201 is an insulating material; the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.
[0109] For example, the process of the first interlayer dielectric layer 201 includes chemical vapor deposition, low-pressure chemical vapor deposition, ion-enhanced chemical vapor deposition, or atomic layer deposition.
[0110] For example, the second interlayer dielectric layer 202 is used to isolate the semiconductor structure from the upper-layer device, providing good isolation. The material of the second interlayer dielectric layer 202 is an insulating material; the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. Since the second interlayer dielectric layer 202 is distributed on the first electrode layer 301 and part of the second electrode layer 303, the thickness of the second interlayer dielectric layer 202 on the first electrode layer 301 is less than the thickness of the second interlayer dielectric layer 202 on the second electrode layer 303. In order to achieve device miniaturization while ensuring isolation, the thickness of the second interlayer dielectric layer 202 on the first electrode layer 301 cannot be too large; its thickness can be 500 to 1000 nanometers. However, this is still relatively thin and cannot balance the large-size first electrode layer 301. The stress in the barrier layer 3012 can easily cause cracks at the edge where the first barrier layer 3012 contacts the second interlayer dielectric layer 202. This solution avoids contact between the end of the first barrier layer 3012 and the second interlayer dielectric layer 202 by placing the first barrier layer 3012 in the groove 3013 of the first metal electrode structure 3011. It also reduces the size and area of the first barrier layer 3012 to a certain extent, thereby effectively avoiding cracks at the end of the first barrier layer 3012 and improving the electrical performance of the capacitor.
[0111] For example, the process of the second interlayer dielectric layer 202 includes chemical vapor deposition, low-pressure chemical vapor deposition, ion-enhanced chemical vapor deposition, or atomic layer deposition.
[0112] Subsequently, a contact structure 4 is formed in the dielectric layer, penetrating the dielectric layer and electrically connecting the first electrode layer and the second electrode layer respectively. Specifically, a photoblocking layer 8 can be formed on the second interlayer dielectric layer 202. This photoblocking layer can be photoresist. The photoblocking layer 8 is then exposed and developed to pattern it, forming an etching window on the photoblocking layer. Subsequently, the second interlayer dielectric layer 202 is etched based on this etching window to form a via 9 in the second interlayer dielectric layer 202. A via 9 is formed on the first barrier layer 3012 and the second barrier layer 3031 respectively, resulting in... Figure 14 The structure shown is then followed by the removal of the light-blocking layer 8.
[0113] Next, conductive material is filled into the through-holes 9 of the second interlayer dielectric layer 202 to form a contact structure 4, resulting in the following: Figure 15 The structure shown.
[0114] The contact structure 4 is used to communicate with the metal layer of the upper device. Optionally, the material of the contact structure 4 is a conductive material, such as one or more of the following metals: copper, tungsten, cobalt, nickel, etc.
[0115] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0116] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.
[0117] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.
[0118] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A semiconductor structure, characterized in that, include: A dielectric layer located on a substrate; A first electrode layer, an insulating layer, and a second electrode layer are located in the dielectric layer, the insulating layer is located on the second electrode layer, the first electrode layer is located on the insulating layer, and the end of the second electrode layer extends out of the ends of the first electrode layer and the insulating layer, exposing a portion of the top surface of the second electrode layer; The first electrode layer includes a first metal electrode structure with a groove and a first barrier layer located in the groove. The first electrode layer, the insulating layer and the second electrode layer constitute a metal-insulating layer-metal capacitor structure.
2. The semiconductor structure according to claim 1, characterized in that, The first metal electrode structure includes a first outer surface and a first side; The groove includes a first inner wall disposed opposite to the first outer side surface, and the first inner wall is the inner wall of the groove adjacent to the first outer side surface. The first inner wall and the first outer side are arranged sequentially along the length direction of the first side; The distance between the first outer side and the first inner wall is 5% to 15% of the length of the first side.
3. The semiconductor structure according to claim 2, characterized in that, The first metal electrode structure further includes a second outer surface; the second outer surface is connected to the first outer surface; The groove further includes a second inner wall disposed opposite to the second outer side, and the second inner wall is connected to the first inner wall; The distance between the second outer surface and the second inner wall is not equal to the distance between the first outer surface and the first inner wall.
4. The semiconductor structure according to any one of claims 1-3, characterized in that, The top of the first barrier layer is flush with the top of the first metal electrode structure.
5. The semiconductor structure according to claim 4, characterized in that, The thickness of the first metal electrode structure is 2 to 4 times the thickness of the first barrier layer.
6. The semiconductor structure according to claim 5, characterized in that, The thickness of the first metal electrode structure is 130 to 230 nanometers; The depth of the groove is 20 to 100 nanometers.
7. The semiconductor structure according to any one of claims 1-6, characterized in that, The second electrode layer includes a stacked second barrier layer, a second metal electrode structure, and a third barrier layer; The insulating layer is provided on the second barrier layer.
8. The semiconductor structure according to claim 7, characterized in that, The thickness of the second metal electrode structure is greater than the thickness of the second barrier layer and the thickness of the third barrier layer.
9. The semiconductor structure according to claim 1, characterized in that, Also includes: The contact structure penetrates the dielectric layer and is electrically connected to the first electrode layer and the second electrode layer, respectively.
10. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A dielectric layer is formed on the substrate; A second electrode layer and an insulating material layer are formed within the dielectric layer, the insulating material layer being on the second electrode layer; A first electrode material layer is formed on the insulating material layer; The first electrode material layer is patterned to form a groove in the first electrode material layer; A first barrier layer is formed in the groove; A portion of the first electrode material layer and a portion of the insulating material layer are removed to expose a portion of the top surface of the second electrode layer. An insulating layer and a first electrode layer are formed on the second electrode layer. The first electrode layer, the insulating layer, and the second electrode layer constitute a metal-insulating layer-metal capacitor structure.
11. The forming method according to claim 10, characterized in that, The formation of the first barrier layer in the groove includes: A barrier material layer is formed on top of the first electrode material layer and within the groove; The barrier material layer is planarized to remove the barrier material layer on top of the first electrode material layer, while retaining the barrier material layer within the groove.
12. The forming method according to claim 10, characterized in that, The insulating material layer is made of one or more of silicon oxide and high dielectric materials.
13. The forming method according to claim 10, characterized in that, The material of the first barrier layer includes tantalum nitride or titanium nitride; The insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.
14. The forming method according to any one of claims 10-13, characterized in that, Also includes: A contact structure is formed in the dielectric layer that penetrates the dielectric layer and electrically connects the first electrode layer and the second electrode layer, respectively.