Capacitor structure, method for manufacturing capacitor structure and bcd device

Abstract

The application provides a capacitor structure, a preparation method of the capacitor structure and a BCD device. The preparation method comprises the following steps: providing a substrate, sequentially forming a lower electrode and a first insulating layer on the substrate; performing etching treatment on the first insulating layer, so that the thickness of the first insulating layer in a partial region is thinned, a plurality of convex parts distributed along a first direction are obtained, the convex parts are convex towards the direction of the lower electrode away from the substrate, and the first direction is perpendicular to the thickness direction of the lower electrode; filling a first protective layer between any two adjacent convex parts, the first protective layer covering the sidewall of the convex part in the first direction; forming an upper electrode on the side of the plurality of convex parts and the first protective layer away from the substrate, and performing etching treatment on the upper electrode, so as to reserve the upper electrode on the surface of the side of the convex part away from the substrate. The application solves the problem that the capacitor structure in the prior art is prone to leakage failure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and more specifically, to a capacitor structure, a method for preparing the capacitor structure, and a BCD device. Background Technology

[0002] Metal-Insulator-Metal (MIM) capacitors enable stable, high-linearity capacitance to be achieved in a small area. In BCD (Bipolar-CMOS-DMOS) technology, MIM is composed of a metal-insulator-metal structure. In the traditional MIM etching process, after depositing the dielectric layer and the top electrode, photoresist (PR) is first spin-coated, followed by development and etching of the top electrode. After etching, the bottom electrode is etched, and a protective layer is deposited on the surface after etching is complete.

[0003] In the aforementioned technology, plasma bombardment causes the electrode portions to be sputtered and detached. The detached particles combine with elements in the photoresist to form polymers. These polymers tend to adhere to the sidewalls of the dielectric layer and are difficult to completely remove by subsequent processes. This can easily cause the upper and lower electrodes of the MIM to conduct, leading to MIM failure.

[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main objective of this application is to provide a capacitor structure, a method for fabricating the capacitor structure, and a BCD device to solve the problem that capacitor structures in the prior art are prone to leakage failure.

[0006] To achieve the above objectives, according to one aspect of this application, a method for fabricating a capacitor structure is provided, comprising: providing a substrate, and sequentially forming a lower electrode and a first insulating layer on the substrate; etching the first insulating layer to reduce the thickness of the first insulating layer in a portion of the region to obtain a plurality of protrusions distributed along a first direction, the protrusions protruding toward the substrate in a direction pointing toward the lower electrode, the first direction being perpendicular to the thickness direction of the lower electrode; filling a first protective layer between any two adjacent protrusions, the first protective layer covering the sidewalls of the protrusions in the first direction; forming an upper electrode on the side of the plurality of protrusions and the first protective layer away from the substrate, and etching the upper electrode to retain the upper electrode located on the surface of the protrusions on the side away from the substrate.

[0007] Optionally, the step of filling the first protective layer between any two adjacent protrusions includes: depositing an oxide material on the first insulating layer on which the plurality of protrusions are formed to form the first protective layer covering the first insulating layer; planarizing the first protective layer until the protrusions are exposed, while retaining the first protective layer located between adjacent protrusions.

[0008] Optionally, the step of forming the upper electrode on the side of the plurality of protrusions and the first protective layer away from the substrate includes: depositing electrode material on the side of the plurality of protrusions and the first protective layer away from the substrate to form the upper electrode; forming a photolithographic pattern layer on the side of the upper electrode away from the substrate; and performing wet etching on the upper electrode using the photolithographic pattern layer as a mask to obtain the upper electrode corresponding to each of the protrusions.

[0009] Optionally, the step of forming the photolithographic pattern layer on the side of the upper electrode away from the substrate includes: sequentially forming a first anti-reflection layer and a first photoresist layer on the side of the upper electrode away from the substrate; exposing and developing the first photoresist layer so that the retained first photoresist layer corresponds to the position of the protrusion; using the first photoresist layer as a mask, etching the first anti-reflection layer to expose the upper electrode.

[0010] Optionally, after forming the upper electrode, the fabrication method further includes removing the first protective layer using a wet etching process or a dry etching process.

[0011] Optionally, after removing the first protective layer, the fabrication method further includes: removing the photolithographic pattern layer; depositing a protective material on the current structure to form a second protective layer covering the upper electrode and the first insulating layer.

[0012] Optionally, the step of etching the first insulating layer to reduce the thickness of the first insulating layer in a certain area to obtain a plurality of protrusions includes: forming a second photoresist layer on the side of the first insulating layer away from the substrate; exposing and developing the second photoresist layer to give the second photoresist layer a pre-pattern and exposing a portion of the first insulating layer; using the second photoresist layer as a mask to etch back a portion of the first insulating layer to form a plurality of grooves, and forming a plurality of protrusions in the unetched portion of the first insulating layer.

[0013] According to another aspect of this application, a capacitor structure is provided, which is prepared by the above-described capacitor structure preparation method. The capacitor structure includes: a lower electrode; a first insulating layer located on the lower electrode, the first insulating layer having a plurality of protrusions distributed along a first direction, the first direction being perpendicular to the thickness direction of the lower electrode; and an upper electrode located on the side of the protrusions opposite to the lower electrode.

[0014] Optionally, the thickness of the first insulating layer between any two adjacent protrusions ranges from 208 Å to 222 Å, and the lower electrode has a first end and a second end opposite to each other in the first direction, with the thickness of the first insulating layer on the surfaces of the first end and the second end ranging from 108 Å to 112 Å.

[0015] According to another aspect of this application, a BCD device is provided, including at least one of the said capacitor structures.

[0016] According to the technical solution of this application, the method for fabricating a capacitor structure includes: providing a substrate; sequentially forming a lower electrode and a first insulating layer on the substrate; etching the first insulating layer to reduce the thickness of the first insulating layer in a certain area, resulting in a plurality of protrusions distributed along a first direction, the protrusions protruding towards the substrate in the direction of the lower electrode, the first direction being perpendicular to the thickness direction of the lower electrode; filling a first protective layer between any two adjacent protrusions, the first protective layer covering the sidewalls of the protrusions in the first direction; forming an upper electrode on the side of the plurality of protrusions and the first protective layer away from the substrate, and etching the upper electrode to retain the upper electrode on the surface of the protrusions on the side away from the substrate. In this application, after forming a lower electrode and a first insulating layer sequentially on a substrate, the first insulating layer is etched to form a protrusion facing the upper electrode. A first protective layer is then filled between adjacent protrusions. Subsequently, the upper electrode is formed, and the portion of the protrusion located on the side facing away from the substrate is etched. This results in an insulating structure between the upper and lower electrodes that includes not only the main body of the first insulating layer but also the first protective layer filled between the protrusions. The first protective layer can effectively isolate the metal material generated during the etching of the upper electrode, preventing the metal material from directly contacting the lower electrode. This directly solves the technical problem in the prior art where the capacitor structure is prone to leakage failure due to the sidewall polymer covering the sidewall of the first insulating layer. This improves the insulation performance of the capacitor structure, prevents short circuit leakage between the upper and lower plates, and thus enhances the reliability of the device. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 A schematic flowchart of a method for fabricating a capacitor structure according to an embodiment of this application is shown;

[0019] Figures 2 to 14 A schematic diagram of the cross-sectional structure of the semiconductor substrate is shown during the fabrication of the capacitor structure.

[0020] The above figures include the following reference numerals:

[0021] 11. Substrate; 12. Lower electrode; 13. First insulating layer; 131. Protrusion; 14. First protective layer; 15. Upper electrode; 16. Photolithographic pattern layer; 161. First anti-reflective layer; 162. First photoresist layer; 17. Second protective layer; 18. Second photoresist layer. Detailed Implementation

[0022] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0026] For ease of description, the following explains some of the nouns or terms used in the embodiments of this application:

[0027] BCD devices refer to mixed-signal integrated circuits manufactured using BCD (Bipolar-CMOS-DMOS) technology. Their core feature is the high integration of bipolar transistors (Bipolar, providing high-speed, high-precision analog processing capabilities), complementary metal-oxide-semiconductor (CMOS, providing low-power, high-integration digital logic processing capabilities), and high-voltage double-diffused metal-oxide-semiconductor (DMOS, providing high-voltage, high-current power drive capabilities) on a single silicon chip. This type of device achieves a perfect fusion of digital control, analog signal processing, and power drive functions through single-chip integration, effectively solving the problems of large size, high cost, and severe signal interference inherent in discrete device solutions.

[0028] As described in the background section, in the prior art, during the fabrication of capacitor structures, metal residues generated in the etching step of the upper electrode can easily come into contact with the lower electrode along the sidewall of the insulating layer between the upper and lower electrodes, leading to communication between the upper and lower electrodes and causing leakage failure of the capacitor structure. To solve the problem of leakage failure of capacitor structures in the prior art, the embodiments of this application provide a capacitor structure, a method for fabricating the capacitor structure, and a BCD device.

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0030] Figure 1 This is a flowchart of a method for fabricating a capacitor structure according to an embodiment of this application. Figure 1 As shown, the method includes the following steps:

[0031] Step S1, as follows Figure 2 As shown, a substrate 11 is provided, on which a lower electrode 12 and a first insulating layer 13 are sequentially formed;

[0032] Specifically, the basic structural layer of a MIM capacitor is constructed by sequentially forming a lower electrode and a first insulating layer on a substrate. The lower electrode, serving as one of the capacitor's plates, provides the conductive foundation for the subsequent capacitor structure; its material can be TiN. The first insulating layer, located above the lower electrode, acts as the capacitor's dielectric layer, isolating the upper and lower electrodes and storing charge; its material can be SiN. This step establishes the physical stacking relationship between the lower electrode and the insulating dielectric in the MIM device, laying the structural foundation for the subsequent formation of the upper electrode and the realization of the capacitor function.

[0033] Step S2, as follows Figure 3 and Figure 4As shown, the first insulating layer 13 is etched to reduce the thickness of the first insulating layer 13 in a certain area, resulting in a plurality of protrusions 131 distributed along the first direction. The protrusions 131 protrude toward the substrate 11 and toward the lower electrode 12. The first direction is perpendicular to the thickness direction of the lower electrode.

[0034] Specifically, the first insulating layer is treated by an etching process, which thins a portion of the first insulating layer, thereby forming multiple protrusions in the structure. These protrusions are characterized by their morphological characteristics: they bulge out from the substrate and point towards the lower electrode. The first insulating layer is not completely separated, which avoids etching the lower electrode and prevents metal residue from the lower electrode etching from adhering to the walls of the first insulating layer, thus preventing the upper and lower electrodes from connecting. After obtaining multiple protrusions, an upper electrode is formed on these protrusions, and the resulting multiple capacitor structures share a common lower electrode.

[0035] Step S3, as follows Figure 5 and Figure 6 As shown, a first protective layer 14 is filled between any two adjacent protrusions 131, and the first protective layer 14 covers the sidewall of the protrusion 131 in the first direction.

[0036] Specifically, by depositing a first protective layer material in the gaps between the protrusions, the sidewalls of the protrusions can be protected. This step uses the first protective layer material to cover and fill the gaps between adjacent protrusions, so that the first protective layer is located between two adjacent protrusions, thereby structurally isolating or protecting the area between the protrusions, and also isolating the subsequently formed upper electrode from the sidewalls of the protrusions.

[0037] Step S4, as follows Figures 7 to 11 As shown, an upper electrode 15 is formed on the side of the protrusions 131 and the first protective layer 14 away from the substrate 11, and the upper electrode 15 is etched to retain the upper electrode 15 on the surface of the protrusions 131 away from the substrate 11.

[0038] Specifically, an upper electrode is constructed on the side of the multiple protrusions facing away from the substrate. After removing the first protective layer, a second protective layer can be formed on this structure, serving as a protective layer for the entire capacitor structure. The initially formed upper electrode is etched to remove electrode material from non-target areas, while ensuring that the upper electrode portion located on the surface of the protrusion facing away from the substrate is retained. Residue from the etching process remains on the surface of the first protective layer. In subsequent processes, as the first protective layer is removed, this residue is also removed, preventing contact with the lower electrode and thus avoiding leakage.

[0039] In this embodiment, the first insulating layer is first etched to form a protrusion facing away from the substrate towards the lower electrode. A first protective layer is then filled between adjacent protrusions. This first protective layer isolates the direct contact path between the lower electrode and the upper electrode, effectively preventing the upper and lower plates from conducting due to the sidewall material covering them. This solves the technical problem in the prior art where the capacitor structure is prone to leakage failure due to the sidewall polymer covering the sidewall of the first insulating layer. This improves the insulation performance of the capacitor structure, prevents short circuits and leakage between the upper and lower plates, and thus enhances the reliability of the device.

[0040] In the above embodiments, the combination of multiple upper electrodes and protrusions in the capacitor structure shares a single lower electrode. Compared to a single upper electrode, the capacitor structure with one insulating part and one lower electrode can reduce series resistance and parasitic capacitance, and can also achieve arbitrary capacitance value transformation. Furthermore, the upper electrodes of the capacitor structure in this application are multiple small-sized upper electrodes, which avoids stress concentration problems compared to a single upper electrode in the prior art, thereby improving the reliability of the capacitor structure. The thickness of the protrusions in this application can be adjusted according to the actual capacitance value required; the larger the required capacitance value, the better.

[0041] In the specific implementation process, filling the first protective layer between any two adjacent protrusions in step S3 above can be achieved through the following steps:

[0042] like Figure 5 As shown, an oxide material is deposited on a first insulating layer 13 having multiple protrusions 131 to form a first protective layer 14 covering the first insulating layer 13; the oxide material can be silicon dioxide. Figure 6 As shown, the first protective layer 14 is planarized until the protrusions 131 are exposed, while retaining the first protective layer 14 between adjacent protrusions 131. In this step, the gaps formed after etching are filled with an oxide material, and planarization ensures that the substrate for the subsequent formation of the upper electrode is flat. This ensures that after the upper electrode 15 is formed, it only contacts the surface of the top of the protrusion 131, while being separated from the sidewall of the protrusion 131 below it by the first protective layer 14. This avoids the problem of reduced insulation performance or leakage between the upper and lower electrodes due to residual polymer adhering to the sidewall of the protrusion 131, thus improving the stability and reliability of the capacitor structure.

[0043] Step S4 of this application, forming the upper electrode on the side of the plurality of protrusions and the first protective layer away from the substrate, can be achieved through the following steps:

[0044] like Figure 7As shown, electrode material is deposited on the side of the multiple protrusions 131 and the first protective layer 14 away from the substrate 11 to form an upper electrode 15; the material of the upper electrode 15 can be TINN. This step can be achieved by using a thin film deposition process to cover the upper surface of the first protective layer 14 and the protrusions 131 with a continuous conductive material, thereby initially constructing the upper electrode 15 structure covering the entire area;

[0045] like Figures 8 to 10 As shown, a photolithographic pattern layer 16 is formed on the side of the upper electrode 15 facing away from the substrate 11, and the upper electrode 15 is wet-etched using the photolithographic pattern layer 16 as a mask to obtain upper electrodes 15 corresponding one-to-one with the protrusions 131. The photolithographic pattern layer 16 serves as a precise positioning mask for subsequent processing, and its pattern design must match the distribution position of the lower protrusions 131. Then, the upper electrode 15 is wet-etched using the photolithographic pattern layer 16 as a mask. By utilizing the isotropic or controlled anisotropic dissolution characteristics of the wet etching solution, excess material of the upper electrode in the area not protected by the photoresist is removed. This process ensures that the upper electrode material is retained only on the surface of the protrusion facing away from the substrate, ultimately forming an independent upper electrode 15 structure corresponding one-to-one with the lower protrusions 131. This wet etching method avoids the problem of polymer insulating layer residue on the sidewalls caused by plasma bombardment in traditional dry etching, ensuring that there is no accidental conduction path between the upper and lower electrodes due to sidewall residue. This effectively prevents leakage between the upper and lower plates of the MIM capacitor and improves the insulation performance and reliability of the device.

[0046] In this step, the amount of wet etching top electrode (WET OE) can be adjusted by calibrating whether the pattern of the overlay lithographic pattern layer is aligned with the protrusions of the previous layer. In semiconductor manufacturing, overlay refers to the alignment accuracy between the lithographic pattern layer and the existing pattern during multi-layer lithography on a wafer. Inaccurate alignment results in an overlay error. WET OE typically refers to the alignment error measured after wet processing (such as wet etching, wet etching, wet cleaning, etc.). Wet processing may slightly affect the surface morphology or thickness of the wafer due to chemical reactions, uneven material removal, etc., potentially leading to deviations in subsequent alignment measurements. Adjusting the WET OE can compensate for or correct this alignment error caused by wet processing through various methods. In the above steps, the photolithographic pattern layer is aligned with the protrusions. If the opening pattern of the photolithographic pattern layer is larger than the pattern between adjacent protrusions, the etching amount for the upper electrode can be adjusted to be less during wet etching. If the opening pattern of the photolithographic pattern layer is smaller than the pattern between adjacent protrusions, the etching amount for the upper electrode can be adjusted to be more during wet etching.

[0047] More specifically, a mathematical model can be built based on known alignment errors to predict the magnitude of alignment deviations introduced by wet processing. Before wet processing, the alignment parameters or process conditions of the lithography machine are pre-adjusted to compensate for potential errors from subsequent processing. During production, the alignment errors are measured, and the subsequent wet processing parameters are dynamically adjusted.

[0048] The steps described above for forming a photolithographic pattern layer on the side of the upper electrode away from the substrate include:

[0049] like Figure 8 As shown, a first anti-reflective layer 161 and a first photoresist layer 162 are sequentially formed on the side of the upper electrode 15 facing away from the substrate 11; as Figure 9 As shown, the first photoresist layer 162 is exposed and developed so that the retained first photoresist layer 162 corresponds to the position of the protrusion 131. This step can first cover an anti-reflective film to suppress the reflection of the underlying material during photolithography exposure using a physical or chemical vapor deposition process, and then spin-coat or deposit a photoresist material that is sensitive to light of a specific wavelength and can be dissolved by the developer. After that, the designed pattern is projected onto the first photoresist layer 162 using a mask. After exposure, the photoresist in the exposed (or unexposed, depending on the type of photoresist) area is dissolved by the developer, thereby retaining the pattern of the first photoresist layer 162 that precisely corresponds to the position of the protrusion 131 on the substrate.

[0050] like Figure 10 As shown, the first antireflective layer 161 is etched using the first photoresist layer 162 as a mask to expose the upper electrode 15. This step removes the first anti-reflective layer 161, which is not protected by the first photoresist layer 162, through processes such as dry etching, thereby exposing the surface of the upper electrode 15 in the corresponding area below, and finally forming a photolithographic pattern layer 16 composed of the first anti-reflective layer 161 and the first photoresist layer 162. By using this process combination, the first anti-reflective layer 161 eliminates the standing wave effect caused by interface reflection, and combined with the high-resolution pattern transfer capability of the first photoresist layer 162, the sidewall verticality and dimensional accuracy of the photolithographic pattern can be improved. This makes the subsequent wet etching process using the photolithographic pattern layer as a mask more selective and uniform, effectively avoiding the shape distortion of the upper electrode 15 and the increase in sidewall roughness caused by excessive or insufficient erosion of the sidewall by the etching solution. This ensures that the final upper electrode 15 corresponds one-to-one with the protrusion 131 and the contact area is controllable, thereby improving the structural consistency and electrical performance stability of the MIM capacitor.

[0051] In some alternative embodiments, after forming the upper electrode in step S4 above, the fabrication method further includes:

[0052] like Figure 11 and Figure 12 As shown, the first protective layer 14 is removed using either wet etching or dry etching. This step, which involves cleaning the upper electrode 15 after patterning, utilizes either wet or dry etching to remove the first protective layer 14. The first protective layer is a material layer used for isolation between multiple protrusions 131. Wet etching typically uses chemical solutions to dissolve and remove isotropic materials, offering good selectivity and minimal damage to the substrate. Dry etching, on the other hand, uses plasma bombardment to achieve precise vertical removal, offering advantages such as steep sidewalls and high control precision. Removing the first protective layer 14 remaining in the electrode gaps or non-functional areas using either of these processes exposes the complete capacitor structure interface, preventing interlayer short circuits or parasitic capacitance interference caused by the residue of the first protective layer 14. This ensures the stability of the insulation performance between the upper and lower electrodes of the MIM capacitor and the consistency of the overall electrical performance of the device.

[0053] In some alternative embodiments, after removing the first protective layer, the preparation method further includes:

[0054] like Figure 12 and Figure 13 As shown, the photolithographic pattern layer 16 is removed. This step can be achieved by a specific cleaning process or ashing step to remove the patterned photoresist that remains as a mask, so as to prevent its residue from contaminating the subsequent process environment or affecting the device performance.

[0055] like Figure 14 As shown, a protective material is deposited on the current structure to form a second protective layer 17 covering the upper electrode 15 and the first insulating layer 13. After removing the first protective layer, a dense dielectric film is uniformly grown on the surface of the upper electrode 15 and the first insulating layer 13 using methods such as chemical vapor deposition or physical vapor deposition. The second protective layer 17 is directly attached to the upper electrode 15 and the first insulating layer 13, forming a continuous protective coating. By employing the above steps, on the one hand, the mask material left by the etching process is promptly removed, avoiding interference from residues on the cleanliness of the capacitor plates; on the other hand, the second protective layer 17 isolates the exposed upper electrode and the first insulating layer 13 from the outside, effectively preventing increased leakage current or insulation failure due to mechanical scratches, chemical corrosion, or environmental moisture intrusion during subsequent packaging or testing, thereby improving the long-term stability and reliability of the capacitor structure.

[0056] In some embodiments, step S2 above involves etching the first insulating layer to thin the thickness of the first insulating layer in certain areas, resulting in multiple protrusions. This can be achieved through the following steps:

[0057] like Figure 3As shown, a second photoresist layer 18 is formed on the side of the first insulating layer 13 away from the substrate 11; the second photoresist layer 18 is exposed and developed to give the second photoresist layer 18 a pre-pattern, and a portion of the first insulating layer 13 is exposed; in this step, the second photoresist layer 18 is first coated and cured on the surface of the first insulating layer 13, and then a portion of the second photoresist layer 18 is removed by exposure and development processes, so that the first insulating layer 13 in the area to be etched is exposed, at which point the second photoresist layer 18 retains a pre-pattern with a specific geometric shape;

[0058] like Figure 3 and Figure 4 As shown, using the second photoresist layer 18 as a mask, a portion of the first insulating layer 13 is etched back to form multiple grooves, while the unetched portion of the first insulating layer 13 forms multiple protrusions 131. In this step, dry or wet etching techniques can be used to selectively remove the exposed first insulating layer 13, i.e., the etch-back process. The etched portion of the first insulating layer 13 forms grooves, while the remaining portion of the first insulating layer 13 forms protrusions 131 facing the lower electrode 12 away from the substrate 11. This process precisely defines the lateral boundary of the protrusions 131 through the photoresist pattern and controls the height of the protrusions 131 by using the etch-back depth. The first protective layer 14 subsequently filled in the grooves can effectively ensure that the protective layer can completely cover the sidewalls, avoiding conduction leakage problems caused by polymer residue or uneven structure on the sidewalls when the upper electrode 15 is formed.

[0059] The preparation method of the capacitor structure described above in this application will be specifically described below with reference to specific embodiments and comparative examples.

[0060] Example 1

[0061] A substrate is provided, on which a lower electrode and a first insulating layer are sequentially formed;

[0062] The first insulating layer is etched to reduce the thickness of the first insulating layer in a certain area, resulting in multiple protrusions that protrude towards the substrate and the lower electrode.

[0063] Specifically, the process involves: forming a second photoresist layer on the side of the first insulating layer away from the substrate; exposing and developing the second photoresist layer to create a pre-pattern on the second photoresist layer, and exposing a portion of the first insulating layer; in this step, the second photoresist layer is first coated and cured on the surface of the first insulating layer, and then a portion of the second photoresist layer is removed through exposure and development processes, exposing the first insulating layer in the area to be etched, at which point the second photoresist layer retains a pre-pattern with a specific geometric shape; then, using the second photoresist layer as a mask, a portion of the first insulating layer is etched back to form multiple grooves, and the un-etched first insulating layer forms multiple protrusions. In this step, the exposed first insulating layer can be selectively removed using dry or wet etching techniques, i.e., an etch-back process. The etched portion of the first insulating layer forms a groove, while the remaining portion forms a protrusion facing the lower electrode away from the substrate. This process precisely defines the lateral boundary of the protrusion using a photoresist pattern and controls the height of the protrusion using the etch-back depth. The first protective layer subsequently filled in the groove can effectively ensure that the protective layer can completely cover the sidewall, avoiding conduction leakage problems caused by polymer residue or uneven structure on the sidewall during the formation of the upper electrode.

[0064] A first protective layer is filled between any two adjacent protrusions. Specifically, an oxide material is deposited on a first insulating layer having multiple protrusions to form a first protective layer covering the first insulating layer. The oxide material can be silicon dioxide. The first protective layer is planarized until the protrusions are exposed, retaining the first protective layer between adjacent protrusions. In this step, the oxide material fills the gaps formed after etching, and planarization ensures a flat substrate for the subsequent formation of the upper electrode. This ensures that after formation, the upper electrode only contacts the surface of the top of the protrusion, while being separated from the sidewall of the protrusion below by the first protective layer. This avoids the problem of decreased insulation performance or leakage between the upper and lower electrodes due to residual polymer adhering to the sidewall of the protrusion, thus improving the stability and reliability of the capacitor structure.

[0065] An upper electrode is formed on the side of the multiple protrusions and the first protective layer facing away from the substrate, and the upper electrode is etched to retain the upper electrode on the surface of the protrusion facing away from the substrate. Specifically, electrode material is deposited on the side of the multiple protrusions and the first protective layer facing away from the substrate to form the upper electrode; the material of the upper electrode can be TIN. This step can be achieved by using a thin film deposition process to cover the upper surface of the first protective layer and the protrusions with a continuous conductive material, thereby initially constructing an upper electrode structure covering the entire area; a first anti-reflection layer and a first photoresist layer are sequentially formed on the side of the upper electrode facing away from the substrate; the first photoresist layer is exposed and developed so that the retained first photoresist layer corresponds to the position of the protrusion, forming a photolithographic pattern layer, and the upper electrode is wet-etched using the photolithographic pattern layer as a mask to obtain the upper electrode corresponding to each protrusion. The photolithographic pattern layer serves as a precise positioning mask for subsequent processing, and its pattern design must match the distribution of the lower layer protrusions. Then, using this photolithographic pattern layer as a mask, wet etching is performed on the upper electrode. Utilizing the isotropic or controlled anisotropic dissolution properties of the wet etching solution, excess material from the upper electrode in areas not protected by the photoresist is removed. This process ensures that the upper electrode material remains only on the surface of the protrusion facing away from the substrate, ultimately forming an independent upper electrode structure corresponding one-to-one with the lower layer protrusions. This wet etching method avoids the problem of polymer insulating layer residues on the sidewalls caused by plasma bombardment in traditional dry etching, ensuring that there are no accidental conductive paths between the upper and lower electrodes due to sidewall residues. This effectively prevents leakage between the upper and lower plates of the MIM capacitor, improving the device's insulation performance and reliability.

[0066] The first protective layer is removed using either wet or dry etching. The photolithographic pattern layer is then removed. This step, which may involve a specific cleaning or ashing process, removes any residual patterned photoresist used as a mask to prevent contamination of subsequent processes or impact on device performance. A protective material is then deposited on the current structure to form a second protective layer covering the top electrode and the first insulating layer.

[0067] According to another embodiment of this application, a capacitor structure is provided, which is prepared using the capacitor structure preparation method described above. Figure 14As shown, the capacitor structure includes: a lower electrode 12; a first insulating layer 13 located on the lower electrode 12, the first insulating layer 13 having a plurality of protrusions 131 distributed along a first direction, the first direction being perpendicular to the thickness direction of the lower electrode 12; and an upper electrode 15 located on the side of the protrusions 131 facing away from the lower electrode 12. During the fabrication process, this capacitor structure forms a first insulating layer with a plurality of protrusions distributed along the first direction on the lower electrode, and sets an upper electrode on the side of the protrusions facing away from the lower electrode. The first insulating layer creates a specific spacing and insulating medium distribution between the upper and lower electrodes, effectively reducing parasitic capacitance and leakage current paths, improving the signal linearity and stability of the MIM capacitor, and avoiding the conduction failure of the upper and lower plates caused by polymer residues during etching. Ultimately, a capacitor structure with high matching accuracy, low noise, and stable performance is obtained.

[0068] In some optional embodiments, the thickness of the first insulating layer between any two adjacent protrusions ranges from 208 Å to 222 Å. The lower electrode has a first end and a second end opposite each other in a first direction, and the thickness of the first insulating layer on the surfaces of the first end and the second end ranges from 108 Å to 112 Å. This limitation allows for the control of the dielectric thickness in the critical region of the capacitor structure. Specifically, the thickness of the first insulating layer between the two protrusions ranges from 208 Å to 222 Å. This ensures that, given the etching process characteristics, the thickness of the first insulating layer at the edge of the lower electrode (i.e., the surfaces of the first and second ends) is strictly controlled within a relatively thin range of 108 Å to 112 Å. This prevents etching of the lower electrode and avoids etching residue from adhering to the sidewalls of the first insulating layer and connecting with the upper electrode.

[0069] According to another embodiment of this application, a BCD device is proposed, including at least one of the above-described capacitor structures. This device integrates the aforementioned capacitor structure, and by employing an improved fabrication process to form a MIM capacitor, the problem of TIN polymer residue caused by plasma bombardment in traditional processes can be effectively avoided, thereby reducing the risk of leakage current between the upper and lower plates of the MIM capacitor. While ensuring high linearity, low noise, and high-precision matching characteristics of the capacitance value, the reliability and overall electrical performance stability of the integrated capacitor in the BCD device are improved.

[0070] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a capacitor structure, characterized in that, include: A substrate is provided on which a lower electrode and a first insulating layer are sequentially formed; The first insulating layer is etched to reduce the thickness of the first insulating layer in a certain area, resulting in a plurality of protrusions distributed along a first direction. The protrusions protrude toward the substrate and toward the lower electrode. The first direction is perpendicular to the thickness direction of the lower electrode. A first protective layer is filled between any two adjacent protrusions, the first protective layer covering the sidewall of the protrusion in the first direction; An upper electrode is formed on the side of the plurality of protrusions and the first protective layer away from the substrate, and the upper electrode is etched to retain the upper electrode on the surface of the protrusions away from the substrate.

2. The preparation method according to claim 1, characterized in that, The step of filling the first protective layer between any two adjacent protrusions includes: An oxide material is deposited on the first insulating layer having a plurality of said protrusions to form the first protective layer covering the first insulating layer; The first protective layer is planarized until the protrusions are exposed, while the first protective layer located between adjacent protrusions is retained.

3. The preparation method according to claim 1, characterized in that, The step of forming the upper electrode on the side of the plurality of protrusions and the first protective layer opposite to the substrate includes: Electrode material is deposited on the side of the plurality of protrusions and the first protective layer opposite to the substrate to form the upper electrode; A photolithographic pattern layer is formed on the side of the upper electrode away from the substrate, and the upper electrode is wet-etched using the photolithographic pattern layer as a mask to obtain the upper electrode that corresponds one-to-one with the protrusion.

4. The preparation method according to claim 3, characterized in that, The step of forming the photolithographic pattern layer on the side of the upper electrode opposite to the substrate includes: A first anti-reflection layer and a first photoresist layer are sequentially formed on the side of the upper electrode opposite to the substrate; The first photoresist layer is exposed and developed so that the retained first photoresist layer corresponds to the position of the protrusion. Using the first photoresist layer as a mask, the first anti-reflection layer is etched to expose the upper electrode.

5. The preparation method according to claim 3, characterized in that, After the step of forming the upper electrode, the preparation method further includes: The first protective layer is removed using either a wet etching process or a dry etching process.

6. The preparation method according to claim 5, characterized in that, After removing the first protective layer, the preparation method further includes: Remove the photolithographic pattern layer; A protective material is deposited on the current structure to form a second protective layer covering the upper electrode and the first insulating layer.

7. The preparation method according to claim 1, characterized in that, The step of etching the first insulating layer to reduce the thickness of the first insulating layer in a certain area to obtain the plurality of protrusions includes: A second photoresist layer is formed on the side of the first insulating layer away from the substrate; The second photoresist layer is exposed and developed to give the second photoresist layer a pre-pattern, and a portion of the first insulating layer is exposed. Using the second photoresist layer as a mask, a portion of the first insulating layer is etched back to form multiple grooves, and the unetched portion of the first insulating layer forms multiple protrusions.

8. A capacitor structure, characterized in that, The capacitor structure is prepared by the method for preparing the capacitor structure according to any one of claims 1 to 7, and the capacitor structure comprises: Lower electrode; A first insulating layer is located on the lower electrode, the first insulating layer having a plurality of protrusions distributed along a first direction, the first direction being perpendicular to the thickness direction of the lower electrode; The upper electrode is located on the side of the protrusion opposite to the lower electrode.

9. The capacitor structure according to claim 8, characterized in that, The thickness of the first insulating layer between any two adjacent protrusions ranges from 208 Å to 222 Å. The lower electrode has a first end and a second end opposite each other in the first direction. The thickness of the first insulating layer on the surfaces of the first end and the second end ranges from 108 Å to 112 Å.

10. A BCD device, characterized in that, It includes at least one capacitor structure as described in claim 8 or 9.

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