Fast soft recovery diode based on local lifetime control and preparation method thereof

Abstract

The application belongs to the technical field of power chips, and provides a fast soft recovery diode based on local lifetime control and a preparation method, wherein the diode comprises a back metal layer, an N+ substrate, an N buffer zone, an N-drift zone, an oxide layer and a front metal layer, a P+ buried layer is formed at the bottom edge of the N buffer zone, n-type buried layers are arranged at intervals in the N-drift zone, P+ anode zones are formed on the n-type buried layers, and Schottky barrier zones are formed between adjacent P+ anode zones. Based on the above four-layer composite process structure of the N+ substrate, the N buffer zone, the N-drift zone and the P+ anode zone, the anode P+ zone and the Schottky barrier zone are alternately distributed; when forward conduction, the number of holes injected into the drift zone is greatly reduced; when reverse bias, the depletion zones of adjacent P+N-junctions expand laterally in the Schottky region to form a shielding barrier, reducing the leakage current generated in the Schottky region; the P+ buried layer and the N+ substrate form an avalanche diode, improving the softness of the reverse recovery of the diode.

Description

Technical Field

[0001] This invention relates to the field of power chip technology, specifically to a fast soft recovery diode based on local lifetime control and its fabrication method. Background Technology

[0002] Fast recovery diodes, as key components for freewheeling, clamping, and rectification, are commonly used in high-frequency inverters, automotive power supplies, and high-power fast charging equipment. Their reverse recovery characteristics determine the high-frequency loss level and operational stability of the entire circuit. Hard recovery diodes are prone to generating spike currents and high-frequency oscillations. In the communications field, high-frequency oscillations can generate broadband electromagnetic noise that severely impacts communication quality. Soft recovery diodes, on the other hand, exhibit smooth current decay, short tailing time, and low peak current, significantly reducing reverse recovery losses, improving circuit stability, and allowing for compatibility with higher switching frequencies.

[0003] Currently, conventional PIN structure reverse recovery peak current (IRM1) is relatively large, and fast recovery diodes are often used in parallel with IGBTs. Current spikes can easily damage other components in the circuit. The reverse recovery current rise slope of conventional PIN structure diodes is also relatively steep, which can easily generate self-excited oscillations. The resulting harmonic components will seriously reduce the operating efficiency of the circuit. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a fast soft recovery diode based on local lifetime control and its fabrication method, thereby solving the problem that the reverse recovery peak current of conventional PIN structures is too large and can easily damage other components in the circuit.

[0005] In a first aspect, the present invention provides a fast soft recovery diode based on local lifetime control, comprising: N+ substrate; An N-buffer zone is disposed on an N+ substrate; The P+ buried layer is formed within the N buffer and is located at the bottom edge of the N buffer. The N-drift region is set on the N-buffer. An oxide layer is disposed on the N-drift region, and a window is formed on the oxide layer; n-type buried layers are spaced out on the N-drift region; P+ anode region, set on n-type buried layer; The Schottky barrier region is located between adjacent P+ anode regions; The front metal layer is disposed on the Schottky barrier region, the P+ anode region and the oxide layer; A back metal layer is disposed on the back side of the N+ substrate.

[0006] Optionally, the thickness of the N+ substrate is 5~15 μm, and the doping concentration is 1E18~1E19 cm⁻¹.-3 .

[0007] Optionally, the thickness of the N-buffer is 15~30 μm, and the doping concentration is 1E15~1E16 cm⁻¹. -3 .

[0008] Optionally, the thickness of the P+ buried layer is 5~15 μm, and the doping concentration is 1E18~1E19 cm⁻¹. -3 .

[0009] Optionally, the thickness of the N-drift region is 40~65 μm, and the doping concentration is 1E14~1E15 cm⁻¹. -3 .

[0010] Optionally, the injected impurity in the n-type buried layer is phosphorus, the injection dose is 1E13~1E14, the injection energy is 50~100 keV, and the injection angle is 7°.

[0011] Optionally, the junction depth of the P+ anode region is 1~10μm, the implanted impurity is boron, the implantation dose is 1E13~1E16, the implantation energy is 50~100keV, and the implantation angle is 7°.

[0012] Optionally, the barrier metal of the Schottky barrier region is Pt.

[0013] Optionally, the front metal layer is Al or AlSiCu; the back metal layer includes Ti, Ni and Ag formed sequentially.

[0014] Secondly, the present invention provides a method for fabricating a fast soft recovery diode based on local lifetime control, comprising: S1. Obtain an N+ substrate; S2. The first portion of an N-buffer layer is grown on an N+ substrate; S3. A P+ buried layer is formed on the first part of the N buffer layer by an ion implantation annealing process; S4. Continue growing the second part of the N-buffer layer; S5. Grow N-drift regions on the N-buffer layer; S6. An oxide layer is formed on the N-drift region, followed by photolithography etching to form an injection window; S7. Perform N-type implantation annealing within the implantation window to form an n-type buried layer, and then perform P-type implantation annealing to form a P+ anode region; S8. Pt is sputtered in the P+ anode region, and Pt atoms are captured by the defects induced by proton irradiation. After high-temperature annealing, interstitial Pt is transformed into substituted Pt, and finally an effective recombination center is formed. S9. Open the Schottky barrier region, re-sputter Pt and alloy; S10. A front metal layer is formed on the N- drift region, and a back metal layer is formed on the bottom of the N+ substrate.

[0015] By adopting the above technical solution, this application has the following beneficial effects: This invention is based on a four-layer composite structure consisting of an N+ substrate, an N buffer zone, an N- drift region, and a P+ anode region. On this basis, the anode P+ region (with an n-type buried layer underneath) and the Schottky barrier region are alternately distributed. During forward conduction, the number of holes injected into the drift region is significantly reduced. During reverse bias, the depletion regions of adjacent P+N- junctions expand laterally, forming a shielding barrier in the Schottky region, reducing leakage current generated in the Schottky region. The P+ buried layer in the N buffer zone and the cathode N+ substrate form an avalanche diode. During reverse recovery, the P+N+ junction avalanches, injecting a certain amount of holes into the base region, improving the softness of the diode's reverse recovery. The diode provided by this invention employs Pt-doped local lifetime control, with recombination centers controlled at the interface between the N-drift region and the N-buffer zone, further reducing reverse recovery time and reverse recovery peak current, thus giving it lower switching losses and enabling it to be used in applications with higher switching frequencies. This invention controls the recombination center at the interface between the N-drift region and the N-buffer zone by localized platinum doping lifetime control, thus avoiding damped oscillations. It also reduces the reverse recovery time and the peak reverse recovery current, thereby reducing switching losses and improving circuit reliability in practical applications. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0017] Figure 1 A schematic diagram of a fast soft recovery diode based on lifetime control provided in an embodiment of the present invention is shown; Figure 2 A top view of the Schottky barrier region and P+ buried layer provided in an embodiment of the present invention is shown; Figure 3 A flowchart illustrating the fabrication method of a fast soft recovery diode based on lifetime control provided in an embodiment of the present invention is shown; Figure 4 A schematic diagram of the product obtained in step S8 of the preparation method provided in the embodiment of the present invention is shown; Figure 5 A schematic diagram of the product obtained by step S9 of the preparation method provided in the embodiment of the present invention is shown; Figure 6A schematic diagram of the doping concentration distribution inside the dual-base region structure used in this invention is shown; Figure 7 This diagram illustrates the minority carrier concentration distribution within the drift region below the diode anode-side P-well and Schottky barrier, as provided in an embodiment of the present invention. Figure 8 A comparison diagram of the reverse recovery curves of the diode provided in the embodiment of the present invention and the conventional PIN structure is shown.

[0018] Figure label: 1-N+ substrate; 2-N buffer zone; 3-P+ buried layer; 4-N-drift region; 5-oxide layer; 6-n-type buried layer; 7-P+ anode region; 8-Schottky barrier region; 9-front metal layer; 10-back metal layer. Detailed Implementation

[0019] The embodiments of the technical solution of the present invention will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore merely examples, and should not be construed as limiting the scope of protection of the present invention.

[0020] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application should have the ordinary meaning as understood by those skilled in the art to which this invention pertains.

[0021] In one embodiment, such as Figure 1 As shown, a fast soft recovery diode based on local lifetime control is provided, comprising: N+ substrate 1, thickness 5~15μm, doping concentration 1E18~1E19cm⁻¹ -3 ; N-buffer 2 is disposed on N+ substrate 1, with a thickness of 15~30μm and a doping concentration of 1E15~1E16cm. -3 ; A P+ buried layer 3 is formed within the N-buffer 2 and located at the bottom edge of the N-buffer 1; the thickness of the P+ buried layer 2 is 5~15μm, and the doping concentration is 1E18~1E19cm. -3 .

[0022] N-drift region 4 is disposed on N-buffer 2; the thickness of N-drift region 4 is 40~65μm, and the doping concentration is 1E14~1E15cm. -3 ; The oxide layer 5 is disposed on the N-drift region 4 and is located at the edge of the N-drift region 4.

[0023] The n-type buried layer 6 is spaced out within the N-drift region 4; the injected impurity of the n-type buried layer 6 is phosphorus, the injection dose is 1E13~1E14, the injection energy is 50~100KeV, and the injection angle is 7°.

[0024] The P+ anode region 7 is spaced within the N- drift region 4 and located on the n-type buried layer 6; the junction depth of the P+ anode region 7 is 1~10μm, the injected impurity is boron, the injection dose is 1E13~1E16, the injection energy is 50~100keV, and the injection angle is 7°.

[0025] Schottky barrier region 8 is located between adjacent P+ anode regions 7; the barrier metal of Schottky barrier region 8 is Pt. Top view as shown... Figure 2 It can be seen that by adjusting the area ratio of the P+ anode region 7 and the Schottky barrier region 8, the anode injection efficiency can be reduced, and the number of minority carriers in the cathode region can be increased, thereby reducing the reverse recovery peak current and improving the reverse recovery softness.

[0026] The front metal layer 9 is disposed on the Schottky barrier region 8, the P+ anode region 7 and the oxide layer 5; the front metal layer 9 is Al or AlSiCu.

[0027] A back metal layer 10 is disposed on the back side of the N+ substrate 1; the back metal layer 10 includes Ti, Ni and Ag formed sequentially from top to bottom.

[0028] Based on the above four-layer composite structure of N+ substrate, N buffer layer, N- drift region, and P+ anode region, the anode P+ region 7 (with the lower n-type buried layer 3) and the Schottky barrier region 8 are alternately distributed. During forward conduction, the number of holes injected into the drift region is greatly reduced. During reverse bias, the depletion region of the adjacent P+N- junction expands laterally to form a shielding barrier in the Schottky region, reducing the leakage current generated in the Schottky region. The buffer layer P+ buried layer and the cathode N+ substrate form an avalanche diode. During reverse recovery, the P+N+ junction avalanche injects a certain amount of holes into the base region, improving the softness of the diode's reverse recovery. The diode provided in this embodiment employs Pt doping local lifetime control, with recombination center controlled at the interface between N-drift region 4 and N-buffer zone 2, further reducing reverse recovery time and reverse recovery peak current, resulting in lower switching losses and enabling its application in higher switching frequency applications.

[0029] In one embodiment, such as Figure 3 As shown, a method for fabricating a fast soft recovery diode based on local lifetime control is provided, including: S1. Obtain an N+ substrate; S2. Grow the first portion of the N buffer layer on the N+ substrate; the thickness of the first portion of the N buffer layer is adapted to the thickness of the p+ buried layer, and the thickness is 5~15μm; S3. A P+ buried layer is formed on the first part of the N buffer layer by an ion implantation annealing process; the P+ buried layer is located at the edge of the N buffer layer and has a doping concentration of 1E18~1E19 cm⁻¹. -3 .

[0030] S4. Continue growing the second part of the N-buffer layer, with a thickness of 15~30 μm and a doping concentration of 1E15~1E16 cm⁻¹. -3 .

[0031] S5. Grow an N-drift region on the N-buffer layer; the N-drift region thickness is 40~65μm, and the doping concentration is 1E14~1E15cm. -3 .

[0032] S6. An oxide layer is formed on the N-drift region, and then multiple injection windows are formed at intervals by photolithography etching process; S7. Perform N-type implantation annealing within the implantation window to form an n-type buried layer, and then perform P-type implantation annealing (gradual junction) to form a P+ anode region; S8. Pt is sputtered in the P+ anode region, and Pt atoms are captured by the induced defects through proton irradiation. After high-temperature annealing, interstitial Pt is transformed into substituted Pt, ultimately forming effective recombination centers, resulting in... Figure 4 The product shown. Proton irradiation energy 100keV~1MeV, irradiation dose 1×10⁻⁶. 11 ~1×10 15 cm -2 The annealing temperature of Pt after proton irradiation is 700~800℃.

[0033] By employing Pt doping local lifetime control, the recombination center is controlled at the interface between the N-drift region and the N-buffer zone, which improves the recombination efficiency of holes and electrons, reduces the reverse recovery time, and improves the reverse recovery characteristics.

[0034] S9. The Schottky barrier region is opened, and Pt is re-sputtered and alloyed. The Pt alloying temperature in the Schottky barrier region is 300~500℃, resulting in the following... Figure 5 The product shown.

[0035] S10. A front metal layer is formed on the N- drift region, and a back metal layer is formed on the bottom of the N+ substrate.

[0036] Figure 6This diagram illustrates the doping concentration distribution within the dual-base region structure used in this invention. During the reverse recovery phase, the remaining charge carriers within the buffer layer become the source of the tail current, effectively improving the softness of the diode's reverse recovery. During reverse recovery, as the depletion region expands into the N-buffer zone, the depletion rate slows down due to the higher doping concentration in the N-buffer zone compared to the N-drift region, resulting in a lower reverse recovery ramp and improved softness.

[0037] Figure 7 This diagram illustrates the minority carrier concentration distribution within the drift region below the Schottky barrier and the anode-side P-well of the fast soft recovery diode provided in this embodiment of the invention. It can be seen that the minority carrier concentration below the Schottky barrier region is almost zero, with only electrons participating in conduction. Therefore, during forward conduction, all the stored charge in the drift region comes from the P+ anode region, reducing the anode injection efficiency. This is reflected in the reverse recovery characteristics by a reduced peak reverse recovery current. During reverse bias, the depletion region of the adjacent P+ N- junction extends laterally, forming a shielding barrier in the Schottky region, reducing the leakage current generated in the Schottky region.

[0038] Figure 8 A comparison of the recovery curves of a conventional PIN structure fast recovery diode and the diode provided in this embodiment of the invention is shown. It can be seen that the conventional PIN structure has a larger reverse recovery peak current (IRM1), and the current spike can easily damage other components in the circuit (fast recovery diodes are often used in parallel with IGBTs); the reverse recovery current rise slope of the conventional PIN structure diode is also relatively steep, which can easily generate self-oscillation, and the generated harmonic components will seriously reduce the operating efficiency of the circuit.

[0039] like Figure 8 As shown, ta is the minority carrier storage time, tb is the recombination time, and the reverse recovery time trr = ta + tb. The reverse recovery softness (S) of a diode is typically characterized by the ratio of tb to ta, i.e., S = tb / ta. A lower S indicates greater reverse recovery softness. The fast soft recovery diode provided in this embodiment reduces the reverse recovery peak current and improves the reverse recovery softness by decreasing the anode injection efficiency and increasing the number of minority carriers in the cathode region. Furthermore, localized Pt doping further reduces the diode's reverse recovery time, resulting in lower switching losses and enabling the fast recovery diode to operate at higher switching frequencies.

[0040] The above embodiments are only used to provide a detailed description of the technical solutions of this application. However, the descriptions of the above embodiments are only for the purpose of helping to understand the methods of the embodiments of the present invention and should not be construed as limiting the embodiments of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art should be covered within the protection scope of the embodiments of the present invention.

Claims

1. A fast soft recovery diode based on local lifetime control, characterized in that, include: N+ substrate; An N-buffer zone is disposed on an N+ substrate; The P+ buried layer is formed within the N buffer and is located at the bottom edge of the N buffer. The N-drift region is set on the N-buffer. An oxide layer is disposed on the N-drift region and located at the edge of the N-drift region; n-type buried layers are spaced out within the N-drift zone; The P+ anode region is spaced out within the N- drift region and located on the n-type buried layer; The Schottky barrier region is located between adjacent P+ anode regions; The front metal layer is disposed on the Schottky barrier region, the P+ anode region and the oxide layer; A back metal layer is disposed on the back side of the N+ substrate.

2. The diode according to claim 1, characterized in that, The N+ substrate has a thickness of 5~15μm and a doping concentration of 1E18~1E19cm. -3 .

3. The diode according to claim 1, characterized in that, The thickness of the N-buffer is 15~30μm, and the doping concentration is 1E15~1E16cm. -3 .

4. The diode according to claim 1, characterized in that, The thickness of the P+ buried layer is 5~15μm, and the doping concentration is 1E18~1E19cm. -3 .

5. The diode according to claim 3, characterized in that, The thickness of the N-drift region is 40~65 μm, and the doping concentration is 1E14~1E15 cm⁻¹. -3 .

6. The diode according to claim 1, characterized in that, The injected impurity in the n-type buried layer is phosphorus, the injection dose is 1E13~1E14, the injection energy is 50~100keV, and the injection angle is 7°.

7. The diode according to claim 1 or 6, characterized in that, The junction depth of the P+ anode region is 1~10μm, the implanted impurity is boron, the implantation dose is 1E13~1E16, the implantation energy is 50~100keV, and the implantation angle is 7°.

8. The diode according to claim 1, characterized in that, The barrier metal of the Schottky barrier region is Pt.

9. The diode according to claim 1, characterized in that, The front metal layer is Al or AlSiCu; the back metal layer consists of Ti, Ni and Ag formed sequentially.

10. A method for fabricating a fast soft recovery diode based on local lifetime control, characterized in that, include: S1. Obtain an N+ substrate; S2. The first portion of an N-buffer layer is grown on an N+ substrate; S3. A P+ buried layer is formed on the first part of the N buffer layer by an ion implantation annealing process; S4. Continue growing the second part of the N-buffer layer; S5. Grow N-drift regions on the N-buffer layer; S6. An oxide layer is formed on the N-drift region, followed by photolithography etching to form an injection window; S7. Perform N-type implantation annealing within the implantation window to form an n-type buried layer, and then perform P-type implantation annealing to form a P+ anode region; S8. Pt is sputtered in the P+ anode region, and Pt atoms are captured by the defects induced by proton irradiation. After high-temperature annealing, interstitial Pt is transformed into substituted Pt, and finally an effective recombination center is formed. S9. Open the Schottky barrier region, re-sputter Pt and alloy; S10. A front metal layer is formed on the N- drift region, and a back metal layer is formed on the bottom of the N+ substrate.

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