A bidirectional ESD chip with a through structure and a manufacturing process thereof

Abstract

The application discloses a kind of through structure bidirectional ESD chip and its manufacturing process, including first conductive type monocrystalline silicon wafer, first conductive type monocrystalline silicon wafer edge is provided with second conductive type through ring second conductive type through ring from the front of first conductive type monocrystalline silicon wafer penetrates to back surface;The middle region of the front of first conductive type monocrystalline silicon wafer and back surface are provided with second conductive type diffusion layer, and second conductive type diffusion layer is connected with second conductive type through ring and is integrated, forms second conductive type area;The front of first conductive type monocrystalline silicon wafer is provided with first metal layer, and back surface is provided with second metal layer, and first metal layer and second metal layer respectively with corresponding second conductive type area form ohmic contact.The application uses asymmetric structure, and doping area of back surface and side surface are connected in series, finally extend to the front, and the breakdown position of PN junction also changes to the front from back surface, improves the packaging yield and reliability of product.

Description

Technical Field

[0001] This invention relates to the field of protection device technology, and in particular to a through-hole bidirectional ESD chip and its fabrication process. Background Technology

[0002] ESD diodes are semiconductor devices specifically designed for electrostatic discharge protection. At their core, they utilize the Zener / avalanche breakdown mechanism of a PN junction to respond to high-voltage electrostatic pulses in nanoseconds, rapidly dissipating surge energy to ground and protecting sensitive downstream circuitry from damage. They maintain a high impedance state under normal operating voltage, having virtually no impact on circuit signals; they automatically shut off after an electrostatic event, are reusable, and are the mainstream electrostatic protection solution in modern electronic systems.

[0003] Bidirectional ESD diodes, as an important type of ESD diode, are mainly used for bidirectional electrostatic protection in circuits and have a wide range of applications. Traditional bidirectional ESD diode chips use silicon single-crystal wafers with a completely symmetrical vertical structure, and are generally manufactured using planar or mesa-type processes (see...). Figure 7 Traditionally, bidirectional ESD chips are packaged using form factors such as SOD-123FL, SMA, SMB, and SMC. Especially for high-power ESD products, these package forms are costly. With the trend towards product miniaturization, some domestic manufacturers have attempted to reduce costs by changing the package form factor, adopting thinner forms like DFN, and using different bonding processes. However, traditional bidirectional ESD chips using DFN packaging encounter the problem of solder overflow onto the chip edges and sides during the packaging process, leading to short circuits between the back and side PN junctions (see...). Figure 8 This affects the product packaging yield and subsequent product reliability. The packaging process requires extremely strict control, but it is impossible to completely eliminate the occurrence of problems. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a through-hole bidirectional ESD chip and its fabrication process. It adopts an asymmetric structure, with the doped regions on the back and sides connected in series and eventually extending to the front. The breakdown location of the PN junction also changes from the back to the front. This design solves a series of problems caused by back solder overflow during the packaging process of traditional bidirectional ESD chips, and improves the packaging yield and reliability of the product.

[0005] The objective of this invention is achieved in part by providing a fabrication process for a through-hole bidirectional ESD chip, comprising the following steps:

[0006] Step S1) Grow silicon dioxide layers on the front and back sides of a first conductivity type single crystal silicon wafer;

[0007] Step S2) Photolithographically etch a second conductivity type through-diffusion window at the edge of the silicon dioxide layer on the front and back sides of the first conductivity type single crystal silicon wafer;

[0008] Step S3) A second type of conductivity impurity is doped on the front and back sides of a single-crystal silicon wafer by ion implantation or liquid source diffusion to form a second type of conductivity doped layer;

[0009] Step S4) The second conductivity type doped layer is redistributed through diffusion at a certain temperature to achieve front and back penetration, forming a second conductivity type through-ring, while a silicon dioxide layer is grown on the surface as a masking layer.

[0010] Step S5) Photolithographically print diffusion windows of the second conductivity type on the silicon dioxide masking layers on the front and back sides of the first conductivity type single crystal silicon wafer;

[0011] Step S6) Diffusion or implantation of impurities of the second conductivity type is performed on the diffusion window of the second conductivity type to form a diffusion layer of the second conductivity type;

[0012] Step S7) The second conductivity type diffusion layer is redistributed through a certain temperature to make the breakdown voltage of the double-sided PN junction reach the target value and be connected to the second conductivity type punch-through ring to form the final second conductivity type region. At the same time, a silicon dioxide layer is grown on the surface as a masking layer.

[0013] Step S8) Photolithographically etch lead hole windows on the silicon dioxide masking layers on the front and back sides of the first conductivity type single crystal silicon wafer;

[0014] Step S9) A first metal layer is evaporated on the front lead hole window, and a second metal layer is evaporated on the back lead hole window;

[0015] Step S10) Photolithographically pattern a metal lead area on the first metal layer on the front side of the first conductivity type single crystal silicon wafer, retain the second metal layer on the back side to form a back metal area, and vacuum alloy the double-sided metals to form an ohmic contact to obtain a through-structure bidirectional ESD chip.

[0016] Furthermore, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

[0017] Furthermore, when the first conductivity type is P-type, the resistivity of the monocrystalline silicon wafer is 0.005~0.60 Ω·cm; when the first conductivity type is N-type, the resistivity of the monocrystalline silicon wafer is 0.003~0.90 Ω·cm.

[0018] Furthermore, when the second conductivity type is N-type, the energy of phosphorus ion implantation in step S3) is 80~150 keV, and the dose is 1×10⁻⁶. 15 / cm2 ~4×10 15 / cm 2 Or, the concentration of the liquid phosphorus source at the diffusion surface is 0.4~1.0 Ω / □;

[0019] When the second conductivity type is P-type, the energy of aluminum ion implantation in step S3) is 100~150 keV, and the dose is 2×10⁻⁶. 15 / cm 2 ~4×10 15 / cm 2 Alternatively, the concentration of the liquid aluminum source at the diffusion surface may be 50~200 Ω / □.

[0020] Furthermore, the diffusion temperature in step S4) is 1260℃~1280℃, the time is 30~50h, and the final penetration width is 100μm~200μm.

[0021] Furthermore, when the second conductivity type is N-type, the phosphorus implantation energy in step S6) is 60~120 keV, and the dose is 2×10⁻⁶. 15 / cm 2 ~3.5×10 15 / cm 2 Alternatively, the phosphorus pre-diffusion temperature is 1050℃~1150℃, the time is 1.5~3 h, and the final sheet resistance is 0.5~3.0 Ω / □.

[0022] When the second conductivity type is P-type, the energy of boron ion implantation in step S6) is 60~120 keV, and the dose is 2×10⁻⁶. 15 / cm 2 ~3×10 15 / cm 2 Alternatively, the boron pre-diffusion temperature can be 1050℃~1150℃ for 2~5 h, resulting in a final sheet resistance of 2.0~5.0 Ω / □.

[0023] Furthermore, the re-diffusion temperature in step S7) is 1050℃~1250℃, the time is 2~50 h, and the final diffusion layer depth is 5~30 μm.

[0024] Furthermore, in step S9), the first metal layer is an aluminum layer with a thickness of 4~7µm, and the second metal layer on the back is a titanium-nickel-silver layer with a thickness of 1.5~3µm.

[0025] Another aspect of the objective of this invention is achieved as follows: a through-hole bidirectional ESD chip includes a first type of conductivity monocrystalline silicon wafer, and a second type of conductivity through-hole ring is disposed on the edge of the first type of conductivity monocrystalline silicon wafer; the second type of conductivity through-hole ring extends from the front side to the back side of the first type of conductivity monocrystalline silicon wafer.

[0026] The first type of conductive single-crystal silicon wafer has a second type of conductive diffusion layer in the middle area of ​​the front side and the back side. The second type of conductive diffusion layer is connected to the second type of conductive through-ring to form a second type of conductive region.

[0027] The first conductivity type single crystal silicon wafer has a first metal layer on its front side and a second metal layer on its back side, and the first metal layer and the second metal layer respectively form ohmic contacts with the corresponding second conductivity type region.

[0028] Furthermore, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows: The chip structure of the present invention adopts an asymmetric structure, with the doped regions on the back and sides connected in series and eventually extending to the front. The breakdown position of the PN junction also changes from the back to the front. This design solves a series of problems caused by back solder overflow in the traditional bidirectional ESD chip packaging process, further improving the packaging yield and reliability of the product and reducing the risk in the packaging process. At the same time, due to the increased doped region on the back, the surge protection capability (IPP) in the back direction is also greatly improved. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0031] Figure 1 This is a cross-sectional view of chip A in Embodiment 1 of the present invention.

[0032] Figure 2 This is a cross-sectional view of chip B in Embodiment 2 of the present invention.

[0033] Figure 3 This is a top view of chip A and chip B of the present invention.

[0034] Figure 4 This is a flowchart illustrating the manufacturing process of chip A in Embodiment 1 of the present invention.

[0035] Figure 5 This is a flowchart illustrating the manufacturing process of chip B in Embodiment 2 of the present invention.

[0036] Figure 6 This is a cross-sectional view of a through-hole bidirectional ESD chip package according to the present invention.

[0037] Figure 7 This is a cross-sectional view of a traditional bidirectional ESD chip.

[0038] Figure 8 This is a cross-sectional view of the package of a traditional bidirectional ESD chip.

[0039] Figure 1 and Figure 4 The reference numerals in the figures are: 1 P-type monocrystalline silicon wafer, 2 silicon dioxide layer, 3 phosphorus ion implantation or diffusion window, 4 concentrated phosphorus layer, 5 concentrated phosphorus through-ring, 6 front phosphorus layer, 7 back phosphorus layer, 8 front lead window, 9 aluminum layer, 10 titanium-nickel-silver layer.

[0040] Figure 2 and Figure 5 The reference numerals in the figures are: 1 N-type single crystal silicon wafer, 2 silicon dioxide layer, 3 aluminum ion implantation or diffusion window, 4 aluminum layer, 5 aluminum through-ring, 6 front boron layer, 7 back boron layer, 8 front lead window, 9 aluminum layer, 10 titanium-nickel-silver layer. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] Example 1: Chip A (N+PN+ punch-through structure bidirectional ESD chip)

[0043] like Figure 1 and 3 The bidirectional ESD chip with a through-hole structure shown includes a P-type monocrystalline silicon wafer 1, with a concentrated phosphorus through-hole ring 5 disposed at the edge of the P-type monocrystalline silicon wafer 1; the concentrated phosphorus through-hole ring 5 extends from the front side to the back side of the P-type monocrystalline silicon wafer 1; a front phosphorus layer 6 is disposed in the middle region of the front side of the P-type monocrystalline silicon wafer 1, and a back phosphorus layer 7 is disposed on the back side of the P-type monocrystalline silicon wafer 1; the front phosphorus layer 6 and the back phosphorus layer 7 are connected to the concentrated phosphorus through-hole ring 5 to form the final N+ region; a front lead window 8 and a back lead window are photolithographically etched on the front and back sides of the P-type monocrystalline silicon wafer 1; an aluminum layer 9 is evaporated on the front lead window 8, and a titanium-nickel-silver layer 10 is evaporated on the back lead window; the aluminum layer 9 and the titanium-nickel-silver layer 10 respectively form ohmic contacts with the corresponding N+ regions.

[0044] like Figure 4 The diagram illustrates a through-hole bidirectional ESD chip and its fabrication process. The fabrication process of chip A includes the following steps:

[0045] Step 1) On a P-type single-crystal silicon wafer with a resistivity of 0.005~0.60 Ω·cm, such as Figure 4 (a) A silicon dioxide layer is grown on the front and back sides by thermal oxidation. See Figure 4 (b);

[0046] Step 2) Photolithographically create N+ through-diffusion windows on the front and back sides of the P-type single-crystal silicon wafer, such as... Figure 4 As shown in (c);

[0047] Step 3) A layer of N+ is doped onto the front and back sides of a P-type single-crystal silicon wafer using ion implantation or diffusion from a liquid phosphorus source. The phosphorus energy E = 80~150 keV, and the dose DOSE = 1 × 10⁻⁶. 15 / cm 2 ~4×10 15 / cm 2 Or the surface concentration R of the liquid phosphorus source diffusion s =0.4~1.0Ω / □, such as Figure 4 As shown in (d);

[0048] Step 4) Through high-temperature, long-duration diffusion, the N+ layer is redistributed, achieving penetration of N+ on both sides to form a through-ring N+. Simultaneously, a silicon dioxide layer is grown on the surface as a masking layer for subsequent diffusion. The redistribution temperature is 1260℃~1280℃, and the time is 100~150h. The final through-ring width is 100~200µm. Figure 4 As shown in (e);

[0049] Step 5) Photolithographically pattern N+ diffusion windows on the silicon dioxide layers on the front and back sides of the P-type single-crystal silicon wafer, such as... Figure 4 As shown in (f);

[0050] Step 6) Perform phosphorus diffusion or phosphorus implantation on the N+ diffusion windows on the front and back sides of the P-type monocrystalline silicon wafer. The phosphorus pre-diffusion temperature is 1050℃~1150℃, and the time is 1.5~3h. The final R... s =0.5~3.0Ω / □, or phosphorus injection energy E=60~120keV, dose DOSE=2×10 15 / cm 2 ~3.5×10 15 / cm 2 ,like Figure 4 As shown in (g);

[0051] Step 7) Re-diffusion at high temperature (1050℃~1250℃) for 2~50h redistributes the N+ layer, resulting in a final diffusion layer depth of 5~30µm. This achieves the target breakdown voltage for the double-sided PN junction and establishes a connection with the N+ through-ring, forming a final N+ region. Simultaneously, a silicon dioxide layer is grown on the surface as a masking layer for subsequent photolithography. Figure 4 As shown in (h);

[0052] Step 8) Photolithographically pattern lead hole windows on the front and back sides of the P-type single-crystal silicon wafer, such as... Figure 4 As shown in (i);

[0053] Step 9) Evaporate a layer of aluminum metal to the front lead hole window of the P-type single crystal silicon wafer, with a thickness of 4~7µm. Evaporate a layer of titanium-nickel-silver metal to the back lead hole window, with a thickness of 1.5~3µm. Figure 4 As shown in (j);

[0054] Step 10) A metal lead area is photolithographically patterned on the front side of a P-type single-crystal silicon wafer, while the titanium-nickel-silver metal on the back side is retained to form a back metal area. Vacuum alloying is then performed on both sides of the metal to form an ohmic contact, thereby realizing the fabrication of an N+PN+ through-hole bidirectional ESD chip. Figure 4 As shown in (k).

[0055] The resistivity of the P-type monocrystalline silicon wafer in step 1) is preferably 0.022~0.024 Ω·cm; the phosphorus source diffusion surface concentration in step 3) is preferably R. s =0.6~0.7Ω / □; In step 4), the preferred diffusion temperature is 1275℃, the time is 130h, and the final penetration width is 140~160µm; In step 6), the preferred phosphorus pre-diffusion temperature is 1040℃, and the time is 2h; In step 7), the preferred re-diffusion temperature is 1220℃, the time is 15h, and the final diffusion layer depth is 17µm; In step 9), the preferred thickness of the front aluminum layer is 5.5µm, and the preferred thickness of the back titanium-nickel-silver layer is 1.8µm; The final bidirectional ESD chip parameters are V BR 13.8~14.5V, IPP is 10%~15% higher than conventional bidirectional ESD chip structures of the same size.

[0056] Example 2: Chip B (P+NP+punch-through bidirectional ESD chip)

[0057] like Figure 2 and 3The bidirectional ESD chip with a through-hole structure shown includes an N-type monocrystalline silicon wafer 1, with an aluminum through-hole ring 5 disposed at the edge of the N-type monocrystalline silicon wafer 1; the aluminum through-hole ring 5 extends from the front side to the back side of the N-type monocrystalline silicon wafer 1; a front boron layer 6 is disposed in the middle region of the front side of the N-type monocrystalline silicon wafer 1, and a back boron layer 7 is disposed on the back side of the N-type monocrystalline silicon wafer 1; the front boron layer 6 and the back boron layer 7 are connected to the aluminum through-hole ring 5 to form the final P+ region; a front lead window 8 and a back lead window are photolithographically etched on the front and back sides of the N-type monocrystalline silicon wafer 1; an aluminum layer 9 is evaporated on the front lead window 8, and a titanium-nickel-silver layer 10 is evaporated on the back lead window; the aluminum layer 9 and the titanium-nickel-silver layer 10 respectively form ohmic contacts with the corresponding P+ regions.

[0058] like Figure 5 The diagram illustrates a through-hole bidirectional ESD chip and its fabrication process. The fabrication process of chip B includes the following steps:

[0059] Step 1) On an N-type single-crystal silicon wafer with a resistivity of 0.003~0.90 Ω·cm, such as Figure 5 As shown in (a); a silicon dioxide layer is grown on both the front and back sides by thermal oxidation, as follows: Figure 5 As shown in (b);

[0060] Step 2) Photolithographically create P+ through-diffusion windows on the front and back sides of the N-type single-crystal silicon wafer, such as... Figure 5 As shown in (c);

[0061] Step 3) Doping a layer of P+ is performed on the front and back sides of an N-type single-crystal silicon wafer using aluminum ion implantation or diffusion from a liquid aluminum source. The aluminum implantation energy is E = 100~150 keV, and the dose DOSE = 2 × 10⁻⁶. 15 / cm 2 ~4×10 15 / cm 2 Or the surface concentration R of the liquid aluminum source diffusion s =50~200Ω / □, such as Figure 5 As shown in (d);

[0062] Step 4) Through high-temperature, long-duration diffusion, the P+ layer is redistributed to achieve penetration between the front and back sides, forming a through-ring P+. Simultaneously, a silicon dioxide layer is grown on the surface as a masking layer for subsequent diffusion. The redistribution temperature is 1260℃~1280℃, and the time is 100~150h. The final through-ring width is 100~200µm. Figure 5 As shown in (e);

[0063] Step 5) Photolithographically create boron implantation or diffusion windows on the silicon dioxide layers on the front and back sides of the N-type single-crystal silicon wafer, such as... Figure 5 (f);

[0064] Step 6) Perform boron implantation or boron diffusion on the P+ diffusion windows on the front and back sides of the N-type single-crystal silicon wafer. The boron ion implantation energy is E = 60~120 keV, and the dose DOSE = 2 × 10⁻⁶. 15 / cm 2 ~3×10 15 / cm 2 Alternatively, the boron pre-diffusion temperature is 1050℃~1150℃, and the time is 2~5h, resulting in R0. s =2.0~5.0Ω / □, such as Figure 5 As shown in (g);

[0065] Step 7) The P+ layer is redistributed through high-temperature (1050℃~1250℃) and time (2~50h) diffusion, resulting in a final diffusion layer depth of 5~30µm. This achieves the target breakdown voltage for the double-sided PN junction and establishes a connection with the P+ through-ring, forming a final P+ region. Simultaneously, a silicon dioxide layer is grown on the surface as a masking layer for subsequent photolithography. Figure 5 As shown in (h);

[0066] Step 8) Photolithographically print lead hole windows on the front and back sides of the N-type single-crystal silicon wafer, such as... Figure 5 As shown in (i);

[0067] Step 9) Evaporate a layer of aluminum metal to the front lead hole window of the N-type single crystal silicon wafer, with a thickness of 4~7µm. Evaporate a layer of titanium-nickel-silver metal to the back lead hole window, with a thickness of 1.5~3µm. Figure 5 As shown in (j);

[0068] Step 10) A metal lead area is photolithographically patterned on the front side of an N-type single-crystal silicon wafer, while the titanium-nickel-silver metal on the back side is retained to form a back metal area. Vacuum alloying is then performed on both sides of the metal to form ohmic contacts, thereby realizing the fabrication of a P+NP+ through-hole bidirectional ESD chip. Figure 5 As shown in (k).

[0069] The resistivity of the N-type single-crystal silicon wafer in step 1) above is preferably 0.046~0.048 Ω·cm; the energy for ion implantation of aluminum in step 3) is preferably E=120 keV, and the dose DOSE=2.5E15 / cm. 2 In step 4), the preferred diffusion temperature is 1275℃, the time is 35h, and the final penetration width is 130~150µm; in step 6), the preferred boron pre-diffusion temperature is 1140℃, the time is 5h, and the final R s=2.0~3.0Ω / □; In step 7), the re-diffusion temperature is preferably 1250℃ and the time is 23h, with a final diffusion layer depth of 22µm; In step 9), the thickness of the front aluminum layer is preferably 5.5µm, and the thickness of the back titanium-nickel-silver layer is preferably 1.8µm; The final bidirectional ESD chip parameters are V BR 42.5~43.5V, IPP is 5%~8% higher than conventional bidirectional ESD chip structures of the same size.

[0070] like Figure 6 As shown in the cross-sectional view of the package of chip A according to embodiment one, an asymmetric structure is adopted, with the doped regions on the back and sides connected in series and eventually extending to the front. The breakdown position of the PN junction also changes from the back to the front. This design solves a series of problems caused by back solder overflow in the traditional bidirectional ESD chip packaging process, and the packaging yield and reliability of the product are further improved. At the same time, the surge protection capability IPP in the back direction is also further improved.

[0071] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A fabrication process for a through-hole bidirectional ESD chip, characterized in that, Includes the following steps: Step S1) Grow silicon dioxide layers on the front and back sides of a first conductivity type single crystal silicon wafer; Step S2) Photolithographically print through-diffusion windows of the second conductivity type at the edges of the silicon dioxide layers on the front and back sides of the first conductivity type single crystal silicon wafer; Step S3) A second type of conductivity impurity is doped on the front and back sides of a single-crystal silicon wafer by ion implantation or liquid source diffusion to form a second type of conductivity doped layer; Step S4) The second conductivity type doped layer is redistributed through diffusion at a certain temperature to achieve front and back penetration, forming a second conductivity type through-ring, while a silicon dioxide layer is grown on the surface as a masking layer. Step S5) Photolithographically print diffusion windows of the second conductivity type on the silicon dioxide masking layers on the front and back sides of the first conductivity type single crystal silicon wafer; Step S6) Diffusion or implantation of impurities of the second conductivity type is performed on the diffusion window of the second conductivity type to form a diffusion layer of the second conductivity type; Step S7) The second conductivity type diffusion layer is redistributed through a certain temperature to make the breakdown voltage of the double-sided PN junction reach the target value and be connected to the second conductivity type punch-through ring to form the final second conductivity type region. At the same time, a silicon dioxide layer is grown on the surface as a masking layer. Step S8) Photolithographically etch lead hole windows on the silicon dioxide masking layers on the front and back sides of the first conductivity type single crystal silicon wafer; Step S9) Evaporate a first metal layer on the front lead hole window and a second metal layer on the back lead hole window; Step S10) Photolithographically pattern a metal lead area on the first metal layer on the front side of the first conductivity type single crystal silicon wafer, retain the second metal layer on the back side to form a back metal area, and vacuum alloy the double-sided metals to form an ohmic contact to obtain a through-structure bidirectional ESD chip.

2. The fabrication process of a through-hole bidirectional ESD chip according to claim 1, characterized in that, The first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

3. The fabrication process of a through-hole bidirectional ESD chip according to claim 2, characterized in that, When the first conductivity type is P-type, the resistivity of the monocrystalline silicon wafer is 0.005~0.60 Ω·cm; when the first conductivity type is N-type, the resistivity of the monocrystalline silicon wafer is 0.003~0.90 Ω·cm.

4. The fabrication process of a through-hole bidirectional ESD chip according to claim 2, characterized in that, When the second conductivity type is N-type, the energy of phosphorus ion implantation in step S3) is 80~150 keV, and the dose is 1×10⁻⁶. 15 / cm 2 ~4×10 15 / cm 2 Or, the concentration of the liquid phosphorus source at the diffusion surface is 0.4~1.0 Ω / □; When the second conductivity type is P-type, the energy of aluminum ion implantation in step S3) is 100~150 keV, and the dose is 2×10⁻⁶. 15 / cm 2 ~4×10 15 / cm 2 Alternatively, the concentration of the liquid aluminum source at the diffusion surface may be 50~200 Ω / □.

5. The fabrication process of a through-hole bidirectional ESD chip according to claim 1, characterized in that, The diffusion temperature in step S4) is 1260℃~1280℃, the time is 30~50h, and the final penetration width is 100μm~200μm.

6. The fabrication process of a through-hole bidirectional ESD chip according to claim 2, characterized in that, When the second conductivity type is N-type, the phosphorus injection energy in step S6) is 60~120 keV, and the dose is 2×10⁻⁶. 15 / cm 2 ~3.5×10 15 / cm 2 Alternatively, the phosphorus pre-diffusion temperature is 1050℃~1150℃, the time is 1.5~3 h, and the final sheet resistance is 0.5~3.0 Ω / □. When the second conductivity type is P-type, the energy of boron ion implantation in step S6) is 60~120 keV, and the dose is 2×10⁻⁶. 15 / cm 2 ~3×10 15 / cm 2 Alternatively, the boron pre-diffusion temperature can be 1050℃~1150℃, the time can be 2~5h, and the final sheet resistance can be 2.0~5.0 Ω / □.

7. The fabrication process of a through-hole bidirectional ESD chip according to claim 1, characterized in that, The re-diffusion temperature in step S7) is 1050℃~1250℃, the time is 2~50h, and the final diffusion layer depth is 5~30 μm.

8. The fabrication process of a through-hole bidirectional ESD chip according to claim 1, characterized in that, In step S9), the first metal layer is an aluminum layer with a thickness of 4~7µm, and the second metal layer on the back is a titanium-nickel-silver layer with a thickness of 1.5~3µm.

9. A through-hole bidirectional ESD chip, comprising a single-crystal silicon wafer of a first conductivity type, characterized in that, The first type of conductive monocrystalline silicon wafer has a second type of conductive through-ring at its edge; the second type of conductive through-ring extends from the front to the back of the first type of conductive monocrystalline silicon wafer. The first type of conductive single-crystal silicon wafer has a second type of conductive diffusion layer in the middle area of ​​the front side and the back side. The second type of conductive diffusion layer is connected to the second type of conductive through-ring to form a second type of conductive region. The first conductivity type single crystal silicon wafer has a first metal layer on its front side and a second metal layer on its back side, and the first metal layer and the second metal layer respectively form ohmic contacts with the corresponding second conductivity type region.

10. A through-hole bidirectional ESD chip according to claim 9, characterized in that, The first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

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